From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16195381AD for ; Thu, 20 Jun 2024 18:19:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.202 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718907568; cv=none; b=gU4VhvMhh48/zKX7mdUw6UycjmX8QNmg4MRtfh4Re3GD8A2sM6ERTv+6MyoszBmC6w+TopoQsHg9RHQfOMzW64BV/T4xXNC8hL+GG3tpSQrcaph566a1RZ/jZyA8uj0T/LyffZ/q+CfibFIELWwKIq4GhhjwgTrBvRVjDX14Ly4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718907568; c=relaxed/simple; bh=4u6zXLqmVGfrUHLuHnED9NbXiWl+6Y1ktystkxMuce0=; h=Date:In-Reply-To:Message-Id:Mime-Version:References:Subject:From: To:Cc:Content-Type; b=MR82s6Uw/6G45ijxotf90kHEZaMw0HvG9a8tGAi3txKmQqiWcEiMNBUmecv73JvcZmi/SBPH4xriy/YCJhSWvvBlEQt5J5yk4kKckUUXRxfVInV6DnSkedKMji4qWVBGDBAwv7IKybYoFEIrpzSbkjQ/GFFd4FC7xt/LiJjiwMc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=xbJ2dJAV; arc=none smtp.client-ip=209.85.219.202 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=flex--irogers.bounces.google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="xbJ2dJAV" Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-dff4a650404so2215213276.3 for ; Thu, 20 Jun 2024 11:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1718907554; x=1719512354; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:from:to:cc:subject:date :message-id:reply-to; bh=blmKl6TPgUE/ql0WP1OIA/nWBvS+XSYwTAFrzkf5cXY=; b=xbJ2dJAVqZ9w/8VkJc1i6XeiQWeKM3sZ0Pel1hi7/DXhNDte1cxOfyB/2v9IsxXc2H qEFz9rbhxIO0CiIrzzAV8WKt5DEssQDgoH8vrAQvoetR1RAVpe2fVJfDItoUlRb2HKsB Tr0Hhni9o5lVrviauf5aAJs0U6y9MEemvZFmFNJet/fdZS6t2Upa1sWYDiY3X3cjdEBY z1HVqBVKexWWi1pTwuDhtQZc9jAyNTbFtGnKJlL8u9Bh6cZKbggIyLl322lTQ7tP1Ayb sZ8bhWaX3r675hIP8XjFeNfzSKIvEU02GkqtHXpW0amBIwnViGGC7ZHpodTpkPPvBinw O/dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1718907554; x=1719512354; h=content-transfer-encoding:cc:to:from:subject:references :mime-version:message-id:in-reply-to:date:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=blmKl6TPgUE/ql0WP1OIA/nWBvS+XSYwTAFrzkf5cXY=; b=M9t3QSIXPZKR7UHD9gc3Tfq5QDcALFz6iEruS2iS+mT7p18MHk6VqESA9xIKf0IPRx w2AIem5IzzyhqCp+jD4vzmJQIJkR48v+vE5dI5yuOOHZ4c/0bGfPojHK+uAySf4MN4aY lcjt9HIa71yRc+s5RRXGg/1Ter+urg5hnKITX+SAl8Qm+D7JbskuQPMxPBv3TJAA8Mkq fUcJzj1hZT1xyzHe7uk1fZRvdGanZ3DAkJs+7jnhjI8ToFbfbhhAdI6Dg/2YoQo09RY7 yb3oGrPYqoeB0gEfstEvlDOMJCASEwhaBC0vdHGxyBEUb04nr1e67ptfen36dSRSqPe0 cZoQ== X-Forwarded-Encrypted: i=1; AJvYcCWk9lRkj2792LTk3T5l56fTtxNm8yZ8XWwjEwm503iZtlp6ROmNfmr8J8/ciL62LR92hkrhh5iyaJFyVUe2lD1bGqVZGCIC3ocE0SiQ X-Gm-Message-State: AOJu0YyzjrlyxzBT/44eBYKMrqiuqondpcj4r30uM698pgh+AF3wGhIx hsncKQmFIxwfIdu8JcTeGGmSJ14R1jpzSckOrJovZ+8fulO5XFusKBjuQI0lE3GePPyW2w8IYPc GHNh/Gg== X-Google-Smtp-Source: AGHT+IGmKi3WbnYvWv/xZCG5/FMwSQQOux/tQVa1bjecaA8ZMKtbWQ5yJKbZIDd4COHyRlPv0v1tjKmKE9PY X-Received: from irogers.svl.corp.google.com ([2620:15c:2a3:200:a6b7:dc01:68ba:649]) (user=irogers job=sendgmr) by 2002:a05:6902:114a:b0:e02:8473:82c4 with SMTP id 3f1490d57ef6-e02be23ccd5mr479912276.11.1718907553914; Thu, 20 Jun 2024 11:19:13 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:15 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-2-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 01/37] perf vendor events: Update alderlake events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.24 to v1.27. Update p-core TMA metrics from v4.7 to v4.8, and the e-core TMA metrics to v3.6. Bring in the event updates v1.27: https://github.com/intel/perfmon/commit/ea4f309a04c50ca77a00da2db130fd7cf06= db978 v1.26: https://github.com/intel/perfmon/commit/0052e68d24d9873d5ff22363677794fa3eb= 05313 The p-core TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 And e-core in: https://github.com/intel/perfmon/commit/d9c2faa70bafe03129dc10f9fe414ef03a9= 5acd9 New events are: EXE_ACTIVITY.2_3_PORTS_UTIL, ICACHE_DATA.STALL_PERIODS, L2_TRANS.L2_WB, MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024, MEM_UOPS_RETIRED.LOCK_LOADS, OFFCORE_REQUESTS.DEMAND_CODE_RD, OFFCORE_REQUESTS.DEMAND_RFO, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD, OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD, RS.EMPTY_RESOURCE, SERIALIZATION.C01_MS_SCB, SW_PREFETCH_ACCESS.ANY, UOPS_ISSUED.ANY, UOPS_ISSUED.CYCLES Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/alderlake/adl-metrics.json | 988 +++++++++--------- .../pmu-events/arch/x86/alderlake/cache.json | 184 +++- .../arch/x86/alderlake/floating-point.json | 20 + .../arch/x86/alderlake/frontend.json | 56 +- .../pmu-events/arch/x86/alderlake/memory.json | 44 + .../arch/x86/alderlake/metricgroups.json | 23 +- .../pmu-events/arch/x86/alderlake/other.json | 37 + .../arch/x86/alderlake/pipeline.json | 214 ++++ .../x86/alderlake/uncore-interconnect.json | 19 + .../arch/x86/alderlake/uncore-memory.json | 25 + .../arch/x86/alderlake/uncore-other.json | 1 + .../arch/x86/alderlake/virtual-memory.json | 26 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 13 files changed, 1115 insertions(+), 524 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json b/to= ols/perf/pmu-events/arch/x86/alderlake/adl-metrics.json index b72c0e2cb946..8fdf4a4225de 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/adl-metrics.json @@ -113,42 +113,30 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to certain allocation restrictions.", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / tma= _info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_alloc_restriction", - "MetricThreshold": "tma_alloc_restriction > 0.1", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to certain allocation restrictions", + "MetricExpr": "tma_core_bound", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_allocation_restriction", + "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_b= ound > 0.1 & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend due to backend stalls", "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / tma_info_core_slot= s", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALL@ / (5 * cpu_atom@CPU_= CLK_UNHALTED.CORE@)", "MetricGroup": "Default;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", "MetricgroupNoGroup": "TopdownL1;Default", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, - { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", - "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "Default;TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound_aux", - "MetricThreshold": "tma_backend_bound_aux > 0.2", - "MetricgroupNoGroup": "TopdownL1;Default", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls. Note that uops must= be available for consumption in order for this event to count. If a uop is= not available (IQ is empty), this event will not count", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "(tma_info_core_slots - (cpu_atom@TOPDOWN_FE_BOUND.A= LL@ + cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RETIRING.ALL@)) / t= ma_info_core_slots", + "MetricExpr": "(5 * cpu_atom@CPU_CLK_UNHALTED.CORE@ - (cpu_atom@TO= PDOWN_FE_BOUND.ALL@ + cpu_atom@TOPDOWN_BE_BOUND.ALL@ + cpu_atom@TOPDOWN_RET= IRING.ALL@)) / (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "Default;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", @@ -158,644 +146,564 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of uops that are not from t= he microsequencer.", - "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@) / tma_info_core_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_base", - "MetricThreshold": "tma_base > 0.6", - "MetricgroupNoGroup": "TopdownL2", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, - { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / tma_info= _core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BACLEARS, which occurs when the Branch T= arget Buffer (BTB) prediction or lack thereof, was corrected by a later bra= nch predictor in the frontend", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_DETECT@ / (5 * cpu= _atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", "MetricName": "tma_branch_detect", - "MetricThreshold": "tma_branch_detect > 0.05", - "PublicDescription": "Counts the number of issue slots that were = not delivered by the frontend due to BACLEARS, which occurs when the Branch= Target Buffer (BTB) prediction or lack thereof, was corrected by a later b= ranch predictor in the frontend. Includes BACLEARS due to all branch types = including conditional and unconditional jumps, returns, and indirect branch= es.", + "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "PublicDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend. Includes BACLEARS due to all branch types i= ncluding conditional and unconditional jumps, returns, and indirect branche= s.", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to branch mispredicts.", - "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / tma_= info_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to branch mispredicts", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MISPREDICT@ / (5 *= cpu_atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", - "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_specul= ation > 0.15", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BTCLEARS, which occurs when the Branch = Target Buffer (BTB) predicts a taken branch.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / tma_inf= o_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BTCLEARS, which occurs when the Branch T= arget Buffer (BTB) predicts a taken branch.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.BRANCH_RESTEER@ / (5 * cp= u_atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", "MetricName": "tma_branch_resteer", - "MetricThreshold": "tma_branch_resteer > 0.05", + "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latenc= y > 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to the microcode sequencer (MS).", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / tma_info_core_slo= ts", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.CISC@ / (5 * cpu_atom@CPU= _CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_cisc", - "MetricThreshold": "tma_cisc > 0.05", + "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 = & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are core execution bound and not attributed to outstanding = demand load or store stalls.", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are bounded by core restrictions and not attributed to an o= utstanding load or stores, or resource limitation", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS@ / (5 = * cpu_atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", - "MetricThreshold": "tma_core_bound > 0.1", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1= ", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to decode stalls.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / tma_info_core_s= lots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to decode stalls.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.DECODE@ / (5 * cpu_atom@C= PU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_decode", - "MetricThreshold": "tma_decode > 0.05", + "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.= 1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory disambiguation.", - "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@= / cpu_atom@MACHINE_CLEARS.SLOW@)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_disambiguation", - "MetricThreshold": "tma_disambiguation > 0.02", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that does not require the = use of microcode, classified as a fast nuke, due to memory ordering, memory= disambiguation and memory renaming", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / (5 * c= pu_atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0= .05 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / tma_info= _core_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MIS= S_AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_H= IT@ / cpu_atom@MEM_BOUND_STALLS.LOAD@", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "MetricThreshold": "tma_dram_bound > 0.1", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to frontend stalls.", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / (5 * cpu_atom@CPU_= CLK_UNHALTED.CORE@)", + "MetricGroup": "Default;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1;Default", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to a machine clear classified as a fast nuke= due to memory ordering, memory disambiguation and memory renaming.", - "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.FASTNUKE@ / tma_in= fo_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", - "MetricName": "tma_fast_nuke", - "MetricThreshold": "tma_fast_nuke > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to instruction cache misses.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / (5 * cpu_atom@C= PU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to frontend bandwidth restrictions due to = decode, predecode, cisc, and other limitations.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / tma= _info_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend bandwidth restrictions due to d= ecode, predecode, cisc, and other limitations.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH@ / (5 = * cpu_atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricName": "tma_ifetch_bandwidth", + "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_boun= d > 0.2", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to frontend bandwidth restrictions due to = decode, predecode, cisc, and other limitations.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / tma_i= nfo_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend latency restrictions due to ica= che misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.FRONTEND_LATENCY@ / (5 * = cpu_atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricName": "tma_ifetch_latency", + "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound= > 0.2", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to FP assists.", - "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cp= u_atom@MACHINE_CLEARS.SLOW@)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_fp_assist", - "MetricThreshold": "tma_fp_assist > 0.02", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, - { - "BriefDescription": "Counts the number of floating point divide op= erations per uop.", - "MetricExpr": "cpu_atom@UOPS_RETIRED.FPDIV@ / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_fpdiv_uops", - "MetricThreshold": "tma_fpdiv_uops > 0.2", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "100 * (cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ + cpu_ato= m@LD_HEAD.PGWALK_AT_RET@) / cpu_atom@CPU_CLK_UNHALTED.CORE@", + "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to frontend stalls.", - "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ALL@ / tma_info_core_slot= s", - "MetricGroup": "Default;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "MetricThreshold": "tma_frontend_bound > 0.2", - "MetricgroupNoGroup": "TopdownL1;Default", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH@ / cpu_atom@= CPU_CLK_UNHALTED.CORE@", + "MetricGroup": "Ifetch", + "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to instruction cache misses.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ICACHE@ / tma_info_core_s= lots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "MetricThreshold": "tma_icache_misses > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.LOAD@ / cpu_atom@CP= U_CLK_UNHALTED.CORE@", + "MetricGroup": "Load_Store_Miss", + "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound", "Unit": "cpu_atom" }, { - "BriefDescription": "", - "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@", - "MetricName": "tma_info_core_clks", + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "100 * cpu_atom@LD_HEAD.ANY_AT_RET@ / cpu_atom@CPU_C= LK_UNHALTED.CORE@", + "MetricGroup": "Mem_Exec", + "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", "Unit": "cpu_atom" }, { - "BriefDescription": "", - "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@", - "MetricName": "tma_info_core_clks_p", + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIR= ED.ALL_BRANCHES@", + "MetricName": "tma_info_br_inst_mix_ipbranch", "Unit": "cpu_atom" }, { - "BriefDescription": "Cycles Per Instruction", - "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", - "MetricName": "tma_info_core_cpi", + "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIR= ED.CALL@", + "MetricName": "tma_info_br_inst_mix_ipcall", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions Per Cycle", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / tma_info_core_clks", - "MetricName": "tma_info_core_ipc", + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_INST_RETIR= ED.FAR_BRANCH@u", + "MetricName": "tma_info_br_inst_mix_ipfarbranch", "Unit": "cpu_atom" }, { - "BriefDescription": "", - "MetricExpr": "5 * tma_info_core_clks", - "MetricName": "tma_info_core_slots", + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETI= RED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken", "Unit": "cpu_atom" }, { - "BriefDescription": "Uops Per Instruction", - "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / INST_RETIRED.ANY", - "MetricName": "tma_info_core_upi", + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIR= ED.COND_TAKEN@", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken", "Unit": "cpu_atom" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = DRAM", - "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / = cpu_atom@MEM_BOUND_STALLS.IFETCH@", - "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent", + "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIR= ED.INDIRECT@", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect", "Unit": "cpu_atom" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = the L2", - "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cp= u_atom@MEM_BOUND_STALLS.IFETCH@", - "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent", + "BriefDescription": "Instructions per retired return Branch Mispre= diction", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIR= ED.RETURN@", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret", "Unit": "cpu_atom" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = the L3", - "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / c= pu_atom@MEM_BOUND_STALLS.IFETCH@", - "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent", + "BriefDescription": "Instructions per retired Branch Misprediction= ", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@BR_MISP_RETIR= ED.ALL_BRANCHES@", + "MetricName": "tma_info_br_inst_mix_ipmispredict", "Unit": "cpu_atom" }, { "BriefDescription": "Ratio of all branches which mispredict", - "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BR_INST_RE= TIRED.ALL_BRANCHES", - "MetricName": "tma_info_inst_mix_branch_mispredict_ratio", + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@B= R_INST_RETIRED.ALL_BRANCHES@", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_rati= o", "Unit": "cpu_atom" }, { "BriefDescription": "Ratio between Mispredicted branches and unkno= wn branches", - "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / BACLEARS.A= NY", - "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_bran= ch_ratio", + "MetricExpr": "cpu_atom@BR_MISP_RETIRED.ALL_BRANCHES@ / cpu_atom@B= ACLEARS.ANY@", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_u= nknown_branch_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / UOPS_RETIRED.A= LL", - "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio", + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.LD_BUF@ / cpu_at= om@CPU_CLK_UNHALTED.CORE@", + "MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / UOPS_RETIRED.AL= L", - "MetricName": "tma_info_inst_mix_idiv_uop_ratio", + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.RSV@ / cpu_atom@= CPU_CLK_UNHALTED.CORE@", + "MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BR= ANCHES", - "MetricName": "tma_info_inst_mix_ipbranch", + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "100 * cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_at= om@CPU_CLK_UNHALTED.CORE@", + "MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles", "Unit": "cpu_atom" }, { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_INST_RETIRED.CALL", - "MetricName": "tma_info_inst_mix_ipcall", + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@INST_RET= IRED.ANY@", + "MetricName": "tma_info_core_cpi", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_INST_RETI= RED.FAR_BRANCH@ / 2)", - "MetricName": "tma_info_inst_mix_ipfarbranch", + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@CPU_CLK_UNHAL= TED.CORE@", + "MetricName": "tma_info_core_ipc", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per Load", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_L= OADS", - "MetricName": "tma_info_inst_mix_ipload", + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "cpu_atom@UOPS_RETIRED.ALL@ / cpu_atom@INST_RETIRED.= ANY@", + "MetricName": "tma_info_core_upi", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / (cpu_atom@BR_MISP_RETI= RED.COND@ - cpu_atom@BR_MISP_RETIRED.COND_TAKEN@)", - "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken", + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_L2_HIT@ / cp= u_atom@MEM_BOUND_STALLS.IFETCH@", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 2hit", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_T= AKEN", - "MetricName": "tma_info_inst_mix_ipmisp_cond_taken", + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_LLC_HIT@ / c= pu_atom@MEM_BOUND_STALLS.IFETCH@", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3hit", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRE= CT", - "MetricName": "tma_info_inst_mix_ipmisp_indirect", + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss subsequently misses in the L3", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.IFETCH_DRAM_HIT@ / = cpu_atom@MEM_BOUND_STALLS.IFETCH@", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3miss", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per retired return Branch Mispre= diction", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RETURN= ", - "MetricName": "tma_info_inst_mix_ipmisp_ret", + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / cpu_= atom@MEM_BOUND_STALLS.LOAD@", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit= ", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per retired Branch Misprediction= ", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BR= ANCHES", - "MetricName": "tma_info_inst_mix_ipmispredict", + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / cpu= _atom@MEM_BOUND_STALLS.LOAD@", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit= ", "Unit": "cpu_atom" }, { - "BriefDescription": "Instructions per Store", - "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / MEM_UOPS_RETIRED.ALL_S= TORES", - "MetricName": "tma_info_inst_mix_ipstore", + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that subsequently misses the L3", + "MetricExpr": "100 * cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / cp= u_atom@MEM_BOUND_STALLS.LOAD@", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3mis= s", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / UOPS_RETIRED.ALL", - "MetricName": "tma_info_inst_mix_microcode_uop_ratio", + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / cpu_atom@= CPU_CLK_UNHALTED.CORE@", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / UOPS_RETIRED.ALL= ", - "MetricName": "tma_info_inst_mix_x87_uop_ratio", + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement", + "MetricExpr": "100 * (cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ + cpu_atom= @MEM_BOUND_STALLS.LOAD@) / cpu_atom@CPU_CLK_UNHALTED.CORE@", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of total non-speculative loads wit= h a address aliasing block", - "MetricExpr": "100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / MEM_UOPS_RETIR= ED.ALL_LOADS", - "MetricName": "tma_info_l1_bound_address_alias_blocks", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full", + "MetricExpr": "100 * (cpu_atom@MEM_SCHEDULER_BLOCK.ST_BUF@ / cpu_a= tom@MEM_SCHEDULER_BLOCK.ALL@) * tma_mem_scheduler", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", - "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / MEM_= UOPS_RETIRED.ALL_LOADS", - "MetricName": "tma_info_l1_bound_load_splits", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory disambiguation", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.DISAMBIGUATION@ / cpu= _atom@INST_RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_disamb_= pki", "Unit": "cpu_atom" }, { - "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", - "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / MEM_UOPS_R= ETIRED.ALL_LOADS", - "MetricName": "tma_info_l1_bound_store_fwd_blocks", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.FP_ASSIST@ / cpu_atom= @INST_RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assi= st_pki", "Unit": "cpu_atom" }, { - "BriefDescription": "Cycle cost per DRAM hit", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_DRAM_HIT@ / MEM_LOAD= _UOPS_RETIRED.DRAM_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_dram_hit", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory ordering", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING@ / cp= u_atom@INST_RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_monuke_= pki", "Unit": "cpu_atom" }, { - "BriefDescription": "Cycle cost per L2 hit", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / MEM_LOAD_U= OPS_RETIRED.L2_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory renaming", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.MRN_NUKE@ / cpu_atom@= INST_RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_mrn_pki= ", "Unit": "cpu_atom" }, { - "BriefDescription": "Cycle cost per LLC hit", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / MEM_LOAD_= UOPS_RETIRED.L3_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to page faults", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / cpu_ato= m@INST_RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fa= ult_pki", "Unit": "cpu_atom" }, { - "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / INST_R= ETIRED.ANY", - "MetricName": "tma_info_memory_memloadpki", + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1e3 * cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom@INST_= RETIRED.ANY@", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki= ", "Unit": "cpu_atom" }, { - "BriefDescription": "Average CPU Utilization", - "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", - "MetricName": "tma_info_system_cpu_utilization", + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.4K_ALIAS@ / cpu_atom@MEM_U= OPS_RETIRED.ALL_LOADS@", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasin= g", "Unit": "cpu_atom" }, { - "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED= .CORE", - "MetricGroup": "Summary", - "MetricName": "tma_info_system_kernel_utilization", + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "100 * cpu_atom@LD_BLOCKS.DATA_UNKNOWN@ / cpu_atom@M= EM_UOPS_RETIRED.ALL_LOADS@", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk", "Unit": "cpu_atom" }, { - "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", - "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", - "MetricGroup": "Power", - "MetricName": "tma_info_system_turbo_utilization", + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "100 * cpu_atom@LD_HEAD.L1_MISS_AT_RET@ / cpu_atom@L= D_HEAD.ANY_AT_RET@", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to Instruction Table Lookaside Buffer (ITL= B) misses.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB@ / tma_info_core_slo= ts", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "MetricThreshold": "tma_itlb_misses > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * cpu_atom@LD_HEAD.OTHER_AT_RET@ / cpu_atom@LD_= HEAD.ANY_AT_RET@", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipeli= neblks", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a load block.", - "MetricExpr": "cpu_atom@LD_HEAD.L1_BOUND_AT_RET@ / tma_info_core_c= lks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "MetricThreshold": "tma_l1_bound > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "100 * cpu_atom@LD_HEAD.PGWALK_AT_RET@ / cpu_atom@LD= _HEAD.ANY_AT_RET@", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ / tma_info_c= ore_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS_= AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_L2_HIT@ = / cpu_atom@MEM_BOUND_STALLS.LOAD@", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "MetricThreshold": "tma_l2_bound > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "100 * cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / cpu_atom= @LD_HEAD.ANY_AT_RET@", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT@ / tma_info_= core_clks - max((cpu_atom@MEM_BOUND_STALLS.LOAD@ - cpu_atom@LD_HEAD.L1_MISS= _AT_RET@) / tma_info_core_clks, 0) * cpu_atom@MEM_BOUND_STALLS.LOAD_LLC_HIT= @ / cpu_atom@MEM_BOUND_STALLS.LOAD@", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "MetricThreshold": "tma_l3_bound > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "100 * cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / cpu_atom@L= D_HEAD.ANY_AT_RET@", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding= ", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to load buffer= full", - "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.LD= _BUF@ / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_ld_buffer", - "MetricThreshold": "tma_ld_buffer > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Instructions per Load", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETI= RED.ALL_LOADS@", + "MetricName": "tma_info_mem_mix_ipload", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", - "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / = tma_info_core_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", - "MetricName": "tma_machine_clears", - "MetricThreshold": "tma_machine_clears > 0.05", - "MetricgroupNoGroup": "TopdownL2", - "ScaleUnit": "100%", + "BriefDescription": "Instructions per Store", + "MetricExpr": "cpu_atom@INST_RETIRED.ANY@ / cpu_atom@MEM_UOPS_RETI= RED.ALL_STORES@", + "MetricName": "tma_info_mem_mix_ipstore", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to memory reservation stalls in which a sche= duler is not able to accept uops.", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / tma_info= _core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_mem_scheduler", - "MetricThreshold": "tma_mem_scheduler > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of total non-speculative loads tha= t perform one or more locks", + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.LOCK_LOADS@ / cpu_a= tom@MEM_UOPS_RETIRED.ALL_LOADS@", + "MetricName": "tma_info_mem_mix_load_locks_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, cpu_atom@LD_HEAD.ANY_AT_RET@= / tma_info_core_clks + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "MetricThreshold": "tma_memory_bound > 0.2", - "MetricgroupNoGroup": "TopdownL2", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", + "MetricExpr": "100 * cpu_atom@MEM_UOPS_RETIRED.SPLIT_LOADS@ / cpu_= atom@MEM_UOPS_RETIRED.ALL_LOADS@", + "MetricName": "tma_info_mem_mix_load_splits_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory ordering.", - "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.MEMORY_ORDERING= @ / cpu_atom@MACHINE_CLEARS.SLOW@)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_memory_ordering", - "MetricThreshold": "tma_memory_ordering > 0.02", - "ScaleUnit": "100%", + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1e3 * cpu_atom@MEM_UOPS_RETIRED.ALL_LOADS@ / cpu_at= om@UOPS_RETIRED.ALL@", + "MetricName": "tma_info_mem_mix_memload_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS)", - "MetricExpr": "cpu_atom@UOPS_RETIRED.MS@ / tma_info_core_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_ms_uops", - "MetricThreshold": "tma_ms_uops > 0.05", - "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "100 * cpu_atom@SERIALIZATION.C01_MS_SCB@ / (5 * cpu= _atom@CPU_CLK_UNHALTED.CORE@)", + "MetricName": "tma_info_serialization _%_tpause_cycles", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to IEC or FPC RAT stalls, which can be due t= o FIQ or IEC reservation stalls in which the integer, floating point or SIM= D scheduler is not able to accept uops.", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / tma_= info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_non_mem_scheduler", - "MetricThreshold": "tma_non_mem_scheduler > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.REF_TSC@ / TSC", + "MetricName": "tma_info_system_cpu_utilization", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to a machine clear (slow nuke).", - "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / tma_info_c= ore_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", - "MetricName": "tma_nuke", - "MetricThreshold": "tma_nuke > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE_P@k / cpu_atom@CPU_C= LK_UNHALTED.CORE@", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_kernel_utilization", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to other common frontend stalls not catego= rized.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / tma_info_core_sl= ots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_other_fb", - "MetricThreshold": "tma_other_fb > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "cpu_atom@CPU_CLK_UNHALTED.CORE@ / cpu_atom@CPU_CLK_= UNHALTED.REF_TSC@", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a number of other lo= ad blocks.", - "MetricExpr": "cpu_atom@LD_HEAD.OTHER_AT_RET@ / tma_info_core_clks= ", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_other_l1", - "MetricThreshold": "tma_other_l1 > 0.05", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.FPDIV@ / cpu_atom@UOPS_= RETIRED.ALL@", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-D= RAM) but could not be correctly attributed or cycles in which the load miss= is waiting on a request buffer.", - "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1= _bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_other_load_store", - "MetricThreshold": "tma_other_load_store > 0.1", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.IDIV@ / cpu_atom@UOPS_R= ETIRED.ALL@", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of uops retired excluding m= s and fp div uops.", - "MetricExpr": "(cpu_atom@TOPDOWN_RETIRING.ALL@ - cpu_atom@UOPS_RET= IRED.MS@ - cpu_atom@UOPS_RETIRED.FPDIV@) / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_other_ret", - "MetricThreshold": "tma_other_ret > 0.3", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of all uops which are microcode op= s", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.MS@ / cpu_atom@UOPS_RET= IRED.ALL@", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to page faults.", - "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.PAGE_FAULT@ / c= pu_atom@MACHINE_CLEARS.SLOW@)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_page_fault", - "MetricThreshold": "tma_page_fault > 0.02", - "ScaleUnit": "100%", + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * cpu_atom@UOPS_RETIRED.X87@ / cpu_atom@UOPS_RE= TIRED.ALL@", + "MetricName": "tma_info_uop_mix_x87_uop_ratio", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to wrong predecodes.", - "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / tma_info_cor= e_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", - "MetricName": "tma_predecode", - "MetricThreshold": "tma_predecode > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB= ) misses.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.ITLB@ / (5 * cpu_atom@CPU= _CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency >= 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to the physical register file unable to acce= pt an entry (marble stalls).", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / tma_info_core= _slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_register", - "MetricThreshold": "tma_register > 0.1", + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS@ / = (5 * cpu_atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculatio= n > 0.15", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to the reorder buffer being full (ROB stalls= ).", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / tma_inf= o_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to memory reservation stalls in which a sched= uler is not able to accept uops", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.MEM_SCHEDULER@ / (5 * cpu= _atom@CPU_CLK_UNHALTED.CORE@)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_reorder_buffer", - "MetricThreshold": "tma_reorder_buffer > 0.1", - "ScaleUnit": "100%", - "Unit": "cpu_atom" - }, - { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", - "MetricName": "tma_resource_bound", - "MetricThreshold": "tma_resource_bound > 0.2", - "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that result= in retirement slots.", - "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / tma_info_core_slot= s", - "MetricGroup": "Default;TopdownL1;tma_L1_group", - "MetricName": "tma_retiring", - "MetricThreshold": "tma_retiring > 0.75", - "MetricgroupNoGroup": "TopdownL1;Default", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to IEC or FPC RAT stalls, which can be due to= FIQ or IEC reservation stalls in which the integer, floating point or SIMD= scheduler is not able to accept uops", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER@ / (5 *= cpu_atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bo= und > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to RSV full re= lative", - "MetricExpr": "tma_mem_scheduler * cpu_atom@MEM_SCHEDULER_BLOCK.RS= V@ / MEM_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_rsv", - "MetricThreshold": "tma_rsv > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that requires the use of m= icrocode (slow nuke)", + "MetricExpr": "cpu_atom@TOPDOWN_BAD_SPECULATION.NUKE@ / (5 * cpu_a= tom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 &= tma_bad_speculation > 0.15)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to scoreboards from the instruction queue (I= Q), jump execution unit (JEU), or microcode sequencer (MS).", - "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / tma_info= _core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_serialization", - "MetricThreshold": "tma_serialization > 0.1", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to other common frontend stalls not categor= ized.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.OTHER@ / (5 * cpu_atom@CP= U_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > = 0.1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to SMC.", - "MetricExpr": "tma_nuke * (cpu_atom@MACHINE_CLEARS.SMC@ / cpu_atom= @MACHINE_CLEARS.SLOW@)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_smc", - "MetricThreshold": "tma_smc > 0.02", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to wrong predecodes.", + "MetricExpr": "cpu_atom@TOPDOWN_FE_BOUND.PREDECODE@ / (5 * cpu_ato= m@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth >= 0.1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to store buffe= r full", - "MetricExpr": "tma_store_bound", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_st_buffer", - "MetricThreshold": "tma_st_buffer > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the physical register file unable to accep= t an entry (marble stalls)", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REGISTER@ / (5 * cpu_atom= @CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2= & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a first level TLB mi= ss.", - "MetricExpr": "cpu_atom@LD_HEAD.DTLB_MISS_AT_RET@ / tma_info_core_= clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_stlb_hit", - "MetricThreshold": "tma_stlb_hit > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the reorder buffer being full (ROB stalls)= ", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.REORDER_BUFFER@ / (5 * cp= u_atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound= > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a second level TLB m= iss requiring a page walk.", - "MetricExpr": "cpu_atom@LD_HEAD.PGWALK_AT_RET@ / tma_info_core_clk= s", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_stlb_miss", - "MetricThreshold": "tma_stlb_miss > 0.05", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a resource limitation", + "MetricExpr": "tma_backend_bound - tma_core_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound >= 0.1", + "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full.", - "MetricExpr": "tma_mem_scheduler * (cpu_atom@MEM_SCHEDULER_BLOCK.S= T_BUF@ / cpu_atom@MEM_SCHEDULER_BLOCK.ALL@)", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "MetricThreshold": "tma_store_bound > 0.1", + "BriefDescription": "Counts the number of issue slots that result = in retirement slots", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "cpu_atom@TOPDOWN_RETIRING.ALL@ / (5 * cpu_atom@CPU_= CLK_UNHALTED.CORE@)", + "MetricGroup": "Default;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1;Default", "ScaleUnit": "100%", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a store forward bloc= k.", - "MetricExpr": "cpu_atom@LD_HEAD.ST_ADDR_AT_RET@ / tma_info_core_cl= ks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "MetricThreshold": "tma_store_fwd_blk > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to scoreboards from the instruction queue (IQ= ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "cpu_atom@TOPDOWN_BE_BOUND.SERIALIZATION@ / (5 * cpu= _atom@CPU_CLK_UNHALTED.CORE@)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%", "Unit": "cpu_atom" }, @@ -818,7 +726,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "78 * cpu_core@ASSISTS.ANY@ / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -838,7 +746,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "cpu_core@topdown\\-be\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -861,7 +769,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricExpr": "cpu_core@topdown\\-br\\-mispredict@ / (cpu_core@top= down\\-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-re= tiring@ + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -920,7 +828,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricExpr": "(25 * tma_info_system_core_frequency * (cpu_core@ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD@ * (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP= _HITM@ / (cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEM= AND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD@))) + 24 * tma_info_system_core_frequ= ency * cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS@) * (1 + cpu_core@MEM_LOA= D_RETIRED.FB_HIT@ / cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / 2) / tma_info_thre= ad_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related m= etrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote= _cache", @@ -941,7 +849,7 @@ { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricExpr": "24 * tma_info_system_core_frequency * (cpu_core@MEM= _LOAD_L3_HIT_RETIRED.XSNP_NO_FWD@ + cpu_core@MEM_LOAD_L3_HIT_RETIRED.XSNP_F= WD@ * (1 - cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM@ / (cpu_core@OCR.D= EMAND_DATA_RD.L3_HIT.SNOOP_HITM@ + cpu_core@OCR.DEMAND_DATA_RD.L3_HIT.SNOOP= _HIT_WITH_FWD@))) * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@MEM_L= OAD_RETIRED.L1_MISS@ / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -961,7 +869,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "cpu_core@ARITH.DIV_ACTIVE@ / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -994,14 +902,14 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%", "Unit": "cpu_core" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu_core@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\= \=3D1@ + cpu_core@DTLB_LOAD_MISSES.WALK_ACTIVE@, max(cpu_core@CYCLE_ACTIVIT= Y.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVITY.CYCLES_L1D_MISS@, 0)) / tma_in= fo_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -1011,7 +919,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu_core@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\= =3D1@ + cpu_core@DTLB_STORE_MISSES.WALK_ACTIVE@) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -1021,7 +929,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "28 * tma_info_system_core_frequency * cpu_core@OCR.= DEMAND_RFO.L3_HIT.SNOOP_HITM@ / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -1031,7 +939,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "cpu_core@L1D_PEND_MISS.FB_FULL@ / tma_info_thread_c= lks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -1045,7 +953,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%", "Unit": "cpu_core" }, @@ -1092,7 +1000,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umas= k\\=3D0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.SCALAR@ / (tma_retir= ing * tma_info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -1102,7 +1010,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0x3c@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "cpu_core@FP_ARITH_INST_RETIRED.VECTOR@ / (tma_retir= ing * tma_info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -1134,7 +1042,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "cpu_core@topdown\\-fe\\-bound@ / (cpu_core@topdown\= \-fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retirin= g@ + cpu_core@topdown\\-be\\-bound@) - cpu_core@INT_MISC.UOP_DROPPING@ / tm= a_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -1145,7 +1053,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.MACRO_= FUSED@ / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", @@ -1166,7 +1074,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "cpu_core@ICACHE_DATA.STALLS@ / tma_info_thread_clks= ", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -1183,7 +1091,7 @@ }, { "BriefDescription": "Instructions per retired mispredicts for cond= itional non-taken branches (lower number means higher occurrence rate).", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_N= TAKEN", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIR= ED.COND_NTAKEN@", "MetricGroup": "Bad;BrMispredicts", "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken", "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_ntaken < 200", @@ -1191,7 +1099,7 @@ }, { "BriefDescription": "Instructions per retired mispredicts for cond= itional taken branches (lower number means higher occurrence rate).", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.COND_T= AKEN", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIR= ED.COND_TAKEN@", "MetricGroup": "Bad;BrMispredicts", "MetricName": "tma_info_bad_spec_ipmisp_cond_taken", "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_taken < 200", @@ -1199,7 +1107,7 @@ }, { "BriefDescription": "Instructions per retired mispredicts for indi= rect CALL or JMP branches (lower number means higher occurrence rate).", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.INDIRE= CT", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIR= ED.INDIRECT@", "MetricGroup": "Bad;BrMispredicts", "MetricName": "tma_info_bad_spec_ipmisp_indirect", "MetricThreshold": "tma_info_bad_spec_ipmisp_indirect < 1e3", @@ -1207,7 +1115,7 @@ }, { "BriefDescription": "Instructions per retired mispredicts for retu= rn branches (lower number means higher occurrence rate).", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.RET", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIR= ED.RET@", "MetricGroup": "Bad;BrMispredicts", "MetricName": "tma_info_bad_spec_ipmisp_ret", "MetricThreshold": "tma_info_bad_spec_ipmisp_ret < 500", @@ -1215,7 +1123,7 @@ }, { "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_MISP_RETIRED.ALL_BR= ANCHES", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_MISP_RETIR= ED.ALL_BRANCHES@", "MetricGroup": "Bad;BadSpec;BrMispredicts", "MetricName": "tma_info_bad_spec_ipmispredict", "MetricThreshold": "tma_info_bad_spec_ipmispredict < 200", @@ -1236,13 +1144,22 @@ "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5", "Unit": "cpu_core" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd = + tma_mite)))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "Unit": "cpu_core" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_lsd + tma_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "Unit": "cpu_core" }, { @@ -1254,34 +1171,27 @@ "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: ", "Unit": "cpu_core" }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL= _BRANCHES@ + cpu_core@BR_INST_RETIRED.NEAR_CALL@) / tma_info_thread_slots -= tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_seque= ncer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20", - "Unit": "cpu_core" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20", "Unit": "cpu_core" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + cp= u_core@BR_INST_RETIRED.NEAR_CALL@) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ + 2 = * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRED.NOP@) / tma_i= nfo_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)", "Unit": "cpu_core" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_lock= _latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_dtlb_load + tma_fb_full + tma_l1_h= it_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full", @@ -1289,8 +1199,8 @@ }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound= / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store= _bound)) * (tma_l1_hit_latency / (tma_dtlb_load + tma_fb_full + tma_l1_hit_= latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency", @@ -1299,16 +1209,16 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: ", "Unit": "cpu_core" }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - c= pu_core@INST_RETIRED.REP_ITERATION@ / cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D= 1@) * (tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_cl= ears_resteers + tma_mispredicts_resteers * tma_other_mispredicts / tma_bran= ch_mispredicts) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unk= nown_branches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_miss= es + tma_itlb_misses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_b= ig_code", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20", "Unit": "cpu_core" @@ -1316,7 +1226,7 @@ { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * ((1 - cpu_core@INST_RETIRED.REP_ITERATION@ / = cpu_core@UOPS_RETIRED.MS\\,cmask\\=3D1@) * (tma_fetch_latency * (tma_ms_swi= tches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_restee= rs * tma_other_mispredicts / tma_branch_mispredicts) / (tma_clears_resteers= + tma_mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers= + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_m= s_switches)) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_b= ranch_mispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other= _nukes / tma_other_nukes + tma_core_bound * (tma_serializing_operation + cp= u_core@RS.EMPTY\\,umask\\=3D1@ / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches", @@ -1324,8 +1234,8 @@ }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)) + tma_me= mory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bou= nd + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store += tma_false_sharing + tma_split_stores + tma_store_latency + tma_streaming_s= tores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_= l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_stor= e / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_late= ncy + tma_streaming_stores)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization", @@ -1334,7 +1244,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (t= ma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_d= ata_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores = + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_mach= ine_clears * (1 - tma_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs", @@ -1343,45 +1253,53 @@ { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers", "Unit": "cpu_core" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls.", + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls.", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (cpu_core@BR_INST_RETIRED.ALL= _BRANCHES@ + 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@INST_RETIRE= D.NOP@) / tma_info_thread_slots - tma_microcode_sequencer / (tma_few_uops_i= nstructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_seque= ncer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of branches that are CALL or RET", - "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_= INST_RETIRED.NEAR_RETURN@) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_CALL@ + cpu_core@BR_= INST_RETIRED.NEAR_RETURN@) / cpu_core@BR_INST_RETIRED.ALL_BRANCHES@", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_branches_callret", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of branches that are non-taken condi= tionals", - "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / BR_INST_RET= IRED.ALL_BRANCHES", + "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_NTAKEN@ / cpu_core@BR= _INST_RETIRED.ALL_BRANCHES@", "MetricGroup": "Bad;Branches;CodeGen;PGO", "MetricName": "tma_info_branches_cond_nt", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of branches that are taken condition= als", - "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_TAKEN@ / BR_INST_RETI= RED.ALL_BRANCHES", + "MetricExpr": "cpu_core@BR_INST_RETIRED.COND_TAKEN@ / cpu_core@BR_= INST_RETIRED.ALL_BRANCHES@", "MetricGroup": "Bad;Branches;CodeGen;PGO", "MetricName": "tma_info_branches_cond_tk", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", - "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR= _INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / BR_I= NST_RETIRED.ALL_BRANCHES", + "MetricExpr": "(cpu_core@BR_INST_RETIRED.NEAR_TAKEN@ - cpu_core@BR= _INST_RETIRED.COND_TAKEN@ - 2 * cpu_core@BR_INST_RETIRED.NEAR_CALL@) / cpu_= core@BR_INST_RETIRED.ALL_BRANCHES@", "MetricGroup": "Bad;Branches", "MetricName": "tma_info_branches_jump", "Unit": "cpu_core" @@ -1442,7 +1360,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 6 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp", "Unit": "cpu_core" }, { @@ -1468,7 +1386,7 @@ }, { "BriefDescription": "Instructions per non-speculative DSB miss (lo= wer number means higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FRONTEND_RETIRED.ANY_D= SB_MISS", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@FRONTEND_RETI= RED.ANY_DSB_MISS@", "MetricGroup": "DSBmiss;Fed", "MetricName": "tma_info_frontend_ipdsb_miss_ret", "MetricThreshold": "tma_info_frontend_ipdsb_miss_ret < 50", @@ -1476,21 +1394,21 @@ }, { "BriefDescription": "Instructions per speculative Unknown Branch M= isprediction (BAClear) (lower number means higher occurrence rate)", - "MetricExpr": "tma_info_inst_mix_instructions / BACLEARS.ANY", + "MetricExpr": "tma_info_inst_mix_instructions / cpu_core@BACLEARS.= ANY@", "MetricGroup": "Fed", "MetricName": "tma_info_frontend_ipunknown_branch", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true code cacheline misses per kilo = instruction", - "MetricExpr": "1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", + "MetricExpr": "1e3 * cpu_core@FRONTEND_RETIRED.L2_MISS@ / cpu_core= @INST_RETIRED.ANY@", "MetricGroup": "IcMiss", "MetricName": "tma_info_frontend_l2mpki_code", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache speculative code cacheline misses pe= r kilo instruction", - "MetricExpr": "1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / INST_RETIRE= D.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.CODE_RD_MISS@ / cpu_core@IN= ST_RETIRED.ANY@", "MetricGroup": "IcMiss", "MetricName": "tma_info_frontend_l2mpki_code_all", "Unit": "cpu_core" @@ -1512,7 +1430,7 @@ }, { "BriefDescription": "Branch instructions per taken branch.", - "MetricExpr": "cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / BR_INST_RE= TIRED.NEAR_TAKEN", + "MetricExpr": "cpu_core@BR_INST_RETIRED.ALL_BRANCHES@ / cpu_core@B= R_INST_RETIRED.NEAR_TAKEN@", "MetricGroup": "Branches;Fed;PGO", "MetricName": "tma_info_inst_mix_bptkbranch", "Unit": "cpu_core" @@ -1527,7 +1445,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INS= T_RETIRED.SCALAR_SINGLE\\,umask\\=3D0x03@ + cpu_core@FP_ARITH_INST_RETIRED.= 128B_PACKED_DOUBLE\\,umask\\=3D0x3c@)", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / (cpu_core@FP_ARITH_INS= T_RETIRED.SCALAR@ + cpu_core@FP_ARITH_INST_RETIRED.VECTOR@)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -1554,7 +1472,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.= SCALAR_DOUBLE", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST= _RETIRED.SCALAR_DOUBLE@", "MetricGroup": "Flops;FpScalar;InsType", "MetricName": "tma_info_inst_mix_iparith_scalar_dp", "MetricThreshold": "tma_info_inst_mix_iparith_scalar_dp < 10", @@ -1563,7 +1481,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / FP_ARITH_INST_RETIRED.= SCALAR_SINGLE", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@FP_ARITH_INST= _RETIRED.SCALAR_SINGLE@", "MetricGroup": "Flops;FpScalar;InsType", "MetricName": "tma_info_inst_mix_iparith_scalar_sp", "MetricThreshold": "tma_info_inst_mix_iparith_scalar_sp < 10", @@ -1572,7 +1490,7 @@ }, { "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.ALL_BR= ANCHES", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIR= ED.ALL_BRANCHES@", "MetricGroup": "Branches;Fed;InsType", "MetricName": "tma_info_inst_mix_ipbranch", "MetricThreshold": "tma_info_inst_mix_ipbranch < 8", @@ -1580,7 +1498,7 @@ }, { "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_C= ALL", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIR= ED.NEAR_CALL@", "MetricGroup": "Branches;Fed;PGO", "MetricName": "tma_info_inst_mix_ipcall", "MetricThreshold": "tma_info_inst_mix_ipcall < 200", @@ -1596,7 +1514,7 @@ }, { "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_L= OADS", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETI= RED.ALL_LOADS@", "MetricGroup": "InsType", "MetricName": "tma_info_inst_mix_ipload", "MetricThreshold": "tma_info_inst_mix_ipload < 3", @@ -1604,14 +1522,14 @@ }, { "BriefDescription": "Instructions per PAUSE (lower number means hi= gher occurrence rate)", - "MetricExpr": "tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.P= AUSE_INST", + "MetricExpr": "tma_info_inst_mix_instructions / cpu_core@CPU_CLK_U= NHALTED.PAUSE_INST@", "MetricGroup": "Flops;FpVector;InsType", "MetricName": "tma_info_inst_mix_ippause", "Unit": "cpu_core" }, { "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / MEM_INST_RETIRED.ALL_S= TORES", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@MEM_INST_RETI= RED.ALL_STORES@", "MetricGroup": "InsType", "MetricName": "tma_info_inst_mix_ipstore", "MetricThreshold": "tma_info_inst_mix_ipstore < 8", @@ -1626,12 +1544,12 @@ "Unit": "cpu_core" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / BR_INST_RETIRED.NEAR_T= AKEN", + "BriefDescription": "Instructions per taken branch", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@BR_INST_RETIR= ED.NEAR_TAKEN@", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 13", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp", + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp", "Unit": "cpu_core" }, { @@ -1664,13 +1582,13 @@ }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", - "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / INST_RETI= RED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@= INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_fb_hpki", "Unit": "cpu_core" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * cpu_core@L1D.REPLACEMENT@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw", @@ -1678,20 +1596,20 @@ }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / INST_RET= IRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L1_MISS@ / cpu_core= @INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_l1mpki", "Unit": "cpu_core" }, { "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", - "MetricExpr": "1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / INST_= RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.ALL_DEMAND_DATA_RD@ / cpu_c= ore@INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_l1mpki_load", "Unit": "cpu_core" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * cpu_core@L2_LINES_IN.ALL@ / 1e9 / duration_tim= e", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw", @@ -1699,48 +1617,55 @@ }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", - "MetricExpr": "1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_= RQSTS.MISS@) / INST_RETIRED.ANY", + "MetricExpr": "1e3 * (cpu_core@L2_RQSTS.REFERENCES@ - cpu_core@L2_= RQSTS.MISS@) / cpu_core@INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_l2hpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", - "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / INST_= RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_HIT@ / cpu_c= ore@INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_l2hpki_load", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / INST_RET= IRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L2_MISS@ / cpu_core= @INST_RETIRED.ANY@", "MetricGroup": "Backend;CacheHits;Mem", "MetricName": "tma_info_memory_l2mpki", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", - "MetricExpr": "1e3 * cpu_core@L2_RQSTS.MISS@ / INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.MISS@ / cpu_core@INST_RETIR= ED.ANY@", "MetricGroup": "CacheHits;Mem;Offcore", "MetricName": "tma_info_memory_l2mpki_all", "Unit": "cpu_core" }, { "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", - "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / INST= _RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.DEMAND_DATA_RD_MISS@ / cpu_= core@INST_RETIRED.ANY@", "MetricGroup": "CacheHits;Mem", "MetricName": "tma_info_memory_l2mpki_load", "Unit": "cpu_core" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * cpu_core@L2_RQSTS.RFO_MISS@ / cpu_core@INST_R= ETIRED.ANY@", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", "MetricExpr": "64 * cpu_core@OFFCORE_REQUESTS.ALL_REQUESTS@ / 1e9 = / duration_time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_memory_l3_cache_access_bw", "Unit": "cpu_core" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * cpu_core@LONGEST_LAT_CACHE.MISS@ / 1e9 / durat= ion_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw", @@ -1748,21 +1673,21 @@ }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", - "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / INST_RET= IRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_RETIRED.L3_MISS@ / cpu_core= @INST_RETIRED.ANY@", "MetricGroup": "Mem", "MetricName": "tma_info_memory_l3mpki", "Unit": "cpu_core" }, { "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD@ / OF= FCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DATA_RD@ / cp= u_core@OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@", "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_data_l2_mlp", "Unit": "cpu_core" }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_R= D@ / OFFCORE_REQUESTS.DEMAND_DATA_RD", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_R= D@ / cpu_core@OFFCORE_REQUESTS.DEMAND_DATA_RD@", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l2_miss_latency", "Unit": "cpu_core" @@ -1776,35 +1701,35 @@ }, { "BriefDescription": "Average Latency for L3 cache miss demand Load= s", - "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAN= D_DATA_RD@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricExpr": "cpu_core@OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAN= D_DATA_RD@ / cpu_core@OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD@", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l3_miss_latency", "Unit": "cpu_core" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", - "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / MEM_LOAD_COMPLETE= D.L1_MISS_ANY", + "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@MEM_LOAD= _COMPLETED.L1_MISS_ANY@", "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency", "Unit": "cpu_core" }, { "BriefDescription": "\"Bus lock\" per kilo instruction", - "MetricExpr": "1e3 * cpu_core@SQ_MISC.BUS_LOCK@ / INST_RETIRED.ANY= ", + "MetricExpr": "1e3 * cpu_core@SQ_MISC.BUS_LOCK@ / cpu_core@INST_RE= TIRED.ANY@", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_bus_lock_pki", "Unit": "cpu_core" }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * cpu_core@MEM_LOAD_MISC_RETIRED.UC@ / INST_RET= IRED.ANY", + "MetricExpr": "1e3 * cpu_core@MEM_LOAD_MISC_RETIRED.UC@ / cpu_core= @INST_RETIRED.ANY@", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki", "Unit": "cpu_core" }, { "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss", - "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / L1D_PEND_MISS.PEN= DING_CYCLES", + "MetricExpr": "cpu_core@L1D_PEND_MISS.PENDING@ / cpu_core@L1D_PEND= _MISS.PENDING_CYCLES@", "MetricGroup": "Mem;MemoryBW;MemoryBound", "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)", @@ -1812,14 +1737,14 @@ }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / INST_R= ETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@ITLB_MISSES.WALK_COMPLETED@ / cpu_co= re@INST_RETIRED.ANY@", "MetricGroup": "Fed;MemoryTLB", "MetricName": "tma_info_memory_tlb_code_stlb_mpki", "Unit": "cpu_core" }, { "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / I= NST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_LOAD_MISSES.WALK_COMPLETED@ / c= pu_core@INST_RETIRED.ANY@", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_memory_tlb_load_stlb_mpki", "Unit": "cpu_core" @@ -1834,21 +1759,42 @@ }, { "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / = INST_RETIRED.ANY", + "MetricExpr": "1e3 * cpu_core@DTLB_STORE_MISSES.WALK_COMPLETED@ / = cpu_core@INST_RETIRED.ANY@", "MetricGroup": "Mem;MemoryTLB", "MetricName": "tma_info_memory_tlb_store_stlb_mpki", "Unit": "cpu_core" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / (cpu_core@UOPS_EXE= CUTED.CORE_CYCLES_GE_1@ / 2 if #SMT_on else cpu_core@UOPS_EXECUTED.THREAD\\= ,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute", "Unit": "cpu_core" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "cpu_core@IDQ.DSB_UOPS@ / cpu_core@IDQ.DSB_CYCLES_AN= Y@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of uops fetched from LSD per c= ycle", + "MetricExpr": "cpu_core@LSD.UOPS@ / cpu_core@LSD.CYCLES_ACTIVE@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_lsd", + "Unit": "cpu_core" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "cpu_core@IDQ.MITE_UOPS@ / cpu_core@IDQ.MITE_CYCLES_= ANY@", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite", + "Unit": "cpu_core" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", - "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / ASSISTS.ANY", + "MetricExpr": "cpu_core@INST_RETIRED.ANY@ / cpu_core@ASSISTS.ANY@", "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", "MetricName": "tma_info_pipeline_ipassist", "MetricThreshold": "tma_info_pipeline_ipassist < 100e3", @@ -1887,14 +1833,14 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization", "Unit": "cpu_core" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.REF_TSC@ / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized", "Unit": "cpu_core" @@ -1925,14 +1871,14 @@ }, { "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / cpu_core@INST_RETIRED= .ANY_P@k", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@INS= T_RETIRED.ANY_P@k", "MetricGroup": "OS", "MetricName": "tma_info_system_kernel_cpi", "Unit": "cpu_core" }, { "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", - "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricExpr": "cpu_core@CPU_CLK_UNHALTED.THREAD_P@k / cpu_core@CPU= _CLK_UNHALTED.THREAD@", "MetricGroup": "OS", "MetricName": "tma_info_system_kernel_utilization", "MetricThreshold": "tma_info_system_kernel_utilization > 0.05", @@ -1971,7 +1917,7 @@ }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", - "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricExpr": "tma_info_thread_clks / cpu_core@CPU_CLK_UNHALTED.RE= F_TSC@", "MetricGroup": "Power", "MetricName": "tma_info_system_turbo_utilization", "Unit": "cpu_core" @@ -1992,7 +1938,7 @@ }, { "BriefDescription": "The ratio of Executed- by Issued-Uops", - "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / UOPS_ISSUED.ANY", + "MetricExpr": "cpu_core@UOPS_EXECUTED.THREAD@ / cpu_core@UOPS_ISSU= ED.ANY@", "MetricGroup": "Cor;Pipeline", "MetricName": "tma_info_thread_execute_per_issue", "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage.", @@ -2021,15 +1967,15 @@ }, { "BriefDescription": "Uops Per Instruction", - "MetricExpr": "tma_retiring * tma_info_thread_slots / INST_RETIRED= .ANY", + "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu_core@INS= T_RETIRED.ANY@", "MetricGroup": "Pipeline;Ret;Retire", "MetricName": "tma_info_thread_uoppi", "MetricThreshold": "tma_info_thread_uoppi > 1.05", "Unit": "cpu_core" }, { - "BriefDescription": "Instruction per taken branch", - "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", + "BriefDescription": "Uops per taken branch", + "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu_core@BR_= INST_RETIRED.NEAR_TAKEN@", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", "MetricThreshold": "tma_info_thread_uptb < 9", @@ -2068,7 +2014,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "cpu_core@ICACHE_TAG.STALLS@ / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -2085,10 +2031,20 @@ "ScaleUnit": "100%", "Unit": "cpu_core" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (cpu_core@MEM_INST_RETIRED.ALL_LOADS@ - cpu= _core@MEM_LOAD_RETIRED.FB_HIT@ - cpu_core@MEM_LOAD_RETIRED.L1_MISS@) * 20 /= 100, max(cpu_core@CYCLE_ACTIVITY.CYCLES_MEM_ANY@ - cpu_core@MEMORY_ACTIVIT= Y.CYCLES_L1D_MISS@, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%", + "Unit": "cpu_core" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(cpu_core@MEMORY_ACTIVITY.STALLS_L1D_MISS@ - cpu_co= re@MEMORY_ACTIVITY.STALLS_L2_MISS@) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -2108,7 +2064,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "9 * tma_info_system_core_frequency * (cpu_core@MEM_= LOAD_RETIRED.L3_HIT@ * (1 + cpu_core@MEM_LOAD_RETIRED.FB_HIT@ / cpu_core@ME= M_LOAD_RETIRED.L1_MISS@ / 2)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -2121,7 +2077,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%", "Unit": "cpu_core" }, @@ -2170,7 +2126,7 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%", "Unit": "cpu_core" }, @@ -2187,7 +2143,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -2198,7 +2154,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clk= s", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -2208,7 +2164,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFF= CORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD@) / tma_info_thread_clks - tm= a_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -2258,7 +2214,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * cpu_= core@INT_MISC.CLEAR_RESTEER_CYCLES@ / tma_info_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -2298,7 +2254,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", "MetricExpr": "tma_light_operations * (cpu_core@BR_INST_RETIRED.AL= L_BRANCHES@ - cpu_core@INST_RETIRED.MACRO_FUSED@) / (tma_retiring * tma_inf= o_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", @@ -2308,7 +2264,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * cpu_core@INST_RETIRED.NOP@ /= (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -2328,7 +2284,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - cpu_core@BR_MISP_= RETIRED.ALL_BRANCHES@ / (cpu_core@INT_MISC.CLEARS_COUNT@ - cpu_core@MACHINE= _CLEARS.COUNT@)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%", @@ -2337,7 +2293,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - cpu_core@MACHINE_CLEA= RS.MEMORY_ORDERING@ / cpu_core@MACHINE_CLEARS.COUNT@), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%", @@ -2395,7 +2351,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu_core@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x8= 0@ + cpu_core@RS.EMPTY\\,umask\\=3D1@) / tma_info_thread_clks * (cpu_core@C= YCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@EXE_ACTIVITY.BOUND_ON_LOADS@) / tma_= info_thread_clks", + "MetricExpr": "(cpu_core@EXE_ACTIVITY.EXE_BOUND_0_PORTS@ + max(cpu= _core@RS.EMPTY\\,umask\\=3D1@ - cpu_core@RESOURCE_STALLS.SCOREBOARD@, 0)) /= tma_info_thread_clks * (cpu_core@CYCLE_ACTIVITY.STALLS_TOTAL@ - cpu_core@E= XE_ACTIVITY.BOUND_ON_LOADS@) / tma_info_thread_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -2428,7 +2384,7 @@ "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "cpu_core@UOPS_EXECUTED.CYCLES_GE_3@ / tma_info_thre= ad_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -2439,7 +2395,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "cpu_core@topdown\\-retiring@ / (cpu_core@topdown\\-= fe\\-bound@ + cpu_core@topdown\\-bad\\-spec@ + cpu_core@topdown\\-retiring@= + cpu_core@topdown\\-be\\-bound@) + 0 * tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -2450,7 +2406,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "cpu_core@RESOURCE_STALLS.SCOREBOARD@ / tma_info_thr= ead_clks + tma_c02_wait", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -2501,7 +2457,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(cpu_core@XQ.FULL_CYCLES@ + cpu_core@L1D_PEND_MISS.= L2_STALLS@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -2531,7 +2487,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(cpu_core@MEM_STORE_RETIRED.L2_HIT@ * 10 * (1 - cpu= _core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.ALL_STORES@)= + (1 - cpu_core@MEM_INST_RETIRED.LOCK_LOADS@ / cpu_core@MEM_INST_RETIRED.A= LL_STORES@) * min(cpu_core@CPU_CLK_UNHALTED.THREAD@, cpu_core@OFFCORE_REQUE= STS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO@)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -2579,7 +2535,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "cpu_core@INT_MISC.UNKNOWN_BRANCH_CYCLES@ / tma_info= _thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", @@ -2588,7 +2544,7 @@ }, { "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", - "MetricExpr": "tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / UOPS_E= XECUTED.THREAD", + "MetricExpr": "tma_retiring * cpu_core@UOPS_EXECUTED.X87@ / cpu_co= re@UOPS_EXECUTED.THREAD@", "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", "MetricName": "tma_x87_use", "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_= light_operations > 0.6)", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/alderlake/cache.json index b3d7f8fb50df..3f51686fe7a8 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.HWPF_MISS", "SampleAfterValue": "1000003", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -38,6 +42,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L1D_PEND_MISS.L2_STALLS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", @@ -47,6 +52,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALLS", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -56,6 +62,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -75,6 +83,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -84,6 +93,7 @@ }, { "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", @@ -93,6 +103,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_RQSTS.REFERENCES]", @@ -102,6 +113,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_RQSTS.MISS]", @@ -111,6 +123,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -120,6 +133,7 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", @@ -129,6 +143,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -138,6 +153,7 @@ }, { "BriefDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_HWPF", "SampleAfterValue": "200003", @@ -146,6 +162,7 @@ }, { "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -155,6 +172,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -164,6 +182,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -173,6 +192,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -182,6 +202,7 @@ }, { "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", @@ -191,6 +212,7 @@ }, { "BriefDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.HWPF_MISS", "SampleAfterValue": "200003", @@ -199,6 +221,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_REQUEST.MISS]", @@ -208,6 +231,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_REQUEST.ALL]", @@ -217,6 +241,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -226,6 +251,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -235,6 +261,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -244,6 +271,7 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", @@ -251,17 +279,29 @@ "UMask": "0x28", "Unit": "cpu_core" }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= core has access to an L3 cache, the LLC is the L3 cache, otherwise it is t= he L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41", "Unit": "cpu_atom" }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -271,15 +311,17 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th= e L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f", "Unit": "cpu_atom" }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -289,6 +331,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", @@ -298,6 +341,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", @@ -307,6 +351,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -316,6 +361,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", @@ -325,6 +371,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", "SampleAfterValue": "200003", @@ -333,6 +380,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", "SampleAfterValue": "200003", @@ -341,6 +389,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "SampleAfterValue": "200003", @@ -349,6 +398,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", @@ -358,6 +408,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -369,6 +420,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -380,6 +432,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -391,6 +444,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -402,6 +456,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -413,6 +468,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -424,6 +480,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -435,6 +492,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -446,6 +504,7 @@ }, { "BriefDescription": "Completed demand load uops that miss the L1 d= -cache.", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "PublicDescription": "Number of completed demand load requests tha= t missed the L1 data cache including shadow misses (FB hits, merge to an on= going L1D miss)", @@ -455,6 +514,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -466,6 +526,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -477,6 +538,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -488,6 +550,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -499,6 +562,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -510,6 +574,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -521,6 +586,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -532,6 +598,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -543,6 +610,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -554,6 +622,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -565,6 +634,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -576,6 +646,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -587,6 +658,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -598,6 +670,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -609,6 +682,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -620,6 +694,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -630,6 +705,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -640,6 +716,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", @@ -650,6 +727,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked for any of the following reasons: load buffer, store buffer or RSV fu= ll.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ALL", "SampleAfterValue": "20003", @@ -658,6 +736,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", "SampleAfterValue": "20003", @@ -666,6 +745,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.RSV", "SampleAfterValue": "20003", @@ -674,6 +754,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", "SampleAfterValue": "20003", @@ -682,6 +763,7 @@ }, { "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "MEM_STORE_RETIRED.L2_HIT", "SampleAfterValue": "200003", @@ -690,6 +772,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -701,6 +784,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -712,6 +796,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 128 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", @@ -725,6 +810,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 16 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", @@ -738,6 +824,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 256 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", @@ -751,6 +838,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 32 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", @@ -764,6 +852,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 4 cycles as define= d in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", @@ -777,6 +866,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 512 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", @@ -790,6 +880,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 64 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", @@ -803,6 +894,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 8 cycles as define= d in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", @@ -814,8 +906,20 @@ "UMask": "0x5", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x21", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -826,6 +930,7 @@ }, { "BriefDescription": "Counts the number of stores uops retired. Cou= nts with or without PEBS enabled.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", @@ -837,6 +942,7 @@ }, { "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe5", "EventName": "MEM_UOP_RETIRED.ANY", "PublicDescription": "Number of retired micro-operations (uops) fo= r load or store memory accesses", @@ -846,6 +952,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -856,6 +963,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -866,6 +974,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another cores caches, data forwarding is required as the data i= s modified.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +985,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -886,6 +996,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +1007,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another cores caches which forwarded the unmodified data to the= requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -906,6 +1018,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -916,6 +1029,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -926,6 +1040,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that resulte= d in a snoop hit in another cores caches, data forwarding is required as th= e data is modified.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -936,6 +1051,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "SampleAfterValue": "100003", @@ -944,6 +1060,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -951,8 +1068,19 @@ "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2", + "Unit": "cpu_core" + }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -960,8 +1088,19 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4", + "Unit": "cpu_core" + }, { "BriefDescription": "This event is deprecated. Refer to new event = OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "Errata": "ADL038", "EventCode": "0x20", @@ -972,6 +1111,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA= _RD", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "ADL038", "EventCode": "0x20", @@ -980,8 +1120,20 @@ "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, { "BriefDescription": "Cycles where at least 1 outstanding demand da= ta read request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -991,6 +1143,7 @@ }, { "BriefDescription": "For every cycle where the core is waiting on = at least 1 outstanding Demand RFO request, increments by 1.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -1001,6 +1154,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "Errata": "ADL038", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", @@ -1008,8 +1162,19 @@ "UMask": "0x8", "Unit": "cpu_core" }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_core" + }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -1019,6 +1184,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -1026,8 +1192,18 @@ "UMask": "0x10", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf", + "Unit": "cpu_core" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -1037,6 +1213,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -1046,6 +1223,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -1055,6 +1233,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", @@ -1064,6 +1243,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json b= /tools/perf/pmu-events/arch/x86/alderlake/floating-point.json index cd291943dc08..b4621c221f58 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.FPDIV_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -19,6 +21,7 @@ }, { "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.SSE_AVX_MIX", "SampleAfterValue": "1000003", @@ -27,6 +30,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is ali= as to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_0", "SampleAfterValue": "2000003", @@ -35,6 +39,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is ali= as to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_1", "SampleAfterValue": "2000003", @@ -43,6 +48,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is ali= as to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_5", "SampleAfterValue": "2000003", @@ -51,6 +57,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V0", "SampleAfterValue": "2000003", @@ -59,6 +66,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V1", "SampleAfterValue": "2000003", @@ -67,6 +75,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V2", "SampleAfterValue": "2000003", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -120,6 +134,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -129,6 +144,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -138,6 +154,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -147,6 +164,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "PublicDescription": "Number of any Vector retired FP arithmetic i= nstructions. The DAZ and FTZ flags in the MXCSR register need to be set wh= en using these events.", @@ -156,6 +174,7 @@ }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -165,6 +184,7 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json b/tools= /perf/pmu-events/arch/x86/alderlake/frontend.json index 542ba4a81996..66735a612ebd 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Clears due to Unknown Branches.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of times the front-end is resteered w= hen it finds a branch instruction in a fetch line. This is called Unknown B= ranch which occurs for the first time a branch instruction is fetched or wh= en the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.MS_BUSY", "SampleAfterValue": "500009", @@ -36,6 +40,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -69,6 +76,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -81,6 +89,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -93,6 +102,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -105,6 +115,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -117,6 +128,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -129,6 +141,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -141,6 +154,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -153,6 +167,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -165,6 +180,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -177,6 +193,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -189,6 +206,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -201,6 +219,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -213,6 +232,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -225,6 +245,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -237,6 +258,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.MS_FLOWS", "MSRIndex": "0x3F7", @@ -248,6 +270,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -260,6 +283,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "MSRIndex": "0x3F7", @@ -271,6 +295,7 @@ }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", @@ -280,6 +305,7 @@ }, { "BriefDescription": "Counts the number of instruction cache misses= .", + "Counter": "0,1,2,3,4,5", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", @@ -289,6 +315,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The decode pipeline works at a 32= Byte granularity.", @@ -296,8 +323,20 @@ "UMask": "0x4", "Unit": "cpu_core" }, + { + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "SampleAfterValue": "500009", + "UMask": "0x4", + "Unit": "cpu_core" + }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", @@ -307,6 +346,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -317,16 +357,18 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the D= SB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the I= DQ.", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_core" }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -336,6 +378,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -346,6 +389,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -356,6 +400,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -365,6 +410,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -375,6 +421,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -386,6 +433,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS).", @@ -395,6 +443,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE= ]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", @@ -404,6 +453,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", @@ -414,6 +464,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", @@ -425,6 +476,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_BUBBLES.CORE]", @@ -434,6 +486,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -444,6 +497,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/memory.json b/tools/p= erf/pmu-events/arch/x86/alderlake/memory.json index 23d36164433f..81a03f53aadc 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to any number of reasons, incl= uding an L1 miss, WCB full, pagewalk, store address block or store data blo= ck, on a load that retires.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.ANY_AT_RET", "SampleAfterValue": "1000003", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to a core bound stall includin= g a store address match, a DTLB miss or a page walk that detains the load f= rom retiring.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.L1_BOUND_AT_RET", "SampleAfterValue": "1000003", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.L1_MISS_AT_RET", "SampleAfterValue": "1000003", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", "PublicDescription": "Counts the number of cycles that the head (o= ldest load) of the load buffer and retirement are both stalled due to other= block cases such as pipeline conflicts, fences, etc.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a page= walk.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.PGWALK_AT_RET", "SampleAfterValue": "1000003", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a stor= e address match.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.ST_ADDR_AT_RET", "SampleAfterValue": "1000003", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", @@ -94,6 +105,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", @@ -104,6 +116,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "9", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", @@ -112,8 +125,23 @@ "UMask": "0x9", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 1024 cycles. Reporte= d latency may be longer than just the memory latency.", + "SampleAfterValue": "53", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -127,6 +155,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -140,6 +169,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -153,6 +183,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -166,6 +197,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -179,6 +211,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -192,6 +225,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -205,6 +239,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -218,6 +253,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -229,6 +265,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -239,6 +276,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -249,6 +287,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -259,6 +298,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +309,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that were no= t supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -279,6 +320,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -289,6 +331,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -297,6 +340,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known by the requesti= ng core to have missed the L3 cache.", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/metricgroups.json b/t= ools/perf/pmu-events/arch/x86/alderlake/metricgroups.json index 7a03835f262c..b54a5fc0861f 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/metricgroups.json @@ -5,8 +5,21 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", @@ -22,14 +35,17 @@ "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "IntVector": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis = Metrics spreadsheet", "MachineClears": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis M= etrics spreadsheet", "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metri= cs spreadsheet", + "Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", @@ -60,6 +76,7 @@ "TopdownL4": "Metrics for top-down breakdown at level 4", "TopdownL5": "Metrics for top-down breakdown at level 5", "TopdownL6": "Metrics for top-down breakdown at level 6", + "load_store_bound": "Grouping from Top-down Microarchitecture Analysis= Metrics spreadsheet", "tma_L1_group": "Metrics for top-down breakdown at level 1", "tma_L2_group": "Metrics for top-down breakdown at level 2", "tma_L3_group": "Metrics for top-down breakdown at level 3", @@ -68,10 +85,8 @@ "tma_L6_group": "Metrics for top-down breakdown at level 6", "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_ut= ilization category", "tma_assists_group": "Metrics contributing to tma_assists category", - "tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bo= und_aux category", "tma_backend_bound_group": "Metrics contributing to tma_backend_bound = category", "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculat= ion category", - "tma_base_group": "Metrics contributing to tma_base category", "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mi= spredicts category", "tma_branch_resteers_group": "Metrics contributing to tma_branch_reste= ers category", "tma_core_bound_group": "Metrics contributing to tma_core_bound catego= ry", @@ -84,6 +99,8 @@ "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category= ", "tma_frontend_bound_group": "Metrics contributing to tma_frontend_boun= d category", "tma_heavy_operations_group": "Metrics contributing to tma_heavy_opera= tions category", + "tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_band= width category", + "tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latenc= y category", "tma_int_operations_group": "Metrics contributing to tma_int_operation= s category", "tma_issue2P": "Metrics related by the issue $issue2P", "tma_issueBM": "Metrics related by the issue $issueBM", @@ -110,11 +127,9 @@ "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_= utilization category", "tma_machine_clears_group": "Metrics contributing to tma_machine_clear= s category", "tma_mem_latency_group": "Metrics contributing to tma_mem_latency cate= gory", - "tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler = category", "tma_memory_bound_group": "Metrics contributing to tma_memory_bound ca= tegory", "tma_microcode_sequencer_group": "Metrics contributing to tma_microcod= e_sequencer category", "tma_mite_group": "Metrics contributing to tma_mite category", - "tma_nuke_group": "Metrics contributing to tma_nuke category", "tma_other_light_ops_group": "Metrics contributing to tma_other_light_= ops category", "tma_ports_utilization_group": "Metrics contributing to tma_ports_util= ization category", "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utili= zed_0 category", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/other.json b/tools/pe= rf/pmu-events/arch/x86/alderlake/other.json index 5250a17d9cae..f95e093f8fcf 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ASSISTS.HARDWARE", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.HARDWARE", "SampleAfterValue": "100003", @@ -9,6 +10,7 @@ }, { "BriefDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.PAGE_FAULT", "SampleAfterValue": "1000003", @@ -17,6 +19,7 @@ }, { "BriefDescription": "CORE_POWER.LICENSE_1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_1", "SampleAfterValue": "200003", @@ -25,6 +28,7 @@ }, { "BriefDescription": "CORE_POWER.LICENSE_2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_2", "SampleAfterValue": "200003", @@ -33,6 +37,7 @@ }, { "BriefDescription": "CORE_POWER.LICENSE_3", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LICENSE_3", "SampleAfterValue": "200003", @@ -41,6 +46,7 @@ }, { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xe4", "EventName": "LBR_INSERTS.ANY", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -81,6 +90,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -101,6 +112,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that have an= y type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -111,6 +123,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -121,6 +134,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -131,6 +145,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", "EventName": "RS.EMPTY", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -140,6 +155,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xa5", @@ -150,8 +166,18 @@ "UMask": "0x7", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty= due to a resource in the back-end", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_RESOURCE", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY_COUNT", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EdgeDetect": "1", @@ -164,6 +190,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xa5", "EventName": "RS_EMPTY.CYCLES", @@ -171,8 +198,18 @@ "UMask": "0x7", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the number of issue slots in a UMWAIT = or TPAUSE instruction where no uop issues due to the instruction putting th= e CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will onl= y put the CPU into C0.1 activity state (not C0.2 activity state)", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x75", + "EventName": "SERIALIZATION.C01_MS_SCB", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, { "BriefDescription": "Cycles the uncore cannot take further request= s", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/alderlake/pipeline.json index df6032e816d4..b7656f77dee9 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.DIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -11,6 +12,7 @@ }, { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.DIV_ACTIVE", @@ -21,6 +23,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -31,6 +34,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divi= der is busy.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", @@ -40,6 +44,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.IDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -50,6 +55,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware. Examples include AD (page Access Dirt= y), FP and AVX related assists.", @@ -59,6 +65,7 @@ }, { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -68,6 +75,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -77,6 +85,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.NEAR_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", @@ -87,6 +96,7 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -96,6 +106,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -106,6 +117,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -116,6 +128,7 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -125,6 +138,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -135,6 +149,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -144,6 +159,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -154,6 +170,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -163,6 +180,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -173,6 +191,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -182,6 +201,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", @@ -192,6 +212,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", @@ -202,6 +223,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -211,6 +233,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -221,6 +244,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -230,6 +254,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -240,6 +265,7 @@ }, { "BriefDescription": "Counts the number of near taken branch instru= ctions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -249,6 +275,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -259,6 +286,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", @@ -269,6 +297,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -278,6 +307,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.NEAR_RETURN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", @@ -288,6 +318,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND_TAKEN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", @@ -298,6 +329,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -307,6 +339,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -316,6 +349,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -325,6 +359,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -335,6 +370,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -345,6 +381,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -354,6 +391,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -364,6 +402,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -373,6 +412,7 @@ }, { "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -383,6 +423,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -392,6 +433,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -402,6 +444,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", @@ -412,6 +455,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", @@ -422,6 +466,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near taken = branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -431,6 +476,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -441,6 +487,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", @@ -451,6 +498,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -461,6 +509,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -470,6 +519,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND_TAKEN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", @@ -480,6 +530,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 li= ght-weight slower wakeup time but more power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C01", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 light-weight slower wakeup time but more power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -489,6 +540,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.2 li= ght-weight faster wakeup time but less power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C02", "PublicDescription": "Counts core clocks when the thread is in the= C0.2 light-weight faster wakeup time but less power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -498,6 +550,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 or= C0.2 or running a PAUSE in C0 ACPI state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C0_WAIT", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions)= or running the PAUSE instruction.", @@ -507,6 +560,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -515,6 +569,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", @@ -523,6 +578,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -532,6 +588,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -541,6 +598,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.PAUSE", "SampleAfterValue": "2000003", @@ -549,6 +607,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xec", @@ -559,6 +618,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -568,6 +628,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -576,6 +637,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the eight programmable counte= rs available for other events. Note: On all current platforms this event st= ops counting during 'throttling (TM)' states duty off periods the processor= is 'halted'. The counter update is done at a lower clock rate then the co= re clock the overflow status bit for this counter may appear 'sticky'. Aft= er the counter has overflowed and software clears the overflow status bit a= nd resets the counter to less than MAX. The reset value to the counter is n= ot clocked immediately so the overflow status bit will flip 'high (1)' and = generate another PMI (if enabled) after which the reset value gets clocked = into the counter. Therefore, software will get the interrupt, read the over= flow status bit '1 for bit 34 while the counter value is less than MAX. Sof= tware should ignore this case.", "SampleAfterValue": "2000003", @@ -584,6 +646,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -593,6 +656,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", @@ -602,6 +666,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. = This event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -610,6 +675,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -618,6 +684,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses a programmable general purpose performance counter.", @@ -626,6 +693,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -634,6 +702,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -643,6 +712,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -652,6 +722,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -661,6 +732,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -670,6 +742,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -679,6 +752,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -688,6 +762,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -695,8 +770,18 @@ "UMask": "0x2", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles total of 2 or 3 uops are executed on a= ll ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "UMask": "0xc", + "Unit": "cpu_core" + }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -706,6 +791,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -715,6 +801,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -724,6 +811,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", @@ -733,6 +821,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -743,6 +832,7 @@ }, { "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", @@ -752,6 +842,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -761,6 +852,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", @@ -770,6 +862,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -779,6 +872,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -788,6 +882,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -797,6 +892,7 @@ }, { "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -806,6 +902,7 @@ }, { "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -816,6 +913,7 @@ }, { "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = precise distribution of samples across instructions retired. It utilizes th= e Precise Distribution of Instructions Retired (PDIR++) feature to fix bias= in how retired instructions get sampled. Use on Fixed Counter 0.", @@ -825,6 +923,7 @@ }, { "BriefDescription": "Iterations of Repeat string retired instructi= ons.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", "PEBS": "1", @@ -835,6 +934,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xad", @@ -846,6 +946,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -855,6 +956,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -864,6 +966,7 @@ }, { "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", "MSRIndex": "0x3F7", @@ -874,6 +977,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -883,6 +987,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.128BIT", "SampleAfterValue": "1000003", @@ -891,6 +996,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.256BIT", "SampleAfterValue": "1000003", @@ -899,6 +1005,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_128", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 128-bit vector instructions.", @@ -908,6 +1015,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_256", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 256-bit vector instructions.", @@ -917,6 +1025,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.MUL_256", "SampleAfterValue": "1000003", @@ -925,6 +1034,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.SHUFFLES", "SampleAfterValue": "1000003", @@ -933,6 +1043,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_128", "SampleAfterValue": "1000003", @@ -941,6 +1052,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_256", "SampleAfterValue": "1000003", @@ -949,6 +1061,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = LD_BLOCKS.ADDRESS_ALIAS", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", @@ -959,6 +1072,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PEBS": "1", @@ -968,6 +1082,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", @@ -977,6 +1092,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", @@ -986,6 +1102,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -995,6 +1112,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -1004,6 +1122,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -1013,6 +1132,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", @@ -1023,6 +1143,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -1033,6 +1154,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -1042,6 +1164,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -1053,6 +1176,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -1061,6 +1185,7 @@ }, { "BriefDescription": "Counts the number of machines clears due to m= emory renaming.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MRN_NUKE", "SampleAfterValue": "1000003", @@ -1069,6 +1194,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -1077,6 +1203,7 @@ }, { "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine with the use of microcode due to SMC= , MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_= TRAP.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SLOW", "SampleAfterValue": "20003", @@ -1085,6 +1212,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -1093,6 +1221,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -1102,6 +1231,7 @@ }, { "BriefDescription": "LFENCE instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", "PublicDescription": "number of LFENCE retired instructions", @@ -1111,6 +1241,7 @@ }, { "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSE= RTS.ANY]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBS": "1", @@ -1121,6 +1252,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -1130,6 +1262,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -1139,6 +1272,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -1147,6 +1281,7 @@ }, { "BriefDescription": "Counts the number of issue slots not consumed= by the backend due to a micro-sequencer (MS) scoreboard, which stalls the = front-end from issuing from the UROM until a specified older uop retires.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x75", "EventName": "SERIALIZATION.NON_C01_MS_SCB", "PublicDescription": "Counts the number of issue slots not consume= d by the backend due to a micro-sequencer (MS) scoreboard, which stalls the= front-end from issuing from the UROM until a specified older uop retires. = The most commonly executed instruction with an MS scoreboard is PAUSE.", @@ -1156,6 +1291,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Number of slots in TMA method where no micro= -operations were being issued from front-end to back-end of the machine due= to lack of back-end resources.", @@ -1165,6 +1301,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= s.", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BAD_SPEC_SLOTS", "PublicDescription": "Number of slots of TMA method that were wast= ed due to incorrect speculation. It covers all types of control-flow or dat= a-related mis-speculations.", @@ -1174,6 +1311,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by (any type of) branch mispredictions. This event es= timates number of speculative operations that were issued but not retired a= s well as the out-of-order engine recovery past a branch misprediction.", @@ -1183,6 +1321,7 @@ }, { "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", "SampleAfterValue": "10000003", @@ -1191,6 +1330,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -1199,6 +1339,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -1208,6 +1349,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", @@ -1216,6 +1358,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -1224,6 +1367,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -1232,6 +1376,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -1240,6 +1385,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "SampleAfterValue": "1000003", @@ -1248,6 +1394,7 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003", @@ -1255,6 +1402,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -1263,6 +1411,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -1271,6 +1420,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -1279,6 +1429,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -1287,6 +1438,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -1295,6 +1447,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -1303,6 +1456,7 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003", @@ -1310,6 +1464,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", @@ -1319,6 +1474,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", @@ -1328,6 +1484,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -1336,6 +1493,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -1344,6 +1502,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "SampleAfterValue": "1000003", @@ -1352,6 +1511,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to a latency related stalls inc= luding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "SampleAfterValue": "1000003", @@ -1360,6 +1520,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", @@ -1369,6 +1530,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -1377,6 +1539,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -1385,6 +1548,7 @@ }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", @@ -1393,6 +1557,7 @@ }, { "BriefDescription": "UOPS_DECODED.DEC0_UOPS", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UOPS_DECODED.DEC0_UOPS", "SampleAfterValue": "1000003", @@ -1401,6 +1566,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Number of uops dispatch to execution port 0= .", @@ -1410,6 +1576,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Number of uops dispatch to execution port 1= .", @@ -1419,6 +1586,7 @@ }, { "BriefDescription": "Uops executed on ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_2_3_10", "PublicDescription": "Number of uops dispatch to execution ports 2= , 3 and 10", @@ -1428,6 +1596,7 @@ }, { "BriefDescription": "Uops executed on ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Number of uops dispatch to execution ports 4= and 9", @@ -1437,6 +1606,7 @@ }, { "BriefDescription": "Uops executed on ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_5_11", "PublicDescription": "Number of uops dispatch to execution ports 5= and 11", @@ -1446,6 +1616,7 @@ }, { "BriefDescription": "Uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Number of uops dispatch to execution port 6= .", @@ -1455,6 +1626,7 @@ }, { "BriefDescription": "Uops executed on ports 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Number of uops dispatch to execution ports = 7 and 8.", @@ -1464,6 +1636,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -1474,6 +1647,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -1484,6 +1658,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -1494,6 +1669,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -1504,6 +1680,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -1514,6 +1691,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -1524,6 +1702,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -1534,6 +1713,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -1544,6 +1724,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.STALLS", @@ -1555,6 +1736,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_EXECUTED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb1", @@ -1566,6 +1748,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -1574,6 +1757,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -1581,8 +1765,18 @@ "UMask": "0x10", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", + "SampleAfterValue": "200003", + "Unit": "cpu_atom" + }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xae", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -1590,8 +1784,19 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1600,6 +1805,7 @@ }, { "BriefDescription": "Cycles with retired uop(s).", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.CYCLES", @@ -1610,6 +1816,7 @@ }, { "BriefDescription": "Retired uops except the last uop of each inst= ruction.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.HEAVY", "PublicDescription": "Counts the number of retired micro-operation= s (uops) except the last uop of each instruction. An instruction that is de= coded into less than two uops does not contribute to the count.", @@ -1619,6 +1826,7 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", @@ -1628,6 +1836,7 @@ }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", @@ -1638,6 +1847,7 @@ }, { "BriefDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "MSRIndex": "0x3F7", @@ -1648,6 +1858,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -1657,6 +1868,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALLS", @@ -1668,6 +1880,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_RETIRED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xc2", @@ -1679,6 +1892,7 @@ }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.j= son b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json index 8bf020a9dfa8..7c0779c74154 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -9,56 +10,69 @@ }, { "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_DAT_OCCUPANCY.ALL", + "Counter": "0", "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_T= RK_OCCUPANCY.RD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -67,14 +81,17 @@ }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_R= EQ_TRK_OCCUPANCY.DRD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -83,8 +100,10 @@ }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD= ]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json b/= tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json index 163d7e7755c4..bcf275cd592a 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every 64B read request entering the M= emory Controller 0 to DRAM (sum of all channels).", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts every 64B write request entering the M= emory Controller 0 to DRAM (sum of all channels). Each write request counts= as a new request incrementing this counter. However, same cache line write= requests (both full and partial) are combined to a single 64 byte data tra= nsfer to DRAM.", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts every 64B read request entering the Me= mory Controller 1 to DRAM (sum of all channels).", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Counts every 64B write request entering the M= emory Controller 1 to DRAM (sum of all channels). Each write request counts= as a new request incrementing this counter. However, same cache line write= requests (both full and partial) are combined to a single 64 byte data tra= nsfer to DRAM.", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x24", "EventName": "UNC_M_ACT_COUNT_RD", "PerPkg": "1", @@ -42,6 +47,7 @@ }, { "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x26", "EventName": "UNC_M_ACT_COUNT_TOTAL", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x25", "EventName": "UNC_M_ACT_COUNT_WR", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", "PerPkg": "1", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", "PerPkg": "1", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Number of clocks", + "Counter": "0,1,2,3,4", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -77,6 +87,7 @@ }, { "BriefDescription": "incoming read request page status is Page Emp= ty", + "Counter": "0,1,2,3,4", "EventCode": "0x1D", "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", "PerPkg": "1", @@ -84,6 +95,7 @@ }, { "BriefDescription": "incoming write request page status is Page Em= pty", + "Counter": "0,1,2,3,4", "EventCode": "0x20", "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", "PerPkg": "1", @@ -91,6 +103,7 @@ }, { "BriefDescription": "incoming read request page status is Page Hit= ", + "Counter": "0,1,2,3,4", "EventCode": "0x1C", "EventName": "UNC_M_DRAM_PAGE_HIT_RD", "PerPkg": "1", @@ -98,6 +111,7 @@ }, { "BriefDescription": "incoming write request page status is Page Hi= t", + "Counter": "0,1,2,3,4", "EventCode": "0x1F", "EventName": "UNC_M_DRAM_PAGE_HIT_WR", "PerPkg": "1", @@ -105,6 +119,7 @@ }, { "BriefDescription": "incoming read request page status is Page Mis= s", + "Counter": "0,1,2,3,4", "EventCode": "0x1E", "EventName": "UNC_M_DRAM_PAGE_MISS_RD", "PerPkg": "1", @@ -112,6 +127,7 @@ }, { "BriefDescription": "incoming write request page status is Page Mi= ss", + "Counter": "0,1,2,3,4", "EventCode": "0x21", "EventName": "UNC_M_DRAM_PAGE_MISS_WR", "PerPkg": "1", @@ -119,6 +135,7 @@ }, { "BriefDescription": "Any Rank at Hot state", + "Counter": "0,1,2,3,4", "EventCode": "0x19", "EventName": "UNC_M_DRAM_THERMAL_HOT", "PerPkg": "1", @@ -126,6 +143,7 @@ }, { "BriefDescription": "Any Rank at Warm state", + "Counter": "0,1,2,3,4", "EventCode": "0x1A", "EventName": "UNC_M_DRAM_THERMAL_WARM", "PerPkg": "1", @@ -133,6 +151,7 @@ }, { "BriefDescription": "Incoming read prefetch request from IA.", + "Counter": "0,1,2,3,4", "EventCode": "0x0A", "EventName": "UNC_M_PREFETCH_RD", "PerPkg": "1", @@ -140,6 +159,7 @@ }, { "BriefDescription": "PRE command sent to DRAM due to page table id= le timer expiration", + "Counter": "0,1,2,3,4", "EventCode": "0x28", "EventName": "UNC_M_PRE_COUNT_IDLE", "PerPkg": "1", @@ -147,6 +167,7 @@ }, { "BriefDescription": "PRE command sent to DRAM for a read/write req= uest", + "Counter": "0,1,2,3,4", "EventCode": "0x27", "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", "PerPkg": "1", @@ -154,6 +175,7 @@ }, { "BriefDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", "EventCode": "0x02", "EventName": "UNC_M_VC0_REQUESTS_RD", "PerPkg": "1", @@ -161,6 +183,7 @@ }, { "BriefDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", "EventCode": "0x03", "EventName": "UNC_M_VC0_REQUESTS_WR", "PerPkg": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", "EventCode": "0x04", "EventName": "UNC_M_VC1_REQUESTS_RD", "PerPkg": "1", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", "EventCode": "0x05", "EventName": "UNC_M_VC1_REQUESTS_WR", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/alderlake/uncore-other.json index 2af92e43b28a..1ac5b5ef8094 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json index 3827d292da80..e0d8f3070778 100644 --- a/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -20,6 +22,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -38,6 +42,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -47,6 +52,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -56,6 +62,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -74,6 +82,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -83,6 +92,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -93,6 +103,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -102,6 +113,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -111,6 +123,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -120,6 +133,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -129,6 +143,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -138,6 +153,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", "SampleAfterValue": "1000003", @@ -155,6 +172,7 @@ }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -163,6 +181,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -172,6 +191,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -182,6 +202,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -191,6 +212,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -200,6 +222,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -209,6 +232,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -218,6 +242,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -227,6 +252,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.DTLB_MISS_AT_RET", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index c9891630be10..ec40215377f3 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,5 +1,5 @@ Family-model,Version,Filename,EventType -GenuineIntel-6-(97|9A|B7|BA|BF),v1.24,alderlake,core +GenuineIntel-6-(97|9A|B7|BA|BF),v1.27,alderlake,core GenuineIntel-6-BE,v1.24,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v29,broadwell,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 65BBC172BAB for ; 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Thu, 20 Jun 2024 11:19:16 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:16 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-3-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 02/37] perf vendor events: Update alderlaken events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.24 to v1.27. Update e-core TMA metrics to v3.6. Bring in the event updates v1.27: https://github.com/intel/perfmon/commit/ea4f309a04c50ca77a00da2db130fd7cf06= db978 v1.26: https://github.com/intel/perfmon/commit/0052e68d24d9873d5ff22363677794fa3eb= 05313 The e-core TMA 3.6 information was updated in: https://github.com/intel/perfmon/commit/d9c2faa70bafe03129dc10f9fe414ef03a9= 5acd9 New events are: MEM_UOPS_RETIRED.LOCK_LOADS, SERIALIZATION.C01_MS_SCB, UOPS_ISSUED.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/alderlaken/adln-metrics.json | 658 ++++++++---------- .../pmu-events/arch/x86/alderlaken/cache.json | 50 +- .../arch/x86/alderlaken/floating-point.json | 2 + .../arch/x86/alderlaken/frontend.json | 3 + .../arch/x86/alderlaken/memory.json | 11 + .../arch/x86/alderlaken/metricgroups.json | 21 +- .../pmu-events/arch/x86/alderlaken/other.json | 13 + .../arch/x86/alderlaken/pipeline.json | 80 +++ .../x86/alderlaken/uncore-interconnect.json | 19 + .../arch/x86/alderlaken/uncore-memory.json | 25 + .../arch/x86/alderlaken/uncore-other.json | 1 + .../arch/x86/alderlaken/virtual-memory.json | 6 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 13 files changed, 503 insertions(+), 388 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json b/= tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json index a35edf7d86a9..447596f924ab 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/adln-metrics.json @@ -85,39 +85,28 @@ "ScaleUnit": "1SMI#" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to certain allocation restrictions.", - "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / tma_info_core= _slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", - "MetricName": "tma_alloc_restriction", - "MetricThreshold": "tma_alloc_restriction > 0.1", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to certain allocation restrictions", + "MetricExpr": "tma_core_bound", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_allocation_restriction", + "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_b= ound > 0.1 & tma_backend_bound > 0.1)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend due to backend stalls", "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "TOPDOWN_BE_BOUND.ALL / tma_info_core_slots", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)", "MetricGroup": "Default;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.1", "MetricgroupNoGroup": "TopdownL1;Default", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. The rest of t= hese subevents count backend stalls, in cycles, due to an outstanding reque= st which is memory bound vs core bound. The subevents are not slot based = events and therefore can not be precisely added or subtracted from the Back= end_Bound_Aux subevents which are slot based.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", - "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "Default;TopdownL1;tma_L1_group", - "MetricName": "tma_backend_bound_aux", - "MetricThreshold": "tma_backend_bound_aux > 0.2", - "MetricgroupNoGroup": "TopdownL1;Default", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that UOPS mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count. All of these s= ubevents count backend stalls, in slots, due to a resource limitation. Th= ese are not cycle based events and therefore can not be precisely added or = subtracted from the Backend_Bound subevents which are cycle based. These s= ubevents are supplementary to Backend_Bound and can be used to analyze resu= lts from a resource perspective at allocation.", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls. Note that uops must= be available for consumption in order for this event to count. If a uop is= not available (IQ is empty), this event will not count", "ScaleUnit": "100%" }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "(tma_info_core_slots - (TOPDOWN_FE_BOUND.ALL + TOPD= OWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / tma_info_core_slots", + "MetricExpr": "(5 * CPU_CLK_UNHALTED.CORE - (TOPDOWN_FE_BOUND.ALL = + TOPDOWN_BE_BOUND.ALL + TOPDOWN_RETIRING.ALL)) / (5 * CPU_CLK_UNHALTED.COR= E)", "MetricGroup": "Default;TopdownL1;tma_L1_group", "MetricName": "tma_bad_speculation", "MetricThreshold": "tma_bad_speculation > 0.15", @@ -126,300 +115,351 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of uops that are not from t= he microsequencer.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS) / tma_info= _core_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_base", - "MetricThreshold": "tma_base > 0.6", - "MetricgroupNoGroup": "TopdownL2", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / tma_info_core_slot= s", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BACLEARS, which occurs when the Branch T= arget Buffer (BTB) prediction or lack thereof, was corrected by a later bra= nch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (5 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", "MetricName": "tma_branch_detect", - "MetricThreshold": "tma_branch_detect > 0.05", - "PublicDescription": "Counts the number of issue slots that were = not delivered by the frontend due to BACLEARS, which occurs when the Branch= Target Buffer (BTB) prediction or lack thereof, was corrected by a later b= ranch predictor in the frontend. Includes BACLEARS due to all branch types = including conditional and unconditional jumps, returns, and indirect branch= es.", + "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "PublicDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend. Includes BACLEARS due to all branch types i= ncluding conditional and unconditional jumps, returns, and indirect branche= s.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to branch mispredicts.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / tma_info_core_= slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to branch mispredicts", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (5 * CPU_CLK_U= NHALTED.CORE)", "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_branch_mispredicts", - "MetricThreshold": "tma_branch_mispredicts > 0.05", + "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_specul= ation > 0.15", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BTCLEARS, which occurs when the Branch = Target Buffer (BTB) predicts a taken branch.", - "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / tma_info_core_slo= ts", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BTCLEARS, which occurs when the Branch T= arget Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (5 * CPU_CLK_UNHA= LTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", "MetricName": "tma_branch_resteer", - "MetricThreshold": "tma_branch_resteer > 0.05", + "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latenc= y > 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to the microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_FE_BOUND.CISC / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / (5 * CPU_CLK_UNHALTED.CORE)= ", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_cisc", - "MetricThreshold": "tma_cisc > 0.05", + "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 = & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are core execution bound and not attributed to outstanding = demand load or store stalls.", - "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are bounded by core restrictions and not attributed to an o= utstanding load or stores, or resource limitation", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (5 * CPU_CLK_= UNHALTED.CORE)", "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_core_bound", - "MetricThreshold": "tma_core_bound > 0.1", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1= ", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to decode stalls.", - "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (5 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_decode", - "MetricThreshold": "tma_decode > 0.05", + "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.= 1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory disambiguation.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.DISAMBIGUATION / MACHINE= _CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_disambiguation", - "MetricThreshold": "tma_disambiguation > 0.02", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that does not require the = use of microcode, classified as a fast nuke, due to memory ordering, memory= disambiguation and memory renaming", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (5 * CPU_CLK_UNH= ALTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0= .05 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / tma_info_core_clks= - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clk= s, 0) * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_dram_bound", - "MetricThreshold": "tma_dram_bound > 0.1", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to frontend stalls.", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL / (5 * CPU_CLK_UNHALTED.CORE)", + "MetricGroup": "Default;TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1;Default", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to a machine clear classified as a fast nuke= due to memory ordering, memory disambiguation and memory renaming.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / tma_info_core_sl= ots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", - "MetricName": "tma_fast_nuke", - "MetricThreshold": "tma_fast_nuke > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (5 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to frontend bandwidth restrictions due to = decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / tma_info_core= _slots", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend bandwidth restrictions due to d= ecode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (5 * CPU_CLK_= UNHALTED.CORE)", "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_bandwidth", - "MetricThreshold": "tma_fetch_bandwidth > 0.1", + "MetricName": "tma_ifetch_bandwidth", + "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_boun= d > 0.2", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to frontend bandwidth restrictions due to = decode, predecode, cisc, and other limitations.", - "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / tma_info_core_s= lots", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend latency restrictions due to ica= che misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (5 * CPU_CLK_UN= HALTED.CORE)", "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", - "MetricName": "tma_fetch_latency", - "MetricThreshold": "tma_fetch_latency > 0.15", + "MetricName": "tma_ifetch_latency", + "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound= > 0.2", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to FP assists.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.FP_ASSIST / MACHINE_CLEA= RS.SLOW)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_fp_assist", - "MetricThreshold": "tma_fp_assist > 0.02", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT= _RET) / CPU_CLK_UNHALTED.CORE", + "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles" }, { - "BriefDescription": "Counts the number of floating point divide op= erations per uop.", - "MetricExpr": "UOPS_RETIRED.FPDIV / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_fpdiv_uops", - "MetricThreshold": "tma_fpdiv_uops > 0.2", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "Ifetch", + "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to frontend stalls.", - "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "TOPDOWN_FE_BOUND.ALL / tma_info_core_slots", - "MetricGroup": "Default;TopdownL1;tma_L1_group", - "MetricName": "tma_frontend_bound", - "MetricThreshold": "tma_frontend_bound > 0.2", - "MetricgroupNoGroup": "TopdownL1;Default", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "100 * MEM_BOUND_STALLS.LOAD / CPU_CLK_UNHALTED.CORE= ", + "MetricGroup": "Load_Store_Miss", + "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to instruction cache misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_icache_misses", - "MetricThreshold": "tma_icache_misses > 0.05", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Mem_Exec", + "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound" + }, + { + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", + "MetricName": "tma_info_br_inst_mix_ipcall" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricName": "tma_info_br_inst_mix_ipfarbranch" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per retired return Branch Mispre= diction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction= ", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipmispredict" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_= BRANCHES", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_rati= o" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unkno= wn branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_u= nknown_branch_ratio" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE", - "MetricName": "tma_info_core_clks" + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles" }, { - "BriefDescription": "", - "MetricExpr": "CPU_CLK_UNHALTED.CORE_P", - "MetricName": "tma_info_core_clks_p" + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CO= RE", + "MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles" }, { "BriefDescription": "Cycles Per Instruction", - "MetricExpr": "tma_info_core_clks / INST_RETIRED.ANY", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY", "MetricName": "tma_info_core_cpi" }, { "BriefDescription": "Instructions Per Cycle", - "MetricExpr": "INST_RETIRED.ANY / tma_info_core_clks", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE", "MetricName": "tma_info_core_ipc" }, - { - "BriefDescription": "", - "MetricExpr": "5 * tma_info_core_clks", - "MetricName": "tma_info_core_slots" - }, { "BriefDescription": "Uops Per Instruction", "MetricExpr": "UOPS_RETIRED.ALL / INST_RETIRED.ANY", "MetricName": "tma_info_core_upi" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = DRAM", + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_ST= ALLS.IFETCH", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 2hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_S= TALLS.IFETCH", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss subsequently misses in the L3", "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_DRAM_HIT / MEM_BOUND_= STALLS.IFETCH", - "MetricName": "tma_info_frontend_inst_miss_cost_dramhit_percent" + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3miss" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = the L2", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_L2_HIT / MEM_BOUND_ST= ALLS.IFETCH", - "MetricName": "tma_info_frontend_inst_miss_cost_l2hit_percent" + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STAL= LS.LOAD", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit" }, { - "BriefDescription": "Percent of instruction miss cost that hit in = the L3", - "MetricExpr": "100 * MEM_BOUND_STALLS.IFETCH_LLC_HIT / MEM_BOUND_S= TALLS.IFETCH", - "MetricName": "tma_info_frontend_inst_miss_cost_l3hit_percent" + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STA= LLS.LOAD", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit" }, { - "BriefDescription": "Ratio of all branches which mispredict", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_= BRANCHES", - "MetricName": "tma_info_inst_mix_branch_mispredict_ratio" + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that subsequently misses the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_BOUND_ST= ALLS.LOAD", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3mis= s" }, { - "BriefDescription": "Ratio between Mispredicted branches and unkno= wn branches", - "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", - "MetricName": "tma_info_inst_mix_branch_mispredict_to_unknown_bran= ch_ratio" + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound" }, { - "BriefDescription": "Percentage of all uops which are FPDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", - "MetricName": "tma_info_inst_mix_fpdiv_uop_ratio" + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement", + "MetricExpr": "100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS.L= OAD) / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound" }, { - "BriefDescription": "Percentage of all uops which are IDiv uops", - "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", - "MetricName": "tma_info_inst_mix_idiv_uop_ratio" + "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full", + "MetricExpr": "100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_B= LOCK.ALL) * tma_mem_scheduler", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound" }, { - "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", - "MetricName": "tma_info_inst_mix_ipbranch" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory disambiguation", + "MetricExpr": "1e3 * MACHINE_CLEARS.DISAMBIGUATION / INST_RETIRED.= ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_disamb_= pki" }, { - "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.CALL", - "MetricName": "tma_info_inst_mix_ipcall" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assi= st_pki" }, { - "BriefDescription": "Instructions per Far Branch", - "MetricExpr": "INST_RETIRED.ANY / (BR_INST_RETIRED.FAR_BRANCH / 2)= ", - "MetricName": "tma_info_inst_mix_ipfarbranch" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory ordering", + "MetricExpr": "1e3 * MACHINE_CLEARS.MEMORY_ORDERING / INST_RETIRED= .ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_monuke_= pki" }, { - "BriefDescription": "Instructions per Load", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", - "MetricName": "tma_info_inst_mix_ipload" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to memory renaming", + "MetricExpr": "1e3 * MACHINE_CLEARS.MRN_NUKE / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_mrn_pki" }, { - "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", - "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", - "MetricName": "tma_info_inst_mix_ipmisp_cond_ntaken" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to page faults", + "MetricExpr": "1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fa= ult_pki" }, { - "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", - "MetricName": "tma_info_inst_mix_ipmisp_cond_taken" + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki" }, { - "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", - "MetricName": "tma_info_inst_mix_ipmisp_indirect" + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOA= DS", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasin= g" }, { - "BriefDescription": "Instructions per retired return Branch Mispre= diction", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", - "MetricName": "tma_info_inst_mix_ipmisp_ret" + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk" }, { - "BriefDescription": "Instructions per retired Branch Misprediction= ", - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", - "MetricName": "tma_info_inst_mix_ipmispredict" + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss" }, { - "BriefDescription": "Instructions per Store", - "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", - "MetricName": "tma_info_inst_mix_ipstore" + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipeli= neblks" }, { - "BriefDescription": "Percentage of all uops which are ucode ops", - "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", - "MetricName": "tma_info_inst_mix_microcode_uop_ratio" + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk" }, { - "BriefDescription": "Percentage of all uops which are x87 uops", - "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", - "MetricName": "tma_info_inst_mix_x87_uop_ratio" + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET= ", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit" }, { - "BriefDescription": "Percentage of total non-speculative loads wit= h a address aliasing block", - "MetricExpr": "100 * LD_BLOCKS.4K_ALIAS / MEM_UOPS_RETIRED.ALL_LOA= DS", - "MetricName": "tma_info_l1_bound_address_alias_blocks" + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding" }, { - "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", - "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", - "MetricName": "tma_info_l1_bound_load_splits" + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_ipload" }, { - "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", - "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", - "MetricName": "tma_info_l1_bound_store_fwd_blocks" + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricName": "tma_info_mem_mix_ipstore" }, { - "BriefDescription": "Cycle cost per DRAM hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_DRAM_HIT / MEM_LOAD_UOPS_RETI= RED.DRAM_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_dram_hit" + "BriefDescription": "Percentage of total non-speculative loads tha= t perform one or more locks", + "MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRE= D.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_locks_ratio" }, { - "BriefDescription": "Cycle cost per L2 hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_LOAD_UOPS_RETIRE= D.L2_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_l2_hit" + "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_splits_ratio" }, { - "BriefDescription": "Cycle cost per LLC hit", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_LOAD_UOPS_RETIR= ED.L3_HIT", - "MetricName": "tma_info_memory_cycles_per_demand_load_l3_hit" + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / UOPS_RETIRED.ALL= ", + "MetricName": "tma_info_mem_mix_memload_ratio" }, { - "BriefDescription": "load ops retired per 1000 instruction", - "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY= ", - "MetricName": "tma_info_memory_memloadpki" + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / (5 * CPU_CLK_UNHAL= TED.CORE)", + "MetricName": "tma_info_serialization _%_tpause_cycles" }, { "BriefDescription": "Average CPU Utilization", @@ -428,194 +468,122 @@ }, { "BriefDescription": "Fraction of cycles spent in Kernel mode", - "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE@k / CPU_CLK_UNHALTED.CORE= ", + "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CO= RE", "MetricGroup": "Summary", "MetricName": "tma_info_system_kernel_utilization" }, { "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", - "MetricExpr": "tma_info_core_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC", "MetricGroup": "Power", "MetricName": "tma_info_system_turbo_utilization" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to Instruction Table Lookaside Buffer (ITL= B) misses.", - "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_latency_group", - "MetricName": "tma_itlb_misses", - "MetricThreshold": "tma_itlb_misses > 0.05", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / UOPS_RETIRED.ALL", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio" }, { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a load block.", - "MetricExpr": "LD_HEAD.L1_BOUND_AT_RET / tma_info_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l1_bound", - "MetricThreshold": "tma_l1_bound > 0.1", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / UOPS_RETIRED.ALL", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio" }, { - "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the L2 Cache.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_L2_HIT / tma_info_core_clks -= max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks,= 0) * MEM_BOUND_STALLS.LOAD_L2_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l2_bound", - "MetricThreshold": "tma_l2_bound > 0.1", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are microcode op= s", + "MetricExpr": "100 * UOPS_RETIRED.MS / UOPS_RETIRED.ALL", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio" }, { - "BriefDescription": "Counts the number of cycles a core is stalled= due to a demand load which hit in the Last Level Cache (LLC) or other core= with HITE/F/M.", - "MetricExpr": "MEM_BOUND_STALLS.LOAD_LLC_HIT / tma_info_core_clks = - max((MEM_BOUND_STALLS.LOAD - LD_HEAD.L1_MISS_AT_RET) / tma_info_core_clks= , 0) * MEM_BOUND_STALLS.LOAD_LLC_HIT / MEM_BOUND_STALLS.LOAD", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_l3_bound", - "MetricThreshold": "tma_l3_bound > 0.1", - "ScaleUnit": "100%" + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / UOPS_RETIRED.ALL", + "MetricName": "tma_info_uop_mix_x87_uop_ratio" }, { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to load buffer= full", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.LD_BUF / ME= M_SCHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_ld_buffer", - "MetricThreshold": "tma_ld_buffer > 0.05", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB= ) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB / (5 * CPU_CLK_UNHALTED.CORE)= ", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency >= 0.15 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / tma_info_c= ore_slots", + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (5 * CPU_C= LK_UNHALTED.CORE)", "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", "MetricName": "tma_machine_clears", - "MetricThreshold": "tma_machine_clears > 0.05", + "MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculatio= n > 0.15", "MetricgroupNoGroup": "TopdownL2", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to memory reservation stalls in which a sche= duler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / tma_info_core_slot= s", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to memory reservation stalls in which a sched= uler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / (5 * CPU_CLK_UNHAL= TED.CORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", "MetricName": "tma_mem_scheduler", - "MetricThreshold": "tma_mem_scheduler > 0.1", + "MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to stores or loads.", - "MetricExpr": "min(tma_backend_bound, LD_HEAD.ANY_AT_RET / tma_inf= o_core_clks + tma_store_bound)", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", - "MetricName": "tma_memory_bound", - "MetricThreshold": "tma_memory_bound > 0.2", - "MetricgroupNoGroup": "TopdownL2", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to memory ordering.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.MEMORY_ORDERING / MACHIN= E_CLEARS.SLOW)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_memory_ordering", - "MetricThreshold": "tma_memory_ordering > 0.02", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS)", - "MetricExpr": "UOPS_RETIRED.MS / tma_info_core_slots", - "MetricGroup": "TopdownL2;tma_L2_group;tma_retiring_group", - "MetricName": "tma_ms_uops", - "MetricThreshold": "tma_ms_uops > 0.05", - "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "Counts the number of uops that are from the = complex flows issued by the micro-sequencer (MS). This includes uops from = flows due to complex instructions, faults, assists, and inserted flows.", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to IEC or FPC RAT stalls, which can be due t= o FIQ or IEC reservation stalls in which the integer, floating point or SIM= D scheduler is not able to accept uops.", - "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / tma_info_core_= slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to IEC or FPC RAT stalls, which can be due to= FIQ or IEC reservation stalls in which the integer, floating point or SIMD= scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (5 * CPU_CLK_U= NHALTED.CORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", "MetricName": "tma_non_mem_scheduler", - "MetricThreshold": "tma_non_mem_scheduler > 0.1", + "MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bo= und > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to a machine clear (slow nuke).", - "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / tma_info_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that requires the use of m= icrocode (slow nuke)", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / (5 * CPU_CLK_UNHALTE= D.CORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", "MetricName": "tma_nuke", - "MetricThreshold": "tma_nuke > 0.05", + "MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 &= tma_bad_speculation > 0.15)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to other common frontend stalls not catego= rized.", - "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to other common frontend stalls not categor= ized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / (5 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_other_fb", - "MetricThreshold": "tma_other_fb > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a number of other lo= ad blocks.", - "MetricExpr": "LD_HEAD.OTHER_AT_RET / tma_info_core_clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_other_l1", - "MetricThreshold": "tma_other_l1 > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hits in the L2, LLC, DRAM or MMIO (Non-D= RAM) but could not be correctly attributed or cycles in which the load miss= is waiting on a request buffer.", - "MetricExpr": "max(0, tma_memory_bound - (tma_store_bound + tma_l1= _bound + tma_l2_bound + tma_l3_bound + tma_dram_bound))", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_other_load_store", - "MetricThreshold": "tma_other_load_store > 0.1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of uops retired excluding m= s and fp div uops.", - "MetricExpr": "(TOPDOWN_RETIRING.ALL - UOPS_RETIRED.MS - UOPS_RETI= RED.FPDIV) / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_base_group", - "MetricName": "tma_other_ret", - "MetricThreshold": "tma_other_ret > 0.3", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to page faults.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.PAGE_FAULT / MACHINE_CLE= ARS.SLOW)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_page_fault", - "MetricThreshold": "tma_page_fault > 0.02", + "MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > = 0.1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to wrong predecodes.", - "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / tma_info_core_slots", - "MetricGroup": "TopdownL3;tma_L3_group;tma_fetch_bandwidth_group", + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / (5 * CPU_CLK_UNHALTED.= CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", "MetricName": "tma_predecode", - "MetricThreshold": "tma_predecode > 0.05", + "MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth >= 0.1 & tma_frontend_bound > 0.2)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to the physical register file unable to acce= pt an entry (marble stalls).", - "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / tma_info_core_slots", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the physical register file unable to accep= t an entry (marble stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / (5 * CPU_CLK_UNHALTED.C= ORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", "MetricName": "tma_register", - "MetricThreshold": "tma_register > 0.1", + "MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2= & tma_backend_bound > 0.1)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to the reorder buffer being full (ROB stalls= ).", - "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / tma_info_core_slo= ts", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the reorder buffer being full (ROB stalls)= ", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / (5 * CPU_CLK_UNHA= LTED.CORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", "MetricName": "tma_reorder_buffer", - "MetricThreshold": "tma_reorder_buffer > 0.1", + "MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound= > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls", - "MetricExpr": "tma_backend_bound", - "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_aux_group= ", + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a resource limitation", + "MetricExpr": "tma_backend_bound - tma_core_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", "MetricName": "tma_resource_bound", - "MetricThreshold": "tma_resource_bound > 0.2", + "MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound >= 0.1", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "Counts the total number of issue slots that= were not consumed by the backend due to backend stalls. Note that uops mu= st be available for consumption in order for this event to count. If a uop= is not available (IQ is empty), this event will not count.", "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of issue slots that result= in retirement slots.", + "BriefDescription": "Counts the number of issue slots that result = in retirement slots", "DefaultMetricgroupName": "TopdownL1", - "MetricExpr": "TOPDOWN_RETIRING.ALL / tma_info_core_slots", + "MetricExpr": "TOPDOWN_RETIRING.ALL / (5 * CPU_CLK_UNHALTED.CORE)", "MetricGroup": "Default;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.75", @@ -623,67 +591,11 @@ "ScaleUnit": "100%" }, { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to RSV full re= lative", - "MetricExpr": "tma_mem_scheduler * MEM_SCHEDULER_BLOCK.RSV / MEM_S= CHEDULER_BLOCK.ALL", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_rsv", - "MetricThreshold": "tma_rsv > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of issue slots that were n= ot consumed by the backend due to scoreboards from the instruction queue (I= Q), jump execution unit (JEU), or microcode sequencer (MS).", - "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / tma_info_core_slot= s", + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to scoreboards from the instruction queue (IQ= ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / (5 * CPU_CLK_UNHAL= TED.CORE)", "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", "MetricName": "tma_serialization", - "MetricThreshold": "tma_serialization > 0.1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of machine clears relative = to the number of nuke slots due to SMC.", - "MetricExpr": "tma_nuke * (MACHINE_CLEARS.SMC / MACHINE_CLEARS.SLO= W)", - "MetricGroup": "TopdownL4;tma_L4_group;tma_nuke_group", - "MetricName": "tma_smc", - "MetricThreshold": "tma_smc > 0.02", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles, relative to the = number of mem_scheduler slots, in which uops are blocked due to store buffe= r full", - "MetricExpr": "tma_store_bound", - "MetricGroup": "TopdownL4;tma_L4_group;tma_mem_scheduler_group", - "MetricName": "tma_st_buffer", - "MetricThreshold": "tma_st_buffer > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a first level TLB mi= ss.", - "MetricExpr": "LD_HEAD.DTLB_MISS_AT_RET / tma_info_core_clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_stlb_hit", - "MetricThreshold": "tma_stlb_hit > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a second level TLB m= iss requiring a page walk.", - "MetricExpr": "LD_HEAD.PGWALK_AT_RET / tma_info_core_clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_stlb_miss", - "MetricThreshold": "tma_stlb_miss > 0.05", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full.", - "MetricExpr": "tma_mem_scheduler * (MEM_SCHEDULER_BLOCK.ST_BUF / M= EM_SCHEDULER_BLOCK.ALL)", - "MetricGroup": "TopdownL3;tma_L3_group;tma_memory_bound_group", - "MetricName": "tma_store_bound", - "MetricThreshold": "tma_store_bound > 0.1", - "ScaleUnit": "100%" - }, - { - "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a store forward bloc= k.", - "MetricExpr": "LD_HEAD.ST_ADDR_AT_RET / tma_info_core_clks", - "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", - "MetricName": "tma_store_fwd_blk", - "MetricThreshold": "tma_store_fwd_blk > 0.05", + "MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", "ScaleUnit": "100%" } ] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json b/tools/p= erf/pmu-events/arch/x86/alderlaken/cache.json index 043445ae14a8..1500033ee19f 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/cache.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/cache.json @@ -1,22 +1,25 @@ [ { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= core has access to an L3 cache, the LLC is the L3 cache, otherwise it is t= he L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th= e L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f" }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", "SampleAfterValue": "200003", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", "SampleAfterValue": "200003", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "SampleAfterValue": "200003", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked for any of the following reasons: load buffer, store buffer or RSV fu= ll.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ALL", "SampleAfterValue": "20003", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", "SampleAfterValue": "20003", @@ -119,6 +134,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.RSV", "SampleAfterValue": "20003", @@ -126,6 +142,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", "SampleAfterValue": "20003", @@ -133,6 +150,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -143,6 +161,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 128 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", @@ -165,6 +185,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 16 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", @@ -177,6 +198,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 256 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", @@ -189,6 +211,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 32 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", @@ -201,6 +224,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 4 cycles as define= d in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", @@ -213,6 +237,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 512 cycles as defi= ned in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", @@ -225,6 +250,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 64 cycles as defin= ed in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", @@ -237,6 +263,7 @@ }, { "BriefDescription": "Counts the number of tagged loads with an ins= truction latency that exceeds or equals the threshold of 8 cycles as define= d in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", @@ -247,8 +274,19 @@ "SampleAfterValue": "1000003", "UMask": "0x5" }, + { + "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "Counter": "0,1,2,3,4,5", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", + "PEBS": "1", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -258,6 +296,7 @@ }, { "BriefDescription": "Counts the number of stores uops retired. Cou= nts with or without PEBS enabled.", + "Counter": "0,1,2,3,4,5", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", @@ -268,6 +307,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -277,6 +317,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -286,6 +327,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -295,6 +337,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +347,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -313,6 +357,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -322,6 +367,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json = b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json index 30e8ca3c1485..484d8b3167f0 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json b/tool= s/perf/pmu-events/arch/x86/alderlaken/frontend.json index 36898bab2bba..2a68f9969da0 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of instruction cache misses= .", + "Counter": "0,1,2,3,4,5", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json b/tools/= perf/pmu-events/arch/x86/alderlaken/memory.json index 863a3ba2b4b2..619488d42a4a 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to any number of reasons, incl= uding an L1 miss, WCB full, pagewalk, store address block or store data blo= ck, on a load that retires.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.ANY_AT_RET", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to a core bound stall includin= g a store address match, a DTLB miss or a page walk that detains the load f= rom retiring.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.L1_BOUND_AT_RET", "SampleAfterValue": "1000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.L1_MISS_AT_RET", "SampleAfterValue": "1000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", "PublicDescription": "Counts the number of cycles that the head (o= ldest load) of the load buffer and retirement are both stalled due to other= block cases such as pipeline conflicts, fences, etc.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a page= walk.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.PGWALK_AT_RET", "SampleAfterValue": "1000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a stor= e address match.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.ST_ADDR_AT_RET", "SampleAfterValue": "1000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache. [L3_MISS_LOCAL is alias to L3_MISS]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/metricgroups.json b/= tools/perf/pmu-events/arch/x86/alderlaken/metricgroups.json index 7b2049cd2694..40984c23a6c9 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/metricgroups.json @@ -1,26 +1,23 @@ { + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis = Metrics spreadsheet", + "Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", "Power": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "TopdownL1": "Metrics for top-down breakdown at level 1", "TopdownL2": "Metrics for top-down breakdown at level 2", "TopdownL3": "Metrics for top-down breakdown at level 3", - "TopdownL4": "Metrics for top-down breakdown at level 4", + "load_store_bound": "Grouping from Top-down Microarchitecture Analysis= Metrics spreadsheet", "tma_L1_group": "Metrics for top-down breakdown at level 1", "tma_L2_group": "Metrics for top-down breakdown at level 2", "tma_L3_group": "Metrics for top-down breakdown at level 3", - "tma_L4_group": "Metrics for top-down breakdown at level 4", - "tma_backend_bound_aux_group": "Metrics contributing to tma_backend_bo= und_aux category", "tma_backend_bound_group": "Metrics contributing to tma_backend_bound = category", "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculat= ion category", - "tma_base_group": "Metrics contributing to tma_base category", - "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwi= dth category", - "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency = category", + "tma_core_bound_group": "Metrics contributing to tma_core_bound catego= ry", "tma_frontend_bound_group": "Metrics contributing to tma_frontend_boun= d category", - "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category", + "tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_band= width category", + "tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latenc= y category", "tma_machine_clears_group": "Metrics contributing to tma_machine_clear= s category", - "tma_mem_scheduler_group": "Metrics contributing to tma_mem_scheduler = category", - "tma_memory_bound_group": "Metrics contributing to tma_memory_bound ca= tegory", - "tma_nuke_group": "Metrics contributing to tma_nuke category", - "tma_resource_bound_group": "Metrics contributing to tma_resource_boun= d category", - "tma_retiring_group": "Metrics contributing to tma_retiring category" + "tma_resource_bound_group": "Metrics contributing to tma_resource_boun= d category" } diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/other.json b/tools/p= erf/pmu-events/arch/x86/alderlaken/other.json index ccc892149dbe..54ddbe2b3b9b 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/other.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xe4", "EventName": "LBR_INSERTS.ANY", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -37,11 +41,20 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", "MSRValue": "0x10800", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of issue slots in a UMWAIT = or TPAUSE instruction where no uop issues due to the instruction putting th= e CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will onl= y put the CPU into C0.1 activity state (not C0.2 activity state)", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x75", + "EventName": "SERIALIZATION.C01_MS_SCB", + "SampleAfterValue": "200003", + "UMask": "0x4" } ] diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json b/tool= s/perf/pmu-events/arch/x86/alderlaken/pipeline.json index 846bcdafca6d..f05db45578ff 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.NEAR_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -58,6 +65,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", @@ -67,6 +75,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Counts the number of near taken branch instru= ctions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -100,6 +112,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", @@ -109,6 +122,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -117,6 +131,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.NEAR_RETURN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", @@ -126,6 +141,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.COND_TAKEN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -143,6 +160,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -151,6 +169,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -159,6 +178,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -167,6 +187,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -175,6 +196,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", @@ -184,6 +206,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", @@ -193,6 +216,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near taken = branch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -201,6 +225,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.INDIRECT", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", @@ -210,6 +235,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -218,6 +244,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_MISP_RETIRED.COND_TAKEN", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", @@ -227,6 +254,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -234,6 +262,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", @@ -241,6 +270,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -256,6 +287,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. = This event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -263,6 +295,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. The core frequency may change from time to time. F= or this reason this event may have a changing ratio with regards to time. T= his event uses a programmable general purpose performance counter.", @@ -270,6 +303,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", @@ -278,6 +312,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -286,6 +321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = LD_BLOCKS.ADDRESS_ALIAS", + "Counter": "0,1,2,3,4,5", "Deprecated": "1", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", @@ -295,6 +331,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PEBS": "1", @@ -303,6 +340,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", @@ -311,6 +349,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -318,6 +357,7 @@ }, { "BriefDescription": "Counts the number of machines clears due to m= emory renaming.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MRN_NUKE", "SampleAfterValue": "1000003", @@ -325,6 +365,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -332,6 +373,7 @@ }, { "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine with the use of microcode due to SMC= , MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_= TRAP.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SLOW", "SampleAfterValue": "20003", @@ -339,6 +381,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -346,6 +389,7 @@ }, { "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to LBR_INSE= RTS.ANY]", + "Counter": "0,1,2,3,4,5", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBS": "1", @@ -355,6 +399,7 @@ }, { "BriefDescription": "Counts the number of issue slots not consumed= by the backend due to a micro-sequencer (MS) scoreboard, which stalls the = front-end from issuing from the UROM until a specified older uop retires.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x75", "EventName": "SERIALIZATION.NON_C01_MS_SCB", "PublicDescription": "Counts the number of issue slots not consume= d by the backend due to a micro-sequencer (MS) scoreboard, which stalls the= front-end from issuing from the UROM until a specified older uop retires. = The most commonly executed instruction with an MS scoreboard is PAUSE.", @@ -363,6 +408,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", @@ -370,6 +416,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -377,6 +424,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -384,6 +432,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -391,6 +440,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "SampleAfterValue": "1000003", @@ -398,12 +448,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -411,6 +463,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -418,6 +471,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -425,6 +479,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -432,6 +487,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -439,6 +495,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "Counter": "0,1,2,3,4,5", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -446,12 +503,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", @@ -460,6 +519,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", @@ -468,6 +528,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -475,6 +536,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -482,6 +544,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "SampleAfterValue": "1000003", @@ -489,6 +552,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to a latency related stalls inc= luding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "SampleAfterValue": "1000003", @@ -496,6 +560,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", @@ -504,6 +569,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -511,6 +577,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -518,13 +585,23 @@ }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", "SampleAfterValue": "1000003" }, + { + "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3,4,5", + "EventCode": "0x0e", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", + "SampleAfterValue": "200003" + }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -532,6 +609,7 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", @@ -540,6 +618,7 @@ }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", @@ -549,6 +628,7 @@ }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "Counter": "0,1,2,3,4,5", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json index 8bf020a9dfa8..7c0779c74154 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -9,56 +10,69 @@ }, { "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_DAT_OCCUPANCY.ALL", + "Counter": "0", "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_T= RK_OCCUPANCY.RD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -67,14 +81,17 @@ }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_R= EQ_TRK_OCCUPANCY.DRD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -83,8 +100,10 @@ }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD= ]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json index 163d7e7755c4..bcf275cd592a 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every 64B read request entering the M= emory Controller 0 to DRAM (sum of all channels).", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts every 64B write request entering the M= emory Controller 0 to DRAM (sum of all channels). Each write request counts= as a new request incrementing this counter. However, same cache line write= requests (both full and partial) are combined to a single 64 byte data tra= nsfer to DRAM.", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts every 64B read request entering the Me= mory Controller 1 to DRAM (sum of all channels).", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Counts every 64B write request entering the M= emory Controller 1 to DRAM (sum of all channels). Each write request counts= as a new request incrementing this counter. However, same cache line write= requests (both full and partial) are combined to a single 64 byte data tra= nsfer to DRAM.", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x24", "EventName": "UNC_M_ACT_COUNT_RD", "PerPkg": "1", @@ -42,6 +47,7 @@ }, { "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x26", "EventName": "UNC_M_ACT_COUNT_TOTAL", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x25", "EventName": "UNC_M_ACT_COUNT_WR", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", "PerPkg": "1", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", "PerPkg": "1", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Number of clocks", + "Counter": "0,1,2,3,4", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -77,6 +87,7 @@ }, { "BriefDescription": "incoming read request page status is Page Emp= ty", + "Counter": "0,1,2,3,4", "EventCode": "0x1D", "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD", "PerPkg": "1", @@ -84,6 +95,7 @@ }, { "BriefDescription": "incoming write request page status is Page Em= pty", + "Counter": "0,1,2,3,4", "EventCode": "0x20", "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR", "PerPkg": "1", @@ -91,6 +103,7 @@ }, { "BriefDescription": "incoming read request page status is Page Hit= ", + "Counter": "0,1,2,3,4", "EventCode": "0x1C", "EventName": "UNC_M_DRAM_PAGE_HIT_RD", "PerPkg": "1", @@ -98,6 +111,7 @@ }, { "BriefDescription": "incoming write request page status is Page Hi= t", + "Counter": "0,1,2,3,4", "EventCode": "0x1F", "EventName": "UNC_M_DRAM_PAGE_HIT_WR", "PerPkg": "1", @@ -105,6 +119,7 @@ }, { "BriefDescription": "incoming read request page status is Page Mis= s", + "Counter": "0,1,2,3,4", "EventCode": "0x1E", "EventName": "UNC_M_DRAM_PAGE_MISS_RD", "PerPkg": "1", @@ -112,6 +127,7 @@ }, { "BriefDescription": "incoming write request page status is Page Mi= ss", + "Counter": "0,1,2,3,4", "EventCode": "0x21", "EventName": "UNC_M_DRAM_PAGE_MISS_WR", "PerPkg": "1", @@ -119,6 +135,7 @@ }, { "BriefDescription": "Any Rank at Hot state", + "Counter": "0,1,2,3,4", "EventCode": "0x19", "EventName": "UNC_M_DRAM_THERMAL_HOT", "PerPkg": "1", @@ -126,6 +143,7 @@ }, { "BriefDescription": "Any Rank at Warm state", + "Counter": "0,1,2,3,4", "EventCode": "0x1A", "EventName": "UNC_M_DRAM_THERMAL_WARM", "PerPkg": "1", @@ -133,6 +151,7 @@ }, { "BriefDescription": "Incoming read prefetch request from IA.", + "Counter": "0,1,2,3,4", "EventCode": "0x0A", "EventName": "UNC_M_PREFETCH_RD", "PerPkg": "1", @@ -140,6 +159,7 @@ }, { "BriefDescription": "PRE command sent to DRAM due to page table id= le timer expiration", + "Counter": "0,1,2,3,4", "EventCode": "0x28", "EventName": "UNC_M_PRE_COUNT_IDLE", "PerPkg": "1", @@ -147,6 +167,7 @@ }, { "BriefDescription": "PRE command sent to DRAM for a read/write req= uest", + "Counter": "0,1,2,3,4", "EventCode": "0x27", "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", "PerPkg": "1", @@ -154,6 +175,7 @@ }, { "BriefDescription": "Incoming VC0 read request", + "Counter": "0,1,2,3,4", "EventCode": "0x02", "EventName": "UNC_M_VC0_REQUESTS_RD", "PerPkg": "1", @@ -161,6 +183,7 @@ }, { "BriefDescription": "Incoming VC0 write request", + "Counter": "0,1,2,3,4", "EventCode": "0x03", "EventName": "UNC_M_VC0_REQUESTS_WR", "PerPkg": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Incoming VC1 read request", + "Counter": "0,1,2,3,4", "EventCode": "0x04", "EventName": "UNC_M_VC1_REQUESTS_RD", "PerPkg": "1", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Incoming VC1 write request", + "Counter": "0,1,2,3,4", "EventCode": "0x05", "EventName": "UNC_M_VC1_REQUESTS_WR", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json b/= tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json index 2af92e43b28a..1ac5b5ef8094 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json index 67fd640f790e..ad2b1349bab4 100644 --- a/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/alderlaken/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", "SampleAfterValue": "1000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", + "Counter": "0,1,2,3,4,5", "EventCode": "0x05", "EventName": "LD_HEAD.DTLB_MISS_AT_RET", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index ec40215377f3..519842e52fcb 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -1,6 +1,6 @@ Family-model,Version,Filename,EventType GenuineIntel-6-(97|9A|B7|BA|BF),v1.27,alderlake,core -GenuineIntel-6-BE,v1.24,alderlaken,core +GenuineIntel-6-BE,v1.27,alderlaken,core GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v29,broadwell,core GenuineIntel-6-56,v11,broadwellde,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C291A1AED55 for ; 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Thu, 20 Jun 2024 11:19:18 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:17 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-4-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 03/37] perf vendor events: Add bonnell counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/bonnell/cache.json | 93 +++++++++++++++++++ .../pmu-events/arch/x86/bonnell/counter.json | 7 ++ .../arch/x86/bonnell/floating-point.json | 32 +++++++ .../pmu-events/arch/x86/bonnell/frontend.json | 11 +++ .../pmu-events/arch/x86/bonnell/memory.json | 19 ++++ .../pmu-events/arch/x86/bonnell/other.json | 56 +++++++++++ .../pmu-events/arch/x86/bonnell/pipeline.json | 44 +++++++++ .../arch/x86/bonnell/virtual-memory.json | 15 +++ 8 files changed, 277 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/bonnell/counter.json diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf= /pmu-events/arch/x86/bonnell/cache.json index 1ca95a70d48a..86582bb8aa39 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/cache.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1 Data Cacheable reads and writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ALL_CACHE_REF", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "L1 Data reads and writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ALL_REF", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Modified cache lines evicted from the L1 data= cache", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.EVICT", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1 Cacheable Data Reads", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.LD", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1 Data line replacements", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.REPL", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Modified cache lines allocated in the L1 data= cache", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.REPLM", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1 Cacheable Data Writes", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE.ST", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Cycles L2 address bus is in use.", + "Counter": "0,1", "EventCode": "0x21", "EventName": "L2_ADS.SELF", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.E_STATE", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.I_STATE", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.MESI", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.M_STATE", "SampleAfterValue": "200000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All data requests from the L1 data cache", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "L2_DATA_RQSTS.SELF.S_STATE", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Cycles the L2 cache data bus is busy.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "L2_DBUS_BUSY.SELF", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Cycles the L2 transfers data to the core.", + "Counter": "0,1", "EventCode": "0x23", "EventName": "L2_DBUS_BUSY_RD.SELF", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.MESI", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 cacheable instruction fetch requests", + "Counter": "0,1", "EventCode": "0x28", "EventName": "L2_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 cache reads", + "Counter": "0,1", "EventCode": "0x29", "EventName": "L2_LD.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and dat= a caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.E_STATE", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and dat= a caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.I_STATE", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and dat= a caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.MESI", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and dat= a caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.M_STATE", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "All read requests from L1 instruction and dat= a caches", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "L2_LD_IFETCH.SELF.S_STATE", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.ANY", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.DEMAND", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 cache misses.", + "Counter": "0,1", "EventCode": "0x24", "EventName": "L2_LINES_IN.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 cache lines evicted.", + "Counter": "0,1", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.E_STATE", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.I_STATE", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.MESI", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.M_STATE", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 locked accesses", + "Counter": "0,1", "EventCode": "0x2B", "EventName": "L2_LOCK.SELF.S_STATE", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L2 cache line modifications.", + "Counter": "0,1", "EventCode": "0x25", "EventName": "L2_M_LINES_IN.SELF", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.ANY", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.DEMAND", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "Modified lines evicted from the L2 cache", + "Counter": "0,1", "EventCode": "0x27", "EventName": "L2_M_LINES_OUT.SELF.PREFETCH", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "Cycles no L2 cache requests are pending", + "Counter": "0,1", "EventCode": "0x32", "EventName": "L2_NO_REQ.SELF", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -491,6 +561,7 @@ }, { "BriefDescription": "Rejected L2 cache requests", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -498,6 +569,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.E_STATE", "SampleAfterValue": "200000", @@ -505,6 +577,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.I_STATE", "SampleAfterValue": "200000", @@ -512,6 +585,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.MESI", "SampleAfterValue": "200000", @@ -519,6 +593,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.M_STATE", "SampleAfterValue": "200000", @@ -526,6 +601,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.ANY.S_STATE", "SampleAfterValue": "200000", @@ -533,6 +609,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -540,6 +617,7 @@ }, { "BriefDescription": "L2 cache demand requests from this core that = missed the L2", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -547,6 +625,7 @@ }, { "BriefDescription": "L2 cache demand requests from this core", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.MESI", "SampleAfterValue": "200000", @@ -554,6 +633,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -561,6 +641,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -568,6 +649,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -575,6 +657,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -582,6 +665,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -589,6 +673,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -596,6 +681,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -603,6 +689,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.E_STATE", "SampleAfterValue": "200000", @@ -610,6 +697,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.I_STATE", "SampleAfterValue": "200000", @@ -617,6 +705,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.MESI", "SampleAfterValue": "200000", @@ -624,6 +713,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.M_STATE", "SampleAfterValue": "200000", @@ -631,6 +721,7 @@ }, { "BriefDescription": "L2 store requests", + "Counter": "0,1", "EventCode": "0x2A", "EventName": "L2_ST.SELF.S_STATE", "SampleAfterValue": "200000", @@ -638,6 +729,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (precise = event).", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "SampleAfterValue": "200000", @@ -645,6 +737,7 @@ }, { "BriefDescription": "Retired loads that miss the L2 cache", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_MISS", "SampleAfterValue": "10000", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/counter.json b/tools/pe= rf/pmu-events/arch/x86/bonnell/counter.json new file mode 100644 index 000000000000..eb89b55f31bd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/bonnell/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/bonnell/floating-point.json index 18bf5ec47e72..d1bd5be95a15 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Floating point assists for retired operations= .", + "Counter": "0,1", "EventCode": "0x11", "EventName": "FP_ASSIST.AR", "SampleAfterValue": "10000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Floating point assists.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "FP_ASSIST.S", "SampleAfterValue": "10000", @@ -15,12 +17,14 @@ }, { "BriefDescription": "SIMD assists invoked.", + "Counter": "0,1", "EventCode": "0xCD", "EventName": "SIMD_ASSIST", "SampleAfterValue": "100000" }, { "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) packed-single instructions.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE", "SampleAfterValue": "2000000", @@ -28,6 +32,7 @@ }, { "BriefDescription": "Retired computational Streaming SIMD Extensio= ns 2 (SSE2) scalar-double instructions.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE", "SampleAfterValue": "2000000", @@ -35,6 +40,7 @@ }, { "BriefDescription": "Retired computational Streaming SIMD Extensio= ns (SSE) scalar-single instructions.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000000", @@ -42,12 +48,14 @@ }, { "BriefDescription": "SIMD Instructions retired.", + "Counter": "0,1", "EventCode": "0xCE", "EventName": "SIMD_INSTR_RETIRED", "SampleAfterValue": "2000000" }, { "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packe= d-single instructions.", + "Counter": "0,1", "EventCode": "0xC7", "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE", "SampleAfterValue": "2000000", @@ -55,6 +63,7 @@ }, { "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) sc= alar-double instructions.", + "Counter": "0,1", "EventCode": "0xC7", "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE", "SampleAfterValue": "2000000", @@ -62,6 +71,7 @@ }, { "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scala= r-single instructions.", + "Counter": "0,1", "EventCode": "0xC7", "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE", "SampleAfterValue": "2000000", @@ -69,6 +79,7 @@ }, { "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) ve= ctor instructions.", + "Counter": "0,1", "EventCode": "0xC7", "EventName": "SIMD_INST_RETIRED.VECTOR", "SampleAfterValue": "2000000", @@ -76,12 +87,14 @@ }, { "BriefDescription": "Saturated arithmetic instructions retired.", + "Counter": "0,1", "EventCode": "0xCF", "EventName": "SIMD_SAT_INSTR_RETIRED", "SampleAfterValue": "2000000" }, { "BriefDescription": "SIMD saturated arithmetic micro-ops retired.", + "Counter": "0,1", "EventCode": "0xB1", "EventName": "SIMD_SAT_UOP_EXEC.AR", "SampleAfterValue": "2000000", @@ -89,12 +102,14 @@ }, { "BriefDescription": "SIMD saturated arithmetic micro-ops executed.= ", + "Counter": "0,1", "EventCode": "0xB1", "EventName": "SIMD_SAT_UOP_EXEC.S", "SampleAfterValue": "2000000" }, { "BriefDescription": "SIMD micro-ops retired (excluding stores).", + "Counter": "0,1", "EventCode": "0xB0", "EventName": "SIMD_UOPS_EXEC.AR", "PEBS": "2", @@ -103,12 +118,14 @@ }, { "BriefDescription": "SIMD micro-ops executed (excluding stores).", + "Counter": "0,1", "EventCode": "0xB0", "EventName": "SIMD_UOPS_EXEC.S", "SampleAfterValue": "2000000" }, { "BriefDescription": "SIMD packed arithmetic micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR", "SampleAfterValue": "2000000", @@ -116,6 +133,7 @@ }, { "BriefDescription": "SIMD packed arithmetic micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S", "SampleAfterValue": "2000000", @@ -123,6 +141,7 @@ }, { "BriefDescription": "SIMD packed logical micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR", "SampleAfterValue": "2000000", @@ -130,6 +149,7 @@ }, { "BriefDescription": "SIMD packed logical micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S", "SampleAfterValue": "2000000", @@ -137,6 +157,7 @@ }, { "BriefDescription": "SIMD packed multiply micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR", "SampleAfterValue": "2000000", @@ -144,6 +165,7 @@ }, { "BriefDescription": "SIMD packed multiply micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S", "SampleAfterValue": "2000000", @@ -151,6 +173,7 @@ }, { "BriefDescription": "SIMD packed micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR", "SampleAfterValue": "2000000", @@ -158,6 +181,7 @@ }, { "BriefDescription": "SIMD packed micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S", "SampleAfterValue": "2000000", @@ -165,6 +189,7 @@ }, { "BriefDescription": "SIMD packed shift micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR", "SampleAfterValue": "2000000", @@ -172,6 +197,7 @@ }, { "BriefDescription": "SIMD packed shift micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S", "SampleAfterValue": "2000000", @@ -179,6 +205,7 @@ }, { "BriefDescription": "SIMD unpacked micro-ops retired", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR", "SampleAfterValue": "2000000", @@ -186,6 +213,7 @@ }, { "BriefDescription": "SIMD unpacked micro-ops executed", + "Counter": "0,1", "EventCode": "0xB3", "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S", "SampleAfterValue": "2000000", @@ -193,6 +221,7 @@ }, { "BriefDescription": "Floating point computational micro-ops retire= d.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "X87_COMP_OPS_EXE.ANY.AR", "PEBS": "2", @@ -201,6 +230,7 @@ }, { "BriefDescription": "Floating point computational micro-ops execut= ed.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "X87_COMP_OPS_EXE.ANY.S", "SampleAfterValue": "2000000", @@ -208,6 +238,7 @@ }, { "BriefDescription": "FXCH uops retired.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "X87_COMP_OPS_EXE.FXCH.AR", "PEBS": "2", @@ -216,6 +247,7 @@ }, { "BriefDescription": "FXCH uops executed.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "X87_COMP_OPS_EXE.FXCH.S", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/p= erf/pmu-events/arch/x86/bonnell/frontend.json index 42284c02c11d..7657fd6d3a11 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "BACLEARS asserted.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles during which instruction fetches are = stalled.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Decode stall due to IQ full", + "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Decode stall due to PFB empty", + "Counter": "0,1", "EventCode": "0x87", "EventName": "DECODE_STALL.PFB_EMPTY", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Instruction fetches.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Icache hit", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Icache miss", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "All Instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.ALL_DECODED", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "CISC macro instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.CISC_DECODED", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Non-CISC macro instructions decoded", + "Counter": "0,1", "EventCode": "0xAA", "EventName": "MACRO_INSTS.NON_CISC_DECODED", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "This event counts the cycles where 1 or more = uops are issued by the micro-sequencer (MS), including microcode assists an= d inserted flows, and written to the IQ.", + "Counter": "0,1", "CounterMask": "1", "EventCode": "0xA9", "EventName": "UOPS.MS_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/per= f/pmu-events/arch/x86/bonnell/memory.json index ac02dc2482c8..f8b45b6fb4d3 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Nonzero segbase 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.BUBBLE", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Nonzero segbase load 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_BUBBLE", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Load splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_SPLIT", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Load splits (At Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Nonzero segbase ld-op-st 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "ld-op-st splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.RMW_SPLIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Memory references that cross an 8-byte bounda= ry.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.SPLIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Memory references that cross an 8-byte bounda= ry (At Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.SPLIT.AR", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "Nonzero segbase store 1 bubble", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_BUBBLE", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Store splits", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_SPLIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Store splits (Ar Retirement)", + "Counter": "0,1", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 hardware prefetch request", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.HW_PREFETCH", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA = instructions executed", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHNTA", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 in= structions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT0", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 in= structions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT1", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 in= structions executed.", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.PREFETCHT2", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Any Software prefetch", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Any Software prefetch", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 an= d PrefetchT2 instructions executed", + "Counter": "0,1", "EventCode": "0x7", "EventName": "PREFETCH.SW_L2", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf= /pmu-events/arch/x86/bonnell/other.json index 782594c8bda5..3a55c101fbf7 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/other.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Bus queue is empty.", + "Counter": "0,1", "EventCode": "0x7D", "EventName": "BUSQ_EMPTY.SELF", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Number of Bus Not Ready signals asserted.", + "Counter": "0,1", "EventCode": "0x61", "EventName": "BUS_BNR_DRV.ALL_AGENTS", "SampleAfterValue": "200000", @@ -15,12 +17,14 @@ }, { "BriefDescription": "Number of Bus Not Ready signals asserted.", + "Counter": "0,1", "EventCode": "0x61", "EventName": "BUS_BNR_DRV.THIS_AGENT", "SampleAfterValue": "200000" }, { "BriefDescription": "Bus cycles while processor receives data.", + "Counter": "0,1", "EventCode": "0x64", "EventName": "BUS_DATA_RCV.SELF", "SampleAfterValue": "200000", @@ -28,6 +32,7 @@ }, { "BriefDescription": "Bus cycles when data is sent on the bus.", + "Counter": "0,1", "EventCode": "0x62", "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS", "SampleAfterValue": "200000", @@ -35,12 +40,14 @@ }, { "BriefDescription": "Bus cycles when data is sent on the bus.", + "Counter": "0,1", "EventCode": "0x62", "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT", "SampleAfterValue": "200000" }, { "BriefDescription": "HITM signal asserted.", + "Counter": "0,1", "EventCode": "0x7B", "EventName": "BUS_HITM_DRV.ALL_AGENTS", "SampleAfterValue": "200000", @@ -48,12 +55,14 @@ }, { "BriefDescription": "HITM signal asserted.", + "Counter": "0,1", "EventCode": "0x7B", "EventName": "BUS_HITM_DRV.THIS_AGENT", "SampleAfterValue": "200000" }, { "BriefDescription": "HIT signal asserted.", + "Counter": "0,1", "EventCode": "0x7A", "EventName": "BUS_HIT_DRV.ALL_AGENTS", "SampleAfterValue": "200000", @@ -61,12 +70,14 @@ }, { "BriefDescription": "HIT signal asserted.", + "Counter": "0,1", "EventCode": "0x7A", "EventName": "BUS_HIT_DRV.THIS_AGENT", "SampleAfterValue": "200000" }, { "BriefDescription": "IO requests waiting in the bus queue.", + "Counter": "0,1", "EventCode": "0x7F", "EventName": "BUS_IO_WAIT.SELF", "SampleAfterValue": "200000", @@ -74,6 +85,7 @@ }, { "BriefDescription": "Bus cycles when a LOCK signal is asserted.", + "Counter": "0,1", "EventCode": "0x63", "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS", "SampleAfterValue": "200000", @@ -81,6 +93,7 @@ }, { "BriefDescription": "Bus cycles when a LOCK signal is asserted.", + "Counter": "0,1", "EventCode": "0x63", "EventName": "BUS_LOCK_CLOCKS.SELF", "SampleAfterValue": "200000", @@ -88,6 +101,7 @@ }, { "BriefDescription": "Outstanding cacheable data read bus requests = duration.", + "Counter": "0,1", "EventCode": "0x60", "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS", "SampleAfterValue": "200000", @@ -95,6 +109,7 @@ }, { "BriefDescription": "Outstanding cacheable data read bus requests = duration.", + "Counter": "0,1", "EventCode": "0x60", "EventName": "BUS_REQUEST_OUTSTANDING.SELF", "SampleAfterValue": "200000", @@ -102,6 +117,7 @@ }, { "BriefDescription": "All bus transactions.", + "Counter": "0,1", "EventCode": "0x70", "EventName": "BUS_TRANS_ANY.ALL_AGENTS", "SampleAfterValue": "200000", @@ -109,6 +125,7 @@ }, { "BriefDescription": "All bus transactions.", + "Counter": "0,1", "EventCode": "0x70", "EventName": "BUS_TRANS_ANY.SELF", "SampleAfterValue": "200000", @@ -116,6 +133,7 @@ }, { "BriefDescription": "Burst read bus transactions.", + "Counter": "0,1", "EventCode": "0x65", "EventName": "BUS_TRANS_BRD.ALL_AGENTS", "SampleAfterValue": "200000", @@ -123,6 +141,7 @@ }, { "BriefDescription": "Burst read bus transactions.", + "Counter": "0,1", "EventCode": "0x65", "EventName": "BUS_TRANS_BRD.SELF", "SampleAfterValue": "200000", @@ -130,6 +149,7 @@ }, { "BriefDescription": "Burst (full cache-line) bus transactions.", + "Counter": "0,1", "EventCode": "0x6E", "EventName": "BUS_TRANS_BURST.ALL_AGENTS", "SampleAfterValue": "200000", @@ -137,6 +157,7 @@ }, { "BriefDescription": "Burst (full cache-line) bus transactions.", + "Counter": "0,1", "EventCode": "0x6E", "EventName": "BUS_TRANS_BURST.SELF", "SampleAfterValue": "200000", @@ -144,6 +165,7 @@ }, { "BriefDescription": "Deferred bus transactions.", + "Counter": "0,1", "EventCode": "0x6D", "EventName": "BUS_TRANS_DEF.ALL_AGENTS", "SampleAfterValue": "200000", @@ -151,6 +173,7 @@ }, { "BriefDescription": "Deferred bus transactions.", + "Counter": "0,1", "EventCode": "0x6D", "EventName": "BUS_TRANS_DEF.SELF", "SampleAfterValue": "200000", @@ -158,6 +181,7 @@ }, { "BriefDescription": "Instruction-fetch bus transactions.", + "Counter": "0,1", "EventCode": "0x68", "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS", "SampleAfterValue": "200000", @@ -165,6 +189,7 @@ }, { "BriefDescription": "Instruction-fetch bus transactions.", + "Counter": "0,1", "EventCode": "0x68", "EventName": "BUS_TRANS_IFETCH.SELF", "SampleAfterValue": "200000", @@ -172,6 +197,7 @@ }, { "BriefDescription": "Invalidate bus transactions.", + "Counter": "0,1", "EventCode": "0x69", "EventName": "BUS_TRANS_INVAL.ALL_AGENTS", "SampleAfterValue": "200000", @@ -179,6 +205,7 @@ }, { "BriefDescription": "Invalidate bus transactions.", + "Counter": "0,1", "EventCode": "0x69", "EventName": "BUS_TRANS_INVAL.SELF", "SampleAfterValue": "200000", @@ -186,6 +213,7 @@ }, { "BriefDescription": "IO bus transactions.", + "Counter": "0,1", "EventCode": "0x6C", "EventName": "BUS_TRANS_IO.ALL_AGENTS", "SampleAfterValue": "200000", @@ -193,6 +221,7 @@ }, { "BriefDescription": "IO bus transactions.", + "Counter": "0,1", "EventCode": "0x6C", "EventName": "BUS_TRANS_IO.SELF", "SampleAfterValue": "200000", @@ -200,6 +229,7 @@ }, { "BriefDescription": "Memory bus transactions.", + "Counter": "0,1", "EventCode": "0x6F", "EventName": "BUS_TRANS_MEM.ALL_AGENTS", "SampleAfterValue": "200000", @@ -207,6 +237,7 @@ }, { "BriefDescription": "Memory bus transactions.", + "Counter": "0,1", "EventCode": "0x6F", "EventName": "BUS_TRANS_MEM.SELF", "SampleAfterValue": "200000", @@ -214,6 +245,7 @@ }, { "BriefDescription": "Partial bus transactions.", + "Counter": "0,1", "EventCode": "0x6B", "EventName": "BUS_TRANS_P.ALL_AGENTS", "SampleAfterValue": "200000", @@ -221,6 +253,7 @@ }, { "BriefDescription": "Partial bus transactions.", + "Counter": "0,1", "EventCode": "0x6B", "EventName": "BUS_TRANS_P.SELF", "SampleAfterValue": "200000", @@ -228,6 +261,7 @@ }, { "BriefDescription": "Partial write bus transaction.", + "Counter": "0,1", "EventCode": "0x6A", "EventName": "BUS_TRANS_PWR.ALL_AGENTS", "SampleAfterValue": "200000", @@ -235,6 +269,7 @@ }, { "BriefDescription": "Partial write bus transaction.", + "Counter": "0,1", "EventCode": "0x6A", "EventName": "BUS_TRANS_PWR.SELF", "SampleAfterValue": "200000", @@ -242,6 +277,7 @@ }, { "BriefDescription": "RFO bus transactions.", + "Counter": "0,1", "EventCode": "0x66", "EventName": "BUS_TRANS_RFO.ALL_AGENTS", "SampleAfterValue": "200000", @@ -249,6 +285,7 @@ }, { "BriefDescription": "RFO bus transactions.", + "Counter": "0,1", "EventCode": "0x66", "EventName": "BUS_TRANS_RFO.SELF", "SampleAfterValue": "200000", @@ -256,6 +293,7 @@ }, { "BriefDescription": "Explicit writeback bus transactions.", + "Counter": "0,1", "EventCode": "0x67", "EventName": "BUS_TRANS_WB.ALL_AGENTS", "SampleAfterValue": "200000", @@ -263,6 +301,7 @@ }, { "BriefDescription": "Explicit writeback bus transactions.", + "Counter": "0,1", "EventCode": "0x67", "EventName": "BUS_TRANS_WB.SELF", "SampleAfterValue": "200000", @@ -270,6 +309,7 @@ }, { "BriefDescription": "Cycles during which interrupts are disabled.", + "Counter": "0,1", "EventCode": "0xC6", "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED", "SampleAfterValue": "2000000", @@ -277,6 +317,7 @@ }, { "BriefDescription": "Cycles during which interrupts are pending an= d disabled.", + "Counter": "0,1", "EventCode": "0xC6", "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED", "SampleAfterValue": "2000000", @@ -284,6 +325,7 @@ }, { "BriefDescription": "Memory cluster signals to block micro-op disp= atch for any reason", + "Counter": "0,1", "EventCode": "0x9", "EventName": "DISPATCH_BLOCKED.ANY", "SampleAfterValue": "200000", @@ -291,12 +333,14 @@ }, { "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technol= ogy (EIST) transitions", + "Counter": "0,1", "EventCode": "0x3A", "EventName": "EIST_TRANS", "SampleAfterValue": "200000" }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.ALL_AGENTS.ANY", "SampleAfterValue": "200000", @@ -304,6 +348,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN", "SampleAfterValue": "200000", @@ -311,6 +356,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.ALL_AGENTS.HIT", "SampleAfterValue": "200000", @@ -318,6 +364,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.ALL_AGENTS.HITM", "SampleAfterValue": "200000", @@ -325,6 +372,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.THIS_AGENT.ANY", "SampleAfterValue": "200000", @@ -332,6 +380,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN", "SampleAfterValue": "200000", @@ -339,6 +388,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.THIS_AGENT.HIT", "SampleAfterValue": "200000", @@ -346,6 +396,7 @@ }, { "BriefDescription": "External snoops.", + "Counter": "0,1", "EventCode": "0x77", "EventName": "EXT_SNOOP.THIS_AGENT.HITM", "SampleAfterValue": "200000", @@ -353,12 +404,14 @@ }, { "BriefDescription": "Hardware interrupts received.", + "Counter": "0,1", "EventCode": "0xC8", "EventName": "HW_INT_RCV", "SampleAfterValue": "200000" }, { "BriefDescription": "Number of segment register loads.", + "Counter": "0,1", "EventCode": "0x6", "EventName": "SEGMENT_REG_LOADS.ANY", "SampleAfterValue": "200000", @@ -366,6 +419,7 @@ }, { "BriefDescription": "Bus stalled for snoops.", + "Counter": "0,1", "EventCode": "0x7E", "EventName": "SNOOP_STALL_DRV.ALL_AGENTS", "SampleAfterValue": "200000", @@ -373,6 +427,7 @@ }, { "BriefDescription": "Bus stalled for snoops.", + "Counter": "0,1", "EventCode": "0x7E", "EventName": "SNOOP_STALL_DRV.SELF", "SampleAfterValue": "200000", @@ -380,6 +435,7 @@ }, { "BriefDescription": "Number of thermal trips", + "Counter": "0,1", "EventCode": "0x3B", "EventName": "THERMAL_TRIP", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/bonnell/pipeline.json index 91b98ee8ba9a..9ff032ab11e2 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Bogus branches", + "Counter": "0,1", "EventCode": "0xE4", "EventName": "BOGUS_BR", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -15,12 +17,14 @@ }, { "BriefDescription": "Retired branch instructions.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Retired branch instructions.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ANY1", "SampleAfterValue": "2000000", @@ -28,6 +32,7 @@ }, { "BriefDescription": "Retired mispredicted branch instructions (pre= cise event).", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_INST_RETIRED.MISPRED", "PEBS": "1", @@ -35,6 +40,7 @@ }, { "BriefDescription": "Retired branch instructions that were mispred= icted not-taken.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN", "SampleAfterValue": "200000", @@ -42,6 +48,7 @@ }, { "BriefDescription": "Retired branch instructions that were mispred= icted taken.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.MISPRED_TAKEN", "SampleAfterValue": "200000", @@ -49,6 +56,7 @@ }, { "BriefDescription": "Retired branch instructions that were predict= ed not-taken.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN", "SampleAfterValue": "2000000", @@ -56,6 +64,7 @@ }, { "BriefDescription": "Retired branch instructions that were predict= ed taken.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.PRED_TAKEN", "SampleAfterValue": "2000000", @@ -63,6 +72,7 @@ }, { "BriefDescription": "Retired taken branch instructions.", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN", "SampleAfterValue": "2000000", @@ -70,6 +80,7 @@ }, { "BriefDescription": "All macro conditional branch instructions.", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.COND", "SampleAfterValue": "2000000", @@ -77,6 +88,7 @@ }, { "BriefDescription": "Only taken macro conditional branch instructi= ons", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN", "SampleAfterValue": "2000000", @@ -84,6 +96,7 @@ }, { "BriefDescription": "All non-indirect calls", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL", "SampleAfterValue": "2000000", @@ -91,6 +104,7 @@ }, { "BriefDescription": "All indirect branches that are not calls.", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.IND", "SampleAfterValue": "2000000", @@ -98,6 +112,7 @@ }, { "BriefDescription": "All indirect calls, including both register a= nd memory indirect.", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.IND_CALL", "SampleAfterValue": "2000000", @@ -105,6 +120,7 @@ }, { "BriefDescription": "All indirect branches that have a return mnem= onic", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.RET", "SampleAfterValue": "2000000", @@ -112,6 +128,7 @@ }, { "BriefDescription": "All macro unconditional branch instructions, = excluding calls and indirects", + "Counter": "0,1", "EventCode": "0x88", "EventName": "BR_INST_TYPE_RETIRED.UNCOND", "SampleAfterValue": "2000000", @@ -119,6 +136,7 @@ }, { "BriefDescription": "Mispredicted cond branch instructions retired= ", + "Counter": "0,1", "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.COND", "SampleAfterValue": "200000", @@ -126,6 +144,7 @@ }, { "BriefDescription": "Mispredicted and taken cond branch instructio= ns retired", + "Counter": "0,1", "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN", "SampleAfterValue": "200000", @@ -133,6 +152,7 @@ }, { "BriefDescription": "Mispredicted ind branches that are not calls", + "Counter": "0,1", "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.IND", "SampleAfterValue": "200000", @@ -140,6 +160,7 @@ }, { "BriefDescription": "Mispredicted indirect calls, including both r= egister and memory indirect.", + "Counter": "0,1", "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL", "SampleAfterValue": "200000", @@ -147,6 +168,7 @@ }, { "BriefDescription": "Mispredicted return branches", + "Counter": "0,1", "EventCode": "0x89", "EventName": "BR_MISSP_TYPE_RETIRED.RETURN", "SampleAfterValue": "200000", @@ -154,6 +176,7 @@ }, { "BriefDescription": "Bus cycles when core is not halted", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.BUS", "SampleAfterValue": "200000", @@ -161,24 +184,28 @@ }, { "BriefDescription": "Core cycles when core is not halted", + "Counter": "Fixed counter 2", "EventCode": "0xA", "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000000" }, { "BriefDescription": "Core cycles when core is not halted", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference cycles when core is not halted.", + "Counter": "Fixed counter 3", "EventCode": "0xA", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles the divider is busy.", + "Counter": "0,1", "EventCode": "0x14", "EventName": "CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -186,6 +213,7 @@ }, { "BriefDescription": "Divide operations retired", + "Counter": "0,1", "EventCode": "0x13", "EventName": "DIV.AR", "SampleAfterValue": "2000000", @@ -193,6 +221,7 @@ }, { "BriefDescription": "Divide operations executed.", + "Counter": "0,1", "EventCode": "0x13", "EventName": "DIV.S", "SampleAfterValue": "2000000", @@ -200,12 +229,14 @@ }, { "BriefDescription": "Instructions retired.", + "Counter": "Fixed counter 1", "EventCode": "0xA", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (precise event).", + "Counter": "0,1", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", @@ -213,6 +244,7 @@ }, { "BriefDescription": "Self-Modifying Code detected.", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "200000", @@ -220,6 +252,7 @@ }, { "BriefDescription": "Multiply operations retired", + "Counter": "0,1", "EventCode": "0x12", "EventName": "MUL.AR", "SampleAfterValue": "2000000", @@ -227,6 +260,7 @@ }, { "BriefDescription": "Multiply operations executed.", + "Counter": "0,1", "EventCode": "0x12", "EventName": "MUL.S", "SampleAfterValue": "2000000", @@ -234,6 +268,7 @@ }, { "BriefDescription": "Micro-op reissues for any cause", + "Counter": "0,1", "EventCode": "0x3", "EventName": "REISSUE.ANY", "SampleAfterValue": "200000", @@ -241,6 +276,7 @@ }, { "BriefDescription": "Micro-op reissues for any cause (At Retiremen= t)", + "Counter": "0,1", "EventCode": "0x3", "EventName": "REISSUE.ANY.AR", "SampleAfterValue": "200000", @@ -248,6 +284,7 @@ }, { "BriefDescription": "Micro-op reissues on a store-load collision", + "Counter": "0,1", "EventCode": "0x3", "EventName": "REISSUE.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -255,6 +292,7 @@ }, { "BriefDescription": "Micro-op reissues on a store-load collision (= At Retirement)", + "Counter": "0,1", "EventCode": "0x3", "EventName": "REISSUE.OVERLAP_STORE.AR", "SampleAfterValue": "200000", @@ -262,6 +300,7 @@ }, { "BriefDescription": "Cycles issue is stalled due to div busy.", + "Counter": "0,1", "EventCode": "0xDC", "EventName": "RESOURCE_STALLS.DIV_BUSY", "SampleAfterValue": "2000000", @@ -269,6 +308,7 @@ }, { "BriefDescription": "All store forwards", + "Counter": "0,1", "EventCode": "0x2", "EventName": "STORE_FORWARDS.ANY", "SampleAfterValue": "200000", @@ -276,6 +316,7 @@ }, { "BriefDescription": "Good store forwards", + "Counter": "0,1", "EventCode": "0x2", "EventName": "STORE_FORWARDS.GOOD", "SampleAfterValue": "200000", @@ -283,6 +324,7 @@ }, { "BriefDescription": "Micro-ops retired.", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "SampleAfterValue": "2000000", @@ -290,6 +332,7 @@ }, { "BriefDescription": "Cycles no micro-ops retired.", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALLED_CYCLES", "SampleAfterValue": "2000000", @@ -297,6 +340,7 @@ }, { "BriefDescription": "Periods no micro-ops retired.", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALLS", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json index 82e07c73cff0..e8512c585572 100644 --- a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Memory accesses that missed the DTLB.", + "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB misses due to load operations.", + "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB misses due to store operations.", + "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L0 DTLB misses due to load operations.", + "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L0 DTLB misses due to store operations", + "Counter": "0,1", "EventCode": "0x8", "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "ITLB flushes.", + "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.FLUSH", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "ITLB hits.", + "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "ITLB misses.", + "Counter": "0,1", "EventCode": "0x82", "EventName": "ITLB.MISSES", "PEBS": "2", @@ -58,6 +66,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (precise eve= nt).", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -66,6 +75,7 @@ }, { "BriefDescription": "Duration of page-walks in core cycles", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.CYCLES", "SampleAfterValue": "2000000", @@ -73,6 +83,7 @@ }, { "BriefDescription": "Duration of D-side only page walks", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "2000000", @@ -80,6 +91,7 @@ }, { "BriefDescription": "Number of D-side only page walks", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.D_SIDE_WALKS", "SampleAfterValue": "200000", @@ -87,6 +99,7 @@ }, { "BriefDescription": "Duration of I-Side page walks", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "SampleAfterValue": "2000000", @@ -94,6 +107,7 @@ }, { "BriefDescription": "Number of I-Side page walks", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.I_SIDE_WALKS", "SampleAfterValue": "200000", @@ -101,6 +115,7 @@ }, { "BriefDescription": "Number of page-walks executed.", + "Counter": "0,1", "EventCode": "0xC", "EventName": "PAGE_WALKS.WALKS", "SampleAfterValue": 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11:19:21 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:18 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-5-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 04/37] perf vendor events: Update broadwell metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/broadwell/bdw-metrics.json | 80 ++--- .../pmu-events/arch/x86/broadwell/cache.json | 275 ++++++++++++++++++ .../arch/x86/broadwell/counter.json | 22 ++ .../arch/x86/broadwell/floating-point.json | 22 ++ .../arch/x86/broadwell/frontend.json | 28 ++ .../pmu-events/arch/x86/broadwell/memory.json | 240 +++++++++++++++ .../arch/x86/broadwell/metricgroups.json | 11 + .../pmu-events/arch/x86/broadwell/other.json | 4 + .../arch/x86/broadwell/pipeline.json | 137 +++++++++ .../arch/x86/broadwell/uncore-cache.json | 24 ++ .../x86/broadwell/uncore-interconnect.json | 7 + .../arch/x86/broadwell/uncore-other.json | 10 - .../arch/x86/broadwell/virtual-memory.json | 38 +++ 13 files changed, 851 insertions(+), 47 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwell/counter.json delete mode 100644 tools/perf/pmu-events/arch/x86/broadwell/uncore-other.j= son diff --git a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json b/to= ols/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json index c20833fb1f58..af620553f958 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/bdw-metrics.json @@ -90,7 +90,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -100,7 +100,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -121,7 +121,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -160,7 +160,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 = + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_= UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS= _L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LO= AD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS *= (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_L= OAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_= UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + ME= M_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -181,7 +181,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + = MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UO= PS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L= 3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD= _UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -190,7 +190,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -227,7 +227,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISS= ES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tm= a_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -236,7 +236,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MI= SSES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) /= tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -245,7 +245,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM = / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -255,7 +255,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -292,7 +292,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -301,7 +301,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -329,7 +329,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -349,7 +349,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -388,7 +388,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0x3c@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -428,7 +428,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0x3c@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -502,12 +502,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -528,7 +528,7 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -540,7 +540,7 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -576,7 +576,13 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -628,7 +634,7 @@ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cm= ask\\=3D1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" @@ -647,13 +653,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -748,7 +754,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -757,7 +763,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_D= URATION\\,cmask\\=3D1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_= clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -775,7 +781,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.ST= ALLS_L2_MISS) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -795,7 +801,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_= UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRE= D.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RET= IRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RET= IRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -844,7 +850,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -854,7 +860,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -863,7 +869,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -892,7 +898,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers = / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Related metrics: tma_branch_mispredicts, tma_info_bad= _spec_branch_misprediction_cost", @@ -1028,7 +1034,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1036,7 +1042,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1065,7 +1071,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -1093,7 +1099,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1110,7 +1116,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tm= a_clears_resteers", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/cache.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/cache.json index f8ee5aefccea..063ec8c2b2a1 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", @@ -67,6 +75,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", @@ -75,6 +84,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -90,6 +101,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "This event counts the total number of L2 cod= e requests.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "SampleAfterValue": "200003", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "SampleAfterValue": "200003", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", @@ -136,6 +153,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -143,6 +161,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", @@ -158,6 +178,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", @@ -166,6 +187,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200003", @@ -189,6 +213,7 @@ }, { "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003", @@ -196,6 +221,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -203,6 +229,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -210,6 +237,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", @@ -218,6 +246,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", @@ -226,6 +255,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", @@ -234,6 +264,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", @@ -242,6 +273,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", @@ -250,6 +282,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", @@ -258,6 +291,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", @@ -266,6 +300,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", @@ -274,6 +309,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", @@ -282,6 +318,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", @@ -290,6 +327,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", @@ -298,6 +336,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -309,6 +348,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -320,6 +360,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -331,6 +372,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -342,6 +384,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70, BDM100", "EventCode": "0xD3", @@ -353,6 +396,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", @@ -363,6 +407,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -373,6 +418,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -383,6 +429,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD1", @@ -394,6 +441,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -404,6 +452,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD1", @@ -415,6 +464,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100, BDE70", "EventCode": "0xD1", @@ -425,6 +475,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -435,6 +486,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -445,6 +497,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD0", @@ -456,6 +509,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -466,6 +520,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -476,6 +531,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", @@ -486,6 +542,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", @@ -496,6 +553,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", @@ -504,6 +562,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", @@ -512,6 +571,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", @@ -520,6 +580,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", @@ -528,6 +589,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", @@ -536,6 +598,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", @@ -544,6 +607,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -553,6 +617,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -563,6 +628,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -573,6 +639,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -583,6 +650,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -592,6 +660,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -601,6 +670,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "BDM76", "EventCode": "0x60", @@ -610,6 +680,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -619,6 +690,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -626,6 +698,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads have = any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -635,6 +708,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -644,6 +718,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -653,6 +728,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -662,6 +738,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -671,6 +748,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -680,6 +758,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -689,6 +768,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP= ", "MSRIndex": "0x1a6,0x1a7", @@ -698,6 +778,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= M", "MSRIndex": "0x1a6,0x1a7", @@ -707,6 +788,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_HIT= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -716,6 +798,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", @@ -725,6 +808,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +818,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NOT= _NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -743,6 +828,7 @@ }, { "BriefDescription": "Counts all prefetch code reads have any respo= nse type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -752,6 +838,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -761,6 +848,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -770,6 +858,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -779,6 +868,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -788,6 +878,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -797,6 +888,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -806,6 +898,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -815,6 +908,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +918,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -833,6 +928,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -842,6 +938,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -851,6 +948,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -860,6 +958,7 @@ }, { "BriefDescription": "Counts all prefetch data reads have any respo= nse type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +968,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +978,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +988,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +998,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1008,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1018,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1028,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1038,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1048,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1058,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1068,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1078,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1088,7 @@ }, { "BriefDescription": "Counts prefetch RFOs have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1098,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1108,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1118,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1128,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1138,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1148,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1158,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1168,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1178,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1188,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1198,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1208,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1218,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs have any re= sponse type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1228,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1238,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1248,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1258,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1268,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1278,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1288,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1298,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1308,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1318,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1328,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1338,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1348,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive) hav= e any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1358,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1368,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1378,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1388,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1398,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1408,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1418,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1428,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1438,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1448,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1458,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1468,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1478,7 @@ }, { "BriefDescription": "Counts all demand code reads have any respons= e type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1488,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1498,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1508,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1518,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1528,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1538,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1548,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1558,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1568,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1578,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1588,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1598,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1608,7 @@ }, { "BriefDescription": "Counts demand data reads have any response ty= pe.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1618,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1628,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1638,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1648,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1658,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1668,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1678,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1688,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1698,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1708,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1718,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1728,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1738,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) have any= response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1748,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1758,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1768,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1778,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1788,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1798,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1808,7 @@ }, { "BriefDescription": "Counts any other requests have any response t= ype.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1818,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1828,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1838,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1848,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1858,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1868,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1878,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1888,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1898,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1908,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1918,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1928,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1938,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1948,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +1958,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +1968,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +1978,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +1988,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +1998,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2008,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.ANY_SNO= OP", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2018,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2028,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2038,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2048,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2058,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2068,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2078,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2088,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2098,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2108,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2118,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2128,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2138,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2148,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2158,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2168,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2178,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2188,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2198,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2208,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2218,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2228,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2012,6 +2238,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2021,6 +2248,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2030,6 +2258,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2039,6 +2268,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2048,6 +2278,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2057,6 +2288,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2066,6 +2298,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2075,6 +2308,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2084,6 +2318,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2093,6 +2328,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -2102,6 +2338,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2111,6 +2348,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2120,6 +2358,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -2129,6 +2368,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2138,6 +2378,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2147,6 +2388,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -2156,6 +2398,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.ANY_SNO= OP", "MSRIndex": "0x1a6,0x1a7", @@ -2165,6 +2408,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -2174,6 +2418,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2183,6 +2428,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", @@ -2192,6 +2438,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", @@ -2201,6 +2448,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2210,6 +2458,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -2219,6 +2468,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2228,6 +2478,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2237,6 +2488,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -2246,6 +2498,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2255,6 +2508,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2264,6 +2518,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NOT_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -2273,6 +2528,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", "MSRIndex": "0x1a6,0x1a7", @@ -2282,6 +2538,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -2291,6 +2548,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_H= IT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2300,6 +2558,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", "MSRIndex": "0x1a6,0x1a7", @@ -2309,6 +2568,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", "MSRIndex": "0x1a6,0x1a7", @@ -2318,6 +2578,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= OT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2327,6 +2588,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -2336,6 +2598,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2345,6 +2608,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2354,6 +2618,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2363,6 +2628,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2372,6 +2638,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2381,6 +2648,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2390,6 +2658,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2399,6 +2668,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2408,6 +2678,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2417,6 +2688,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2426,6 +2698,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2435,6 +2708,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2444,6 +2718,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks = in the super queue.", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/counter.json b/tools/= perf/pmu-events/arch/x86/broadwell/counter.json new file mode 100644 index 000000000000..1be6522e2bbc --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwell/counter.json @@ -0,0 +1,22 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "cbox_0", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json b= /tools/perf/pmu-events/arch/x86/broadwell/floating-point.json index 986869252e71..9bf595af3f42 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "SampleAfterValue": "2000006", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -71,6 +80,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -79,6 +89,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", @@ -110,6 +124,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", @@ -126,6 +142,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", @@ -134,6 +151,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "SampleAfterValue": "1000003", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -148,6 +167,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json b/tools= /perf/pmu-events/arch/x86/broadwell/frontend.json index bd5da39564e1..db3488abf9fc 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFDATA_STALL", "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", @@ -101,6 +113,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -109,6 +122,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -118,6 +132,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -144,6 +161,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -154,6 +172,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -162,6 +181,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", @@ -170,6 +190,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/memory.json b/tools/p= erf/pmu-events/arch/x86/broadwell/memory.json index b01ed47072bc..77fbfe99a522 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of times HLE abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 128", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 16", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 256", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -113,6 +125,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 32", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -126,6 +139,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 4", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -139,6 +153,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 512", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -152,6 +167,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 64", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -165,6 +181,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", @@ -186,6 +204,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", @@ -194,6 +213,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -203,6 +223,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -212,6 +233,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -230,6 +253,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -239,6 +263,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -248,6 +273,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -257,6 +283,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -266,6 +293,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -275,6 +303,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -284,6 +313,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -293,6 +323,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -302,6 +333,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= _DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -311,6 +343,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -320,6 +353,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -329,6 +363,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -338,6 +373,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -347,6 +383,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -356,6 +393,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -365,6 +403,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -374,6 +413,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -383,6 +423,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -392,6 +433,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -401,6 +443,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -410,6 +453,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -419,6 +463,7 @@ }, { "BriefDescription": "Counts all prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -428,6 +473,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -437,6 +483,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -446,6 +493,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -455,6 +503,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -464,6 +513,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -473,6 +523,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -482,6 +533,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -491,6 +543,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -500,6 +553,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -509,6 +563,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -518,6 +573,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -527,6 +583,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -536,6 +593,7 @@ }, { "BriefDescription": "Counts all prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -545,6 +603,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -554,6 +613,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -563,6 +623,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -572,6 +633,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -581,6 +643,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -590,6 +653,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", "MSRIndex": "0x1a6,0x1a7", @@ -599,6 +663,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HITM", "MSRIndex": "0x1a6,0x1a7", @@ -608,6 +673,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -617,6 +683,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", @@ -626,6 +693,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", @@ -635,6 +703,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -644,6 +713,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -653,6 +723,7 @@ }, { "BriefDescription": "Counts prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -662,6 +733,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -671,6 +743,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -680,6 +753,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -689,6 +763,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -698,6 +773,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -707,6 +783,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", @@ -716,6 +793,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HI= TM", "MSRIndex": "0x1a6,0x1a7", @@ -725,6 +803,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_HI= T_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +813,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", @@ -743,6 +823,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", @@ -752,6 +833,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= N_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -761,6 +843,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= T_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -770,6 +853,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -779,6 +863,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -788,6 +873,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -797,6 +883,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -806,6 +893,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -815,6 +903,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +913,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.ANY_SNOOP= ", "MSRIndex": "0x1a6,0x1a7", @@ -833,6 +923,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT= M", "MSRIndex": "0x1a6,0x1a7", @@ -842,6 +933,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_HIT= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -851,6 +943,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", @@ -860,6 +953,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +963,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NON= _DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +973,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.L3_MISS_LOCAL_DRAM.SNOOP_NOT= _NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +983,7 @@ }, { "BriefDescription": "Counts writebacks (modified to exclusive)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.SUPPLIER_NONE.SNOOP_NON_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +993,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1003,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1013,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1023,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1033,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1043,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1053,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1063,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1073,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1083,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1093,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1103,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1113,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1123,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1133,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1143,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1153,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1163,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1173,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1183,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1193,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1203,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1213,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1223,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1233,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1243,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1253,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1263,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1273,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1283,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1293,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1303,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1313,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1323,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1333,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1343,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1353,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1363,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1373,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1383,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1393,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1403,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1413,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1423,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1433,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1443,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.SNOOP_NON_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1453,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1463,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1473,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1483,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1493,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1503,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1513,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1523,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1533,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1543,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1553,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1563,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.SUPPLIER_NONE.SNOOP_N= ON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1573,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NON_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1583,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1593,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1603,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1613,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1623,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1633,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1643,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1653,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1663,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1673,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1683,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1693,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1703,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1713,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1723,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1733,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1743,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1753,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1763,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1773,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1783,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1793,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1803,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1813,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1823,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1833,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.SNOOP_NON_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1843,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1853,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1863,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1873,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1883,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1893,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1903,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1913,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1923,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1933,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1943,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +1953,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.SUPPLIER_NONE.SNOOP_N= ON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +1963,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NON_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +1973,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +1983,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +1993,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2003,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2013,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2023,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2033,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2043,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2053,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2063,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2073,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2083,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2093,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2103,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2113,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2123,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2133,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2143,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2153,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2163,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2173,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2183,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2193,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2203,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2213,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2223,7 @@ }, { "BriefDescription": "Number of times RTM abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "2", @@ -2012,6 +2233,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -2020,6 +2242,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", @@ -2028,6 +2251,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", @@ -2036,6 +2260,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", @@ -2044,6 +2269,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", @@ -2052,6 +2278,7 @@ }, { "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -2060,6 +2287,7 @@ }, { "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", @@ -2068,6 +2296,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -2075,6 +2304,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", @@ -2083,6 +2313,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -2091,6 +2322,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -2099,6 +2331,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -2106,6 +2339,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", @@ -2114,6 +2348,7 @@ }, { "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -2122,6 +2357,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -2130,6 +2366,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -2138,6 +2375,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -2146,6 +2384,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -2154,6 +2393,7 @@ }, { "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/metricgroups.json b/t= ools/perf/pmu-events/arch/x86/broadwell/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/other.json b/tools/pe= rf/pmu-events/arch/x86/broadwell/other.json index 1c2a5b001949..f0de6a71719b 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json b/tools= /perf/pmu-events/arch/x86/broadwell/pipeline.json index 9a902d2160e6..c03f77539362 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -166,6 +186,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -175,6 +196,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -184,6 +206,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "This event counts not taken branch instructi= ons retired.", @@ -192,6 +215,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -200,6 +224,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", @@ -216,6 +242,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -224,6 +251,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", @@ -263,6 +295,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", @@ -270,6 +303,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -288,6 +323,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -297,6 +333,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -306,6 +343,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -313,6 +351,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", @@ -322,6 +361,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -329,6 +369,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -336,6 +377,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -343,6 +385,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", @@ -352,6 +395,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -359,6 +403,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -367,12 +412,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -381,12 +428,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -395,6 +444,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -404,6 +454,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -412,6 +463,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -421,6 +473,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -430,6 +483,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -438,6 +492,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -447,6 +502,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -455,6 +511,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -464,6 +521,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -472,6 +530,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -481,6 +540,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -490,6 +550,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -498,6 +559,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -506,6 +568,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", @@ -514,6 +577,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", @@ -521,6 +585,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "BDM61", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -529,6 +594,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "BDM11, BDM55", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -539,6 +605,7 @@ }, { "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", @@ -547,6 +614,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RAT_STALL_CYCLES", "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", @@ -555,6 +623,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -565,6 +634,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -573,6 +643,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", @@ -580,6 +651,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", @@ -588,6 +660,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", @@ -596,6 +669,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", @@ -604,6 +678,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", @@ -612,6 +687,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -620,6 +696,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -628,6 +705,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -635,6 +713,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -644,6 +723,7 @@ }, { "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", @@ -652,6 +732,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", @@ -660,6 +741,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", @@ -668,6 +750,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "SampleAfterValue": "1000003", @@ -675,6 +758,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -682,6 +766,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "SampleAfterValue": "100003", @@ -689,6 +774,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "This event counts resource-related stall cyc= les.", @@ -697,6 +783,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", @@ -705,6 +792,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", @@ -713,6 +801,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", @@ -721,6 +810,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", @@ -729,6 +819,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", @@ -737,6 +828,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -747,6 +839,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -755,6 +848,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -763,6 +857,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -771,6 +866,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -779,6 +875,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -787,6 +884,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -795,6 +893,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -803,6 +902,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -811,6 +911,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -819,6 +920,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -827,6 +929,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -835,6 +938,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -843,6 +947,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -851,6 +956,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -859,6 +965,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -867,6 +974,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -875,6 +983,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -883,6 +992,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -891,6 +1001,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -901,6 +1012,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -909,6 +1021,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -918,6 +1031,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,6 +1039,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -934,6 +1049,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -941,6 +1057,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -950,6 +1067,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -957,6 +1075,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -966,6 +1085,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -973,6 +1093,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -982,6 +1103,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,6 +1111,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -998,6 +1121,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,6 +1129,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -1014,6 +1139,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1021,6 +1147,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -1030,6 +1157,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "SampleAfterValue": "2000003", @@ -1037,6 +1165,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", @@ -1045,6 +1174,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", @@ -1053,6 +1183,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "SampleAfterValue": "2000003", @@ -1060,6 +1191,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -1067,6 +1199,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -1077,6 +1210,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1086,6 +1220,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1095,6 +1230,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1105,6 +1241,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json b/t= ools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json index c5cc43825cb9..c4c57febdc72 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -73,6 +81,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -82,6 +91,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -91,6 +101,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -100,6 +111,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", @@ -108,6 +120,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", @@ -124,10 +138,20 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", "Unit": "CBOX" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "Unit": "cbox_0" } ] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.j= son b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json index 64af685274a2..99f8cc992a24 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Each cycle counts number of all Core outgoing= valid entries. Such entry is defined as valid from its allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.;", + "Counter": "0", "CounterMask": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries that are in DirectData mode. Such entry is defined as vali= d when it is allocated till data sent to Core (first chunk, IDI0). Applicab= le for IA Cores' requests in normal case.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.DRD_DIRECT", "PerPkg": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Total number of Core outgoing entries allocat= ed. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Number of Core coherent Data Read entries all= ocated in DirectData mode", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", "PerPkg": "1", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/broadwell/uncore-other.json deleted file mode 100644 index 58be90d7cc93..000000000000 --- a/tools/perf/pmu-events/arch/x86/broadwell/uncore-other.json +++ /dev/null @@ -1,10 +0,0 @@ -[ - { - "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", - "EventCode": "0xff", - "EventName": "UNC_CLOCK.SOCKET", - "PerPkg": "1", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", - "Unit": "CLOCK" - } -] diff --git a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json index 93621e004d88..eb1d9541e26c 100644 --- a/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwell/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", @@ -149,6 +167,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", @@ -165,6 +185,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", @@ -174,6 +195,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -188,6 +211,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", @@ -212,6 +238,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", @@ -230,6 +258,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", @@ -239,6 +268,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", @@ -247,6 +277,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -263,6 +295,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -271,6 +304,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", @@ -287,6 +322,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -295,6 +331,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", @@ -303,6 +340,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 068DD1B47B0 for ; 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Thu, 20 Jun 2024 11:19:23 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:19 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-6-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 05/37] perf vendor events: Update broadwellde metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/broadwellde/bdwde-metrics.json | 80 ++-- .../arch/x86/broadwellde/cache.json | 76 ++++ .../arch/x86/broadwellde/counter.json | 42 ++ .../arch/x86/broadwellde/floating-point.json | 22 + .../arch/x86/broadwellde/frontend.json | 28 ++ .../arch/x86/broadwellde/memory.json | 39 ++ .../arch/x86/broadwellde/metricgroups.json | 11 + .../arch/x86/broadwellde/other.json | 4 + .../arch/x86/broadwellde/pipeline.json | 137 +++++++ .../arch/x86/broadwellde/uncore-cache.json | 382 ++++++++++++++++++ .../x86/broadwellde/uncore-interconnect.json | 70 ++++ .../arch/x86/broadwellde/uncore-io.json | 62 +++ .../arch/x86/broadwellde/uncore-memory.json | 322 +++++++++++++++ .../arch/x86/broadwellde/uncore-power.json | 57 +++ .../arch/x86/broadwellde/virtual-memory.json | 38 ++ 15 files changed, 1333 insertions(+), 37 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwellde/counter.json diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json = b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json index 826357787201..2e1380248684 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json @@ -90,7 +90,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -100,7 +100,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -121,7 +121,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -160,7 +160,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 = + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_= UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS= _L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LO= AD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS *= (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_L= OAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_= UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + ME= M_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related m= etrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote= _cache", @@ -181,7 +181,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + = MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UO= PS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L= 3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD= _UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -190,7 +190,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -227,7 +227,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISS= ES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tm= a_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -236,7 +236,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MI= SSES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) /= tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -246,7 +246,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -283,7 +283,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -292,7 +292,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -320,7 +320,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -340,7 +340,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -380,7 +380,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0x3c@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -420,7 +420,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0x3c@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -494,12 +494,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -520,7 +520,7 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -532,7 +532,7 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -568,7 +568,13 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -620,7 +626,7 @@ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cm= ask\\=3D1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" @@ -639,13 +645,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -740,7 +746,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -749,7 +755,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_D= URATION\\,cmask\\=3D1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_= clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -767,7 +773,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.ST= ALLS_L2_MISS) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -787,7 +793,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_= UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRE= D.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RET= IRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RET= IRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_mem_latency", @@ -829,14 +835,14 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -846,7 +852,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -855,7 +861,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -884,7 +890,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers = / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= ", @@ -1017,7 +1023,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -1026,7 +1032,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1055,7 +1061,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -1083,7 +1089,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1101,7 +1107,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tm= a_clears_resteers", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json b/tools/= perf/pmu-events/arch/x86/broadwellde/cache.json index 6784331ac1cb..315d7f041731 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", @@ -67,6 +75,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", @@ -75,6 +84,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -90,6 +101,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "This event counts the total number of L2 cod= e requests.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "SampleAfterValue": "200003", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "SampleAfterValue": "200003", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", @@ -136,6 +153,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -143,6 +161,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", @@ -158,6 +178,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", @@ -166,6 +187,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200003", @@ -189,6 +213,7 @@ }, { "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003", @@ -196,6 +221,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -203,6 +229,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -210,6 +237,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", @@ -218,6 +246,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", @@ -226,6 +255,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", @@ -234,6 +264,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", @@ -242,6 +273,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", @@ -250,6 +282,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", @@ -258,6 +291,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", @@ -266,6 +300,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", @@ -274,6 +309,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", @@ -282,6 +318,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", @@ -290,6 +327,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", @@ -298,6 +336,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -309,6 +348,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -320,6 +360,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -331,6 +372,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -342,6 +384,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70, BDM100", "EventCode": "0xD3", @@ -353,6 +396,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -363,6 +407,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -373,6 +418,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -383,6 +429,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", @@ -393,6 +440,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -403,6 +451,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -413,6 +462,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD1", @@ -424,6 +474,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -434,6 +485,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD1", @@ -445,6 +497,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100, BDE70", "EventCode": "0xD1", @@ -455,6 +508,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -465,6 +519,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -475,6 +530,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD0", @@ -486,6 +542,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -496,6 +553,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -506,6 +564,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", @@ -516,6 +575,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", @@ -526,6 +586,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", @@ -542,6 +604,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", @@ -550,6 +613,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", @@ -558,6 +622,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", @@ -566,6 +631,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", @@ -574,6 +640,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -583,6 +650,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -593,6 +661,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -603,6 +672,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -613,6 +683,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -622,6 +693,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -631,6 +703,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "BDM76", "EventCode": "0x60", @@ -640,6 +713,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -649,6 +723,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -656,6 +731,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks = in the super queue.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/counter.json b/tool= s/perf/pmu-events/arch/x86/broadwellde/counter.json new file mode 100644 index 000000000000..ada968d0a038 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellde/counter.json @@ -0,0 +1,42 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "HA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json= b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json index 986869252e71..9bf595af3f42 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "SampleAfterValue": "2000006", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -71,6 +80,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -79,6 +89,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", @@ -110,6 +124,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", @@ -126,6 +142,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", @@ -134,6 +151,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "SampleAfterValue": "1000003", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -148,6 +167,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/frontend.json index bd5da39564e1..db3488abf9fc 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFDATA_STALL", "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", @@ -101,6 +113,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -109,6 +122,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -118,6 +132,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -144,6 +161,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -154,6 +172,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -162,6 +181,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", @@ -170,6 +190,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json b/tools= /perf/pmu-events/arch/x86/broadwellde/memory.json index 041b6ff4062e..31a74eed2f7d 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of times HLE abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 128", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 16", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 256", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -113,6 +125,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 32", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -126,6 +139,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 4", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -139,6 +153,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 512", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -152,6 +167,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 64", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -165,6 +181,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", @@ -186,6 +204,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", @@ -194,6 +213,7 @@ }, { "BriefDescription": "Number of times RTM abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -203,6 +223,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -211,6 +232,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", @@ -219,6 +241,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", @@ -227,6 +250,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", @@ -235,6 +259,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", @@ -243,6 +268,7 @@ }, { "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -251,6 +277,7 @@ }, { "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", @@ -259,6 +286,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -266,6 +294,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", @@ -274,6 +303,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -282,6 +312,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -290,6 +321,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -297,6 +329,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", @@ -305,6 +338,7 @@ }, { "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -313,6 +347,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -321,6 +356,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -329,6 +365,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -337,6 +374,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -345,6 +383,7 @@ }, { "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/metricgroups.json b= /tools/perf/pmu-events/arch/x86/broadwellde/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/other.json b/tools/= perf/pmu-events/arch/x86/broadwellde/other.json index 1c2a5b001949..f0de6a71719b 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json b/too= ls/perf/pmu-events/arch/x86/broadwellde/pipeline.json index 9a902d2160e6..c03f77539362 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -166,6 +186,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -175,6 +196,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -184,6 +206,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "This event counts not taken branch instructi= ons retired.", @@ -192,6 +215,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -200,6 +224,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", @@ -216,6 +242,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -224,6 +251,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", @@ -263,6 +295,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", @@ -270,6 +303,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -288,6 +323,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -297,6 +333,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -306,6 +343,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -313,6 +351,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", @@ -322,6 +361,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -329,6 +369,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -336,6 +377,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -343,6 +385,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", @@ -352,6 +395,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -359,6 +403,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -367,12 +412,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -381,12 +428,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -395,6 +444,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -404,6 +454,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -412,6 +463,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -421,6 +473,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -430,6 +483,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -438,6 +492,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -447,6 +502,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -455,6 +511,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -464,6 +521,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -472,6 +530,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -481,6 +540,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -490,6 +550,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -498,6 +559,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -506,6 +568,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", @@ -514,6 +577,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", @@ -521,6 +585,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "BDM61", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -529,6 +594,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "BDM11, BDM55", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -539,6 +605,7 @@ }, { "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", @@ -547,6 +614,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RAT_STALL_CYCLES", "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", @@ -555,6 +623,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -565,6 +634,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -573,6 +643,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", @@ -580,6 +651,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", @@ -588,6 +660,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", @@ -596,6 +669,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", @@ -604,6 +678,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", @@ -612,6 +687,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -620,6 +696,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -628,6 +705,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -635,6 +713,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -644,6 +723,7 @@ }, { "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", @@ -652,6 +732,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", @@ -660,6 +741,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", @@ -668,6 +750,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "SampleAfterValue": "1000003", @@ -675,6 +758,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -682,6 +766,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "SampleAfterValue": "100003", @@ -689,6 +774,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "This event counts resource-related stall cyc= les.", @@ -697,6 +783,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", @@ -705,6 +792,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", @@ -713,6 +801,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", @@ -721,6 +810,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", @@ -729,6 +819,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", @@ -737,6 +828,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -747,6 +839,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -755,6 +848,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -763,6 +857,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -771,6 +866,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -779,6 +875,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -787,6 +884,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -795,6 +893,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -803,6 +902,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -811,6 +911,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -819,6 +920,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -827,6 +929,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -835,6 +938,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -843,6 +947,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -851,6 +956,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -859,6 +965,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -867,6 +974,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -875,6 +983,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -883,6 +992,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -891,6 +1001,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -901,6 +1012,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -909,6 +1021,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -918,6 +1031,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,6 +1039,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -934,6 +1049,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -941,6 +1057,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -950,6 +1067,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -957,6 +1075,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -966,6 +1085,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -973,6 +1093,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -982,6 +1103,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,6 +1111,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -998,6 +1121,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,6 +1129,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -1014,6 +1139,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1021,6 +1147,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -1030,6 +1157,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "SampleAfterValue": "2000003", @@ -1037,6 +1165,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", @@ -1045,6 +1174,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", @@ -1053,6 +1183,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "SampleAfterValue": "2000003", @@ -1060,6 +1191,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -1067,6 +1199,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -1077,6 +1210,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1086,6 +1220,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1095,6 +1230,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1105,6 +1241,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json index 56bba6d4e0f6..f5b5ae1150c3 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", @@ -8,12 +9,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", @@ -22,6 +25,7 @@ }, { "BriefDescription": "FaST wire asserted", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cache Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", "PerPkg": "1", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Cache Lookups; Any Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.READ", "PerPkg": "1", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.F_STATE", "PerPkg": "1", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.I_STATE", "PerPkg": "1", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", @@ -120,6 +134,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", @@ -129,6 +144,7 @@ }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", "PerPkg": "1", @@ -138,6 +154,7 @@ }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS", "PerPkg": "1", @@ -147,6 +164,7 @@ }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM", "PerPkg": "1", @@ -156,6 +174,7 @@ }, { "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", @@ -165,6 +184,7 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -174,6 +194,7 @@ }, { "BriefDescription": "Cbo Misc", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", @@ -183,6 +204,7 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", @@ -192,6 +214,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 0", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", @@ -201,6 +224,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 1", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", @@ -210,6 +234,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 2", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE2", "PerPkg": "1", @@ -219,6 +244,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE3", "PerPkg": "1", @@ -228,6 +254,7 @@ }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.LRU_DECREMENT", "PerPkg": "1", @@ -237,6 +264,7 @@ }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", "PerPkg": "1", @@ -246,6 +274,7 @@ }, { "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.ALL", "PerPkg": "1", @@ -255,6 +284,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.CCW", "PerPkg": "1", @@ -264,6 +294,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.CW", "PerPkg": "1", @@ -273,6 +304,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -282,6 +314,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -291,6 +324,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -300,6 +334,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -309,6 +344,7 @@ }, { "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.ALL", "PerPkg": "1", @@ -318,6 +354,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.CCW", "PerPkg": "1", @@ -327,6 +364,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.CW", "PerPkg": "1", @@ -336,6 +374,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -345,6 +384,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -354,6 +394,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -363,6 +404,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -372,6 +414,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.ALL", "PerPkg": "1", @@ -381,6 +424,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.CCW", "PerPkg": "1", @@ -390,6 +434,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.CW", "PerPkg": "1", @@ -399,6 +444,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -408,6 +454,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -417,6 +464,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -426,6 +474,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -435,6 +484,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AD", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", @@ -443,6 +493,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AK", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", @@ -451,6 +502,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; BL", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", @@ -459,6 +511,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", @@ -467,6 +520,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.ANY", "PerPkg": "1", @@ -476,6 +530,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DN", "PerPkg": "1", @@ -485,6 +540,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DOWN", "PerPkg": "1", @@ -494,6 +550,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.UP", "PerPkg": "1", @@ -503,6 +560,7 @@ }, { "BriefDescription": "AD", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", @@ -511,6 +569,7 @@ }, { "BriefDescription": "AK", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", @@ -519,6 +578,7 @@ }, { "BriefDescription": "BL", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", @@ -527,6 +587,7 @@ }, { "BriefDescription": "IV", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", @@ -535,6 +596,7 @@ }, { "BriefDescription": "Number of cycles the Cbo is actively throttli= ng traffic onto the Ring in order to limit bounce traffic.", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", @@ -542,6 +604,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "PerPkg": "1", @@ -551,6 +614,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", @@ -560,6 +624,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", "PerPkg": "1", @@ -569,6 +634,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", "PerPkg": "1", @@ -578,6 +644,7 @@ }, { "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IPQ", "PerPkg": "1", @@ -587,6 +654,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ", "PerPkg": "1", @@ -596,6 +664,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", "PerPkg": "1", @@ -605,6 +674,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ", "PerPkg": "1", @@ -614,6 +684,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ", "PerPkg": "1", @@ -623,6 +694,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IPQ", "PerPkg": "1", @@ -632,6 +704,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IRQ", "PerPkg": "1", @@ -641,6 +714,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", @@ -650,6 +724,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.PRQ", "PerPkg": "1", @@ -659,6 +734,7 @@ }, { "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -668,6 +744,7 @@ }, { "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", "PerPkg": "1", @@ -677,6 +754,7 @@ }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", "PerPkg": "1", @@ -686,6 +764,7 @@ }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -695,6 +774,7 @@ }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -704,6 +784,7 @@ }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", "PerPkg": "1", @@ -713,6 +794,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -722,6 +804,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", @@ -731,6 +814,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", @@ -740,6 +824,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -749,6 +834,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.NID", "PerPkg": "1", @@ -758,6 +844,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -767,6 +854,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", @@ -776,6 +864,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -785,6 +874,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -794,6 +884,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", "PerPkg": "1", @@ -803,6 +894,7 @@ }, { "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", "PerPkg": "1", @@ -812,6 +904,7 @@ }, { "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", "PerPkg": "1", @@ -821,6 +914,7 @@ }, { "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -830,6 +924,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", "PerPkg": "1", @@ -839,6 +934,7 @@ }, { "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -848,6 +944,7 @@ }, { "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", "PerPkg": "1", @@ -857,6 +954,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", "PerPkg": "1", @@ -866,6 +964,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -875,6 +974,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -884,6 +984,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filte= r", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", "PerPkg": "1", @@ -893,6 +994,7 @@ }, { "BriefDescription": "Ingress Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -902,6 +1004,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -911,6 +1014,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", "PerPkg": "1", @@ -920,6 +1024,7 @@ }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ", "PerPkg": "1", @@ -929,6 +1034,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -938,6 +1044,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -947,6 +1054,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -956,6 +1064,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -965,6 +1074,7 @@ }, { "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", @@ -974,6 +1084,7 @@ }, { "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", @@ -983,6 +1094,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", @@ -992,6 +1104,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", @@ -1001,6 +1114,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", @@ -1010,6 +1124,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1019,6 +1134,7 @@ }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", @@ -1028,6 +1144,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", @@ -1037,6 +1154,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1046,6 +1164,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", @@ -1055,6 +1174,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", @@ -1064,6 +1184,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", @@ -1073,6 +1194,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", @@ -1082,6 +1204,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", @@ -1091,6 +1214,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", @@ -1100,6 +1224,7 @@ }, { "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", @@ -1109,6 +1234,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", @@ -1118,6 +1244,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", @@ -1127,6 +1254,7 @@ }, { "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", @@ -1136,6 +1264,7 @@ }, { "BriefDescription": "TOR Occupancy; Any", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.ALL", "PerPkg": "1", @@ -1145,6 +1274,7 @@ }, { "BriefDescription": "TOR Occupancy; Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", "PerPkg": "1", @@ -1154,6 +1284,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -1163,6 +1294,7 @@ }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", @@ -1172,6 +1304,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", "PerPkg": "1", @@ -1181,6 +1314,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", "PerPkg": "1", @@ -1190,6 +1324,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1199,6 +1334,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", "PerPkg": "1", @@ -1208,6 +1344,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", "PerPkg": "1", @@ -1217,6 +1354,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1226,6 +1364,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", "PerPkg": "1", @@ -1235,6 +1374,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", "PerPkg": "1", @@ -1244,6 +1384,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", "PerPkg": "1", @@ -1253,6 +1394,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", "PerPkg": "1", @@ -1262,6 +1404,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", "PerPkg": "1", @@ -1271,6 +1414,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", "PerPkg": "1", @@ -1280,6 +1424,7 @@ }, { "BriefDescription": "TOR Occupancy; Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", @@ -1289,6 +1434,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -1298,6 +1444,7 @@ }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", @@ -1307,6 +1454,7 @@ }, { "BriefDescription": "TOR Occupancy; Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.WB", "PerPkg": "1", @@ -1316,6 +1464,7 @@ }, { "BriefDescription": "Onto AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", @@ -1324,6 +1473,7 @@ }, { "BriefDescription": "Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", @@ -1332,6 +1482,7 @@ }, { "BriefDescription": "Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", @@ -1340,6 +1491,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", "PerPkg": "1", @@ -1349,6 +1501,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CORE", "PerPkg": "1", @@ -1358,6 +1511,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", "PerPkg": "1", @@ -1367,6 +1521,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CORE", "PerPkg": "1", @@ -1376,6 +1531,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", "PerPkg": "1", @@ -1385,6 +1541,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", @@ -1394,6 +1551,7 @@ }, { "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", "PerPkg": "1", @@ -1403,6 +1561,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AD_CORE", "PerPkg": "1", @@ -1412,6 +1571,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AK_BOTH", "PerPkg": "1", @@ -1421,6 +1581,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.BL_BOTH", "PerPkg": "1", @@ -1430,6 +1591,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.IV", "PerPkg": "1", @@ -1439,6 +1601,7 @@ }, { "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE", "PerPkg": "1", @@ -1447,6 +1610,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", "PerPkg": "1", @@ -1456,6 +1620,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", "PerPkg": "1", @@ -1465,6 +1630,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", "PerPkg": "1", @@ -1474,6 +1640,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", "PerPkg": "1", @@ -1483,6 +1650,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "PerPkg": "1", @@ -1492,6 +1660,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "PerPkg": "1", @@ -1501,6 +1670,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_H_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", @@ -1508,6 +1678,7 @@ }, { "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_H_DIRECT2CORE_COUNT", "PerPkg": "1", @@ -1516,6 +1687,7 @@ }, { "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", "PerPkg": "1", @@ -1524,6 +1696,7 @@ }, { "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1532,6 +1705,7 @@ }, { "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", @@ -1540,6 +1714,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", "PerPkg": "1", @@ -1549,6 +1724,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", "PerPkg": "1", @@ -1558,6 +1734,7 @@ }, { "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1567,6 +1744,7 @@ }, { "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", "PerPkg": "1", @@ -1576,6 +1754,7 @@ }, { "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.SET", "PerPkg": "1", @@ -1585,6 +1764,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is A= ckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", "PerPkg": "1", @@ -1593,6 +1773,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; All Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALL", "PerPkg": "1", @@ -1601,6 +1782,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALLOCS", "PerPkg": "1", @@ -1609,6 +1791,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.EVICTS", "PerPkg": "1", @@ -1617,6 +1800,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.HOM", "PerPkg": "1", @@ -1625,6 +1809,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalid= ations", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.INVALS", "PerPkg": "1", @@ -1633,6 +1818,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= dCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", "PerPkg": "1", @@ -1641,6 +1827,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSP", "PerPkg": "1", @@ -1649,6 +1836,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1657,6 +1845,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1665,6 +1854,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= sSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDS", "PerPkg": "1", @@ -1673,6 +1863,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", "PerPkg": "1", @@ -1681,6 +1872,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOI", "PerPkg": "1", @@ -1689,6 +1881,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "PerPkg": "1", @@ -1697,6 +1890,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "PerPkg": "1", @@ -1705,6 +1899,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "PerPkg": "1", @@ -1713,6 +1908,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE= ", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "PerPkg": "1", @@ -1721,6 +1917,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "PerPkg": "1", @@ -1729,6 +1926,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1737,6 +1935,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1745,6 +1944,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "PerPkg": "1", @@ -1753,6 +1953,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "PerPkg": "1", @@ -1761,6 +1962,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "PerPkg": "1", @@ -1769,6 +1971,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "PerPkg": "1", @@ -1777,6 +1980,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALL", "PerPkg": "1", @@ -1785,6 +1989,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Allocations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", "PerPkg": "1", @@ -1793,6 +1998,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.HOM", "PerPkg": "1", @@ -1801,6 +2007,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Invalidations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.INVALS", "PerPkg": "1", @@ -1809,6 +2016,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "PerPkg": "1", @@ -1817,6 +2025,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSP", "PerPkg": "1", @@ -1825,6 +2034,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1833,6 +2043,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1841,6 +2052,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", "PerPkg": "1", @@ -1849,6 +2061,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "PerPkg": "1", @@ -1857,6 +2070,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", "PerPkg": "1", @@ -1865,6 +2079,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", "PerPkg": "1", @@ -1874,6 +2089,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", "PerPkg": "1", @@ -1883,6 +2099,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2", "PerPkg": "1", @@ -1892,6 +2109,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", "PerPkg": "1", @@ -1901,6 +2119,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", "PerPkg": "1", @@ -1910,6 +2129,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2", "PerPkg": "1", @@ -1919,6 +2139,7 @@ }, { "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_H_IMC_READS.NORMAL", "PerPkg": "1", @@ -1928,6 +2149,7 @@ }, { "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", @@ -1935,6 +2157,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.ALL", "PerPkg": "1", @@ -1944,6 +2167,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL", "PerPkg": "1", @@ -1953,6 +2177,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", @@ -1962,6 +2187,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -1971,6 +2197,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", @@ -1980,6 +2207,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", "PerPkg": "1", @@ -1988,6 +2216,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", "PerPkg": "1", @@ -1996,6 +2225,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0", "PerPkg": "1", @@ -2005,6 +2235,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1", "PerPkg": "1", @@ -2014,6 +2245,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS2", "PerPkg": "1", @@ -2023,6 +2255,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS3", "PerPkg": "1", @@ -2032,6 +2265,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0", "PerPkg": "1", @@ -2041,6 +2275,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1", "PerPkg": "1", @@ -2050,6 +2285,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Cancelled", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.CANCELLED", "PerPkg": "1", @@ -2059,6 +2295,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.INVITOE_LOCAL", "PerPkg": "1", @@ -2068,6 +2305,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL", "PerPkg": "1", @@ -2077,6 +2315,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL", "PerPkg": "1", @@ -2086,6 +2325,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE", "PerPkg": "1", @@ -2095,6 +2335,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE_USEFUL", "PerPkg": "1", @@ -2104,6 +2345,7 @@ }, { "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.ALL", "PerPkg": "1", @@ -2113,6 +2355,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", "PerPkg": "1", @@ -2122,6 +2365,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", "PerPkg": "1", @@ -2131,6 +2375,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", "PerPkg": "1", @@ -2140,6 +2385,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", "PerPkg": "1", @@ -2149,6 +2395,7 @@ }, { "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -2158,6 +2405,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -2167,6 +2415,7 @@ }, { "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", @@ -2176,6 +2425,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -2185,6 +2435,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -2194,6 +2445,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", @@ -2203,6 +2455,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -2212,6 +2465,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -2221,6 +2475,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW", "PerPkg": "1", @@ -2230,6 +2485,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -2239,6 +2495,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -2248,6 +2505,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW", "PerPkg": "1", @@ -2257,6 +2515,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -2266,6 +2525,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -2275,6 +2535,7 @@ }, { "BriefDescription": "HA AK Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.ALL", "PerPkg": "1", @@ -2284,6 +2545,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW", "PerPkg": "1", @@ -2293,6 +2555,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -2302,6 +2565,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -2311,6 +2575,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW", "PerPkg": "1", @@ -2320,6 +2585,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -2329,6 +2595,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -2338,6 +2605,7 @@ }, { "BriefDescription": "HA BL Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.ALL", "PerPkg": "1", @@ -2347,6 +2615,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW", "PerPkg": "1", @@ -2356,6 +2625,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -2365,6 +2635,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -2374,6 +2645,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW", "PerPkg": "1", @@ -2383,6 +2655,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -2392,6 +2665,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -2401,6 +2675,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -2410,6 +2685,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -2419,6 +2695,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -2428,6 +2705,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -2437,6 +2715,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -2446,6 +2725,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -2455,6 +2735,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -2464,6 +2745,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", @@ -2473,6 +2755,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2482,6 +2765,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2491,6 +2775,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2500,6 +2785,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2509,6 +2795,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2518,6 +2805,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2527,6 +2815,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2536,6 +2825,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2545,6 +2835,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Local Requests= ", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL", "PerPkg": "1", @@ -2554,6 +2845,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Remote Request= s", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE", "PerPkg": "1", @@ -2563,6 +2855,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL", "PerPkg": "1", @@ -2572,6 +2865,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Local Request= s", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -2581,6 +2875,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Remote Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -2590,6 +2885,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local= Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2599,6 +2895,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remot= e Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -2608,6 +2905,7 @@ }, { "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", @@ -2617,6 +2915,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -2626,6 +2925,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -2635,6 +2935,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspS", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPS", "PerPkg": "1", @@ -2644,6 +2945,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -2653,6 +2955,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -2662,6 +2965,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", "PerPkg": "1", @@ -2671,6 +2975,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", "PerPkg": "1", @@ -2680,6 +2985,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", "PerPkg": "1", @@ -2689,6 +2995,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", "PerPkg": "1", @@ -2698,6 +3005,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", "PerPkg": "1", @@ -2707,6 +3015,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", "PerPkg": "1", @@ -2716,6 +3025,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", @@ -2725,6 +3035,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", "PerPkg": "1", @@ -2734,6 +3045,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", "PerPkg": "1", @@ -2743,6 +3055,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -2752,6 +3065,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -2761,6 +3075,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -2770,6 +3085,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -2779,6 +3095,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", "PerPkg": "1", @@ -2788,6 +3105,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", "PerPkg": "1", @@ -2797,6 +3115,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", "PerPkg": "1", @@ -2806,6 +3125,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", "PerPkg": "1", @@ -2815,6 +3135,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", "PerPkg": "1", @@ -2824,6 +3145,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", "PerPkg": "1", @@ -2833,6 +3155,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", "PerPkg": "1", @@ -2842,6 +3165,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", "PerPkg": "1", @@ -2851,6 +3175,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", "PerPkg": "1", @@ -2860,6 +3185,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", "PerPkg": "1", @@ -2869,6 +3195,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", "PerPkg": "1", @@ -2878,6 +3205,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", "PerPkg": "1", @@ -2887,6 +3215,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles Completely Used", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL", "PerPkg": "1", @@ -2896,6 +3225,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Use= d", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP", "PerPkg": "1", @@ -2905,6 +3235,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "PerPkg": "1", @@ -2914,6 +3245,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -2923,6 +3255,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -2932,6 +3265,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -2941,6 +3275,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -2950,6 +3285,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -2959,6 +3295,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -2968,6 +3305,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -2977,6 +3315,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -2986,6 +3325,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2995,6 +3335,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -3004,6 +3345,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_H_TxR_AD.HOM", "PerPkg": "1", @@ -3013,6 +3355,7 @@ }, { "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3022,6 +3365,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3031,6 +3375,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3040,6 +3385,7 @@ }, { "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", "PerPkg": "1", @@ -3049,6 +3395,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3058,6 +3405,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3067,6 +3415,7 @@ }, { "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.ALL", "PerPkg": "1", @@ -3076,6 +3425,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", "PerPkg": "1", @@ -3085,6 +3435,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", "PerPkg": "1", @@ -3094,6 +3445,7 @@ }, { "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3103,6 +3455,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3112,6 +3465,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3121,6 +3475,7 @@ }, { "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", "PerPkg": "1", @@ -3130,6 +3485,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3139,6 +3495,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3148,6 +3505,7 @@ }, { "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.ALL", "PerPkg": "1", @@ -3157,6 +3515,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", "PerPkg": "1", @@ -3166,6 +3525,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", "PerPkg": "1", @@ -3175,6 +3535,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CACHE", "PerPkg": "1", @@ -3184,6 +3545,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CORE", "PerPkg": "1", @@ -3193,6 +3555,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_QPI", "PerPkg": "1", @@ -3202,6 +3565,7 @@ }, { "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3211,6 +3575,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3220,6 +3585,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3229,6 +3595,7 @@ }, { "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", "PerPkg": "1", @@ -3238,6 +3605,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3247,6 +3615,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3256,6 +3625,7 @@ }, { "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.ALL", "PerPkg": "1", @@ -3265,6 +3635,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", "PerPkg": "1", @@ -3274,6 +3645,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", "PerPkg": "1", @@ -3283,6 +3655,7 @@ }, { "BriefDescription": "Injection Starvation; For AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.AK", "PerPkg": "1", @@ -3292,6 +3665,7 @@ }, { "BriefDescription": "Injection Starvation; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.BL", "PerPkg": "1", @@ -3301,6 +3675,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -3310,6 +3685,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -3319,6 +3695,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -3328,6 +3705,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -3337,6 +3715,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -3346,6 +3725,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -3355,6 +3735,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -3364,6 +3745,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect= .json b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json index 910395977a6e..58031f397168 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Number of clocks in the IRP.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Coherent Ops; PCIItoM", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Coherent Ops; RFO", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_TIMEOUT", "PerPkg": "1", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Data Throttled", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.DATA_THROTTLE", "PerPkg": "1", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Misc Events - Set 1", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_I", "PerPkg": "1", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", @@ -242,6 +269,7 @@ }, { "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", @@ -250,6 +278,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -258,6 +287,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", @@ -266,6 +296,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -274,6 +305,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -282,6 +314,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", @@ -290,6 +323,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -298,6 +332,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -306,6 +341,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", @@ -314,6 +350,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -322,6 +359,7 @@ }, { "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", @@ -331,6 +369,7 @@ }, { "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", @@ -349,6 +389,7 @@ }, { "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", @@ -358,6 +399,7 @@ }, { "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", @@ -367,6 +409,7 @@ }, { "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", @@ -376,6 +419,7 @@ }, { "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", @@ -385,6 +429,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", "PerPkg": "1", @@ -394,6 +439,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.OTHER", "PerPkg": "1", @@ -403,6 +449,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.RD_PREF", "PerPkg": "1", @@ -412,6 +459,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -430,6 +479,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -439,6 +489,7 @@ }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -447,6 +498,7 @@ }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -455,6 +507,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", "PerPkg": "1", @@ -463,6 +516,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", "PerPkg": "1", @@ -471,6 +525,7 @@ }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", @@ -479,6 +534,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", @@ -488,6 +544,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", @@ -497,6 +554,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", @@ -506,6 +564,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", @@ -515,6 +574,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", @@ -524,6 +584,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", @@ -533,6 +594,7 @@ }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", @@ -541,6 +603,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", @@ -550,6 +613,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", @@ -559,6 +623,7 @@ }, { "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", @@ -568,6 +633,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", @@ -577,6 +643,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", @@ -586,6 +653,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", @@ -595,6 +663,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", @@ -604,6 +673,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json b/to= ols/perf/pmu-events/arch/x86/broadwellde/uncore-io.json index 01e04daf03da..daef7accdbcb 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_R2_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -50,6 +56,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -59,6 +66,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -68,6 +76,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -77,6 +86,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -86,6 +96,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -95,6 +106,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.ALL", "PerPkg": "1", @@ -104,6 +116,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW", "PerPkg": "1", @@ -113,6 +126,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -122,6 +136,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -131,6 +146,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW", "PerPkg": "1", @@ -140,6 +156,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -149,6 +166,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -158,6 +176,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Dn", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.DN", "PerPkg": "1", @@ -167,6 +186,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Up", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.UP", "PerPkg": "1", @@ -176,6 +196,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.ALL", "PerPkg": "1", @@ -185,6 +206,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW", "PerPkg": "1", @@ -194,6 +216,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -203,6 +226,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -212,6 +236,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW", "PerPkg": "1", @@ -221,6 +246,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -230,6 +256,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -239,6 +266,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.ALL", "PerPkg": "1", @@ -248,6 +276,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW", "PerPkg": "1", @@ -257,6 +286,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -266,6 +296,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -275,6 +306,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW", "PerPkg": "1", @@ -284,6 +316,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -293,6 +326,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -302,6 +336,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.ANY", "PerPkg": "1", @@ -311,6 +346,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CCW", "PerPkg": "1", @@ -320,6 +356,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CW", "PerPkg": "1", @@ -329,6 +366,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -338,6 +376,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -347,6 +386,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCB", "PerPkg": "1", @@ -356,6 +396,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCS", "PerPkg": "1", @@ -365,6 +406,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -374,6 +416,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -383,6 +426,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -392,6 +436,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -401,6 +446,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -410,6 +456,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -419,6 +466,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -428,6 +476,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -437,6 +486,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -446,6 +496,7 @@ }, { "BriefDescription": "Egress Cycles Full; AD", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", "PerPkg": "1", @@ -455,6 +506,7 @@ }, { "BriefDescription": "Egress Cycles Full; AK", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", "PerPkg": "1", @@ -464,6 +516,7 @@ }, { "BriefDescription": "Egress Cycles Full; BL", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", "PerPkg": "1", @@ -473,6 +526,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AD", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AD", "PerPkg": "1", @@ -482,6 +536,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AK", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AK", "PerPkg": "1", @@ -491,6 +546,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; BL", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.BL", "PerPkg": "1", @@ -500,6 +556,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", "PerPkg": "1", @@ -509,6 +566,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", "PerPkg": "1", @@ -518,6 +576,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", "PerPkg": "1", @@ -527,6 +586,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", "PerPkg": "1", @@ -536,6 +596,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", "PerPkg": "1", @@ -545,6 +606,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json = b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json index a764234a3584..ddc83d3885ae 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", @@ -36,6 +40,7 @@ }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", @@ -52,6 +58,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -61,6 +68,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -70,6 +78,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -79,6 +88,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", @@ -87,6 +97,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -96,6 +107,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", @@ -104,6 +116,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -113,6 +126,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", @@ -122,6 +136,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -131,12 +146,14 @@ }, { "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_DCLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", @@ -145,6 +162,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -154,6 +172,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -163,6 +182,7 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", @@ -180,6 +201,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", @@ -189,6 +211,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", @@ -198,6 +221,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", @@ -207,6 +231,7 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "PerPkg": "1", @@ -223,6 +249,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", @@ -232,6 +259,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", @@ -241,6 +269,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", @@ -250,6 +279,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", @@ -259,6 +289,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", @@ -268,6 +299,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", @@ -277,6 +309,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", @@ -286,6 +319,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", @@ -295,6 +329,7 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", @@ -303,6 +338,7 @@ }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -310,6 +346,7 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "PerPkg": "1", @@ -318,6 +355,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", @@ -327,6 +365,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", @@ -336,6 +375,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", @@ -345,6 +385,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", @@ -354,6 +395,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", @@ -363,6 +405,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", @@ -372,6 +415,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", @@ -381,6 +425,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", @@ -390,6 +435,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", @@ -399,6 +445,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", @@ -408,6 +455,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", "PerPkg": "1", @@ -417,6 +465,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", @@ -426,6 +475,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -435,6 +485,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -444,6 +495,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -453,6 +505,7 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", @@ -461,6 +514,7 @@ }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", @@ -469,6 +523,7 @@ }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", @@ -477,6 +532,7 @@ }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", @@ -485,6 +541,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -494,6 +551,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", @@ -502,6 +560,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", @@ -511,6 +570,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", @@ -520,6 +580,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", @@ -529,6 +590,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", @@ -538,6 +600,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", @@ -547,6 +610,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", @@ -556,6 +620,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", @@ -565,6 +630,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", @@ -574,6 +640,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", @@ -583,6 +650,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", @@ -592,6 +660,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", @@ -601,6 +670,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", @@ -610,6 +680,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", @@ -619,6 +690,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", @@ -628,6 +700,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", @@ -637,6 +710,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -646,6 +720,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -655,6 +730,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -664,6 +740,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -673,6 +750,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -682,6 +760,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", @@ -690,6 +769,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", @@ -699,6 +779,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", @@ -708,6 +789,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", @@ -717,6 +799,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", @@ -726,6 +809,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", @@ -735,6 +819,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", @@ -744,6 +829,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", @@ -753,6 +839,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", @@ -762,6 +849,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", @@ -771,6 +859,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", @@ -780,6 +869,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", @@ -789,6 +879,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", @@ -798,6 +889,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", @@ -807,6 +899,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", @@ -816,6 +909,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", @@ -825,6 +919,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -834,6 +929,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -843,6 +939,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -852,6 +949,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -861,6 +959,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", @@ -869,6 +968,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -878,6 +978,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", @@ -886,6 +987,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", @@ -895,6 +997,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", @@ -904,6 +1007,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", @@ -913,6 +1017,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", @@ -922,6 +1027,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", @@ -931,6 +1037,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", @@ -940,6 +1047,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", @@ -949,6 +1057,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", @@ -958,6 +1067,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", @@ -967,6 +1077,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", @@ -976,6 +1087,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", @@ -985,6 +1097,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", @@ -994,6 +1107,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", @@ -1003,6 +1117,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", @@ -1012,6 +1127,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", @@ -1021,6 +1137,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -1030,6 +1147,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -1039,6 +1157,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -1048,6 +1167,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -1057,6 +1177,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -1066,6 +1187,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", @@ -1074,6 +1196,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", @@ -1083,6 +1206,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", @@ -1092,6 +1216,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", @@ -1101,6 +1226,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", @@ -1110,6 +1236,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", @@ -1119,6 +1246,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", @@ -1128,6 +1256,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", @@ -1137,6 +1266,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", @@ -1146,6 +1276,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", @@ -1155,6 +1286,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", @@ -1164,6 +1296,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", @@ -1173,6 +1306,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", @@ -1182,6 +1316,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", @@ -1191,6 +1326,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", @@ -1200,6 +1336,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", @@ -1209,6 +1346,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -1218,6 +1356,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -1227,6 +1366,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -1236,6 +1376,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -1245,6 +1386,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -1254,6 +1396,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", @@ -1262,6 +1405,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", @@ -1271,6 +1415,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", @@ -1280,6 +1425,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", @@ -1289,6 +1435,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", @@ -1298,6 +1445,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", @@ -1307,6 +1455,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", @@ -1316,6 +1465,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", @@ -1325,6 +1475,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", @@ -1334,6 +1485,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", @@ -1343,6 +1495,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", @@ -1352,6 +1505,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", @@ -1361,6 +1515,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", @@ -1370,6 +1525,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", @@ -1379,6 +1535,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", @@ -1388,6 +1545,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", @@ -1397,6 +1555,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -1406,6 +1565,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -1415,6 +1575,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -1424,6 +1585,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -1433,6 +1595,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -1442,6 +1605,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", @@ -1450,6 +1614,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", @@ -1459,6 +1624,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", @@ -1468,6 +1634,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", @@ -1477,6 +1644,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", @@ -1486,6 +1654,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", @@ -1495,6 +1664,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", @@ -1504,6 +1674,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", @@ -1513,6 +1684,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", @@ -1522,6 +1694,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", @@ -1531,6 +1704,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", @@ -1540,6 +1714,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", @@ -1549,6 +1724,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", @@ -1558,6 +1734,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", @@ -1567,6 +1744,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", @@ -1576,6 +1754,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", @@ -1585,6 +1764,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -1594,6 +1774,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -1603,6 +1784,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -1612,6 +1794,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", @@ -1621,6 +1804,7 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", @@ -1629,6 +1813,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -1637,6 +1822,7 @@ }, { "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", @@ -1644,6 +1830,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", @@ -1652,6 +1839,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", @@ -1660,6 +1848,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", @@ -1668,6 +1857,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", @@ -1676,6 +1866,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", @@ -1684,6 +1875,7 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", @@ -1692,6 +1884,7 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", @@ -1700,6 +1893,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", @@ -1708,6 +1902,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", @@ -1716,6 +1911,7 @@ }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", @@ -1723,6 +1919,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -1732,6 +1929,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", @@ -1740,6 +1938,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", @@ -1749,6 +1948,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", @@ -1758,6 +1958,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", @@ -1767,6 +1968,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", @@ -1776,6 +1978,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", @@ -1785,6 +1988,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", @@ -1794,6 +1998,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", @@ -1803,6 +2008,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", @@ -1812,6 +2018,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", @@ -1821,6 +2028,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", @@ -1830,6 +2038,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", @@ -1839,6 +2048,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", @@ -1848,6 +2058,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", @@ -1857,6 +2068,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", @@ -1866,6 +2078,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", @@ -1875,6 +2088,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -1884,6 +2098,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -1893,6 +2108,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -1902,6 +2118,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -1911,6 +2128,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -1920,6 +2138,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", @@ -1928,6 +2147,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", @@ -1937,6 +2157,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", @@ -1946,6 +2167,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", @@ -1955,6 +2177,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", @@ -1964,6 +2187,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", @@ -1973,6 +2197,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", @@ -1982,6 +2207,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", @@ -1991,6 +2217,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", @@ -2000,6 +2227,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", @@ -2009,6 +2237,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", @@ -2018,6 +2247,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", @@ -2027,6 +2257,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", @@ -2036,6 +2267,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", @@ -2045,6 +2277,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", @@ -2054,6 +2287,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", @@ -2063,6 +2297,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -2072,6 +2307,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -2081,6 +2317,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -2090,6 +2327,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -2099,6 +2337,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -2108,6 +2347,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", @@ -2116,6 +2356,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", @@ -2125,6 +2366,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", @@ -2134,6 +2376,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", @@ -2143,6 +2386,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", @@ -2152,6 +2396,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", @@ -2161,6 +2406,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", @@ -2170,6 +2416,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", @@ -2179,6 +2426,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", @@ -2188,6 +2436,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", @@ -2197,6 +2446,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", @@ -2206,6 +2456,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", @@ -2215,6 +2466,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", @@ -2224,6 +2476,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", @@ -2233,6 +2486,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", @@ -2242,6 +2496,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", @@ -2251,6 +2506,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -2260,6 +2516,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -2269,6 +2526,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -2278,6 +2536,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -2287,6 +2546,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -2296,6 +2556,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", @@ -2304,6 +2565,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", @@ -2313,6 +2575,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", @@ -2322,6 +2585,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", @@ -2331,6 +2595,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", @@ -2340,6 +2605,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", @@ -2349,6 +2615,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", @@ -2358,6 +2625,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", @@ -2367,6 +2635,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", @@ -2376,6 +2645,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", @@ -2385,6 +2655,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", @@ -2394,6 +2665,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", @@ -2403,6 +2675,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", @@ -2412,6 +2685,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", @@ -2421,6 +2695,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", @@ -2430,6 +2705,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", @@ -2439,6 +2715,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -2448,6 +2725,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -2457,6 +2735,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -2466,6 +2745,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -2475,6 +2755,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -2484,6 +2765,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", @@ -2492,6 +2774,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", @@ -2501,6 +2784,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", @@ -2510,6 +2794,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", @@ -2519,6 +2804,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", @@ -2528,6 +2814,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", @@ -2537,6 +2824,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", @@ -2546,6 +2834,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", @@ -2555,6 +2844,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", @@ -2564,6 +2854,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", @@ -2573,6 +2864,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", @@ -2582,6 +2874,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", @@ -2591,6 +2884,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", @@ -2600,6 +2894,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", @@ -2609,6 +2904,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", @@ -2618,6 +2914,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", @@ -2627,6 +2924,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -2636,6 +2934,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -2645,6 +2944,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -2654,6 +2954,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -2663,6 +2964,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -2672,6 +2974,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", @@ -2680,6 +2983,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", @@ -2689,6 +2993,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", @@ -2698,6 +3003,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", @@ -2707,6 +3013,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", @@ -2716,6 +3023,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", @@ -2725,6 +3033,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", @@ -2734,6 +3043,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", @@ -2743,6 +3053,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", @@ -2752,6 +3063,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", @@ -2761,6 +3073,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", @@ -2770,6 +3083,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", @@ -2779,6 +3093,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", @@ -2788,6 +3103,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", @@ -2797,6 +3113,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", @@ -2806,6 +3123,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", @@ -2815,6 +3133,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -2824,6 +3143,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -2833,6 +3153,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -2842,6 +3163,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json b= /tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json index 320aaab53a0b..afdc636b9855 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", "PerPkg": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", "PerPkg": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", "PerPkg": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", "PerPkg": "1", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", "PerPkg": "1", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", "PerPkg": "1", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", "PerPkg": "1", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS_CORE0", "PerPkg": "1", @@ -160,6 +180,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_P_DEMOTIONS_CORE1", "PerPkg": "1", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_P_DEMOTIONS_CORE10", "PerPkg": "1", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3B", "EventName": "UNC_P_DEMOTIONS_CORE11", "PerPkg": "1", @@ -184,6 +207,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_P_DEMOTIONS_CORE12", "PerPkg": "1", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_P_DEMOTIONS_CORE13", "PerPkg": "1", @@ -200,6 +225,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_P_DEMOTIONS_CORE14", "PerPkg": "1", @@ -208,6 +234,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_P_DEMOTIONS_CORE15", "PerPkg": "1", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_P_DEMOTIONS_CORE16", "PerPkg": "1", @@ -224,6 +252,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", @@ -232,6 +261,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", @@ -240,6 +270,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_P_DEMOTIONS_CORE3", "PerPkg": "1", @@ -248,6 +279,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_P_DEMOTIONS_CORE4", "PerPkg": "1", @@ -256,6 +288,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_P_DEMOTIONS_CORE5", "PerPkg": "1", @@ -264,6 +297,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_P_DEMOTIONS_CORE6", "PerPkg": "1", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_P_DEMOTIONS_CORE7", "PerPkg": "1", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_P_DEMOTIONS_CORE8", "PerPkg": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_P_DEMOTIONS_CORE9", "PerPkg": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", @@ -304,6 +342,7 @@ }, { "BriefDescription": "OS Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", "PerPkg": "1", @@ -312,6 +351,7 @@ }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", @@ -320,6 +360,7 @@ }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", @@ -328,6 +369,7 @@ }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", @@ -336,6 +378,7 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", @@ -344,6 +387,7 @@ }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "PerPkg": "1", @@ -352,6 +396,7 @@ }, { "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", "PerPkg": "1", @@ -360,6 +405,7 @@ }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "PerPkg": "1", @@ -368,6 +414,7 @@ }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "PerPkg": "1", @@ -376,6 +423,7 @@ }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "PerPkg": "1", @@ -384,6 +432,7 @@ }, { "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", "PerPkg": "1", @@ -392,6 +441,7 @@ }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "Filter": "occ_sel=3D1", @@ -401,6 +451,7 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "Filter": "occ_sel=3D2", @@ -410,6 +461,7 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "Filter": "occ_sel=3D3", @@ -419,6 +471,7 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", @@ -427,6 +480,7 @@ }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", @@ -435,6 +489,7 @@ }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", @@ -443,6 +498,7 @@ }, { "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", "PerPkg": "1", @@ -451,6 +507,7 @@ }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json index 93621e004d88..eb1d9541e26c 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", @@ -149,6 +167,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", @@ -165,6 +185,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", @@ -174,6 +195,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -188,6 +211,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", @@ -212,6 +238,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", @@ -230,6 +258,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", @@ -239,6 +268,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", @@ -247,6 +277,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -263,6 +295,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -271,6 +304,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", @@ -287,6 +322,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -295,6 +331,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", @@ -303,6 +340,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-pg1-f202.google.com (mail-pg1-f202.google.com [209.85.215.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 791EC376E9 for ; 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Thu, 20 Jun 2024 11:19:26 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:20 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-7-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 06/37] perf vendor events: Update broadwellx metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/broadwellx/bdx-metrics.json | 128 ++--- .../pmu-events/arch/x86/broadwellx/cache.json | 88 ++++ .../arch/x86/broadwellx/counter.json | 57 +++ .../arch/x86/broadwellx/floating-point.json | 22 + .../arch/x86/broadwellx/frontend.json | 28 ++ .../arch/x86/broadwellx/memory.json | 58 +++ .../arch/x86/broadwellx/metricgroups.json | 11 + .../pmu-events/arch/x86/broadwellx/other.json | 4 + .../arch/x86/broadwellx/pipeline.json | 137 ++++++ .../arch/x86/broadwellx/uncore-cache.json | 399 +++++++++++++++ .../x86/broadwellx/uncore-interconnect.json | 454 ++++++++++++++++++ .../arch/x86/broadwellx/uncore-io.json | 62 +++ .../arch/x86/broadwellx/uncore-memory.json | 326 +++++++++++++ .../arch/x86/broadwellx/uncore-power.json | 57 +++ .../arch/x86/broadwellx/virtual-memory.json | 38 ++ 15 files changed, 1787 insertions(+), 82 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/broadwellx/counter.json diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json b/t= ools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json index 0aed533da882..0577d7460082 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/bdx-metrics.json @@ -68,7 +68,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -292,7 +292,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -302,7 +302,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -323,7 +323,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -362,7 +362,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 = + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_= UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS= _L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LO= AD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_D= RAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RET= IRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + ME= M_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS= _RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_= HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_U= OPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM = + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED= .REMOTE_FWD)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -383,7 +383,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + = MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UO= PS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L= 3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD= _UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRA= M + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIR= ED.REMOTE_FWD))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -392,7 +392,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -429,7 +429,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + cpu@DTLB_LOAD_MISS= ES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_LOAD_MISSES.WALK_COMPLETED) / tm= a_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -438,7 +438,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + cpu@DTLB_STORE_MI= SSES.WALK_DURATION\\,cmask\\=3D1@ + 7 * DTLB_STORE_MISSES.WALK_COMPLETED) /= tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -447,7 +447,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_= HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info= _thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -457,7 +457,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -494,7 +494,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -503,7 +503,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -531,7 +531,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -551,7 +551,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -590,7 +590,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0x3c@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -630,7 +630,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0x3c@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -704,12 +704,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -730,23 +730,11 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, - { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.= ANY", @@ -754,17 +742,11 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", @@ -796,16 +778,16 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + "MetricName": "tma_info_memory_l3_cache_fill_bw" }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", @@ -819,29 +801,17 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_data_l2_mlp" }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "tma_info_memory_load_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" + "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, { "BriefDescription": "Average Parallel L2 cache miss demand Loads", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" + "MetricName": "tma_info_memory_latency_load_l2_mlp" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -858,12 +828,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_= DURATION + DTLB_STORE_MISSES.WALK_DURATION + 7 * (DTLB_STORE_MISSES.WALK_CO= MPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED)) / = (2 * tma_info_core_core_clks)", @@ -872,7 +836,7 @@ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cm= ask\\=3D1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" @@ -891,13 +855,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1012,7 +976,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1021,7 +985,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_D= URATION\\,cmask\\=3D1@ + 7 * ITLB_MISSES.WALK_COMPLETED) / tma_info_thread_= clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -1039,7 +1003,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.ST= ALLS_L2_MISS) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -1059,7 +1023,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_= UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRE= D.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RET= IRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_= MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_L= OAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE= _FWD))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -1117,7 +1081,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1127,7 +1091,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -1136,7 +1100,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -1165,7 +1129,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES * tma_branch_resteers = / (BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY)", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Related metrics: tma_branch_mispredicts, tma_info_bad= _spec_branch_misprediction_cost", @@ -1301,7 +1265,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1328,7 +1292,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1357,7 +1321,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -1385,7 +1349,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1402,7 +1366,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "tma_branch_resteers - tma_mispredicts_resteers - tm= a_clears_resteers", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json b/tools/p= erf/pmu-events/arch/x86/broadwellx/cache.json index 781e7c64e71f..beeda41b428a 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements= including opportunistic replacements, and replacements that require stall-= for-replace or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "This event counts duration of L1D miss outst= anding, that is each cycle number of Fill Buffers (FB) outstanding required= by Demand Reads. FB either is held by demand loads, or it is held by non-d= emand loads and gets hit at least once by demand. The valid outstanding int= erval is defined until the FB deallocation by one of the following ways: fr= om FB allocation, if FB is allocated by demand; from the demand Hit FB, if = it is allocated by hardware or software prefetch.\nNote: In the L1D, a Dema= nd Read contains cacheable or noncacheable demand loads, including ones cau= sing cache-line splits and reads due to page walks resulted from any reques= t type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "This event counts the number of WB requests = that hit L2 cache.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es filling the L2. Counting does not cover rejects.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "This event counts the number of L2 cache lin= es in the Exclusive state filling the L2. Counting does not cover rejects.", @@ -67,6 +75,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "This event counts the number of L2 cache lin= es in the Invalidate state filling the L2. Counting does not cover rejects.= ", @@ -75,6 +84,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "This event counts the number of L2 cache lin= es in the Shared state filling the L2. Counting does not cover rejects.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -90,6 +101,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "This event counts the total number of L2 cod= e requests.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "This event counts the number of demand Data = Read requests (including requests from L1D hardware prefetchers). These loa= ds may hit or miss L2 cache. Only non rejected loads are counted.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "SampleAfterValue": "200003", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "SampleAfterValue": "200003", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "This event counts the total number of reques= ts from the L2 hardware prefetchers.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "This event counts the total number of RFO (r= ead for ownership) requests to L2 cache. L2 RFO requests include both L1D d= emand RFO misses as well as L1D RFO prefetches.", @@ -136,6 +153,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -143,6 +161,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache.", @@ -158,6 +178,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "This event counts the number of demand Data = Read requests that miss L2 cache. Only not rejected loads are counted.", @@ -166,6 +187,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "This event counts the number of requests fro= m the L2 hardware prefetchers that miss L2 cache.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200003", @@ -189,6 +213,7 @@ }, { "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200003", @@ -196,6 +221,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -203,6 +229,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -210,6 +237,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "This event counts L2 or L3 HW prefetches tha= t access L2 cache including rejects.", @@ -218,6 +246,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "This event counts transactions that access t= he L2 pipe including snoops, pagewalks, and so on.", @@ -226,6 +255,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "This event counts the number of L2 cache acc= esses when fetching instructions.", @@ -234,6 +264,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "This event counts Demand Data Read requests = that access L2 cache, including rejects.", @@ -242,6 +273,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "This event counts L1D writebacks that access= L2 cache.", @@ -250,6 +282,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "This event counts L2 fill requests that acce= ss L2 cache.", @@ -258,6 +291,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "This event counts L2 writebacks that access = L2 cache.", @@ -266,6 +300,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "PublicDescription": "This event counts Read for Ownership (RFO) r= equests that access L2 cache.", @@ -274,6 +309,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", @@ -282,6 +318,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts core-originated cacheable = demand requests that miss the last level cache (LLC). Demand requests inclu= de loads, RFOs, and hardware prefetches from L1D, and instruction fetches f= rom IFU.", @@ -290,6 +327,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts core-originated cacheable = demand requests that refer to the last level cache (LLC). Demand requests i= nclude loads, RFOs, and hardware prefetches from L1D, and instruction fetch= es from IFU.", @@ -298,6 +336,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -309,6 +348,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -320,6 +360,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -331,6 +372,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD2", @@ -342,6 +384,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70, BDM100", "EventCode": "0xD3", @@ -353,6 +396,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -363,6 +407,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -373,6 +418,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDE70", "EventCode": "0xD3", @@ -383,6 +429,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", @@ -393,6 +440,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -403,6 +451,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -413,6 +462,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD1", @@ -424,6 +474,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -434,6 +485,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100", "EventCode": "0xD1", @@ -445,6 +497,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM100, BDE70", "EventCode": "0xD1", @@ -455,6 +508,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -465,6 +519,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -475,6 +530,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "BDM35", "EventCode": "0xD0", @@ -486,6 +542,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -496,6 +553,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -506,6 +564,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", @@ -516,6 +575,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", @@ -526,6 +586,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "This event counts the demand and prefetch da= ta reads. All Core Data Reads include cacheable Demands and L2 prefetchers = (not L3 prefetchers). Counting also covers reads due to page walks resulted= from any request type.", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "This event counts memory transactions reache= d the super queue including requests initiated by the core, all L3 prefetch= es, page walks, and so on.", @@ -542,6 +604,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "This event counts both cacheable and non-cac= heable code read requests.", @@ -550,6 +613,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "This event counts the Demand Data Read reque= sts sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING= to determine average latency in the uncore.", @@ -558,6 +622,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "This event counts the demand RFO (read for o= wnership) requests including regular RFOs, locks, ItoM.", @@ -566,6 +631,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "This event counts the number of cases when t= he offcore requests buffer cannot take more entries for the core. This can = happen when the superqueue does not contain eligible entries, or when L1D w= riteback pending FIFO requests is full.\nNote: Writeback pending FIFO has s= ix entries.", @@ -574,6 +640,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -583,6 +650,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -593,6 +661,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -603,6 +672,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "BDM76", "EventCode": "0x60", @@ -613,6 +683,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -622,6 +693,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -631,6 +703,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "BDM76", "EventCode": "0x60", @@ -640,6 +713,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "BDM76", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -649,6 +723,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -656,6 +731,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -665,6 +741,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -674,6 +751,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -683,6 +761,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -692,6 +771,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoops to sibling cores hit in either E/S state= and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -701,6 +781,7 @@ }, { "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -710,6 +791,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -719,6 +801,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -728,6 +811,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -737,6 +821,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -746,6 +831,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -755,6 +841,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +851,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "This event counts the number of split locks = in the super queue.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/counter.json b/tools= /perf/pmu-events/arch/x86/broadwellx/counter.json new file mode 100644 index 000000000000..9fde9c0a896d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/broadwellx/counter.json @@ -0,0 +1,57 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "HA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R3QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "SBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "1", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json = b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json index 986869252e71..9bf595af3f42 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 2 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they= perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 4 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 4 c= alculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQ= RT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twi= ce as they perform 8 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational double precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed double precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "SampleAfterValue": "2000006", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational packed floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* packed double and single precision floating= -point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RC= P DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.PACKED", "SampleAfterValue": "2000004", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Each count represents 1 computation operation. Applies to SSE* and= AVX* scalar double and single precision floating-point instructions: ADD S= UB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions c= ount twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar double= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -71,6 +80,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar single= precision floating-point instructions retired; some instructions will coun= t twice as noted below. Each count represents 1 computational operation. A= pplies to SSE* and AVX* scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -79,6 +89,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational single precis= ion floating-point instructions retired; some instructions will count twice= as noted below. Applies to SSE* and AVX* scalar and packed single precisio= n floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQR= T RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count= twice as they perform multiple calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SINGLE", "SampleAfterValue": "2000005", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "This event counts any input SSE* FP assist -= invalid operation, denormal operand, dividing by zero, SNaN operand. Count= ing includes only cases involving penalties that required micro-code assist= intervention.", @@ -110,6 +124,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "This event counts the number of SSE* floatin= g point (FP) micro-code assist (numeric overflow/underflow) when the output= value (destination register) is invalid. Counting covers only cases involv= ing penalties that require micro-code assist intervention.", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "This event counts x87 floating point (FP) mi= cro-code assist (invalid operation, denormal operand, SNaN operand) when th= e input value (one of the source operands to an FP instruction) is invalid.= ", @@ -126,6 +142,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "This event counts the number of x87 floating= point (FP) micro-code assist (numeric overflow/underflow, inexact result) = when the output value (destination register) is invalid.", @@ -134,6 +151,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "SampleAfterValue": "1000003", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -148,6 +167,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "Errata": "BDM30", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Micro-op dispatches cancelled due to insuffic= ient SIMD physical register file read ports", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF", "PublicDescription": "This event counts the number of micro-operat= ions cancelled after they were dispatched from the scheduler to the executi= on units when the total number of physical register read ports across all d= ispatch ports exceeds the read bandwidth of the physical register file. Th= e SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPC= MPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VM= SUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more= information.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/frontend.json index bd5da39564e1..db3488abf9fc 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts Decode Stream Buffer (DSB)= -to-MITE switch true penalty cycles. These cycles do not include uops route= d through because of the switch itself, for example, when Instruction Decod= e Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (I= DQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge = mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receivin= g the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) = to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths.= Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode S= tream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer = (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six = cycles in which no uops are delivered to the IDQ. Most often, such switches= from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.= ", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "This event counts the number of both cacheab= le and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Re= ads including UC fetches.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFDATA_STALL", "PublicDescription": "This event counts cycles during which the de= mand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes UC acces= ses.", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) pa= th. Counting includes uops that may bypass the IDQ.", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "PublicDescription": "This counts the number of cycles that the in= struction decoder queue is empty and can indicate that the application may = be bound in the front end. It does not determine whether there are uops be= ing delivered to the Alloc stage since uops can be delivered by bypass skip= ping the Instruction Decode Queue (IDQ) when it is empty.", @@ -101,6 +113,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -109,6 +122,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -118,6 +132,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "This event counts the number of uops deliver= ed to Instruction Decode Queue (IDQ) from the MITE path. Counting includes = uops that may bypass the IDQ. This also means that uops are not being deliv= ered from the Decode Stream Buffer (DSB).", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -144,6 +161,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -154,6 +172,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by Decode Stream Buffer (DSB) that are being delivered to Instruction De= code Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting inclu= des uops that may bypass the IDQ.", @@ -162,6 +181,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "This event counts the number of uops initiat= ed by MITE and delivered to Instruction Decode Queue (IDQ) while the Microc= ode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.= ", @@ -170,6 +190,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "This event counts the total number of uops d= elivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (M= S) is busy. Counting includes uops that may bypass the IDQ. Uops maybe init= iated by Decode Stream Buffer (DSB) or MITE.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to Resource Allocation Table (RAT) per thread adding 4 x when Resou= rce Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ= ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0= ,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation = Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (R= AT) is stalled for the thread (including uop drops and clear BE conditions)= ; \n c. Instruction Decode Queue (IDQ) delivers four uops.", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json b/tools/= perf/pmu-events/arch/x86/broadwellx/memory.json index a7449e5b68dc..86246f632d79 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of times HLE abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an HLE abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= HLE abort.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an HLE abort.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times HLE caused a fault.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times HLE aborted and was not due = to the abort conditions in subevents 3-6.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of times HLE commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of times we entered an HLE region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region\n d= oes not count nested transactions.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3= . cross SMT-HW-thread snoop (stores) hitting load buffer.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 128", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 16", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 256", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -113,6 +125,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 32", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -126,6 +139,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 4", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -139,6 +153,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 512", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -152,6 +167,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 64", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -165,6 +181,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 8", + "Counter": "3", "Data_LA": "1", "Errata": "BDM100, BDM35", "EventCode": "0xcd", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "This event counts speculative cache-line spl= it load uops dispatched to the L1 cache.", @@ -186,6 +204,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "This event counts speculative cache line spl= it store-address (STA) uops dispatched to the L1 cache.", @@ -194,6 +213,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -203,6 +223,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -212,6 +233,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -230,6 +253,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -239,6 +263,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -248,6 +273,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", "MSRIndex": "0x1a6,0x1a7", @@ -257,6 +283,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -266,6 +293,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -275,6 +303,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -284,6 +313,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -293,6 +323,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", @@ -302,6 +333,7 @@ }, { "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -311,6 +343,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -320,6 +353,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -329,6 +363,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -338,6 +373,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -347,6 +383,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -356,6 +393,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -365,6 +403,7 @@ }, { "BriefDescription": "Number of times RTM abort was triggered", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -374,6 +413,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM abort was attributed = to a Memory condition (See TSX_Memory event for additional details).", @@ -382,6 +422,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "PublicDescription": "Number of times the TSX watchdog signaled an= RTM abort.", @@ -390,6 +431,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "PublicDescription": "Number of times a disallowed operation cause= d an RTM abort.", @@ -398,6 +440,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", "PublicDescription": "Number of times a RTM caused a fault.", @@ -406,6 +449,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times RTM aborted and was not due = to the abort conditions in subevents 3-6.", @@ -414,6 +458,7 @@ }, { "BriefDescription": "Number of times RTM commit succeeded", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -422,6 +467,7 @@ }, { "BriefDescription": "Number of times we entered an RTM region; doe= s not count nested transactions", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region\n d= oes not count nested transactions.", @@ -430,6 +476,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -437,6 +484,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroup= per instruction.", @@ -445,6 +493,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -453,6 +502,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -461,6 +511,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -468,6 +519,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to an evicted line caused by a transaction overflow", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Number of times a TSX Abort was triggered du= e to an evicted line caused by a transaction overflow.", @@ -476,6 +528,7 @@ }, { "BriefDescription": "Number of times a TSX line had a cache confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -484,6 +537,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to release/commit but data and address mismatch", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -492,6 +546,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to commit but Lock Buffer not empty", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -500,6 +555,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to attempting an unsupported alignment from Lock Buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -508,6 +564,7 @@ }, { "BriefDescription": "Number of times a TSX Abort was triggered due= to a non-release/commit store to lock", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -516,6 +573,7 @@ }, { "BriefDescription": "Number of times we could not allocate Lock Bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/metricgroups.json b/= tools/perf/pmu-events/arch/x86/broadwellx/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/other.json b/tools/p= erf/pmu-events/arch/x86/broadwellx/other.json index 1c2a5b001949..f0de6a71719b 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/other.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "This event counts the unhalted core cycles d= uring which the thread is in the ring 0 privileged mode.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "This event counts unhalted core cycles durin= g which the thread is in rings 1, 2, or 3.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "This event counts cycles in which the L1 and= L2 are locked due to a UC lock or split lock. A lock is asserted in case o= f locked memory access, due to noncacheable memory, locked operation that s= pans two cache lines, or a page walk from the noncacheable page table. L1D = and L2 locks have a very high performance penalty and it is highly recommen= ded to avoid such access.", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json b/tool= s/perf/pmu-events/arch/x86/broadwellx/pipeline.json index 9a902d2160e6..c03f77539362 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "This event counts the number of the divide o= perations executed. Uses edge-detect and a cmask value of 1 on ARITH.FPU_DI= V_ACTIVE to get the number of the divide operations executed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired branch instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-conditional branch instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "PublicDescription": "This event counts both taken and not taken s= peculative and retired macro-unconditional branch instructions, excluding c= alls and indirects.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired direct near calls.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches excluding calls and return branche= s.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts both taken and not taken s= peculative and retired indirect branches that have a return mnemonic.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken macro-conditiona= l branch instructions.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "PublicDescription": "This event counts taken speculative and reti= red macro-conditional branch instructions excluding calls and indirect bran= ches.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red direct near calls.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red indirect branches excluding calls and return branches.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "This event counts taken speculative and reti= red indirect calls including both register and memory indirect.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "PublicDescription": "This event counts taken speculative and reti= red indirect branches that have a return mnemonic.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all (macro) branch instruc= tions retired.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS)", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "BDW98", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -166,6 +186,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -175,6 +196,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -184,6 +206,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "This event counts not taken branch instructi= ons retired.", @@ -192,6 +215,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -200,6 +224,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted macro conditional branch instructions.", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts both taken and not taken m= ispredicted indirect branches excluding calls and returns.", @@ -216,6 +242,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -224,6 +251,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "This event counts not taken speculative and = retired mispredicted macro conditional branch instructions.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "This event counts taken speculative and reti= red mispredicted macro conditional branch instructions.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches excluding calls and returns.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "PublicDescription": "This event counts taken speculative and reti= red mispredicted indirect branches that have a return mnemonic.", @@ -263,6 +295,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "This event counts all mispredicted macro bra= nch instructions retired.", @@ -270,6 +303,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -288,6 +323,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -297,6 +333,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -306,6 +343,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -313,6 +351,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "This is a fixed-frequency event programmed t= o general counters. It counts when the core is unhalted at 100 Mhz.", @@ -322,6 +361,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -329,6 +369,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -336,6 +377,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts. \nNote: On all current platforms this event stops counting during 'thr= ottling (TM)' states duty off periods the processor is 'halted'. This even= t is clocked by base clock (100 Mhz) on Sandy Bridge. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -343,6 +385,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= (counts at 100 MHz rate).", @@ -352,6 +395,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "100003", @@ -359,6 +403,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -367,12 +412,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -381,12 +428,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -395,6 +444,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -404,6 +454,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -412,6 +463,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -421,6 +473,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -430,6 +483,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -438,6 +492,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -447,6 +502,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -455,6 +511,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -464,6 +521,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -472,6 +530,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -481,6 +540,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -490,6 +550,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -498,6 +559,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -506,6 +568,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "This event counts stalls occurred due to cha= nging prefix length (66, 67 or REX.W when they change the length of the dec= oded instruction). Occurrences counting is proportional to the number of pr= efixes in a 16B-line. This may result in the following penalties: three-cyc= le penalty for each LCP in a 16-byte chunk.", @@ -514,6 +577,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. \nNotes: INST_RETIRED.ANY is counted by a designated fixed coun= ter, leaving the four (eight when Hyperthreading is disabled) programmable = counters available for other events. INST_RETIRED.ANY_P is counted by a pro= grammable counter and it is an architectural performance event. \nCounting:= Faulting executions of GETSEC/VM entry/VM Exit/MWait will not count as ret= ired instructions.", "SampleAfterValue": "2000003", @@ -521,6 +585,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "BDM61", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -529,6 +594,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "BDM11, BDM55", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -539,6 +605,7 @@ }, { "BriefDescription": "FP operations retired. X87 FP operations tha= t have no exceptions:", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PublicDescription": "This event counts FP operations retired. For= X87 FP operations that have no exceptions counting also includes flows tha= t have several X87, or flows that use X87 uops in the exception handling.", @@ -547,6 +614,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RAT_STALL_CYCLES", "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", @@ -555,6 +623,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -565,6 +634,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -573,6 +643,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", @@ -580,6 +651,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts how many times the load op= eration got the true Block-on-Store blocking code preventing store forwardi= ng. This includes cases when:\n - preceding store conflicts with the load (= incomplete overlap);\n - store forwarding is impossible due to u-arch limit= ations;\n - preceding lock RMW operations are not forwarded;\n - store has = the no-forward bit set (uncacheable/page-split/masked stores);\n - all-bloc= king stores are used (mostly, fences and port I/O);\nand others.\nThe most = common case is a load blocked due to its address range overlapping with a p= receding smaller uncompleted store. Note: This event does not take into acc= ount cases of out-of-SW-control (for example, SbTailHit), unknown physical = STA, and cases of blocking loads on store due to being non-WB memory type o= r a lock. These cases are covered by other events.\nSee the table of not su= pported store forwards in the Optimization Guide.", @@ -588,6 +660,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "This event counts false dependencies in MOB = when the partial comparison upon loose net check and dependency was resolve= d by the Enhanced Loose net mechanism. This may not result in high performa= nce penalties. Loose net checks can fail when loads and stores are 4k alias= ed.", @@ -596,6 +669,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the hardware pr= efetch.", @@ -604,6 +678,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "This event counts all not software-prefetch = load dispatches that hit the fill buffer (FB) allocated for the software pr= efetch. It can also be incremented by some lock instructions. So it should = only be used with profiling so that the locks can be excluded by asm inspec= tion of the nearby instructions.", @@ -612,6 +687,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -620,6 +696,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -628,6 +705,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -635,6 +713,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -644,6 +723,7 @@ }, { "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "PublicDescription": "This event counts both thread-specific (TS) = and all-thread (AT) nukes.", @@ -652,6 +732,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", @@ -660,6 +741,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event counts self-modifying code (SMC) = detected, which causes a machine clear.", @@ -668,6 +750,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "SampleAfterValue": "1000003", @@ -675,6 +758,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -682,6 +766,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "SampleAfterValue": "100003", @@ -689,6 +774,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "This event counts resource-related stall cyc= les.", @@ -697,6 +783,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "PublicDescription": "This event counts ROB full stall cycles. Thi= s counts cycles that the pipeline backend blocked uop delivery from the fro= nt end.", @@ -705,6 +792,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "PublicDescription": "This event counts stall cycles caused by abs= ence of eligible entries in the reservation station (RS). This may result f= rom RS overflow, or from RS deallocation because of the RS array Write Port= allocation scheme (each RS entry has two write ports instead of four. As a= result, empty entries could not be used, although RS is not really full). = This counts cycles that the pipeline backend blocked uop delivery from the = front end.", @@ -713,6 +801,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts stall cycles caused by the= store buffer (SB) overflow (excluding draining from synch). This counts cy= cles that the pipeline backend blocked uop delivery from the front end.", @@ -721,6 +810,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "This event counts cases of saving new LBR re= cords by hardware. This assumes proper enabling of LBRs and takes into acco= unt LBR filtering done by the LBR_SELECT register.", @@ -729,6 +819,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "This event counts cycles during which the re= servation station (RS) is empty for the thread.\nNote: In ST-mode, not acti= ve thread should drive 0. This is usually caused by severely costly branch = mispredictions, or allocator/FE issues.", @@ -737,6 +828,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -747,6 +839,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -755,6 +848,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -763,6 +857,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -771,6 +866,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -779,6 +875,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -787,6 +884,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -795,6 +893,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -803,6 +902,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -811,6 +911,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -819,6 +920,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -827,6 +929,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -835,6 +938,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -843,6 +947,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -851,6 +956,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -859,6 +965,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -867,6 +974,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -875,6 +983,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -883,6 +992,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -891,6 +1001,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -901,6 +1012,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -909,6 +1021,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 0.", @@ -918,6 +1031,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -925,6 +1039,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 1.", @@ -934,6 +1049,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -941,6 +1057,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 2.", @@ -950,6 +1067,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -957,6 +1075,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 3.", @@ -966,6 +1085,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -973,6 +1093,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 4.", @@ -982,6 +1103,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -989,6 +1111,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 5.", @@ -998,6 +1121,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -1005,6 +1129,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 6.", @@ -1014,6 +1139,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -1021,6 +1147,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7", "PublicDescription": "This event counts, on the per-thread basis, = cycles during which uops are dispatched from the Reservation Station (RS) t= o port 7.", @@ -1030,6 +1157,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "SampleAfterValue": "2000003", @@ -1037,6 +1165,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of Uops issued = by the Resource Allocation Table (RAT) to the reservation station (RS).", @@ -1045,6 +1174,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops being allocated. = Such uops considered perf sensitive\n added by GSR u-arch.", @@ -1053,6 +1183,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "SampleAfterValue": "2000003", @@ -1060,6 +1191,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -1067,6 +1199,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -1077,6 +1210,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1086,6 +1220,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1095,6 +1230,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1105,6 +1241,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json index 400d784d1457..b55b305aecaa 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "LLC prefetch misses for code reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x191", @@ -12,6 +13,7 @@ }, { "BriefDescription": "LLC prefetch misses for data reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", "Filter": "filter_opc=3D0x192", @@ -23,6 +25,7 @@ }, { "BriefDescription": "LLC misses - demand and prefetch data reads -= excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=3D0x182", @@ -34,6 +37,7 @@ }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.mi= ss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_READ", "Filter": "filter_opc=3D0x187,filter_nc=3D1", @@ -45,6 +49,7 @@ }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.m= iss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "filter_opc=3D0x18f,filter_nc=3D1", @@ -56,6 +61,7 @@ }, { "BriefDescription": "PCIe write misses (full cache line). Derived = from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", @@ -67,6 +73,7 @@ }, { "BriefDescription": "LLC misses for PCIe read current. Derived fro= m unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_READ", "Filter": "filter_opc=3D0x19e", @@ -78,6 +85,7 @@ }, { "BriefDescription": "ItoM write misses (as part of fast string mem= cpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_op= code", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8", @@ -89,6 +97,7 @@ }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc= _c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", "Filter": "filter_opc=3D0x190", @@ -100,6 +109,7 @@ }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "filter_opc=3D0x187", @@ -111,6 +121,7 @@ }, { "BriefDescription": "L2 demand and L2 prefetch code references to = LLC. Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x181", @@ -122,6 +133,7 @@ }, { "BriefDescription": "PCIe writes (partial cache line). Derived fro= m unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=3D0x180,filter_tid=3D0x3e", @@ -132,6 +144,7 @@ }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_ins= erts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_READ", "Filter": "filter_opc=3D0x19e", @@ -143,6 +156,7 @@ }, { "BriefDescription": "PCIe write references (full cache line). Deri= ved from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", @@ -154,6 +168,7 @@ }, { "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "filter_opc=3D0x18c", @@ -165,6 +180,7 @@ }, { "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "filter_opc=3D0x18d", @@ -176,6 +192,7 @@ }, { "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", @@ -183,12 +200,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", @@ -197,6 +216,7 @@ }, { "BriefDescription": "FaST wire asserted", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", @@ -205,6 +225,7 @@ }, { "BriefDescription": "All LLC Misses (code+ data rd + data wr - inc= luding demand and prefetch)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", "Filter": "filter_state=3D0x1", @@ -216,6 +237,7 @@ }, { "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -225,6 +247,7 @@ }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", "PerPkg": "1", @@ -234,6 +257,7 @@ }, { "BriefDescription": "Cache Lookups; Any Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.READ", "PerPkg": "1", @@ -243,6 +267,7 @@ }, { "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -252,6 +277,7 @@ }, { "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", @@ -261,6 +287,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.F_STATE", "PerPkg": "1", @@ -279,6 +307,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.I_STATE", "PerPkg": "1", @@ -288,6 +317,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", @@ -297,6 +327,7 @@ }, { "BriefDescription": "M line evictions from LLC (writebacks to memo= ry)", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", @@ -307,6 +338,7 @@ }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", "PerPkg": "1", @@ -316,6 +348,7 @@ }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS", "PerPkg": "1", @@ -325,6 +358,7 @@ }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM", "PerPkg": "1", @@ -334,6 +368,7 @@ }, { "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", @@ -343,6 +378,7 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -352,6 +388,7 @@ }, { "BriefDescription": "Cbo Misc", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", @@ -361,6 +398,7 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", @@ -370,6 +408,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 0", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", @@ -379,6 +418,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 1", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", @@ -388,6 +428,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 2", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE2", "PerPkg": "1", @@ -397,6 +438,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE3", "PerPkg": "1", @@ -406,6 +448,7 @@ }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.LRU_DECREMENT", "PerPkg": "1", @@ -415,6 +458,7 @@ }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", "PerPkg": "1", @@ -424,6 +468,7 @@ }, { "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.ALL", "PerPkg": "1", @@ -433,6 +478,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN", "PerPkg": "1", @@ -442,6 +488,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -451,6 +498,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -460,6 +508,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP", "PerPkg": "1", @@ -469,6 +518,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -478,6 +528,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -487,6 +538,7 @@ }, { "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.ALL", "PerPkg": "1", @@ -496,6 +548,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN", "PerPkg": "1", @@ -505,6 +558,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -514,6 +568,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -523,6 +578,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP", "PerPkg": "1", @@ -532,6 +588,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -541,6 +598,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -550,6 +608,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.ALL", "PerPkg": "1", @@ -559,6 +618,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN", "PerPkg": "1", @@ -568,6 +628,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -577,6 +638,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -586,6 +648,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP", "PerPkg": "1", @@ -595,6 +658,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -604,6 +668,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -613,6 +678,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AD", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", @@ -621,6 +687,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AK", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", @@ -629,6 +696,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; BL", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", @@ -637,6 +705,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", @@ -645,6 +714,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.ANY", "PerPkg": "1", @@ -654,6 +724,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DN", "PerPkg": "1", @@ -663,6 +734,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DOWN", "PerPkg": "1", @@ -672,6 +744,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.UP", "PerPkg": "1", @@ -681,6 +754,7 @@ }, { "BriefDescription": "AD", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", @@ -689,6 +763,7 @@ }, { "BriefDescription": "AK", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", @@ -697,6 +772,7 @@ }, { "BriefDescription": "BL", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", @@ -705,6 +781,7 @@ }, { "BriefDescription": "IV", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", @@ -713,6 +790,7 @@ }, { "BriefDescription": "Number of cycles the Cbo is actively throttli= ng traffic onto the Ring in order to limit bounce traffic.", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", @@ -720,6 +798,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "PerPkg": "1", @@ -729,6 +808,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", @@ -738,6 +818,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", "PerPkg": "1", @@ -747,6 +828,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", "PerPkg": "1", @@ -756,6 +838,7 @@ }, { "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IPQ", "PerPkg": "1", @@ -765,6 +848,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ", "PerPkg": "1", @@ -774,6 +858,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", "PerPkg": "1", @@ -783,6 +868,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ", "PerPkg": "1", @@ -792,6 +878,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ", "PerPkg": "1", @@ -801,6 +888,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IPQ", "PerPkg": "1", @@ -810,6 +898,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IRQ", "PerPkg": "1", @@ -819,6 +908,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", @@ -828,6 +918,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.PRQ", "PerPkg": "1", @@ -837,6 +928,7 @@ }, { "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -846,6 +938,7 @@ }, { "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", "PerPkg": "1", @@ -855,6 +948,7 @@ }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", "PerPkg": "1", @@ -864,6 +958,7 @@ }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -873,6 +968,7 @@ }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -882,6 +978,7 @@ }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", "PerPkg": "1", @@ -891,6 +988,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -900,6 +998,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", @@ -909,6 +1008,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", @@ -918,6 +1018,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -927,6 +1028,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.NID", "PerPkg": "1", @@ -936,6 +1038,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -945,6 +1048,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", @@ -954,6 +1058,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -963,6 +1068,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -972,6 +1078,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", "PerPkg": "1", @@ -981,6 +1088,7 @@ }, { "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", "PerPkg": "1", @@ -990,6 +1098,7 @@ }, { "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", "PerPkg": "1", @@ -999,6 +1108,7 @@ }, { "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -1008,6 +1118,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", "PerPkg": "1", @@ -1017,6 +1128,7 @@ }, { "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -1026,6 +1138,7 @@ }, { "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", "PerPkg": "1", @@ -1035,6 +1148,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", "PerPkg": "1", @@ -1044,6 +1158,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -1053,6 +1168,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -1062,6 +1178,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filte= r", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", "PerPkg": "1", @@ -1071,6 +1188,7 @@ }, { "BriefDescription": "Ingress Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -1080,6 +1198,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -1089,6 +1208,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", "PerPkg": "1", @@ -1098,6 +1218,7 @@ }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ", "PerPkg": "1", @@ -1107,6 +1228,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -1116,6 +1238,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -1125,6 +1248,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -1134,6 +1258,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -1143,6 +1268,7 @@ }, { "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", @@ -1152,6 +1278,7 @@ }, { "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", @@ -1161,6 +1288,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", @@ -1170,6 +1298,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", @@ -1179,6 +1308,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", @@ -1188,6 +1318,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1197,6 +1328,7 @@ }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", @@ -1206,6 +1338,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", @@ -1215,6 +1348,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1224,6 +1358,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", @@ -1233,6 +1368,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", @@ -1242,6 +1378,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", @@ -1251,6 +1388,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", @@ -1260,6 +1398,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", @@ -1269,6 +1408,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", @@ -1278,6 +1418,7 @@ }, { "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", @@ -1287,6 +1428,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", @@ -1296,6 +1438,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", @@ -1305,6 +1448,7 @@ }, { "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", @@ -1314,6 +1458,7 @@ }, { "BriefDescription": "TOR Occupancy; Any", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.ALL", "PerPkg": "1", @@ -1323,6 +1468,7 @@ }, { "BriefDescription": "TOR Occupancy; Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", "PerPkg": "1", @@ -1332,6 +1478,7 @@ }, { "BriefDescription": "Occupancy counter for LLC data reads (demand = and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", "Filter": "filter_opc=3D0x182", @@ -1342,6 +1489,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -1351,6 +1499,7 @@ }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", @@ -1360,6 +1509,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", "PerPkg": "1", @@ -1369,6 +1519,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", "PerPkg": "1", @@ -1378,6 +1529,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1387,6 +1539,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", "PerPkg": "1", @@ -1396,6 +1549,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", "PerPkg": "1", @@ -1405,6 +1559,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1414,6 +1569,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", "PerPkg": "1", @@ -1423,6 +1579,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", "PerPkg": "1", @@ -1432,6 +1589,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", "PerPkg": "1", @@ -1441,6 +1599,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", "PerPkg": "1", @@ -1450,6 +1609,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", "PerPkg": "1", @@ -1459,6 +1619,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", "PerPkg": "1", @@ -1468,6 +1629,7 @@ }, { "BriefDescription": "TOR Occupancy; Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", @@ -1477,6 +1639,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -1486,6 +1649,7 @@ }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", @@ -1495,6 +1659,7 @@ }, { "BriefDescription": "TOR Occupancy; Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.WB", "PerPkg": "1", @@ -1504,6 +1669,7 @@ }, { "BriefDescription": "Onto AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", @@ -1512,6 +1678,7 @@ }, { "BriefDescription": "Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", @@ -1520,6 +1687,7 @@ }, { "BriefDescription": "Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", @@ -1528,6 +1696,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", "PerPkg": "1", @@ -1537,6 +1706,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CORE", "PerPkg": "1", @@ -1546,6 +1716,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", "PerPkg": "1", @@ -1555,6 +1726,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CORE", "PerPkg": "1", @@ -1564,6 +1736,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", "PerPkg": "1", @@ -1573,6 +1746,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", @@ -1582,6 +1756,7 @@ }, { "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", "PerPkg": "1", @@ -1591,6 +1766,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AD_CORE", "PerPkg": "1", @@ -1600,6 +1776,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AK_BOTH", "PerPkg": "1", @@ -1609,6 +1786,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.BL_BOTH", "PerPkg": "1", @@ -1618,6 +1796,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.IV", "PerPkg": "1", @@ -1627,6 +1806,7 @@ }, { "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE", "PerPkg": "1", @@ -1635,6 +1815,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", "PerPkg": "1", @@ -1644,6 +1825,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", "PerPkg": "1", @@ -1653,6 +1835,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", "PerPkg": "1", @@ -1662,6 +1845,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", "PerPkg": "1", @@ -1671,6 +1855,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "PerPkg": "1", @@ -1680,6 +1865,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "PerPkg": "1", @@ -1689,6 +1875,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_H_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", @@ -1696,6 +1883,7 @@ }, { "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_H_DIRECT2CORE_COUNT", "PerPkg": "1", @@ -1704,6 +1892,7 @@ }, { "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", "PerPkg": "1", @@ -1712,6 +1901,7 @@ }, { "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1720,6 +1910,7 @@ }, { "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", @@ -1728,6 +1919,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", "PerPkg": "1", @@ -1737,6 +1929,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", "PerPkg": "1", @@ -1746,6 +1939,7 @@ }, { "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1755,6 +1949,7 @@ }, { "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", "PerPkg": "1", @@ -1764,6 +1959,7 @@ }, { "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.SET", "PerPkg": "1", @@ -1773,6 +1969,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is A= ckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", "PerPkg": "1", @@ -1781,6 +1978,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; All Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALL", "PerPkg": "1", @@ -1789,6 +1987,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALLOCS", "PerPkg": "1", @@ -1797,6 +1996,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.EVICTS", "PerPkg": "1", @@ -1805,6 +2005,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.HOM", "PerPkg": "1", @@ -1813,6 +2014,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalid= ations", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.INVALS", "PerPkg": "1", @@ -1821,6 +2023,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= dCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", "PerPkg": "1", @@ -1829,6 +2032,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSP", "PerPkg": "1", @@ -1837,6 +2041,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1845,6 +2050,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1853,6 +2059,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= sSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDS", "PerPkg": "1", @@ -1861,6 +2068,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", "PerPkg": "1", @@ -1869,6 +2077,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOI", "PerPkg": "1", @@ -1877,6 +2086,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "PerPkg": "1", @@ -1885,6 +2095,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "PerPkg": "1", @@ -1893,6 +2104,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "PerPkg": "1", @@ -1901,6 +2113,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE= ", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "PerPkg": "1", @@ -1909,6 +2122,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "PerPkg": "1", @@ -1917,6 +2131,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1925,6 +2140,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1933,6 +2149,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "PerPkg": "1", @@ -1941,6 +2158,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "PerPkg": "1", @@ -1949,6 +2167,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "PerPkg": "1", @@ -1957,6 +2176,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "PerPkg": "1", @@ -1965,6 +2185,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALL", "PerPkg": "1", @@ -1973,6 +2194,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Allocations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", "PerPkg": "1", @@ -1981,6 +2203,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.HOM", "PerPkg": "1", @@ -1989,6 +2212,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Invalidations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.INVALS", "PerPkg": "1", @@ -1997,6 +2221,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "PerPkg": "1", @@ -2005,6 +2230,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSP", "PerPkg": "1", @@ -2013,6 +2239,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "PerPkg": "1", @@ -2021,6 +2248,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "PerPkg": "1", @@ -2029,6 +2257,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", "PerPkg": "1", @@ -2037,6 +2266,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "PerPkg": "1", @@ -2045,6 +2275,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", "PerPkg": "1", @@ -2053,6 +2284,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", "PerPkg": "1", @@ -2062,6 +2294,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", "PerPkg": "1", @@ -2071,6 +2304,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2", "PerPkg": "1", @@ -2080,6 +2314,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", "PerPkg": "1", @@ -2089,6 +2324,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", "PerPkg": "1", @@ -2098,6 +2334,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2", "PerPkg": "1", @@ -2107,6 +2344,7 @@ }, { "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_H_IMC_READS.NORMAL", "PerPkg": "1", @@ -2116,6 +2354,7 @@ }, { "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", @@ -2123,6 +2362,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.ALL", "PerPkg": "1", @@ -2132,6 +2372,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL", "PerPkg": "1", @@ -2141,6 +2382,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", @@ -2150,6 +2392,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -2159,6 +2402,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", @@ -2168,6 +2412,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", "PerPkg": "1", @@ -2176,6 +2421,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", "PerPkg": "1", @@ -2184,6 +2430,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0", "PerPkg": "1", @@ -2193,6 +2440,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1", "PerPkg": "1", @@ -2202,6 +2450,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS2", "PerPkg": "1", @@ -2211,6 +2460,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS3", "PerPkg": "1", @@ -2220,6 +2470,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0", "PerPkg": "1", @@ -2229,6 +2480,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1", "PerPkg": "1", @@ -2238,6 +2490,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Cancelled", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.CANCELLED", "PerPkg": "1", @@ -2247,6 +2500,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.INVITOE_LOCAL", "PerPkg": "1", @@ -2256,6 +2510,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL", "PerPkg": "1", @@ -2265,6 +2520,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL", "PerPkg": "1", @@ -2274,6 +2530,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE", "PerPkg": "1", @@ -2283,6 +2540,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE_USEFUL", "PerPkg": "1", @@ -2292,6 +2550,7 @@ }, { "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.ALL", "PerPkg": "1", @@ -2301,6 +2560,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", "PerPkg": "1", @@ -2310,6 +2570,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", "PerPkg": "1", @@ -2319,6 +2580,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", "PerPkg": "1", @@ -2328,6 +2590,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", "PerPkg": "1", @@ -2337,6 +2600,7 @@ }, { "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -2346,6 +2610,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -2355,6 +2620,7 @@ }, { "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", @@ -2364,6 +2630,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -2373,6 +2640,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -2382,6 +2650,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", @@ -2391,6 +2660,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -2400,6 +2670,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -2409,6 +2680,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW", "PerPkg": "1", @@ -2418,6 +2690,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -2427,6 +2700,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -2436,6 +2710,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW", "PerPkg": "1", @@ -2445,6 +2720,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -2454,6 +2730,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -2463,6 +2740,7 @@ }, { "BriefDescription": "HA AK Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.ALL", "PerPkg": "1", @@ -2472,6 +2750,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW", "PerPkg": "1", @@ -2481,6 +2760,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -2490,6 +2770,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -2499,6 +2780,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW", "PerPkg": "1", @@ -2508,6 +2790,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -2517,6 +2800,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -2526,6 +2810,7 @@ }, { "BriefDescription": "HA BL Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.ALL", "PerPkg": "1", @@ -2535,6 +2820,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW", "PerPkg": "1", @@ -2544,6 +2830,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -2553,6 +2840,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -2562,6 +2850,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW", "PerPkg": "1", @@ -2571,6 +2860,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -2580,6 +2870,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -2589,6 +2880,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -2598,6 +2890,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -2607,6 +2900,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -2616,6 +2910,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -2625,6 +2920,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -2634,6 +2930,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -2643,6 +2940,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -2652,6 +2950,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", @@ -2661,6 +2960,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2670,6 +2970,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2679,6 +2980,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2688,6 +2990,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2697,6 +3000,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2706,6 +3010,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2715,6 +3020,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2724,6 +3030,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2733,6 +3040,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Local Requests= ", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL", "PerPkg": "1", @@ -2742,6 +3050,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Remote Request= s", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE", "PerPkg": "1", @@ -2751,6 +3060,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL", "PerPkg": "1", @@ -2760,6 +3070,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Local Request= s", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -2769,6 +3080,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Remote Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -2778,6 +3090,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local= Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2787,6 +3100,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remot= e Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -2796,6 +3110,7 @@ }, { "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", @@ -2805,6 +3120,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -2814,6 +3130,7 @@ }, { "BriefDescription": "M line forwarded from remote cache with no wr= iteback to memory", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -2824,6 +3141,7 @@ }, { "BriefDescription": "Shared line response from remote cache", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPS", "PerPkg": "1", @@ -2834,6 +3152,7 @@ }, { "BriefDescription": "Shared line forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -2844,6 +3163,7 @@ }, { "BriefDescription": "M line forwarded from remote cache along with= writeback to memory", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -2854,6 +3174,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", "PerPkg": "1", @@ -2863,6 +3184,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", "PerPkg": "1", @@ -2872,6 +3194,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", "PerPkg": "1", @@ -2881,6 +3204,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", "PerPkg": "1", @@ -2890,6 +3214,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", "PerPkg": "1", @@ -2899,6 +3224,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", "PerPkg": "1", @@ -2908,6 +3234,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", @@ -2917,6 +3244,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", "PerPkg": "1", @@ -2926,6 +3254,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", "PerPkg": "1", @@ -2935,6 +3264,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -2944,6 +3274,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -2953,6 +3284,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -2962,6 +3294,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -2971,6 +3304,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", "PerPkg": "1", @@ -2980,6 +3314,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", "PerPkg": "1", @@ -2989,6 +3324,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", "PerPkg": "1", @@ -2998,6 +3334,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", "PerPkg": "1", @@ -3007,6 +3344,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", "PerPkg": "1", @@ -3016,6 +3354,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", "PerPkg": "1", @@ -3025,6 +3364,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", "PerPkg": "1", @@ -3034,6 +3374,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", "PerPkg": "1", @@ -3043,6 +3384,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", "PerPkg": "1", @@ -3052,6 +3394,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", "PerPkg": "1", @@ -3061,6 +3404,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", "PerPkg": "1", @@ -3070,6 +3414,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", "PerPkg": "1", @@ -3079,6 +3424,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles Completely Used", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3088,6 +3434,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Use= d", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP", "PerPkg": "1", @@ -3097,6 +3444,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "PerPkg": "1", @@ -3106,6 +3454,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -3115,6 +3464,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -3124,6 +3474,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3133,6 +3484,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3142,6 +3494,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3151,6 +3504,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3160,6 +3514,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3169,6 +3524,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3178,6 +3534,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3187,6 +3544,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -3196,6 +3554,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_H_TxR_AD.HOM", "PerPkg": "1", @@ -3205,6 +3564,7 @@ }, { "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3214,6 +3574,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3223,6 +3584,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3232,6 +3594,7 @@ }, { "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", "PerPkg": "1", @@ -3241,6 +3604,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3250,6 +3614,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3259,6 +3624,7 @@ }, { "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.ALL", "PerPkg": "1", @@ -3268,6 +3634,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", "PerPkg": "1", @@ -3277,6 +3644,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", "PerPkg": "1", @@ -3286,6 +3654,7 @@ }, { "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3295,6 +3664,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3304,6 +3674,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3313,6 +3684,7 @@ }, { "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", "PerPkg": "1", @@ -3322,6 +3694,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3331,6 +3704,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3340,6 +3714,7 @@ }, { "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.ALL", "PerPkg": "1", @@ -3349,6 +3724,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", "PerPkg": "1", @@ -3358,6 +3734,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", "PerPkg": "1", @@ -3367,6 +3744,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CACHE", "PerPkg": "1", @@ -3376,6 +3754,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CORE", "PerPkg": "1", @@ -3385,6 +3764,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_QPI", "PerPkg": "1", @@ -3394,6 +3774,7 @@ }, { "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3403,6 +3784,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3412,6 +3794,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3421,6 +3804,7 @@ }, { "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", "PerPkg": "1", @@ -3430,6 +3814,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3439,6 +3824,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3448,6 +3834,7 @@ }, { "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.ALL", "PerPkg": "1", @@ -3457,6 +3844,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", "PerPkg": "1", @@ -3466,6 +3854,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", "PerPkg": "1", @@ -3475,6 +3864,7 @@ }, { "BriefDescription": "Injection Starvation; For AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.AK", "PerPkg": "1", @@ -3484,6 +3874,7 @@ }, { "BriefDescription": "Injection Starvation; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.BL", "PerPkg": "1", @@ -3493,6 +3884,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -3502,6 +3894,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -3511,6 +3904,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -3520,6 +3914,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -3529,6 +3924,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -3538,6 +3934,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -3547,6 +3944,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -3556,6 +3954,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json index b9fb216bee16..765d44012bba 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of non data (control) flits transmitte= d . Derived from unc_q_txl_flits_g0.non_data", + "Counter": "0,1,2,3", "EventName": "QPI_CTL_BANDWIDTH_TX", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of data flits transmitted . Derived fr= om unc_q_txl_flits_g0.data", + "Counter": "0,1,2,3", "EventName": "QPI_DATA_BANDWIDTH_TX", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Number of clocks in the IRP.", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Coherent Ops; PCIItoM", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Coherent Ops; RFO", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_TIMEOUT", "PerPkg": "1", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Data Throttled", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.DATA_THROTTLE", "PerPkg": "1", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Misc Events - Set 1", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_I", "PerPkg": "1", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", @@ -260,6 +289,7 @@ }, { "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", @@ -268,6 +298,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -276,6 +307,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", @@ -284,6 +316,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -292,6 +325,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -300,6 +334,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", @@ -308,6 +343,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -316,6 +352,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -324,6 +361,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", @@ -332,6 +370,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", @@ -349,6 +389,7 @@ }, { "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", @@ -358,6 +399,7 @@ }, { "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", @@ -367,6 +409,7 @@ }, { "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", @@ -376,6 +419,7 @@ }, { "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", @@ -385,6 +429,7 @@ }, { "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", @@ -394,6 +439,7 @@ }, { "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", @@ -403,6 +449,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", "PerPkg": "1", @@ -412,6 +459,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.OTHER", "PerPkg": "1", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.RD_PREF", "PerPkg": "1", @@ -430,6 +479,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", @@ -439,6 +489,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -448,6 +499,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -457,6 +509,7 @@ }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -465,6 +518,7 @@ }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -473,6 +527,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", "PerPkg": "1", @@ -481,6 +536,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", "PerPkg": "1", @@ -489,6 +545,7 @@ }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", @@ -497,6 +554,7 @@ }, { "BriefDescription": "Number of qfclks", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", @@ -505,6 +563,7 @@ }, { "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", @@ -513,6 +572,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", @@ -522,6 +582,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", "PerPkg": "1", @@ -531,6 +592,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", @@ -540,6 +602,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss, Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", "PerPkg": "1", @@ -549,6 +612,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", "PerPkg": "1", @@ -558,6 +622,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT I= nvalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", "PerPkg": "1", @@ -567,6 +632,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss and Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", "PerPkg": "1", @@ -576,6 +642,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", "PerPkg": "1", @@ -585,6 +652,7 @@ }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", @@ -593,6 +661,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -601,6 +670,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", @@ -609,6 +679,7 @@ }, { "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", @@ -617,6 +688,7 @@ }, { "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", "PerPkg": "1", @@ -626,6 +698,7 @@ }, { "BriefDescription": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", "PerPkg": "1", @@ -634,6 +707,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", "PerPkg": "1", @@ -643,6 +717,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", "PerPkg": "1", @@ -652,6 +727,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", "PerPkg": "1", @@ -661,6 +737,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", "PerPkg": "1", @@ -670,6 +747,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", "PerPkg": "1", @@ -679,6 +757,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", "PerPkg": "1", @@ -688,6 +767,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", "PerPkg": "1", @@ -697,6 +777,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", "PerPkg": "1", @@ -706,6 +787,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", "PerPkg": "1", @@ -715,6 +797,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", "PerPkg": "1", @@ -724,6 +807,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", "PerPkg": "1", @@ -733,6 +817,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", "PerPkg": "1", @@ -742,6 +827,7 @@ }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", @@ -750,6 +836,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", @@ -758,6 +845,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", "PerPkg": "1", @@ -767,6 +855,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", "PerPkg": "1", @@ -776,6 +865,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", "PerPkg": "1", @@ -785,6 +875,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", "PerPkg": "1", @@ -794,6 +885,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", "PerPkg": "1", @@ -803,6 +895,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", "PerPkg": "1", @@ -812,6 +905,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", "PerPkg": "1", @@ -821,6 +915,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", "PerPkg": "1", @@ -830,6 +925,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", "PerPkg": "1", @@ -839,6 +935,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", "PerPkg": "1", @@ -848,6 +945,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", "PerPkg": "1", @@ -857,6 +955,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", "PerPkg": "1", @@ -866,6 +965,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", @@ -875,6 +975,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", @@ -884,6 +985,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", @@ -893,6 +995,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", @@ -902,6 +1005,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", @@ -911,6 +1015,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", @@ -920,6 +1025,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", @@ -929,6 +1035,7 @@ }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", @@ -938,6 +1045,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", @@ -947,6 +1055,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -956,6 +1065,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -965,6 +1075,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", @@ -974,6 +1085,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -983,6 +1095,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -992,6 +1105,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", @@ -1000,6 +1114,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", "PerPkg": "1", @@ -1009,6 +1124,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", "PerPkg": "1", @@ -1018,6 +1134,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", "PerPkg": "1", @@ -1027,6 +1144,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", "PerPkg": "1", @@ -1036,6 +1154,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", "PerPkg": "1", @@ -1045,6 +1164,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", "PerPkg": "1", @@ -1054,6 +1174,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", "PerPkg": "1", @@ -1063,6 +1184,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", "PerPkg": "1", @@ -1072,6 +1194,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", "PerPkg": "1", @@ -1081,6 +1204,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", "PerPkg": "1", @@ -1090,6 +1214,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", "PerPkg": "1", @@ -1099,6 +1224,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", "PerPkg": "1", @@ -1108,6 +1234,7 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", @@ -1116,6 +1243,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", "PerPkg": "1", @@ -1125,6 +1253,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", "PerPkg": "1", @@ -1134,6 +1263,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", "PerPkg": "1", @@ -1143,6 +1273,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", "PerPkg": "1", @@ -1152,6 +1283,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", "PerPkg": "1", @@ -1161,6 +1293,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", "PerPkg": "1", @@ -1170,6 +1303,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", "PerPkg": "1", @@ -1179,6 +1313,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", "PerPkg": "1", @@ -1188,6 +1323,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", "PerPkg": "1", @@ -1197,6 +1333,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", "PerPkg": "1", @@ -1206,6 +1343,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", "PerPkg": "1", @@ -1215,6 +1353,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", "PerPkg": "1", @@ -1224,6 +1363,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", "PerPkg": "1", @@ -1233,6 +1373,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", "PerPkg": "1", @@ -1242,6 +1383,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", "PerPkg": "1", @@ -1251,6 +1393,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", "PerPkg": "1", @@ -1260,6 +1403,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", "PerPkg": "1", @@ -1269,6 +1413,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", "PerPkg": "1", @@ -1278,6 +1423,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", "PerPkg": "1", @@ -1287,6 +1433,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.GV", "PerPkg": "1", @@ -1296,6 +1443,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", "PerPkg": "1", @@ -1305,6 +1453,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", "PerPkg": "1", @@ -1314,6 +1463,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", "PerPkg": "1", @@ -1323,6 +1473,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", "PerPkg": "1", @@ -1332,6 +1483,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", "PerPkg": "1", @@ -1341,6 +1493,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", "PerPkg": "1", @@ -1350,6 +1503,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -1358,6 +1512,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", @@ -1366,6 +1521,7 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", @@ -1374,6 +1530,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", "PerPkg": "1", @@ -1383,6 +1540,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", "PerPkg": "1", @@ -1392,6 +1550,7 @@ }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", @@ -1400,6 +1559,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", @@ -1408,6 +1568,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", @@ -1416,6 +1577,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency.", @@ -1424,6 +1586,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of data flits transmitted over QPI on the DR= S (Data Response) channel. DRS flits are used to transmit data with cohere= ncy. This does not count data flits transmitted over the NCB channel which= transmits non-coherent data. This includes only the data flits (not the h= eader).", @@ -1432,6 +1595,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of protocol flits transmitted over QPI on th= e DRS (Data Response) channel. DRS flits are used to transmit data with co= herency. This does not count data flits transmitted over the NCB channel w= hich transmits non-coherent data. This includes only the header flits (not= the data). This includes extended headers.", @@ -1440,6 +1604,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of flits transmitted over QPI on the home channel.= ", @@ -1448,6 +1613,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of non-request flits transmitted over QPI on the h= ome channel. These are most commonly snoop responses, and this event can b= e used as a proxy for that.", @@ -1456,6 +1622,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of data request transmitted over QPI on the home c= hannel. This basically counts the number of remote memory requests transmi= tted over QPI. In conjunction with the local read count in the Home Agent,= one can calculate the number of LLC Misses.", @@ -1464,6 +1631,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of snoop request flits transmitted over QPI. Thes= e requests are contained in the snoop channel. This does not include snoop= responses, which are transmitted on the home channel.", @@ -1472,6 +1640,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", @@ -1481,6 +1650,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -1490,6 +1660,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -1499,6 +1670,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", @@ -1508,6 +1680,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -1517,6 +1690,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -1526,6 +1700,7 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", @@ -1534,6 +1709,7 @@ }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", @@ -1542,6 +1718,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1551,6 +1728,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1560,6 +1738,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1569,6 +1748,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1578,6 +1758,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1587,6 +1768,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1596,6 +1778,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1605,6 +1788,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1614,6 +1798,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1623,6 +1808,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1632,6 +1818,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1641,6 +1828,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1650,6 +1838,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", "PerPkg": "1", @@ -1658,6 +1847,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", "PerPkg": "1", @@ -1666,6 +1856,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1675,6 +1866,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1684,6 +1876,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shar= ed VN", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", "PerPkg": "1", @@ -1693,6 +1886,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1702,6 +1896,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1711,6 +1906,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for S= hared VN", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", "PerPkg": "1", @@ -1720,6 +1916,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1729,6 +1926,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1738,6 +1936,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1747,6 +1946,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1756,6 +1956,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1765,6 +1966,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1774,6 +1976,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1783,6 +1986,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1792,6 +1996,7 @@ }, { "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", @@ -1800,6 +2005,7 @@ }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", @@ -1808,6 +2014,7 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_R3_CLOCKTICKS", "PerPkg": "1", @@ -1816,6 +2023,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", "PerPkg": "1", @@ -1825,6 +2033,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", "PerPkg": "1", @@ -1834,6 +2043,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", "PerPkg": "1", @@ -1843,6 +2053,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", "PerPkg": "1", @@ -1852,6 +2063,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", "PerPkg": "1", @@ -1861,6 +2073,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", "PerPkg": "1", @@ -1870,6 +2083,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", "PerPkg": "1", @@ -1879,6 +2093,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", "PerPkg": "1", @@ -1888,6 +2103,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", "PerPkg": "1", @@ -1897,6 +2113,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", "PerPkg": "1", @@ -1906,6 +2123,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", "PerPkg": "1", @@ -1915,6 +2133,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", "PerPkg": "1", @@ -1924,6 +2143,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", "PerPkg": "1", @@ -1933,6 +2153,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", "PerPkg": "1", @@ -1942,6 +2163,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", "PerPkg": "1", @@ -1951,6 +2173,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", "PerPkg": "1", @@ -1960,6 +2183,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", "PerPkg": "1", @@ -1969,6 +2193,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", "PerPkg": "1", @@ -1978,6 +2203,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", "PerPkg": "1", @@ -1987,6 +2213,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", "PerPkg": "1", @@ -1996,6 +2223,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", "PerPkg": "1", @@ -2004,6 +2232,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", "PerPkg": "1", @@ -2012,6 +2241,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0xD", "EventName": "UNC_R3_IOT_CTS_HI.CTS2", "PerPkg": "1", @@ -2021,6 +2251,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0xD", "EventName": "UNC_R3_IOT_CTS_HI.CTS3", "PerPkg": "1", @@ -2030,6 +2261,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0xC", "EventName": "UNC_R3_IOT_CTS_LO.CTS0", "PerPkg": "1", @@ -2039,6 +2271,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0xC", "EventName": "UNC_R3_IOT_CTS_LO.CTS1", "PerPkg": "1", @@ -2048,6 +2281,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2057,6 +2291,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2066,6 +2301,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2075,6 +2311,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2084,6 +2321,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2093,6 +2331,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2102,6 +2341,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2111,6 +2351,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2120,6 +2361,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2129,6 +2371,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2138,6 +2381,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2147,6 +2391,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2156,6 +2401,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2165,6 +2411,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2174,6 +2421,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2183,6 +2431,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2192,6 +2441,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2201,6 +2451,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2210,6 +2461,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2219,6 +2471,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2228,6 +2481,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2237,6 +2491,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2246,6 +2501,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; All", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.ALL", "PerPkg": "1", @@ -2255,6 +2511,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW", "PerPkg": "1", @@ -2264,6 +2521,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -2273,6 +2531,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -2282,6 +2541,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW", "PerPkg": "1", @@ -2291,6 +2551,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -2300,6 +2561,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -2309,6 +2571,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; All", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.ALL", "PerPkg": "1", @@ -2318,6 +2581,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW", "PerPkg": "1", @@ -2327,6 +2591,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -2336,6 +2601,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -2345,6 +2611,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW", "PerPkg": "1", @@ -2354,6 +2621,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -2363,6 +2631,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -2372,6 +2641,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; All", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.ALL", "PerPkg": "1", @@ -2381,6 +2651,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW", "PerPkg": "1", @@ -2390,6 +2661,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -2399,6 +2671,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -2408,6 +2681,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW", "PerPkg": "1", @@ -2417,6 +2691,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -2426,6 +2701,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -2435,6 +2711,7 @@ }, { "BriefDescription": "R3 IV Ring in Use; Any", + "Counter": "0,1,2", "EventCode": "0xA", "EventName": "UNC_R3_RING_IV_USED.ANY", "PerPkg": "1", @@ -2444,6 +2721,7 @@ }, { "BriefDescription": "R3 IV Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0xA", "EventName": "UNC_R3_RING_IV_USED.CW", "PerPkg": "1", @@ -2453,6 +2731,7 @@ }, { "BriefDescription": "Ring Stop Starved; AK", + "Counter": "0,1,2", "EventCode": "0xE", "EventName": "UNC_R3_RING_SINK_STARVED.AK", "PerPkg": "1", @@ -2462,6 +2741,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", "PerPkg": "1", @@ -2471,6 +2751,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", "PerPkg": "1", @@ -2480,6 +2761,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", "PerPkg": "1", @@ -2489,6 +2771,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", "PerPkg": "1", @@ -2498,6 +2781,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", "PerPkg": "1", @@ -2507,6 +2791,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", "PerPkg": "1", @@ -2516,6 +2801,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", "PerPkg": "1", @@ -2525,6 +2811,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", "PerPkg": "1", @@ -2534,6 +2821,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", "PerPkg": "1", @@ -2543,6 +2831,7 @@ }, { "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.DRS", "PerPkg": "1", @@ -2552,6 +2841,7 @@ }, { "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.HOM", "PerPkg": "1", @@ -2561,6 +2851,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCB", "PerPkg": "1", @@ -2570,6 +2861,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCS", "PerPkg": "1", @@ -2579,6 +2871,7 @@ }, { "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NDR", "PerPkg": "1", @@ -2588,6 +2881,7 @@ }, { "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.SNP", "PerPkg": "1", @@ -2597,6 +2891,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", "PerPkg": "1", @@ -2606,6 +2901,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", "PerPkg": "1", @@ -2615,6 +2911,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", "PerPkg": "1", @@ -2624,6 +2921,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", "PerPkg": "1", @@ -2633,6 +2931,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", "PerPkg": "1", @@ -2642,6 +2941,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", "PerPkg": "1", @@ -2651,6 +2951,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", "PerPkg": "1", @@ -2660,6 +2961,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", "PerPkg": "1", @@ -2669,6 +2971,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", "PerPkg": "1", @@ -2678,6 +2981,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", "PerPkg": "1", @@ -2687,6 +2991,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", "PerPkg": "1", @@ -2696,6 +3001,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", "PerPkg": "1", @@ -2705,6 +3011,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2714,6 +3021,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2723,6 +3031,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2732,6 +3041,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2741,6 +3051,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2750,6 +3061,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2759,6 +3071,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2B", "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2768,6 +3081,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2B", "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2777,6 +3091,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -2786,6 +3101,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -2795,6 +3111,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -2804,6 +3121,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -2813,6 +3131,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_AD", "PerPkg": "1", @@ -2822,6 +3141,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_AK", "PerPkg": "1", @@ -2831,6 +3151,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_BL", "PerPkg": "1", @@ -2840,6 +3161,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_AD", "PerPkg": "1", @@ -2849,6 +3171,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_AK", "PerPkg": "1", @@ -2858,6 +3181,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_BL", "PerPkg": "1", @@ -2867,6 +3191,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2876,6 +3201,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2885,6 +3211,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -2894,6 +3221,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -2903,6 +3231,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -2912,6 +3241,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -2921,6 +3251,7 @@ }, { "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", @@ -2930,6 +3261,7 @@ }, { "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", @@ -2939,6 +3271,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", @@ -2948,6 +3281,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", "PerPkg": "1", @@ -2957,6 +3291,7 @@ }, { "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", "PerPkg": "1", @@ -2966,6 +3301,7 @@ }, { "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", "PerPkg": "1", @@ -2975,6 +3311,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2984,6 +3321,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2993,6 +3331,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -3002,6 +3341,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -3011,6 +3351,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -3020,6 +3361,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -3029,6 +3371,7 @@ }, { "BriefDescription": "VN1 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", "PerPkg": "1", @@ -3038,6 +3381,7 @@ }, { "BriefDescription": "VN1 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", "PerPkg": "1", @@ -3047,6 +3391,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", "PerPkg": "1", @@ -3056,6 +3401,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", "PerPkg": "1", @@ -3065,6 +3411,7 @@ }, { "BriefDescription": "VN1 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", "PerPkg": "1", @@ -3074,6 +3421,7 @@ }, { "BriefDescription": "VN1 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", "PerPkg": "1", @@ -3083,6 +3431,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -3092,6 +3441,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -3101,6 +3451,7 @@ }, { "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -3110,6 +3461,7 @@ }, { "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -3119,6 +3471,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -3128,6 +3481,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -3137,6 +3491,7 @@ }, { "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -3146,6 +3501,7 @@ }, { "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -3155,6 +3511,7 @@ }, { "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_S_BOUNCE_CONTROL", "PerPkg": "1", @@ -3162,12 +3519,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_S_CLOCKTICKS", "PerPkg": "1", "Unit": "SBOX" }, { "BriefDescription": "FaST wire asserted", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_S_FAST_ASSERTED", "PerPkg": "1", @@ -3176,6 +3535,7 @@ }, { "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.ALL", "PerPkg": "1", @@ -3185,6 +3545,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN", "PerPkg": "1", @@ -3194,6 +3555,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -3203,6 +3565,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -3212,6 +3575,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP", "PerPkg": "1", @@ -3221,6 +3585,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -3230,6 +3595,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -3239,6 +3605,7 @@ }, { "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.ALL", "PerPkg": "1", @@ -3248,6 +3615,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN", "PerPkg": "1", @@ -3257,6 +3625,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -3266,6 +3635,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -3275,6 +3645,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP", "PerPkg": "1", @@ -3284,6 +3655,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -3293,6 +3665,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -3302,6 +3675,7 @@ }, { "BriefDescription": "BL Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.ALL", "PerPkg": "1", @@ -3311,6 +3685,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN", "PerPkg": "1", @@ -3320,6 +3695,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -3329,6 +3705,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -3338,6 +3715,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP", "PerPkg": "1", @@ -3347,6 +3725,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -3356,6 +3735,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -3365,6 +3745,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", @@ -3373,6 +3754,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", @@ -3381,6 +3763,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", @@ -3389,6 +3772,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", @@ -3397,6 +3781,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_S_RING_IV_USED.DN", "PerPkg": "1", @@ -3406,6 +3791,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_S_RING_IV_USED.UP", "PerPkg": "1", @@ -3415,6 +3801,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", @@ -3423,6 +3810,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", @@ -3431,6 +3819,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", @@ -3439,6 +3828,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", @@ -3447,6 +3837,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", @@ -3456,6 +3847,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", @@ -3465,6 +3857,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", @@ -3474,6 +3867,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", @@ -3483,6 +3877,7 @@ }, { "BriefDescription": "Bypass; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AD_BNC", "PerPkg": "1", @@ -3492,6 +3887,7 @@ }, { "BriefDescription": "Bypass; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AD_CRD", "PerPkg": "1", @@ -3501,6 +3897,7 @@ }, { "BriefDescription": "Bypass; AK", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AK", "PerPkg": "1", @@ -3510,6 +3907,7 @@ }, { "BriefDescription": "Bypass; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.BL_BNC", "PerPkg": "1", @@ -3519,6 +3917,7 @@ }, { "BriefDescription": "Bypass; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.BL_CRD", "PerPkg": "1", @@ -3528,6 +3927,7 @@ }, { "BriefDescription": "Bypass; IV", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.IV", "PerPkg": "1", @@ -3537,6 +3937,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", @@ -3546,6 +3947,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", @@ -3555,6 +3957,7 @@ }, { "BriefDescription": "Injection Starvation; AK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AK", "PerPkg": "1", @@ -3564,6 +3967,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", @@ -3573,6 +3977,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", @@ -3582,6 +3987,7 @@ }, { "BriefDescription": "Injection Starvation; IVF Credit", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.IFV", "PerPkg": "1", @@ -3591,6 +3997,7 @@ }, { "BriefDescription": "Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.IV", "PerPkg": "1", @@ -3600,6 +4007,7 @@ }, { "BriefDescription": "Ingress Allocations; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AD_BNC", "PerPkg": "1", @@ -3609,6 +4017,7 @@ }, { "BriefDescription": "Ingress Allocations; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AD_CRD", "PerPkg": "1", @@ -3618,6 +4027,7 @@ }, { "BriefDescription": "Ingress Allocations; AK", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AK", "PerPkg": "1", @@ -3627,6 +4037,7 @@ }, { "BriefDescription": "Ingress Allocations; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.BL_BNC", "PerPkg": "1", @@ -3636,6 +4047,7 @@ }, { "BriefDescription": "Ingress Allocations; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.BL_CRD", "PerPkg": "1", @@ -3645,6 +4057,7 @@ }, { "BriefDescription": "Ingress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.IV", "PerPkg": "1", @@ -3654,6 +4067,7 @@ }, { "BriefDescription": "Ingress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", "PerPkg": "1", @@ -3663,6 +4077,7 @@ }, { "BriefDescription": "Ingress Occupancy; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", @@ -3672,6 +4087,7 @@ }, { "BriefDescription": "Ingress Occupancy; AK", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AK", "PerPkg": "1", @@ -3681,6 +4097,7 @@ }, { "BriefDescription": "Ingress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", @@ -3690,6 +4107,7 @@ }, { "BriefDescription": "Ingress Occupancy; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", @@ -3699,6 +4117,7 @@ }, { "BriefDescription": "Ingress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.IV", "PerPkg": "1", @@ -3708,6 +4127,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.AD", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.AD", "PerPkg": "1", @@ -3716,6 +4136,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.AK", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.AK", "PerPkg": "1", @@ -3724,6 +4145,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.BL", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.BL", "PerPkg": "1", @@ -3732,6 +4154,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AD_BNC", "PerPkg": "1", @@ -3741,6 +4164,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AD_CRD", "PerPkg": "1", @@ -3750,6 +4174,7 @@ }, { "BriefDescription": "Egress Allocations; AK", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AK", "PerPkg": "1", @@ -3759,6 +4184,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.BL_BNC", "PerPkg": "1", @@ -3768,6 +4194,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.BL_CRD", "PerPkg": "1", @@ -3777,6 +4204,7 @@ }, { "BriefDescription": "Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.IV", "PerPkg": "1", @@ -3786,6 +4214,7 @@ }, { "BriefDescription": "Egress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", "PerPkg": "1", @@ -3795,6 +4224,7 @@ }, { "BriefDescription": "Egress Occupancy; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", "PerPkg": "1", @@ -3804,6 +4234,7 @@ }, { "BriefDescription": "Egress Occupancy; AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AK", "PerPkg": "1", @@ -3813,6 +4244,7 @@ }, { "BriefDescription": "Egress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", "PerPkg": "1", @@ -3822,6 +4254,7 @@ }, { "BriefDescription": "Egress Occupancy; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", "PerPkg": "1", @@ -3831,6 +4264,7 @@ }, { "BriefDescription": "Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.IV", "PerPkg": "1", @@ -3840,6 +4274,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.AD", "PerPkg": "1", @@ -3849,6 +4284,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.AK", "PerPkg": "1", @@ -3858,6 +4294,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.BL", "PerPkg": "1", @@ -3867,6 +4304,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.IV", "PerPkg": "1", @@ -3876,6 +4314,7 @@ }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", @@ -3883,6 +4322,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", @@ -3892,6 +4332,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", @@ -3901,6 +4342,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", @@ -3910,6 +4352,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", @@ -3919,6 +4362,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", @@ -3928,6 +4372,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", @@ -3937,6 +4382,7 @@ }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", @@ -3945,6 +4391,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", @@ -3954,6 +4401,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", @@ -3963,6 +4411,7 @@ }, { "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", @@ -3972,6 +4421,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", @@ -3981,6 +4431,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", @@ -3990,6 +4441,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", @@ -3999,6 +4451,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", @@ -4008,6 +4461,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json b/too= ls/perf/pmu-events/arch/x86/broadwellx/uncore-io.json index 01e04daf03da..daef7accdbcb 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_R2_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -50,6 +56,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -59,6 +66,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -68,6 +76,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -77,6 +86,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -86,6 +96,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -95,6 +106,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.ALL", "PerPkg": "1", @@ -104,6 +116,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW", "PerPkg": "1", @@ -113,6 +126,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -122,6 +136,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -131,6 +146,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW", "PerPkg": "1", @@ -140,6 +156,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -149,6 +166,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -158,6 +176,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Dn", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.DN", "PerPkg": "1", @@ -167,6 +186,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Up", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.UP", "PerPkg": "1", @@ -176,6 +196,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.ALL", "PerPkg": "1", @@ -185,6 +206,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW", "PerPkg": "1", @@ -194,6 +216,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -203,6 +226,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -212,6 +236,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW", "PerPkg": "1", @@ -221,6 +246,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -230,6 +256,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -239,6 +266,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; All", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.ALL", "PerPkg": "1", @@ -248,6 +276,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW", "PerPkg": "1", @@ -257,6 +286,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -266,6 +296,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -275,6 +306,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW", "PerPkg": "1", @@ -284,6 +316,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -293,6 +326,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -302,6 +336,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.ANY", "PerPkg": "1", @@ -311,6 +346,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CCW", "PerPkg": "1", @@ -320,6 +356,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CW", "PerPkg": "1", @@ -329,6 +366,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -338,6 +376,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -347,6 +386,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCB", "PerPkg": "1", @@ -356,6 +396,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCS", "PerPkg": "1", @@ -365,6 +406,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -374,6 +416,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -383,6 +426,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -392,6 +436,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -401,6 +446,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -410,6 +456,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -419,6 +466,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -428,6 +476,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -437,6 +486,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -446,6 +496,7 @@ }, { "BriefDescription": "Egress Cycles Full; AD", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", "PerPkg": "1", @@ -455,6 +506,7 @@ }, { "BriefDescription": "Egress Cycles Full; AK", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", "PerPkg": "1", @@ -464,6 +516,7 @@ }, { "BriefDescription": "Egress Cycles Full; BL", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", "PerPkg": "1", @@ -473,6 +526,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AD", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AD", "PerPkg": "1", @@ -482,6 +536,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AK", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AK", "PerPkg": "1", @@ -491,6 +546,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; BL", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.BL", "PerPkg": "1", @@ -500,6 +556,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", "PerPkg": "1", @@ -509,6 +566,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", "PerPkg": "1", @@ -518,6 +576,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", "PerPkg": "1", @@ -527,6 +586,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", "PerPkg": "1", @@ -536,6 +596,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", "PerPkg": "1", @@ -545,6 +606,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json index b5a33e7a68c6..45555316f8ea 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,6 +23,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", @@ -30,6 +33,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", @@ -39,6 +43,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -48,6 +53,7 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", @@ -56,6 +62,7 @@ }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", @@ -72,6 +80,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -81,6 +90,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -90,6 +100,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -99,6 +110,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Clockticks in the Memory Controller using a d= edicated 48-bit Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -158,18 +176,21 @@ }, { "BriefDescription": "Clockticks in the Memory Controller using one= of the programmable counters", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS_P", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_CLOCKTICKS_P", + "Counter": "0,1,2,3", "EventName": "UNC_M_DCLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", @@ -178,6 +199,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -196,6 +219,7 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", @@ -231,6 +258,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", @@ -240,6 +268,7 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", @@ -248,6 +277,7 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "PerPkg": "1", @@ -256,6 +286,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", @@ -265,6 +296,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", @@ -274,6 +306,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", @@ -283,6 +316,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", @@ -292,6 +326,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", @@ -301,6 +336,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", @@ -310,6 +346,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", @@ -319,6 +356,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", @@ -328,6 +366,7 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", @@ -336,6 +375,7 @@ }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -343,6 +383,7 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "PerPkg": "1", @@ -351,6 +392,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", @@ -360,6 +402,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", @@ -369,6 +412,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", @@ -378,6 +422,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", @@ -387,6 +432,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", @@ -396,6 +442,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", @@ -405,6 +452,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", @@ -414,6 +462,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", @@ -423,6 +472,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", @@ -432,6 +482,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", @@ -441,6 +492,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", "PerPkg": "1", @@ -450,6 +502,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", @@ -459,6 +512,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -468,6 +522,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -477,6 +532,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -486,6 +542,7 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", @@ -494,6 +551,7 @@ }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", @@ -502,6 +560,7 @@ }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", @@ -510,6 +569,7 @@ }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", @@ -518,6 +578,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -527,6 +588,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", @@ -535,6 +597,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", @@ -544,6 +607,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", @@ -553,6 +617,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", @@ -562,6 +627,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", @@ -571,6 +637,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", @@ -580,6 +647,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", @@ -589,6 +657,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", @@ -598,6 +667,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", @@ -607,6 +677,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", @@ -616,6 +687,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", @@ -625,6 +697,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", @@ -634,6 +707,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", @@ -643,6 +717,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", @@ -652,6 +727,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", @@ -661,6 +737,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", @@ -670,6 +747,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -679,6 +757,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -688,6 +767,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -697,6 +777,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -706,6 +787,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -715,6 +797,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", @@ -723,6 +806,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", @@ -732,6 +816,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", @@ -741,6 +826,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", @@ -750,6 +836,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", @@ -759,6 +846,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", @@ -768,6 +856,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", @@ -777,6 +866,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", @@ -786,6 +876,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", @@ -795,6 +886,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", @@ -804,6 +896,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", @@ -813,6 +906,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", @@ -822,6 +916,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", @@ -831,6 +926,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", @@ -840,6 +936,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", @@ -849,6 +946,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", @@ -858,6 +956,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -867,6 +966,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -876,6 +976,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -885,6 +986,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -894,6 +996,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", @@ -902,6 +1005,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -911,6 +1015,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", @@ -919,6 +1024,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", @@ -928,6 +1034,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", @@ -937,6 +1044,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", @@ -946,6 +1054,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", @@ -955,6 +1064,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", @@ -964,6 +1074,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", @@ -973,6 +1084,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", @@ -982,6 +1094,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", @@ -991,6 +1104,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", @@ -1000,6 +1114,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", @@ -1009,6 +1124,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", @@ -1018,6 +1134,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", @@ -1027,6 +1144,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", @@ -1036,6 +1154,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", @@ -1045,6 +1164,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", @@ -1054,6 +1174,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -1063,6 +1184,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -1072,6 +1194,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -1081,6 +1204,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -1090,6 +1214,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -1099,6 +1224,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", @@ -1107,6 +1233,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", @@ -1116,6 +1243,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", @@ -1125,6 +1253,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", @@ -1134,6 +1263,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", @@ -1143,6 +1273,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", @@ -1152,6 +1283,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", @@ -1161,6 +1293,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", @@ -1170,6 +1303,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", @@ -1179,6 +1313,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", @@ -1188,6 +1323,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", @@ -1197,6 +1333,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", @@ -1206,6 +1343,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", @@ -1215,6 +1353,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", @@ -1224,6 +1363,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", @@ -1233,6 +1373,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", @@ -1242,6 +1383,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -1251,6 +1393,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -1260,6 +1403,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -1269,6 +1413,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -1278,6 +1423,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -1287,6 +1433,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", @@ -1295,6 +1442,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", @@ -1304,6 +1452,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", @@ -1313,6 +1462,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", @@ -1322,6 +1472,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", @@ -1331,6 +1482,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", @@ -1340,6 +1492,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", @@ -1349,6 +1502,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", @@ -1358,6 +1512,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", @@ -1367,6 +1522,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", @@ -1376,6 +1532,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", @@ -1385,6 +1542,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", @@ -1394,6 +1552,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", @@ -1403,6 +1562,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", @@ -1412,6 +1572,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", @@ -1421,6 +1582,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", @@ -1430,6 +1592,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -1439,6 +1602,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -1448,6 +1612,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -1457,6 +1622,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -1466,6 +1632,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -1475,6 +1642,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", @@ -1483,6 +1651,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", @@ -1492,6 +1661,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", @@ -1501,6 +1671,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", @@ -1510,6 +1681,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", @@ -1519,6 +1691,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", @@ -1528,6 +1701,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", @@ -1537,6 +1711,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", @@ -1546,6 +1721,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", @@ -1555,6 +1731,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", @@ -1564,6 +1741,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", @@ -1573,6 +1751,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", @@ -1582,6 +1761,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", @@ -1591,6 +1771,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", @@ -1600,6 +1781,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", @@ -1609,6 +1791,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", @@ -1618,6 +1801,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -1627,6 +1811,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -1636,6 +1821,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -1645,6 +1831,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", @@ -1654,6 +1841,7 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", @@ -1662,6 +1850,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -1670,6 +1859,7 @@ }, { "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", @@ -1677,6 +1867,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", @@ -1685,6 +1876,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", @@ -1693,6 +1885,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", @@ -1701,6 +1894,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", @@ -1709,6 +1903,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", @@ -1717,6 +1912,7 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", @@ -1725,6 +1921,7 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", @@ -1733,6 +1930,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", @@ -1741,6 +1939,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", @@ -1749,6 +1948,7 @@ }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", @@ -1756,6 +1956,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -1765,6 +1966,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", @@ -1773,6 +1975,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", @@ -1782,6 +1985,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", @@ -1791,6 +1995,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", @@ -1800,6 +2005,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", @@ -1809,6 +2015,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", @@ -1818,6 +2025,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", @@ -1827,6 +2035,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", @@ -1836,6 +2045,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", @@ -1845,6 +2055,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", @@ -1854,6 +2065,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", @@ -1863,6 +2075,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", @@ -1872,6 +2085,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", @@ -1881,6 +2095,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", @@ -1890,6 +2105,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", @@ -1899,6 +2115,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", @@ -1908,6 +2125,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -1917,6 +2135,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -1926,6 +2145,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -1935,6 +2155,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -1944,6 +2165,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -1953,6 +2175,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", @@ -1961,6 +2184,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", @@ -1970,6 +2194,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", @@ -1979,6 +2204,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", @@ -1988,6 +2214,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", @@ -1997,6 +2224,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", @@ -2006,6 +2234,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", @@ -2015,6 +2244,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", @@ -2024,6 +2254,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", @@ -2033,6 +2264,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", @@ -2042,6 +2274,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", @@ -2051,6 +2284,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", @@ -2060,6 +2294,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", @@ -2069,6 +2304,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", @@ -2078,6 +2314,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", @@ -2087,6 +2324,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", @@ -2096,6 +2334,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -2105,6 +2344,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -2114,6 +2354,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -2123,6 +2364,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -2132,6 +2374,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -2141,6 +2384,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", @@ -2149,6 +2393,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", @@ -2158,6 +2403,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", @@ -2167,6 +2413,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", @@ -2176,6 +2423,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", @@ -2185,6 +2433,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", @@ -2194,6 +2443,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", @@ -2203,6 +2453,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", @@ -2212,6 +2463,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", @@ -2221,6 +2473,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", @@ -2230,6 +2483,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", @@ -2239,6 +2493,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", @@ -2248,6 +2503,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", @@ -2257,6 +2513,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", @@ -2266,6 +2523,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", @@ -2275,6 +2533,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", @@ -2284,6 +2543,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -2293,6 +2553,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -2302,6 +2563,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -2311,6 +2573,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -2320,6 +2583,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -2329,6 +2593,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", @@ -2337,6 +2602,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", @@ -2346,6 +2612,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", @@ -2355,6 +2622,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", @@ -2364,6 +2632,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", @@ -2373,6 +2642,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", @@ -2382,6 +2652,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", @@ -2391,6 +2662,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", @@ -2400,6 +2672,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", @@ -2409,6 +2682,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", @@ -2418,6 +2692,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", @@ -2427,6 +2702,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", @@ -2436,6 +2712,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", @@ -2445,6 +2722,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", @@ -2454,6 +2732,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", @@ -2463,6 +2742,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", @@ -2472,6 +2752,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -2481,6 +2762,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -2490,6 +2772,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -2499,6 +2782,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -2508,6 +2792,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -2517,6 +2802,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", @@ -2525,6 +2811,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", @@ -2534,6 +2821,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", @@ -2543,6 +2831,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", @@ -2552,6 +2841,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", @@ -2561,6 +2851,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", @@ -2570,6 +2861,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", @@ -2579,6 +2871,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", @@ -2588,6 +2881,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", @@ -2597,6 +2891,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", @@ -2606,6 +2901,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", @@ -2615,6 +2911,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", @@ -2624,6 +2921,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", @@ -2633,6 +2931,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", @@ -2642,6 +2941,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", @@ -2651,6 +2951,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", @@ -2660,6 +2961,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -2669,6 +2971,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -2678,6 +2981,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -2687,6 +2991,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -2696,6 +3001,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -2705,6 +3011,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", @@ -2713,6 +3020,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", @@ -2722,6 +3030,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", @@ -2731,6 +3040,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", @@ -2740,6 +3050,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", @@ -2749,6 +3060,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", @@ -2758,6 +3070,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", @@ -2767,6 +3080,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", @@ -2776,6 +3090,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", @@ -2785,6 +3100,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", @@ -2794,6 +3110,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", @@ -2803,6 +3120,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", @@ -2812,6 +3130,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", @@ -2821,6 +3140,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", @@ -2830,6 +3150,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", @@ -2839,6 +3160,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", @@ -2848,6 +3170,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -2857,6 +3180,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -2866,6 +3190,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -2875,6 +3200,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json b/= tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json index 320aaab53a0b..afdc636b9855 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", "PerPkg": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", "PerPkg": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", "PerPkg": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", "PerPkg": "1", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", "PerPkg": "1", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", "PerPkg": "1", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", "PerPkg": "1", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS_CORE0", "PerPkg": "1", @@ -160,6 +180,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_P_DEMOTIONS_CORE1", "PerPkg": "1", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_P_DEMOTIONS_CORE10", "PerPkg": "1", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3B", "EventName": "UNC_P_DEMOTIONS_CORE11", "PerPkg": "1", @@ -184,6 +207,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_P_DEMOTIONS_CORE12", "PerPkg": "1", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_P_DEMOTIONS_CORE13", "PerPkg": "1", @@ -200,6 +225,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_P_DEMOTIONS_CORE14", "PerPkg": "1", @@ -208,6 +234,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_P_DEMOTIONS_CORE15", "PerPkg": "1", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_P_DEMOTIONS_CORE16", "PerPkg": "1", @@ -224,6 +252,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", @@ -232,6 +261,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", @@ -240,6 +270,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_P_DEMOTIONS_CORE3", "PerPkg": "1", @@ -248,6 +279,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_P_DEMOTIONS_CORE4", "PerPkg": "1", @@ -256,6 +288,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_P_DEMOTIONS_CORE5", "PerPkg": "1", @@ -264,6 +297,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_P_DEMOTIONS_CORE6", "PerPkg": "1", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_P_DEMOTIONS_CORE7", "PerPkg": "1", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_P_DEMOTIONS_CORE8", "PerPkg": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_P_DEMOTIONS_CORE9", "PerPkg": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", @@ -304,6 +342,7 @@ }, { "BriefDescription": "OS Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", "PerPkg": "1", @@ -312,6 +351,7 @@ }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", @@ -320,6 +360,7 @@ }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", @@ -328,6 +369,7 @@ }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", @@ -336,6 +378,7 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", @@ -344,6 +387,7 @@ }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "PerPkg": "1", @@ -352,6 +396,7 @@ }, { "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", "PerPkg": "1", @@ -360,6 +405,7 @@ }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "PerPkg": "1", @@ -368,6 +414,7 @@ }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "PerPkg": "1", @@ -376,6 +423,7 @@ }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "PerPkg": "1", @@ -384,6 +432,7 @@ }, { "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", "PerPkg": "1", @@ -392,6 +441,7 @@ }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "Filter": "occ_sel=3D1", @@ -401,6 +451,7 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "Filter": "occ_sel=3D2", @@ -410,6 +461,7 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "Filter": "occ_sel=3D3", @@ -419,6 +471,7 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", @@ -427,6 +480,7 @@ }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", @@ -435,6 +489,7 @@ }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", @@ -443,6 +498,7 @@ }, { "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", "PerPkg": "1", @@ -451,6 +507,7 @@ }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json index 93621e004d88..eb1d9541e26c 100644 --- a/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/broadwellx/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", @@ -149,6 +167,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "PublicDescription": "This event counts cycles for an extended pag= e table walk. The Extended Page directory cache differs from standard TLB c= aches by the operating system that use it. Virtual machine operating system= s use the extended page directory cache, while guest operating systems use = the standard TLB caches.", @@ -157,6 +176,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "This event counts the number of flushes of t= he big or small ITLB pages. Counting include both TLB Flush (covering all s= ets) and TLB Set Clear (set-specific).", @@ -165,6 +185,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", @@ -174,6 +195,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "SampleAfterValue": "100003", @@ -188,6 +211,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K).", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "SampleAfterValue": "100003", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", @@ -212,6 +238,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", @@ -230,6 +258,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "Errata": "BDM69", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", @@ -239,6 +268,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", @@ -247,6 +277,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", @@ -255,6 +286,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -263,6 +295,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -271,6 +304,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB.= ", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", @@ -287,6 +322,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP.", + "Counter": "0,1,2,3", "Errata": "BDM69, BDM98", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -295,6 +331,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "This event counts the number of DTLB flush a= ttempts of the thread-specific entries.", @@ -303,6 +340,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "This event counts the number of any STLB flu= sh attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8E3C1B47D4 for ; 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Thu, 20 Jun 2024 11:19:29 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:21 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-8-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 07/37] perf vendor events: Update cascadelakex events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.21 to v1.22. Bring in the event updates v1.22 https://github.com/intel/perfmon/commit/013877729c4ed96427932ca48722bc3bfd2= a0075 The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 New events are: SW_PREFETCH_ACCESS.ANY Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/cascadelakex/cache.json | 1245 ++++++++ .../arch/x86/cascadelakex/clx-metrics.json | 310 +- .../arch/x86/cascadelakex/counter.json | 52 + .../arch/x86/cascadelakex/floating-point.json | 16 + .../arch/x86/cascadelakex/frontend.json | 49 + .../arch/x86/cascadelakex/memory.json | 743 +++++ .../arch/x86/cascadelakex/metricgroups.json | 13 + .../arch/x86/cascadelakex/other.json | 168 ++ .../arch/x86/cascadelakex/pipeline.json | 104 +- .../arch/x86/cascadelakex/uncore-cache.json | 2293 +++++++++++++++ .../x86/cascadelakex/uncore-interconnect.json | 2536 +++++++++++++++++ .../arch/x86/cascadelakex/uncore-io.json | 703 +++++ .../arch/x86/cascadelakex/uncore-memory.json | 985 +++++++ .../arch/x86/cascadelakex/uncore-power.json | 50 + .../arch/x86/cascadelakex/virtual-memory.json | 28 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 16 files changed, 9108 insertions(+), 189 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/cascadelakex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/cache.json index a842f05cb60d..8bad700ff8ea 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines can be either in= modified state or clean state. Modified lines may either be written back t= o L3 or directly written to memory and not allocated in L3. Clean lines ma= y either be allocated in L3 or dropped", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines can be either i= n modified state or clean state. Modified lines may either be written back = to L3 or directly written to memory and not allocated in L3. Clean lines m= ay either be allocated in L3 or dropped.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared state. A non-threaded event.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "SampleAfterValue": "200003", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "SampleAfterValue": "200003", @@ -73,6 +82,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Demand requests that miss L2 cache.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Demand requests to L2 cache.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", @@ -121,6 +136,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -129,6 +145,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -137,6 +154,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -161,6 +181,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "All requests that miss L2 cache.", @@ -169,6 +190,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", @@ -177,6 +199,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", @@ -185,6 +208,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "All L2 requests.", @@ -193,6 +217,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -201,6 +226,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -209,6 +235,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -217,6 +244,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", @@ -226,6 +254,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", @@ -235,6 +264,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -245,6 +275,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -255,6 +286,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ANY", @@ -265,6 +297,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -274,6 +307,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -284,6 +318,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -304,6 +340,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -314,6 +351,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -324,6 +362,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -334,6 +373,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -343,6 +383,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -353,6 +394,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -363,6 +405,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -372,6 +415,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -381,6 +425,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was remote HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -391,6 +436,7 @@ }, { "BriefDescription": "Retired load instructions with remote Intel(R= ) Optane(TM) DC persistent memory as the data source where the data request= missed all caches.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", @@ -401,6 +447,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -410,6 +457,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -420,6 +468,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -430,6 +479,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -440,6 +490,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -450,6 +501,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -460,6 +512,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -470,6 +523,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -480,6 +534,7 @@ }, { "BriefDescription": "Retired load instructions with local Intel(R)= Optane(TM) DC persistent memory as the data source where the data request = missed all caches.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", @@ -490,6 +545,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA= _RD.L3_HIT.ANY_SNOOP OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -499,6 +555,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.AL= L_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -508,6 +565,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR= .ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -517,6 +575,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD = OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_HIT.HIT_OTH= ER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -526,6 +585,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.AL= L_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -535,6 +595,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -544,6 +605,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_DAT= A_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -553,6 +615,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_DAT= A_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -562,6 +625,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.ALL_D= ATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -571,6 +635,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE OCR= .ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -580,6 +645,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD = OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -589,6 +655,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FW= D OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -598,6 +665,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED OCR= .ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -607,6 +675,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -616,6 +685,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -625,6 +695,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.ALL_D= ATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -634,6 +705,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE OCR= .ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -643,6 +715,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD = OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -652,6 +725,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FW= D OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -661,6 +735,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED OCR= .ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -670,6 +745,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -679,6 +755,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -688,6 +765,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.ALL_D= ATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -697,6 +775,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE OCR= .ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -706,6 +785,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD = OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -715,6 +795,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FW= D OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -724,6 +805,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED OCR= .ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -733,6 +815,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -742,6 +825,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -751,6 +835,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.ALL_D= ATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -760,6 +845,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE OCR= .ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -769,6 +855,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD = OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -778,6 +865,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FW= D OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -787,6 +875,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED OCR= .ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -796,6 +885,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -805,6 +895,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -814,6 +905,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_P= F_DATA_RD.L3_HIT.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -823,6 +915,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR= .ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER= _CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -832,6 +925,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD = OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_= OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -841,6 +935,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_F= WD OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_HI= T.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -850,6 +945,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR= .ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_N= EEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -859,6 +955,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -868,6 +965,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS OCR.ALL_= PF_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -877,6 +975,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE OCR.ALL_= PF_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -886,6 +985,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP OCR.AL= L_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -895,6 +995,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE = OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -904,6 +1005,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FW= D OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -913,6 +1015,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO= _FWD OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -922,6 +1025,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED = OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -931,6 +1035,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -940,6 +1045,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -949,6 +1055,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP OCR.AL= L_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -958,6 +1065,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE = OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -967,6 +1075,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FW= D OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -976,6 +1085,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO= _FWD OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -985,6 +1095,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED = OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -994,6 +1105,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1003,6 +1115,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1012,6 +1125,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP OCR.AL= L_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1021,6 +1135,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE = OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1030,6 +1145,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FW= D OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1039,6 +1155,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO= _FWD OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1048,6 +1165,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED = OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1057,6 +1175,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1066,6 +1185,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1075,6 +1195,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP OCR.AL= L_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1084,6 +1205,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE = OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1093,6 +1215,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FW= D OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1102,6 +1225,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO= _FWD OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1111,6 +1235,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED = OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1120,6 +1245,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1129,6 +1255,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1138,6 +1265,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP OCR.ALL_PF_RF= O.L3_HIT.ANY_SNOOP OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1147,6 +1275,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL= _PF_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1156,6 +1285,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.= ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_F= WD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1165,6 +1295,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD O= CR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_= CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1174,6 +1305,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL= _PF_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1183,6 +1315,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1192,6 +1325,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS OCR.ALL_PF_R= FO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1201,6 +1335,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE OCR.ALL_PF_R= FO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1210,6 +1345,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_PF= _RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1219,6 +1355,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.= ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1228,6 +1365,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD O= CR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1237,6 +1375,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD= OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1246,6 +1385,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.= ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1255,6 +1395,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1264,6 +1405,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1273,6 +1415,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_PF= _RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1282,6 +1425,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.= ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1291,6 +1435,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD O= CR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1300,6 +1445,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD= OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1309,6 +1455,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.= ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1318,6 +1465,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1327,6 +1475,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1336,6 +1485,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_PF= _RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1345,6 +1495,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.= ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1354,6 +1505,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD O= CR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1363,6 +1515,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD= OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1372,6 +1525,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.= ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1381,6 +1535,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1390,6 +1545,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1399,6 +1555,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_PF= _RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1408,6 +1565,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.= ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1417,6 +1575,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD O= CR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1426,6 +1585,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD= OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1435,6 +1595,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.= ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1444,6 +1605,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1453,6 +1615,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1462,6 +1625,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.ANY_SNOOP OCR.ALL_READS.= L3_HIT.ANY_SNOOP OCR.ALL_READS.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1471,6 +1635,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_= READS.L3_HIT.HITM_OTHER_CORE OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1480,6 +1645,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.A= LL_READS.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1489,6 +1655,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OC= R.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_HIT.HIT_OTHER_COR= E_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1498,6 +1665,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_= READS.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1507,6 +1675,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1516,6 +1685,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_MISS OCR.ALL_READS= .L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1525,6 +1695,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT.SNOOP_NONE OCR.ALL_READS= .L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1534,6 +1705,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP OCR.ALL_REA= DS.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1543,6 +1715,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE OCR.A= LL_READS.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1552,6 +1725,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD OC= R.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1561,6 +1735,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD = OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1570,6 +1745,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED OCR.A= LL_READS.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1579,6 +1755,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1588,6 +1765,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1597,6 +1775,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP OCR.ALL_REA= DS.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1606,6 +1785,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE OCR.A= LL_READS.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1615,6 +1795,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD OC= R.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1624,6 +1805,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD = OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1633,6 +1815,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED OCR.A= LL_READS.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1642,6 +1825,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1651,6 +1835,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1660,6 +1845,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP OCR.ALL_REA= DS.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1669,6 +1855,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE OCR.A= LL_READS.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1678,6 +1865,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD OC= R.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1687,6 +1875,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD = OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1696,6 +1885,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED OCR.A= LL_READS.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1705,6 +1895,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1714,6 +1905,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1723,6 +1915,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP OCR.ALL_REA= DS.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1732,6 +1925,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE OCR.A= LL_READS.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1741,6 +1935,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD OC= R.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1750,6 +1945,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD = OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1759,6 +1955,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED OCR.A= LL_READS.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1768,6 +1965,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1777,6 +1975,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1786,6 +1985,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP OCR.ALL_RFO.L3_H= IT.ANY_SNOOP OCR.ALL_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1795,6 +1995,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE OCR.ALL_RF= O.L3_HIT.HITM_OTHER_CORE OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1804,6 +2005,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL= _RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1813,6 +2015,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.= ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_F= WD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1822,6 +2025,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RF= O.L3_HIT.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1831,6 +2035,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1840,6 +2045,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS OCR.ALL_RFO.L3_= HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1849,6 +2055,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE OCR.ALL_RFO.L3_= HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1858,6 +2065,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP OCR.ALL_RFO.L= 3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1867,6 +2075,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE OCR.ALL= _RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1876,6 +2085,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD OCR.= ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1885,6 +2095,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD O= CR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1894,6 +2105,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED OCR.ALL= _RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1903,6 +2115,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1912,6 +2125,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1921,6 +2135,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP OCR.ALL_RFO.L= 3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1930,6 +2145,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE OCR.ALL= _RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1939,6 +2155,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD OCR.= ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1948,6 +2165,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD O= CR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1957,6 +2175,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED OCR.ALL= _RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1966,6 +2185,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1975,6 +2195,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1984,6 +2205,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP OCR.ALL_RFO.L= 3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1993,6 +2215,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE OCR.ALL= _RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2002,6 +2225,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD OCR.= ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2011,6 +2235,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD O= CR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2020,6 +2245,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED OCR.ALL= _RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2029,6 +2255,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2038,6 +2265,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2047,6 +2275,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP OCR.ALL_RFO.L= 3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2056,6 +2285,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE OCR.ALL= _RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2065,6 +2295,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD OCR.= ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2074,6 +2305,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD O= CR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2083,6 +2315,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED OCR.ALL= _RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2092,6 +2325,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2101,6 +2335,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2110,6 +2345,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2119,6 +2355,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2128,6 +2365,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2137,6 +2375,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO= _FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2146,6 +2385,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2155,6 +2395,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2164,6 +2405,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2173,6 +2415,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2182,6 +2425,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2191,6 +2435,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2200,6 +2445,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2209,6 +2455,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2218,6 +2465,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2227,6 +2475,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2236,6 +2485,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2245,6 +2495,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2254,6 +2505,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2263,6 +2515,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2272,6 +2525,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2281,6 +2535,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2290,6 +2545,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2299,6 +2555,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2308,6 +2565,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2317,6 +2575,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2326,6 +2585,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2335,6 +2595,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2344,6 +2605,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2353,6 +2615,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2362,6 +2625,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2371,6 +2635,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2380,6 +2645,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2389,6 +2655,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2398,6 +2665,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2407,6 +2675,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2416,6 +2685,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2425,6 +2695,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2434,6 +2705,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2443,6 +2715,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2452,6 +2725,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2461,6 +2735,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2470,6 +2745,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2479,6 +2755,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2488,6 +2765,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2497,6 +2775,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2506,6 +2785,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2515,6 +2795,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2524,6 +2805,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2533,6 +2815,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2542,6 +2825,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2551,6 +2835,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2560,6 +2845,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2569,6 +2855,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2578,6 +2865,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2587,6 +2875,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2596,6 +2885,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2605,6 +2895,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2614,6 +2905,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2623,6 +2915,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2632,6 +2925,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2641,6 +2935,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2650,6 +2945,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2659,6 +2955,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2668,6 +2965,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2677,6 +2975,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2686,6 +2985,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2695,6 +2995,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2704,6 +3005,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2713,6 +3015,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2722,6 +3025,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2731,6 +3035,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2740,6 +3045,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2749,6 +3055,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2758,6 +3065,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.ANY_SNOOP OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2767,6 +3075,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2776,6 +3085,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2785,6 +3095,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2794,6 +3105,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2803,6 +3115,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2812,6 +3125,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2821,6 +3135,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2830,6 +3145,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2839,6 +3155,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2848,6 +3165,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2857,6 +3175,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2866,6 +3185,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2875,6 +3195,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2884,6 +3205,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2893,6 +3215,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2902,6 +3225,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2911,6 +3235,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2920,6 +3245,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2929,6 +3255,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2938,6 +3265,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2947,6 +3275,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2956,6 +3285,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2965,6 +3295,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2974,6 +3305,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2983,6 +3315,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2992,6 +3325,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3001,6 +3335,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3010,6 +3345,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3019,6 +3355,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3028,6 +3365,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3037,6 +3375,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3046,6 +3385,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3055,6 +3395,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3064,6 +3405,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3073,6 +3415,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3082,6 +3425,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.AN= Y_SNOOP OCR.OTHER.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3091,6 +3435,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HI= TM_OTHER_CORE OCR.OTHER.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3100,6 +3445,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HI= T_OTHER_CORE_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3109,6 +3455,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.HI= T_OTHER_CORE_NO_FWD OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3118,6 +3465,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.NO= _SNOOP_NEEDED OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3127,6 +3475,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3136,6 +3485,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SN= OOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3145,6 +3495,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT.SN= OOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3154,6 +3505,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E= .ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3163,6 +3515,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E= .HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3172,6 +3525,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E= .HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3181,6 +3535,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E= .HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3190,6 +3545,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_E= .NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3199,6 +3555,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3208,6 +3565,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3217,6 +3575,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F= .ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3226,6 +3585,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F= .HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3235,6 +3595,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F= .HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3244,6 +3605,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F= .HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3253,6 +3615,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_F= .NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3262,6 +3625,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3271,6 +3635,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3280,6 +3645,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M= .ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3289,6 +3655,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M= .HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3298,6 +3665,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M= .HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3307,6 +3675,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M= .HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3316,6 +3685,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_M= .NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3325,6 +3695,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3334,6 +3705,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3343,6 +3715,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S= .ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3352,6 +3725,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S= .HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3361,6 +3735,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S= .HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3370,6 +3745,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S= .HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3379,6 +3755,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_HIT_S= .NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3388,6 +3765,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3397,6 +3775,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3406,6 +3785,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP OCR.PF= _L1D_AND_SW.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3415,6 +3795,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE = OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3424,6 +3805,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_F= WD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3433,6 +3815,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_N= O_FWD OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3442,6 +3825,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED = OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3451,6 +3835,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3460,6 +3845,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3469,6 +3855,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3478,6 +3865,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3487,6 +3875,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CO= RE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3496,6 +3885,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3505,6 +3895,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_COR= E_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3514,6 +3905,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEED= ED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3523,6 +3915,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3532,6 +3925,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3541,6 +3935,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3550,6 +3945,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CO= RE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3559,6 +3955,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3568,6 +3965,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_COR= E_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3577,6 +3975,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEED= ED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3586,6 +3985,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3595,6 +3995,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3604,6 +4005,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3613,6 +4015,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CO= RE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3622,6 +4025,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3631,6 +4035,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_COR= E_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3640,6 +4045,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEED= ED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3649,6 +4055,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3658,6 +4065,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3667,6 +4075,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3676,6 +4085,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CO= RE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3685,6 +4095,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3694,6 +4105,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_COR= E_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3703,6 +4115,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEED= ED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3712,6 +4125,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3721,6 +4135,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3730,6 +4145,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3739,6 +4155,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_HIT.HIT= M_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3748,6 +4165,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_HIT.= HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3757,6 +4175,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_H= IT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3766,6 +4185,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_HIT.NO_= SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3775,6 +4195,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3784,6 +4205,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3793,6 +4215,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3802,6 +4225,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3811,6 +4235,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3820,6 +4245,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3829,6 +4255,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3838,6 +4265,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3847,6 +4275,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3856,6 +4285,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3865,6 +4295,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3874,6 +4305,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3883,6 +4315,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3892,6 +4325,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3901,6 +4335,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3910,6 +4345,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3919,6 +4355,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3928,6 +4365,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3937,6 +4375,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3946,6 +4385,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3955,6 +4395,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3964,6 +4405,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3973,6 +4415,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3982,6 +4425,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3991,6 +4435,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4000,6 +4445,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4009,6 +4455,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4018,6 +4465,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4027,6 +4475,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4036,6 +4485,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4045,6 +4495,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4054,6 +4505,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4063,6 +4515,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CO= RE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4072,6 +4525,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_= CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4081,6 +4535,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_HIT.HIT_OTH= ER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4090,6 +4545,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEED= ED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4099,6 +4555,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4108,6 +4565,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4117,6 +4575,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4126,6 +4585,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4135,6 +4595,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4144,6 +4605,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4153,6 +4615,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4162,6 +4625,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4171,6 +4635,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4180,6 +4645,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4189,6 +4655,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4198,6 +4665,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4207,6 +4675,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4216,6 +4685,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4225,6 +4695,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4234,6 +4705,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4243,6 +4715,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4252,6 +4725,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4261,6 +4735,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4270,6 +4745,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4279,6 +4755,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4288,6 +4765,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4297,6 +4775,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4306,6 +4785,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4315,6 +4795,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4324,6 +4805,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4333,6 +4815,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4342,6 +4825,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4351,6 +4835,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4360,6 +4845,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4369,6 +4855,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4378,6 +4865,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_HIT= .ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4387,6 +4875,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_DATA_RD.= L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4396,6 +4885,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA_= RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4405,6 +4895,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_DA= TA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4414,6 +4905,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD.= L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4423,6 +4915,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4432,6 +4925,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4441,6 +4935,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4450,6 +4945,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4459,6 +4955,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4468,6 +4965,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4477,6 +4975,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4486,6 +4985,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4495,6 +4995,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4504,6 +5005,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4513,6 +5015,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4522,6 +5025,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4531,6 +5035,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4540,6 +5045,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4549,6 +5055,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4558,6 +5065,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4567,6 +5075,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4576,6 +5085,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4585,6 +5095,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4594,6 +5105,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4603,6 +5115,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4612,6 +5125,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4621,6 +5135,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4630,6 +5145,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4639,6 +5155,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4648,6 +5165,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4657,6 +5175,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4666,6 +5185,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4675,6 +5195,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4684,6 +5205,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4693,6 +5215,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4702,6 +5225,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4711,6 +5235,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_HIT.HITM_OT= HER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4720,6 +5245,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_HIT.HIT_= OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4729,6 +5255,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_HIT.H= IT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4738,6 +5265,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_HIT.NO_SNOO= P_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4747,6 +5275,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4756,6 +5285,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4765,6 +5295,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4774,6 +5305,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4783,6 +5315,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4792,6 +5325,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4801,6 +5335,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4810,6 +5345,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4819,6 +5355,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4828,6 +5365,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4837,6 +5375,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4846,6 +5385,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4855,6 +5395,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4864,6 +5405,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4873,6 +5415,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4882,6 +5425,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4891,6 +5435,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4900,6 +5445,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4909,6 +5455,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4918,6 +5465,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4927,6 +5475,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4936,6 +5485,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -4945,6 +5495,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -4954,6 +5505,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -4963,6 +5515,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -4972,6 +5525,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -4981,6 +5535,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4990,6 +5545,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -4999,6 +5555,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -5008,6 +5565,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -5017,6 +5575,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -5026,6 +5585,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -5034,6 +5594,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -5042,6 +5603,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", @@ -5050,6 +5612,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -5058,6 +5621,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -5066,6 +5630,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", @@ -5074,6 +5639,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -5082,6 +5648,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -5091,6 +5658,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -5100,6 +5668,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -5109,6 +5678,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -5118,6 +5688,7 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -5126,6 +5697,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", @@ -5134,6 +5706,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -5142,6 +5715,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", @@ -5150,6 +5724,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", @@ -5160,6 +5735,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", @@ -5170,6 +5746,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", @@ -5180,6 +5757,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_F= WD", @@ -5190,6 +5768,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", @@ -5200,6 +5779,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", @@ -5210,6 +5790,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_F= WD", @@ -5220,6 +5801,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_MISS", @@ -5230,6 +5812,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_NONE", @@ -5240,6 +5823,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.ANY_SNOOP", @@ -5250,6 +5834,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HITM_OTHER_COR= E", @@ -5260,6 +5845,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE= _FWD", @@ -5270,6 +5856,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.HIT_OTHER_CORE= _NO_FWD", @@ -5280,6 +5867,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDE= D", @@ -5290,6 +5878,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_MISS", @@ -5300,6 +5889,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_E.SNOOP_NONE", @@ -5310,6 +5900,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.ANY_SNOOP", @@ -5320,6 +5911,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HITM_OTHER_COR= E", @@ -5330,6 +5922,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE= _FWD", @@ -5340,6 +5933,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.HIT_OTHER_CORE= _NO_FWD", @@ -5350,6 +5944,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDE= D", @@ -5360,6 +5955,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_MISS", @@ -5370,6 +5966,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_F.SNOOP_NONE", @@ -5380,6 +5977,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.ANY_SNOOP", @@ -5390,6 +5988,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HITM_OTHER_COR= E", @@ -5400,6 +5999,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE= _FWD", @@ -5410,6 +6010,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.HIT_OTHER_CORE= _NO_FWD", @@ -5420,6 +6021,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDE= D", @@ -5430,6 +6032,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_MISS", @@ -5440,6 +6043,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_M.SNOOP_NONE", @@ -5450,6 +6054,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.ANY_SNOOP", @@ -5460,6 +6065,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HITM_OTHER_COR= E", @@ -5470,6 +6076,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE= _FWD", @@ -5480,6 +6087,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.HIT_OTHER_CORE= _NO_FWD", @@ -5490,6 +6098,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDE= D", @@ -5500,6 +6109,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_MISS", @@ -5510,6 +6120,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT_S.SNOOP_NONE", @@ -5520,6 +6131,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_S= NOOP", @@ -5530,6 +6142,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP= _NONE", @@ -5540,6 +6153,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP= _NOT_NEEDED", @@ -5550,6 +6164,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP= ", @@ -5560,6 +6175,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHE= R_CORE", @@ -5570,6 +6186,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER= _CORE_FWD", @@ -5580,6 +6197,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER= _CORE_NO_FWD", @@ -5590,6 +6208,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_= NEEDED", @@ -5600,6 +6219,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MIS= S", @@ -5610,6 +6230,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NON= E", @@ -5620,6 +6241,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", @@ -5630,6 +6252,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", @@ -5640,6 +6263,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", @@ -5650,6 +6274,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_FWD", @@ -5660,6 +6285,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", @@ -5670,6 +6296,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", @@ -5680,6 +6307,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", @@ -5690,6 +6318,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_MISS", @@ -5700,6 +6329,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_NONE", @@ -5710,6 +6340,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.ANY_SNOOP", @@ -5720,6 +6351,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HITM_OTHER_= CORE", @@ -5730,6 +6362,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", @@ -5740,6 +6373,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", @@ -5750,6 +6384,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.NO_SNOOP_NE= EDED", @@ -5760,6 +6395,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_MISS", @@ -5770,6 +6406,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_E.SNOOP_NONE", @@ -5780,6 +6417,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.ANY_SNOOP", @@ -5790,6 +6428,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HITM_OTHER_= CORE", @@ -5800,6 +6439,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", @@ -5810,6 +6450,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", @@ -5820,6 +6461,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.NO_SNOOP_NE= EDED", @@ -5830,6 +6472,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_MISS", @@ -5840,6 +6483,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_F.SNOOP_NONE", @@ -5850,6 +6494,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.ANY_SNOOP", @@ -5860,6 +6505,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HITM_OTHER_= CORE", @@ -5870,6 +6516,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", @@ -5880,6 +6527,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", @@ -5890,6 +6538,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.NO_SNOOP_NE= EDED", @@ -5900,6 +6549,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_MISS", @@ -5910,6 +6560,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_M.SNOOP_NONE", @@ -5920,6 +6571,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.ANY_SNOOP", @@ -5930,6 +6582,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HITM_OTHER_= CORE", @@ -5940,6 +6593,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", @@ -5950,6 +6604,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", @@ -5960,6 +6615,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.NO_SNOOP_NE= EDED", @@ -5970,6 +6626,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_MISS", @@ -5980,6 +6637,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT_S.SNOOP_NONE", @@ -5990,6 +6648,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.AN= Y_SNOOP", @@ -6000,6 +6659,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", @@ -6010,6 +6670,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", @@ -6020,6 +6681,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", @@ -6030,6 +6692,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_O= THER_CORE", @@ -6040,6 +6703,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", @@ -6050,6 +6714,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", @@ -6060,6 +6725,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", @@ -6070,6 +6736,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", @@ -6080,6 +6747,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", @@ -6090,6 +6758,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", @@ -6100,6 +6769,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", @@ -6110,6 +6780,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", @@ -6120,6 +6791,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_FW= D", @@ -6130,6 +6802,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", @@ -6140,6 +6813,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", @@ -6150,6 +6824,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", @@ -6160,6 +6835,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_MISS", @@ -6170,6 +6846,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_NONE", @@ -6180,6 +6857,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.ANY_SNOOP", @@ -6190,6 +6868,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HITM_OTHER_CORE= ", @@ -6200,6 +6879,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_= FWD", @@ -6210,6 +6890,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.HIT_OTHER_CORE_= NO_FWD", @@ -6220,6 +6901,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.NO_SNOOP_NEEDED= ", @@ -6230,6 +6912,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_MISS", @@ -6240,6 +6923,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_E.SNOOP_NONE", @@ -6250,6 +6934,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.ANY_SNOOP", @@ -6260,6 +6945,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HITM_OTHER_CORE= ", @@ -6270,6 +6956,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_= FWD", @@ -6280,6 +6967,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.HIT_OTHER_CORE_= NO_FWD", @@ -6290,6 +6978,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.NO_SNOOP_NEEDED= ", @@ -6300,6 +6989,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_MISS", @@ -6310,6 +7000,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_F.SNOOP_NONE", @@ -6320,6 +7011,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.ANY_SNOOP", @@ -6330,6 +7022,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HITM_OTHER_CORE= ", @@ -6340,6 +7033,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_= FWD", @@ -6350,6 +7044,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.HIT_OTHER_CORE_= NO_FWD", @@ -6360,6 +7055,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.NO_SNOOP_NEEDED= ", @@ -6370,6 +7066,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_MISS", @@ -6380,6 +7077,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_M.SNOOP_NONE", @@ -6390,6 +7088,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.ANY_SNOOP", @@ -6400,6 +7099,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HITM_OTHER_CORE= ", @@ -6410,6 +7110,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_= FWD", @@ -6420,6 +7121,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.HIT_OTHER_CORE_= NO_FWD", @@ -6430,6 +7132,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.NO_SNOOP_NEEDED= ", @@ -6440,6 +7143,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_MISS", @@ -6450,6 +7154,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT_S.SNOOP_NONE", @@ -6460,6 +7165,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SN= OOP", @@ -6470,6 +7176,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NONE", @@ -6480,6 +7187,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NOT_NEEDED", @@ -6490,6 +7198,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", @@ -6500,6 +7209,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER= _CORE", @@ -6510,6 +7220,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_FWD", @@ -6520,6 +7231,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_NO_FWD", @@ -6530,6 +7242,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_N= EEDED", @@ -6540,6 +7253,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS= ", @@ -6550,6 +7264,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE= ", @@ -6560,6 +7275,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", @@ -6570,6 +7286,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.ANY_SNOOP", @@ -6580,6 +7297,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", @@ -6590,6 +7308,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD= ", @@ -6600,6 +7319,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_= FWD", @@ -6610,6 +7330,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.NO_SNOOP_NEEDED", @@ -6620,6 +7341,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_HIT_WITH_FWD= ", @@ -6630,6 +7352,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_MISS", @@ -6640,6 +7363,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.SNOOP_NONE", @@ -6650,6 +7374,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.ANY_SNOOP", @@ -6660,6 +7385,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HITM_OTHER_CORE", @@ -6670,6 +7396,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_F= WD", @@ -6680,6 +7407,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", @@ -6690,6 +7418,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.NO_SNOOP_NEEDED", @@ -6700,6 +7429,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_MISS", @@ -6710,6 +7440,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_E.SNOOP_NONE", @@ -6720,6 +7451,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.ANY_SNOOP", @@ -6730,6 +7462,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HITM_OTHER_CORE", @@ -6740,6 +7473,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_F= WD", @@ -6750,6 +7484,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", @@ -6760,6 +7495,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.NO_SNOOP_NEEDED", @@ -6770,6 +7506,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_MISS", @@ -6780,6 +7517,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_F.SNOOP_NONE", @@ -6790,6 +7528,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.ANY_SNOOP", @@ -6800,6 +7539,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HITM_OTHER_CORE", @@ -6810,6 +7550,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_F= WD", @@ -6820,6 +7561,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", @@ -6830,6 +7572,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.NO_SNOOP_NEEDED", @@ -6840,6 +7583,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_MISS", @@ -6850,6 +7594,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_M.SNOOP_NONE", @@ -6860,6 +7605,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.ANY_SNOOP", @@ -6870,6 +7616,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HITM_OTHER_CORE", @@ -6880,6 +7627,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_F= WD", @@ -6890,6 +7638,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", @@ -6900,6 +7649,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.NO_SNOOP_NEEDED", @@ -6910,6 +7660,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_MISS", @@ -6920,6 +7671,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT_S.SNOOP_NONE", @@ -6930,6 +7682,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNO= OP", @@ -6940,6 +7693,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", @@ -6950,6 +7704,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", @@ -6960,6 +7715,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", @@ -6970,6 +7726,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HITM_OTHER_= CORE", @@ -6980,6 +7737,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", @@ -6990,6 +7748,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", @@ -7000,6 +7759,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NE= EDED", @@ -7010,6 +7770,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", @@ -7020,6 +7781,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", @@ -7030,6 +7792,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", @@ -7040,6 +7803,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", @@ -7050,6 +7814,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", @@ -7060,6 +7825,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_FWD", @@ -7070,6 +7836,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", @@ -7080,6 +7847,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", @@ -7090,6 +7858,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -7100,6 +7869,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_MISS", @@ -7110,6 +7880,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_NONE", @@ -7120,6 +7891,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.ANY_SNOOP", @@ -7130,6 +7902,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HITM_OTHER_CORE", @@ -7140,6 +7913,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD= ", @@ -7150,6 +7924,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_= FWD", @@ -7160,6 +7935,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.NO_SNOOP_NEEDED", @@ -7170,6 +7946,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_MISS", @@ -7180,6 +7957,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_E.SNOOP_NONE", @@ -7190,6 +7968,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.ANY_SNOOP", @@ -7200,6 +7979,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HITM_OTHER_CORE", @@ -7210,6 +7990,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD= ", @@ -7220,6 +8001,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_= FWD", @@ -7230,6 +8012,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.NO_SNOOP_NEEDED", @@ -7240,6 +8023,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_MISS", @@ -7250,6 +8034,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_F.SNOOP_NONE", @@ -7260,6 +8045,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.ANY_SNOOP", @@ -7270,6 +8056,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HITM_OTHER_CORE", @@ -7280,6 +8067,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD= ", @@ -7290,6 +8078,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_= FWD", @@ -7300,6 +8089,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.NO_SNOOP_NEEDED", @@ -7310,6 +8100,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_MISS", @@ -7320,6 +8111,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_M.SNOOP_NONE", @@ -7330,6 +8122,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.ANY_SNOOP", @@ -7340,6 +8133,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HITM_OTHER_CORE", @@ -7350,6 +8144,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD= ", @@ -7360,6 +8155,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_= FWD", @@ -7370,6 +8166,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.NO_SNOOP_NEEDED", @@ -7380,6 +8177,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_MISS", @@ -7390,6 +8188,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT_S.SNOOP_NONE", @@ -7400,6 +8199,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP= ", @@ -7410,6 +8210,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NON= E", @@ -7420,6 +8221,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT= _NEEDED", @@ -7430,6 +8232,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", @@ -7440,6 +8243,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CO= RE", @@ -7450,6 +8254,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_COR= E_FWD", @@ -7460,6 +8265,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_COR= E_NO_FWD", @@ -7470,6 +8276,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEED= ED", @@ -7480,6 +8287,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", @@ -7490,6 +8298,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", @@ -7500,6 +8309,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", @@ -7510,6 +8320,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", @@ -7520,6 +8331,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", @@ -7530,6 +8342,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_FWD", @@ -7540,6 +8353,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", @@ -7550,6 +8364,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEED= ED", @@ -7560,6 +8375,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", @@ -7570,6 +8386,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", @@ -7580,6 +8397,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", @@ -7590,6 +8408,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", @@ -7600,6 +8419,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HITM_OTHER_= CORE", @@ -7610,6 +8430,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", @@ -7620,6 +8441,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", @@ -7630,6 +8452,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.NO_SNOOP_NE= EDED", @@ -7640,6 +8463,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", @@ -7650,6 +8474,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", @@ -7660,6 +8485,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.ANY_SNOOP", @@ -7670,6 +8496,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HITM_OTHER_= CORE", @@ -7680,6 +8507,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", @@ -7690,6 +8518,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", @@ -7700,6 +8529,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.NO_SNOOP_NE= EDED", @@ -7710,6 +8540,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_MISS", @@ -7720,6 +8551,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_F.SNOOP_NONE", @@ -7730,6 +8562,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", @@ -7740,6 +8573,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HITM_OTHER_= CORE", @@ -7750,6 +8584,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", @@ -7760,6 +8595,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", @@ -7770,6 +8606,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.NO_SNOOP_NE= EDED", @@ -7780,6 +8617,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", @@ -7790,6 +8628,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", @@ -7800,6 +8639,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", @@ -7810,6 +8650,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HITM_OTHER_= CORE", @@ -7820,6 +8661,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", @@ -7830,6 +8672,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", @@ -7840,6 +8683,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.NO_SNOOP_NE= EDED", @@ -7850,6 +8694,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", @@ -7860,6 +8705,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", @@ -7870,6 +8716,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.AN= Y_SNOOP", @@ -7880,6 +8727,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", @@ -7890,6 +8738,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", @@ -7900,6 +8749,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", @@ -7910,6 +8760,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_O= THER_CORE", @@ -7920,6 +8771,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", @@ -7930,6 +8782,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", @@ -7940,6 +8793,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", @@ -7950,6 +8804,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", @@ -7960,6 +8815,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", @@ -7970,6 +8826,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", @@ -7980,6 +8837,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", @@ -7990,6 +8848,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", @@ -8000,6 +8859,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_FWD", @@ -8010,6 +8870,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", @@ -8020,6 +8881,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", @@ -8030,6 +8892,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", @@ -8040,6 +8903,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", @@ -8050,6 +8914,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", @@ -8060,6 +8925,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", @@ -8070,6 +8936,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HITM_OTHER_= CORE", @@ -8080,6 +8947,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_FWD", @@ -8090,6 +8958,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.HIT_OTHER_C= ORE_NO_FWD", @@ -8100,6 +8969,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.NO_SNOOP_NE= EDED", @@ -8110,6 +8980,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", @@ -8120,6 +8991,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", @@ -8130,6 +9002,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.ANY_SNOOP", @@ -8140,6 +9013,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HITM_OTHER_= CORE", @@ -8150,6 +9024,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_FWD", @@ -8160,6 +9035,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.HIT_OTHER_C= ORE_NO_FWD", @@ -8170,6 +9046,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.NO_SNOOP_NE= EDED", @@ -8180,6 +9057,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_MISS", @@ -8190,6 +9068,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_F.SNOOP_NONE", @@ -8200,6 +9079,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", @@ -8210,6 +9090,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HITM_OTHER_= CORE", @@ -8220,6 +9101,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_FWD", @@ -8230,6 +9112,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.HIT_OTHER_C= ORE_NO_FWD", @@ -8240,6 +9123,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.NO_SNOOP_NE= EDED", @@ -8250,6 +9134,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", @@ -8260,6 +9145,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", @@ -8270,6 +9156,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", @@ -8280,6 +9167,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HITM_OTHER_= CORE", @@ -8290,6 +9178,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_FWD", @@ -8300,6 +9189,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.HIT_OTHER_C= ORE_NO_FWD", @@ -8310,6 +9200,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.NO_SNOOP_NE= EDED", @@ -8320,6 +9211,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", @@ -8330,6 +9222,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", @@ -8340,6 +9233,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.AN= Y_SNOOP", @@ -8350,6 +9244,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NONE", @@ -8360,6 +9255,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SN= OOP_NOT_NEEDED", @@ -8370,6 +9266,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", @@ -8380,6 +9277,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_O= THER_CORE", @@ -8390,6 +9288,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_FWD", @@ -8400,6 +9299,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OT= HER_CORE_NO_FWD", @@ -8410,6 +9310,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNO= OP_NEEDED", @@ -8420,6 +9321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", @@ -8430,6 +9332,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", @@ -8440,6 +9343,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", @@ -8450,6 +9354,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", @@ -8460,6 +9365,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", @@ -8470,6 +9376,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_FW= D", @@ -8480,6 +9387,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", @@ -8490,6 +9398,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", @@ -8500,6 +9409,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", @@ -8510,6 +9420,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", @@ -8520,6 +9431,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", @@ -8530,6 +9442,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", @@ -8540,6 +9453,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HITM_OTHER_CORE= ", @@ -8550,6 +9464,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_= FWD", @@ -8560,6 +9475,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.HIT_OTHER_CORE_= NO_FWD", @@ -8570,6 +9486,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.NO_SNOOP_NEEDED= ", @@ -8580,6 +9497,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", @@ -8590,6 +9508,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", @@ -8600,6 +9519,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.ANY_SNOOP", @@ -8610,6 +9530,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HITM_OTHER_CORE= ", @@ -8620,6 +9541,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_= FWD", @@ -8630,6 +9552,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.HIT_OTHER_CORE_= NO_FWD", @@ -8640,6 +9563,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.NO_SNOOP_NEEDED= ", @@ -8650,6 +9574,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_MISS", @@ -8660,6 +9585,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_F.SNOOP_NONE", @@ -8670,6 +9596,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", @@ -8680,6 +9607,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HITM_OTHER_CORE= ", @@ -8690,6 +9618,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_= FWD", @@ -8700,6 +9629,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.HIT_OTHER_CORE_= NO_FWD", @@ -8710,6 +9640,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.NO_SNOOP_NEEDED= ", @@ -8720,6 +9651,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", @@ -8730,6 +9662,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", @@ -8740,6 +9673,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", @@ -8750,6 +9684,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HITM_OTHER_CORE= ", @@ -8760,6 +9695,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_= FWD", @@ -8770,6 +9706,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.HIT_OTHER_CORE_= NO_FWD", @@ -8780,6 +9717,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.NO_SNOOP_NEEDED= ", @@ -8790,6 +9728,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", @@ -8800,6 +9739,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", @@ -8810,6 +9750,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SN= OOP", @@ -8820,6 +9761,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NONE", @@ -8830,6 +9772,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_= NOT_NEEDED", @@ -8840,6 +9783,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", @@ -8850,6 +9794,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER= _CORE", @@ -8860,6 +9805,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_FWD", @@ -8870,6 +9816,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_= CORE_NO_FWD", @@ -8880,6 +9827,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_N= EEDED", @@ -8890,6 +9838,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", @@ -8900,6 +9849,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", @@ -8910,6 +9860,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", @@ -8920,6 +9871,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", @@ -8930,6 +9882,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HITM_OTHER_CORE", @@ -8940,6 +9893,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_FWD", @@ -8950,6 +9904,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.HIT_OTHER_CORE_NO_FWD", @@ -8960,6 +9915,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.NO_SNOOP_NEEDED", @@ -8970,6 +9926,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -8980,6 +9937,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", @@ -8990,6 +9948,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", @@ -9000,6 +9959,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", @@ -9010,6 +9970,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HITM_OTHER_CORE", @@ -9020,6 +9981,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_FWD", @@ -9030,6 +9992,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.HIT_OTHER_CORE_NO_FW= D", @@ -9040,6 +10003,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.NO_SNOOP_NEEDED", @@ -9050,6 +10014,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", @@ -9060,6 +10025,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", @@ -9070,6 +10036,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.ANY_SNOOP", @@ -9080,6 +10047,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HITM_OTHER_CORE", @@ -9090,6 +10058,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_FWD", @@ -9100,6 +10069,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.HIT_OTHER_CORE_NO_FW= D", @@ -9110,6 +10080,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.NO_SNOOP_NEEDED", @@ -9120,6 +10091,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_MISS", @@ -9130,6 +10102,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_F.SNOOP_NONE", @@ -9140,6 +10113,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", @@ -9150,6 +10124,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HITM_OTHER_CORE", @@ -9160,6 +10135,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_FWD", @@ -9170,6 +10146,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.HIT_OTHER_CORE_NO_FW= D", @@ -9180,6 +10157,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.NO_SNOOP_NEEDED", @@ -9190,6 +10168,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", @@ -9200,6 +10179,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", @@ -9210,6 +10190,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", @@ -9220,6 +10201,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HITM_OTHER_CORE", @@ -9230,6 +10212,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_FWD", @@ -9240,6 +10223,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.HIT_OTHER_CORE_NO_FW= D", @@ -9250,6 +10234,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.NO_SNOOP_NEEDED", @@ -9260,6 +10245,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", @@ -9270,6 +10256,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", @@ -9280,6 +10267,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", @@ -9290,6 +10278,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", @@ -9300,6 +10289,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_N= EEDED", @@ -9310,6 +10300,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", @@ -9320,6 +10311,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE= ", @@ -9330,6 +10322,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_= FWD", @@ -9340,6 +10333,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_= NO_FWD", @@ -9350,6 +10344,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED= ", @@ -9360,6 +10355,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", @@ -9370,6 +10366,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", @@ -9380,6 +10377,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", @@ -9390,6 +10388,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", @@ -9400,6 +10399,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COR= E", @@ -9410,6 +10410,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _FWD", @@ -9420,6 +10421,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _NO_FWD", @@ -9430,6 +10432,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDE= D", @@ -9440,6 +10443,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH= _FWD", @@ -9450,6 +10454,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_MISS", @@ -9460,6 +10465,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_NONE", @@ -9470,6 +10476,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.ANY_SNOOP", @@ -9480,6 +10487,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HITM_OTHER_C= ORE", @@ -9490,6 +10498,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CO= RE_FWD", @@ -9500,6 +10509,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", @@ -9510,6 +10520,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.NO_SNOOP_NEE= DED", @@ -9520,6 +10531,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_MISS", @@ -9530,6 +10542,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_E.SNOOP_NONE", @@ -9540,6 +10553,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.ANY_SNOOP", @@ -9550,6 +10564,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HITM_OTHER_C= ORE", @@ -9560,6 +10575,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CO= RE_FWD", @@ -9570,6 +10586,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", @@ -9580,6 +10597,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.NO_SNOOP_NEE= DED", @@ -9590,6 +10608,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_MISS", @@ -9600,6 +10619,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_F.SNOOP_NONE", @@ -9610,6 +10630,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.ANY_SNOOP", @@ -9620,6 +10641,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HITM_OTHER_C= ORE", @@ -9630,6 +10652,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CO= RE_FWD", @@ -9640,6 +10663,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", @@ -9650,6 +10674,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.NO_SNOOP_NEE= DED", @@ -9660,6 +10685,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_MISS", @@ -9670,6 +10696,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_M.SNOOP_NONE", @@ -9680,6 +10707,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.ANY_SNOOP", @@ -9690,6 +10718,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HITM_OTHER_C= ORE", @@ -9700,6 +10729,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CO= RE_FWD", @@ -9710,6 +10740,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", @@ -9720,6 +10751,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.NO_SNOOP_NEE= DED", @@ -9730,6 +10762,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_MISS", @@ -9740,6 +10773,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT_S.SNOOP_NONE", @@ -9750,6 +10784,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY= _SNOOP", @@ -9760,6 +10795,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", @@ -9770,6 +10806,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", @@ -9780,6 +10817,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNO= OP", @@ -9790,6 +10828,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OT= HER_CORE", @@ -9800,6 +10839,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", @@ -9810,6 +10850,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", @@ -9820,6 +10861,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOO= P_NEEDED", @@ -9830,6 +10872,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_M= ISS", @@ -9840,6 +10883,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_N= ONE", @@ -9850,6 +10894,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", @@ -9860,6 +10905,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", @@ -9870,6 +10916,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COR= E", @@ -9880,6 +10927,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _FWD", @@ -9890,6 +10938,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", @@ -9900,6 +10949,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", @@ -9910,6 +10960,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", @@ -9920,6 +10971,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_MISS", @@ -9930,6 +10982,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_NONE", @@ -9940,6 +10993,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.ANY_SNOOP", @@ -9950,6 +11004,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HITM_OTHER_C= ORE", @@ -9960,6 +11015,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_FWD", @@ -9970,6 +11026,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", @@ -9980,6 +11037,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.NO_SNOOP_NEE= DED", @@ -9990,6 +11048,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_MISS", @@ -10000,6 +11059,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_E.SNOOP_NONE", @@ -10010,6 +11070,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.ANY_SNOOP", @@ -10020,6 +11081,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HITM_OTHER_C= ORE", @@ -10030,6 +11092,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_FWD", @@ -10040,6 +11103,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", @@ -10050,6 +11114,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.NO_SNOOP_NEE= DED", @@ -10060,6 +11125,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_MISS", @@ -10070,6 +11136,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_F.SNOOP_NONE", @@ -10080,6 +11147,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.ANY_SNOOP", @@ -10090,6 +11158,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HITM_OTHER_C= ORE", @@ -10100,6 +11169,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_FWD", @@ -10110,6 +11180,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", @@ -10120,6 +11191,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.NO_SNOOP_NEE= DED", @@ -10130,6 +11202,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_MISS", @@ -10140,6 +11213,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_M.SNOOP_NONE", @@ -10150,6 +11224,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.ANY_SNOOP", @@ -10160,6 +11235,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HITM_OTHER_C= ORE", @@ -10170,6 +11246,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_FWD", @@ -10180,6 +11257,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", @@ -10190,6 +11268,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.NO_SNOOP_NEE= DED", @@ -10200,6 +11279,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_MISS", @@ -10210,6 +11290,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT_S.SNOOP_NONE", @@ -10220,6 +11301,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY= _SNOOP", @@ -10230,6 +11312,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", @@ -10240,6 +11323,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", @@ -10250,6 +11334,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", @@ -10260,6 +11345,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OT= HER_CORE", @@ -10270,6 +11356,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", @@ -10280,6 +11367,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", @@ -10290,6 +11378,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOO= P_NEEDED", @@ -10300,6 +11389,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", @@ -10310,6 +11400,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", @@ -10320,6 +11411,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", @@ -10330,6 +11422,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", @@ -10340,6 +11433,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", @@ -10350,6 +11444,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_FWD= ", @@ -10360,6 +11455,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", @@ -10370,6 +11466,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", @@ -10380,6 +11477,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", @@ -10390,6 +11488,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_MISS", @@ -10400,6 +11499,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_NONE", @@ -10410,6 +11510,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.ANY_SNOOP", @@ -10420,6 +11521,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HITM_OTHER_CORE", @@ -10430,6 +11532,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_F= WD", @@ -10440,6 +11543,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", @@ -10450,6 +11554,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.NO_SNOOP_NEEDED", @@ -10460,6 +11565,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_MISS", @@ -10470,6 +11576,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_E.SNOOP_NONE", @@ -10480,6 +11587,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.ANY_SNOOP", @@ -10490,6 +11598,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HITM_OTHER_CORE", @@ -10500,6 +11609,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_F= WD", @@ -10510,6 +11620,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", @@ -10520,6 +11631,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.NO_SNOOP_NEEDED", @@ -10530,6 +11642,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_MISS", @@ -10540,6 +11653,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_F.SNOOP_NONE", @@ -10550,6 +11664,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.ANY_SNOOP", @@ -10560,6 +11675,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HITM_OTHER_CORE", @@ -10570,6 +11686,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_F= WD", @@ -10580,6 +11697,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", @@ -10590,6 +11708,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.NO_SNOOP_NEEDED", @@ -10600,6 +11719,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_MISS", @@ -10610,6 +11730,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_M.SNOOP_NONE", @@ -10620,6 +11741,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.ANY_SNOOP", @@ -10630,6 +11752,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HITM_OTHER_CORE", @@ -10640,6 +11763,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_F= WD", @@ -10650,6 +11774,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", @@ -10660,6 +11785,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.NO_SNOOP_NEEDED", @@ -10670,6 +11796,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_MISS", @@ -10680,6 +11807,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT_S.SNOOP_NONE", @@ -10690,6 +11818,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNO= OP", @@ -10700,6 +11829,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", @@ -10710,6 +11840,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", @@ -10720,6 +11851,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", @@ -10730,6 +11862,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_= CORE", @@ -10740,6 +11873,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", @@ -10750,6 +11884,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", @@ -10760,6 +11895,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NE= EDED", @@ -10770,6 +11906,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", @@ -10780,6 +11917,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", @@ -10790,6 +11928,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", @@ -10800,6 +11939,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", @@ -10810,6 +11950,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COR= E", @@ -10820,6 +11961,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _FWD", @@ -10830,6 +11972,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", @@ -10840,6 +11983,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", @@ -10850,6 +11994,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", @@ -10860,6 +12005,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_MISS", @@ -10870,6 +12016,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_NONE", @@ -10880,6 +12027,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.ANY_SNOOP", @@ -10890,6 +12038,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HITM_OTHER_C= ORE", @@ -10900,6 +12049,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_FWD", @@ -10910,6 +12060,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.HIT_OTHER_CO= RE_NO_FWD", @@ -10920,6 +12071,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.NO_SNOOP_NEE= DED", @@ -10930,6 +12082,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_MISS", @@ -10940,6 +12093,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_E.SNOOP_NONE", @@ -10950,6 +12104,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.ANY_SNOOP", @@ -10960,6 +12115,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HITM_OTHER_C= ORE", @@ -10970,6 +12126,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_FWD", @@ -10980,6 +12137,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.HIT_OTHER_CO= RE_NO_FWD", @@ -10990,6 +12148,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.NO_SNOOP_NEE= DED", @@ -11000,6 +12159,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_MISS", @@ -11010,6 +12170,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_F.SNOOP_NONE", @@ -11020,6 +12181,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.ANY_SNOOP", @@ -11030,6 +12192,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HITM_OTHER_C= ORE", @@ -11040,6 +12203,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_FWD", @@ -11050,6 +12214,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.HIT_OTHER_CO= RE_NO_FWD", @@ -11060,6 +12225,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.NO_SNOOP_NEE= DED", @@ -11070,6 +12236,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_MISS", @@ -11080,6 +12247,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_M.SNOOP_NONE", @@ -11090,6 +12258,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.ANY_SNOOP", @@ -11100,6 +12269,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HITM_OTHER_C= ORE", @@ -11110,6 +12280,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_FWD", @@ -11120,6 +12291,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.HIT_OTHER_CO= RE_NO_FWD", @@ -11130,6 +12302,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.NO_SNOOP_NEE= DED", @@ -11140,6 +12313,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_MISS", @@ -11150,6 +12324,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT_S.SNOOP_NONE", @@ -11160,6 +12335,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY= _SNOOP", @@ -11170,6 +12346,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NONE", @@ -11180,6 +12357,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNO= OP_NOT_NEEDED", @@ -11190,6 +12368,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNO= OP", @@ -11200,6 +12379,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OT= HER_CORE", @@ -11210,6 +12390,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_FWD", @@ -11220,6 +12401,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTH= ER_CORE_NO_FWD", @@ -11230,6 +12412,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOO= P_NEEDED", @@ -11240,6 +12423,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_M= ISS", @@ -11250,6 +12434,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_N= ONE", @@ -11260,6 +12445,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", @@ -11270,6 +12456,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", @@ -11280,6 +12467,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", @@ -11290,6 +12478,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_FWD= ", @@ -11300,6 +12489,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", @@ -11310,6 +12500,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", @@ -11320,6 +12511,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", @@ -11330,6 +12522,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_MISS", @@ -11340,6 +12533,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_NONE", @@ -11350,6 +12544,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.ANY_SNOOP", @@ -11360,6 +12555,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HITM_OTHER_CORE", @@ -11370,6 +12566,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_F= WD", @@ -11380,6 +12577,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.HIT_OTHER_CORE_N= O_FWD", @@ -11390,6 +12588,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.NO_SNOOP_NEEDED", @@ -11400,6 +12599,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_MISS", @@ -11410,6 +12610,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_E.SNOOP_NONE", @@ -11420,6 +12621,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.ANY_SNOOP", @@ -11430,6 +12632,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HITM_OTHER_CORE", @@ -11440,6 +12643,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_F= WD", @@ -11450,6 +12654,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.HIT_OTHER_CORE_N= O_FWD", @@ -11460,6 +12665,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.NO_SNOOP_NEEDED", @@ -11470,6 +12676,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_MISS", @@ -11480,6 +12687,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_F.SNOOP_NONE", @@ -11490,6 +12698,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.ANY_SNOOP", @@ -11500,6 +12709,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HITM_OTHER_CORE", @@ -11510,6 +12720,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_F= WD", @@ -11520,6 +12731,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.HIT_OTHER_CORE_N= O_FWD", @@ -11530,6 +12742,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.NO_SNOOP_NEEDED", @@ -11540,6 +12753,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_MISS", @@ -11550,6 +12764,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_M.SNOOP_NONE", @@ -11560,6 +12775,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.ANY_SNOOP", @@ -11570,6 +12786,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HITM_OTHER_CORE", @@ -11580,6 +12797,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_F= WD", @@ -11590,6 +12808,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.HIT_OTHER_CORE_N= O_FWD", @@ -11600,6 +12819,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.NO_SNOOP_NEEDED", @@ -11610,6 +12830,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_MISS", @@ -11620,6 +12841,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT_S.SNOOP_NONE", @@ -11630,6 +12852,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNO= OP", @@ -11640,6 +12863,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= ONE", @@ -11650,6 +12874,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_N= OT_NEEDED", @@ -11660,6 +12885,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", @@ -11670,6 +12896,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_= CORE", @@ -11680,6 +12907,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_FWD", @@ -11690,6 +12918,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_C= ORE_NO_FWD", @@ -11700,6 +12929,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NE= EDED", @@ -11710,6 +12940,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", @@ -11720,6 +12951,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", @@ -11730,14 +12962,24 @@ }, { "BriefDescription": "Number of cache line split locks sent to unco= re.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "SampleAfterValue": "2000003", @@ -11745,6 +12987,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", @@ -11752,6 +12995,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", @@ -11759,6 +13003,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json b= /tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json index 297046818efe..b02a89e14c5d 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/clx-metrics.json @@ -68,7 +68,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -163,7 +163,7 @@ }, { "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12C= C0233@ / INST_RETIRED.ANY", + "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12c= c0233@ / INST_RETIRED.ANY", "MetricName": "llc_code_read_mpi_demand_plus_prefetch", "ScaleUnit": "1per_instr" }, @@ -187,7 +187,7 @@ }, { "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12D= 40433@ / INST_RETIRED.ANY", + "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12d= 40433@ / INST_RETIRED.ANY", "MetricName": "llc_data_read_mpi_demand_plus_prefetch", "ScaleUnit": "1per_instr" }, @@ -328,7 +328,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info= _thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -337,7 +337,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (IN= T_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) /= tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -358,7 +358,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -396,7 +396,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3= _HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.= DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER= _CORE_FWD))) + 44 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRE= D.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)= / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -417,7 +417,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "44 * tma_info_system_core_frequency * (MEM_LOAD_L3_= HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAND_= DATA_RD.L3_HIT.HITM_OTHER_CORE / (OCR.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE= + OCR.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_CORE_FWD))) * (1 + MEM_LOAD_RETIRED.= FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -435,7 +435,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -466,14 +466,14 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -482,7 +482,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -492,7 +492,7 @@ "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(110 * tma_info_system_core_frequency * (OCR.DEMAND= _RFO.L3_MISS.REMOTE_HITM + OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM) + 47.5 * tma_= info_system_core_frequency * (OCR.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE + OCR.P= F_L2_RFO.L3_HIT.HITM_OTHER_CORE)) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -502,7 +502,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -515,7 +515,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -530,6 +530,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;= tma_issueD0", "MetricName": "tma_few_uops_instructions", @@ -558,7 +559,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -605,7 +606,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -615,7 +616,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / U= OPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", @@ -634,7 +635,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDAT= A_STALL\\,cmask\\=3D1\\,edge@) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -667,24 +668,6 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BO= UND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.T= HREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU= _CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL= + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if = ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_= MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_POR= TS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE= _BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTE= D.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / = CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_U= TIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD = if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STAL= LS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_= PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_ut= ilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "tma_info_botlnk_core_bound_likely" - }, - { - "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHE= S.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2= * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@) / CPU_CLK_U= NHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CL= EAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_U= NHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + D= ECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_d= sb)))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "tma_info_botlnk_dsb_misses" - }, - { - "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", - "MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDA= TA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@)= / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16= B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@) / CPU_CLK_UNHALTED.THREAD += ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCL= ES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) = + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_= CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.T= HREAD)))", - "MetricGroup": "Fed;FetchLat;IcMiss", - "MetricName": "tma_info_botlnk_ic_misses" - }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricConstraint": "NO_GROUP_EVENTS", @@ -693,6 +676,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -700,7 +691,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -710,40 +701,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency = + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latenc= y + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound = + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l1= _hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_= latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -751,23 +736,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -775,8 +760,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= 4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_lo= ads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_s= tore_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_= split_stores + tma_store_latency)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= 4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_l= atency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_st= ore_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma= _false_sharing + tma_split_stores + tma_store_latency)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -784,7 +769,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) *= tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + t= ma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound = + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sha= ring) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bou= nd + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / = (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency = - tma_store_latency)) + tma_machine_clears * (1 - tma_other_nukes / tma_oth= er_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -793,18 +778,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -858,7 +850,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_R= ETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) / (2 * tma_info_core_core_clks= )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -875,7 +867,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 4 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -936,7 +928,7 @@ { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -1032,18 +1024,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" - }, - { - "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", - "MetricGroup": "Fed;MemoryTLB", - "MetricName": "tma_info_memory_code_stlb_mpki" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -1081,12 +1067,6 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, - { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -1094,17 +1074,11 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -1118,29 +1092,11 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, - { - "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" - }, - { - "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_silent_pki" - }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", @@ -1172,29 +1128,23 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duratio= n_time * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -1207,29 +1157,17 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_data_l2_mlp" }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "tma_info_memory_load_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" + "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, { "BriefDescription": "Average Parallel L2 cache miss demand Loads", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" + "MetricName": "tma_info_memory_latency_load_l2_mlp" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -1237,15 +1175,9 @@ "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, - { - "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_load_stlb_mpki" - }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "tma_info_memory_uc_load_pki", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -1256,18 +1188,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, - { - "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_store_stlb_mpki" - }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -1295,17 +1215,23 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_uc_load_pki" - }, - { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.A= NY)", @@ -1328,13 +1254,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1513,7 +1439,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1522,7 +1448,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1537,11 +1463,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_M= ISS) / tma_info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1559,7 +1494,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "17 * tma_info_system_core_frequency * (MEM_LOAD_RET= IRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2))= / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1571,7 +1506,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1616,7 +1551,7 @@ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", "MetricName": "tma_local_mem", "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 &= (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)= ))", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM_PS", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM", "ScaleUnit": "100%" }, { @@ -1625,14 +1560,14 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1642,7 +1577,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1651,7 +1586,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1678,6 +1613,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.M= S_UOPS / tma_info_thread_slots", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operatio= ns_group;tma_issueMC;tma_issueMS", "MetricName": "tma_microcode_sequencer", @@ -1688,7 +1624,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1724,7 +1660,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", @@ -1733,7 +1669,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETI= RED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1751,7 +1687,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1759,7 +1695,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1857,7 +1793,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * = RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOT= AL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks", + "MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_cl= ks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1885,7 +1821,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else= UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1912,7 +1848,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1922,7 +1858,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clk= s", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related me= trics: tma_ms_switches", @@ -1959,7 +1895,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1987,7 +1923,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -2020,7 +1956,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/counter.json b/too= ls/perf/pmu-events/arch/x86/cascadelakex/counter.json new file mode 100644 index 000000000000..e94b76404856 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/counter.json @@ -0,0 +1,52 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + }, + { + "Unit": "M3UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "1", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json index bb4d5101f962..1c709983b65f 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 512-bit packe= d double precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 8 computation operat= ions, one for each element. Applies to SSE* and AVX* packed double precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT= DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they p= erform 2 calculations per element. The DAZ and FTZ flags in the MXCSR regi= ster need to be set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 512-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 16 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT= DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they p= erform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQR= T DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they = perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR regi= ster need to be set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SU= B instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision and double precision floating-point instructions retire= d; some instructions will count twice as noted below. Each count represent= s 1 computational operation. Applies to SIMD scalar single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.= FM(N)ADD/SUB instructions count twice as they perform 2 calculations per = element. The DAZ and FTZ flags in the MXCSR register need to be set when us= ing these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Intel AVX-512 computational 512-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xCF", "EventName": "FP_ARITH_INST_RETIRED2.128BIT_PACKED_BF16", "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 512-bit packed BFloat16 floating-point instruction retired. Applies to= the ZMM based VDPBF16PS instruction. Each count represents 64 computation= operations. This event is only supported on products formerly named Cooper= Lake and is not supported on products formerly named Cascade Lake.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Intel AVX-512 computational 128-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xCF", "EventName": "FP_ARITH_INST_RETIRED2.256BIT_PACKED_BF16", "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 128-bit packed BFloat16 floating-point instruction retired. Applies to= the XMM based VDPBF16PS instruction. Each count represents 16 computation = operations. This event is only supported on products formerly named Cooper = Lake and is not supported on products formerly named Cascade Lake.", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Intel AVX-512 computational 256-bit packed BF= loat16 instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xCF", "EventName": "FP_ARITH_INST_RETIRED2.512BIT_PACKED_BF16", "PublicDescription": "Counts once for each Intel AVX-512 computati= onal 256-bit packed BFloat16 floating-point instruction retired. Applies to= the YMM based VDPBF16PS instruction. Each count represents 32 computation= operations. This event is only supported on products formerly named Cooper= Lake and is not supported on products formerly named Cascade Lake.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/frontend.json index d6f543471b24..0e1dedce00f2 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking = MITE requires two or three cycles delay.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -66,6 +73,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -86,6 +95,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -107,6 +118,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -118,6 +130,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -128,6 +141,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -149,6 +164,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "MSRIndex": "0x3F7", @@ -159,6 +175,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "MSRIndex": "0x3F7", @@ -169,6 +186,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -180,6 +198,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -190,6 +209,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -200,6 +220,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -210,6 +231,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -232,6 +255,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", @@ -240,6 +264,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "SampleAfterValue": "200003", @@ -247,6 +272,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "SampleAfterValue": "200003", @@ -254,6 +280,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "SampleAfterValue": "200003", @@ -261,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "SampleAfterValue": "200003", @@ -268,6 +296,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -277,6 +306,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -286,6 +316,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -295,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -304,6 +336,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -313,6 +346,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -322,6 +356,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -331,6 +366,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", @@ -339,6 +375,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -348,6 +385,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", @@ -356,6 +394,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -365,6 +404,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -374,6 +414,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -382,6 +423,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -392,6 +434,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -400,6 +443,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", @@ -408,6 +452,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -417,6 +462,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -426,6 +472,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -435,6 +482,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -444,6 +492,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json b/tool= s/perf/pmu-events/arch/x86/cascadelakex/memory.json index c69b2c33334b..bab4ca603f08 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "Errata": "SKL089", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -135,6 +150,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -159,6 +176,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -171,6 +189,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -183,6 +202,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_DAT= A_RD.L3_MISS.ANY_SNOOP OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -192,6 +212,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.A= LL_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -201,6 +222,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OC= R.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_= CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -210,6 +232,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD= OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS.HIT_= OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -219,6 +242,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.A= LL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -228,6 +252,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM OCR.ALL_D= ATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -237,6 +262,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD OC= R.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -246,6 +272,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL_DA= TA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -255,6 +282,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL_DA= TA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -264,6 +292,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -273,6 +302,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER= _CORE OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -282,6 +312,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -291,6 +322,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -300,6 +332,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_N= EEDED OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -309,6 +342,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -318,6 +352,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS= _OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -327,6 +362,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -336,6 +372,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MIS= S_OR_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -345,6 +382,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_= SNOOP OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -354,6 +392,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM= _OTHER_CORE OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_= CORE", "MSRIndex": "0x1a6,0x1a7", @@ -363,6 +402,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_C= ORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -372,6 +412,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_NO_FWD OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_C= ORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -381,6 +422,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_S= NOOP_NEEDED OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -390,6 +432,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -399,6 +442,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -408,6 +452,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_= PF_DATA_RD.L3_MISS.ANY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -417,6 +462,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OC= R.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OT= HER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -426,6 +472,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD= OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS.H= IT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -435,6 +482,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_= FWD OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_= MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -444,6 +492,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OC= R.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOO= P_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -453,6 +502,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM OCR.AL= L_PF_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -462,6 +512,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD= OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -471,6 +522,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS OCR.ALL= _PF_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -480,6 +532,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE OCR.ALL= _PF_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -489,6 +542,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNO= OP OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -498,6 +552,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OT= HER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -507,6 +562,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTH= ER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -516,6 +572,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTH= ER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -525,6 +582,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOO= P_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +592,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_M= ISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -543,6 +602,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_M= ISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -552,6 +612,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_N= ONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -561,6 +622,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_= MISS_OR_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -570,6 +632,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.A= NY_SNOOP OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", @@ -579,6 +642,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.H= ITM_OTHER_CORE OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTH= ER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -588,6 +652,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.H= IT_OTHER_CORE_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -597,6 +662,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.H= IT_OTHER_CORE_NO_FWD OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -606,6 +672,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.N= O_SNOOP_NEEDED OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -615,6 +682,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.S= NOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +692,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.S= NOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", @@ -633,6 +702,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP OCR.ALL_PF_R= FO.L3_MISS.ANY_SNOOP OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -642,6 +712,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.AL= L_PF_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -651,6 +722,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR= .ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_COR= E_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -660,6 +732,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD = OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS.HIT_OTH= ER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -669,6 +742,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.AL= L_PF_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -678,6 +752,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM OCR.ALL_PF= _RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -687,6 +762,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR= .ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -696,6 +772,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS OCR.ALL_PF_= RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -705,6 +782,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE OCR.ALL_PF_= RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +792,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -723,6 +802,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_= CORE OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -732,6 +812,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_C= ORE_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -741,6 +822,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_C= ORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -750,6 +832,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NE= EDED OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -759,6 +842,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -768,6 +852,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_= OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -777,6 +862,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -786,6 +872,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS= _OR_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -795,6 +882,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_S= NOOP OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -804,6 +892,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_= OTHER_CORE OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -813,6 +902,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_O= THER_CORE_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -822,6 +912,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_O= THER_CORE_NO_FWD OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO= _FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -831,6 +922,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SN= OOP_NEEDED OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -840,6 +932,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP= _MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -849,6 +942,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP= _NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -858,6 +952,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.ANY_SNOOP OCR.ALL_READS= .L3_MISS.ANY_SNOOP OCR.ALL_READS.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -867,6 +962,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE OCR.ALL= _READS.L3_MISS.HITM_OTHER_CORE OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +972,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.= ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_F= WD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -885,6 +982,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD O= CR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_READS.L3_MISS.HIT_OTHER_= CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -894,6 +992,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL= _READS.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -903,6 +1002,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HITM OCR.ALL_REA= DS.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -912,6 +1012,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD OCR.= ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -921,6 +1022,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_MISS OCR.ALL_READ= S.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -930,6 +1032,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS.SNOOP_NONE OCR.ALL_READ= S.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -939,6 +1042,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP O= CR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -948,6 +1052,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_C= ORE OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -957,6 +1062,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CO= RE_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -966,6 +1072,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CO= RE_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -975,6 +1082,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEE= DED OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -984,6 +1092,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -993,6 +1102,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_O= R_NO_FWD OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1002,6 +1112,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1011,6 +1122,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_= OR_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -1020,6 +1132,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SN= OOP OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1029,6 +1142,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_O= THER_CORE OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -1038,6 +1152,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OT= HER_CORE_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1047,6 +1162,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OT= HER_CORE_NO_FWD OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_F= WD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1056,6 +1172,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNO= OP_NEEDED OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1065,6 +1182,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_= MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1074,6 +1192,7 @@ }, { "BriefDescription": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_= NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1083,6 +1202,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP OCR.ALL_RFO.L3_= MISS.ANY_SNOOP OCR.ALL_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1092,6 +1212,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE OCR.ALL_R= FO.L3_MISS.HITM_OTHER_CORE OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1101,6 +1222,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.AL= L_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1110,6 +1232,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR= .ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_N= O_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1119,6 +1242,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_R= FO.L3_MISS.NO_SNOOP_NEEDED OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1128,6 +1252,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM OCR.ALL_RFO.L= 3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1137,6 +1262,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD OCR.AL= L_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -1146,6 +1272,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS OCR.ALL_RFO.L3= _MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1155,6 +1282,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE OCR.ALL_RFO.L3= _MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1164,6 +1292,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP OCR= .ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1173,6 +1302,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_COR= E OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1182,6 +1312,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1191,6 +1322,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1200,6 +1332,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1209,6 +1342,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1218,6 +1352,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1227,6 +1362,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1236,6 +1372,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1245,6 +1382,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOO= P OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1254,6 +1392,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTH= ER_CORE OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1263,6 +1402,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1272,6 +1412,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1281,6 +1422,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -1290,6 +1432,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1299,6 +1442,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1308,6 +1452,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.ANY_SNOOP OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1317,6 +1462,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1326,6 +1472,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1335,6 +1482,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_= NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1344,6 +1492,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1353,6 +1502,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1362,6 +1512,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -1371,6 +1522,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1380,6 +1532,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1389,6 +1542,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1398,6 +1552,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1407,6 +1562,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1416,6 +1572,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1425,6 +1582,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1434,6 +1592,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1443,6 +1602,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1452,6 +1612,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1461,6 +1622,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1470,6 +1632,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", @@ -1479,6 +1642,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTH= ER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1488,6 +1652,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1497,6 +1662,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1506,6 +1672,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1515,6 +1682,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", @@ -1524,6 +1692,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", @@ -1533,6 +1702,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.ANY_SNOOP OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1542,6 +1712,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.HITM_OTHER_CORE OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1551,6 +1722,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1560,6 +1732,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_F= WD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1569,6 +1742,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1578,6 +1752,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1587,6 +1762,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -1596,6 +1772,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1605,6 +1782,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1614,6 +1792,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1623,6 +1802,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1632,6 +1812,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1641,6 +1822,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1650,6 +1832,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1659,6 +1842,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1668,6 +1852,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1677,6 +1862,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1686,6 +1872,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.L= 3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1695,6 +1882,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", @@ -1704,6 +1892,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTH= ER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1713,6 +1902,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1722,6 +1912,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHE= R_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1731,6 +1922,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP= _NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1740,6 +1932,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", @@ -1749,6 +1942,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", @@ -1758,6 +1952,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.ANY_SNOOP OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1767,6 +1962,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.HITM_OTHER_CORE OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1776,6 +1972,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1785,6 +1982,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_= NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1794,6 +1992,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1803,6 +2002,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1812,6 +2012,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -1821,6 +2022,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1830,6 +2032,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1839,6 +2042,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1848,6 +2052,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1857,6 +2062,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1866,6 +2072,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1875,6 +2082,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1884,6 +2092,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1893,6 +2102,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -1902,6 +2112,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1911,6 +2122,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1920,6 +2132,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1929,6 +2142,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -1938,6 +2152,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1947,6 +2162,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1956,6 +2172,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1965,6 +2182,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1974,6 +2192,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1983,6 +2202,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.A= NY_SNOOP OCR.OTHER.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1992,6 +2212,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.H= ITM_OTHER_CORE OCR.OTHER.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2001,6 +2222,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.H= IT_OTHER_CORE_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2010,6 +2232,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.H= IT_OTHER_CORE_NO_FWD OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2019,6 +2242,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.N= O_SNOOP_NEEDED OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2028,6 +2252,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.R= EMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2037,6 +2262,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.R= EMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -2046,6 +2272,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.S= NOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2055,6 +2282,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS.S= NOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2064,6 +2292,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2073,6 +2302,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2082,6 +2312,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2091,6 +2322,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2100,6 +2332,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2109,6 +2342,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2118,6 +2352,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_L= OCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2127,6 +2362,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2136,6 +2372,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_R= EMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2145,6 +2382,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2154,6 +2392,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2163,6 +2402,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -2172,6 +2412,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2181,6 +2422,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.L3_MISS_= REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2190,6 +2432,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2199,6 +2442,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2208,6 +2452,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP OCR.P= F_L1D_AND_SW.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2217,6 +2462,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE= OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2226,6 +2472,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_= FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2235,6 +2482,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_= NO_FWD OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2244,6 +2492,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED= OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2253,6 +2502,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2262,6 +2512,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORW= ARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -2271,6 +2522,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2280,6 +2532,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2289,6 +2542,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY= _SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2298,6 +2552,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT= M_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -2307,6 +2562,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT= _OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2316,6 +2572,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT= _OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2325,6 +2582,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_= SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -2334,6 +2592,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2343,6 +2602,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2352,6 +2612,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2361,6 +2622,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2370,6 +2632,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DR= AM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP= ", "MSRIndex": "0x1a6,0x1a7", @@ -2379,6 +2642,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DR= AM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHE= R_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2388,6 +2652,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DR= AM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2397,6 +2662,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DR= AM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2406,6 +2672,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DR= AM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2415,6 +2682,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", @@ -2424,6 +2692,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", @@ -2433,6 +2702,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNO= OP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2442,6 +2712,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_DATA_RD.L3_MISS.H= ITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2451,6 +2722,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_DATA_RD.L3_MIS= S.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2460,6 +2732,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_DATA_RD.L3_= MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2469,6 +2742,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_DATA_RD.L3_MISS.N= O_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2478,6 +2752,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2487,6 +2762,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -2496,6 +2772,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2505,6 +2782,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2514,6 +2792,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2523,6 +2802,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -2532,6 +2812,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2541,6 +2822,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2550,6 +2832,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -2559,6 +2842,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2568,6 +2852,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2577,6 +2862,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2586,6 +2872,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2595,6 +2882,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP= ", "MSRIndex": "0x1a6,0x1a7", @@ -2604,6 +2892,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHE= R_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2613,6 +2902,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2622,6 +2912,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2631,6 +2922,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2640,6 +2932,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", @@ -2649,6 +2942,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", @@ -2658,6 +2952,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2667,6 +2962,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_= CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2676,6 +2972,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L2_RFO.L3_MISS.HIT_OTHE= R_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2685,6 +2982,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L2_RFO.L3_MISS.HIT_O= THER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2694,6 +2992,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NE= EDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2703,6 +3002,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2712,6 +3012,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -2721,6 +3022,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2730,6 +3032,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2739,6 +3042,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2748,6 +3052,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2757,6 +3062,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2766,6 +3072,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -2775,6 +3082,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2784,6 +3092,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2793,6 +3102,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -2802,6 +3112,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2811,6 +3122,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -2820,6 +3132,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2829,6 +3142,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -2838,6 +3152,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2847,6 +3162,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2856,6 +3172,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -2865,6 +3182,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2874,6 +3192,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2883,6 +3202,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP OCR.PF_L3_DATA_RD.L3_MI= SS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2892,6 +3212,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_DATA_RD= .L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2901,6 +3222,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_DATA= _RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2910,6 +3232,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_D= ATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2919,6 +3242,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_DATA_RD= .L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -2928,6 +3252,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2937,6 +3262,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -2946,6 +3272,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2955,6 +3282,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2964,6 +3292,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2973,6 +3302,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -2982,6 +3312,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2991,6 +3322,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3000,6 +3332,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -3009,6 +3342,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3018,6 +3352,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3027,6 +3362,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3036,6 +3372,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3045,6 +3382,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP= ", "MSRIndex": "0x1a6,0x1a7", @@ -3054,6 +3392,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHE= R_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3063,6 +3402,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3072,6 +3412,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_= NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER= _CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3081,6 +3422,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3090,6 +3432,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MIS= S", "MSRIndex": "0x1a6,0x1a7", @@ -3099,6 +3442,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NON= E", "MSRIndex": "0x1a6,0x1a7", @@ -3108,6 +3452,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3117,6 +3462,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE OCR.PF_L3_RFO.L3_MISS.HITM_= OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3126,6 +3472,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD OCR.PF_L3_RFO.L3_MISS.HI= T_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3135,6 +3482,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD OCR.PF_L3_RFO.L3_MISS= .HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3144,6 +3492,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED OCR.PF_L3_RFO.L3_MISS.NO_SN= OOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3153,6 +3502,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -3162,6 +3512,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -3171,6 +3522,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3180,6 +3532,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3189,6 +3542,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3198,6 +3552,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -3207,6 +3562,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3216,6 +3572,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -3225,6 +3582,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -3234,6 +3592,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3243,6 +3602,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -3252,6 +3612,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3261,6 +3622,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -3270,6 +3632,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -3279,6 +3642,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -3288,6 +3652,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3297,6 +3662,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -3306,6 +3672,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -3315,6 +3682,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -3324,6 +3692,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -3333,6 +3702,7 @@ }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -3341,6 +3711,7 @@ }, { "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -3349,6 +3720,7 @@ }, { "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -3356,6 +3728,7 @@ }, { "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -3364,6 +3737,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", @@ -3374,6 +3748,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HITM_OTHER_CORE= ", @@ -3384,6 +3759,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_= FWD", @@ -3394,6 +3770,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.HIT_OTHER_CORE_= NO_FWD", @@ -3404,6 +3781,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.NO_SNOOP_NEEDED= ", @@ -3414,6 +3792,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", @@ -3424,6 +3803,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORW= ARD", @@ -3434,6 +3814,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS", @@ -3444,6 +3825,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_NONE", @@ -3454,6 +3836,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_= SNOOP", @@ -3464,6 +3847,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HITM= _OTHER_CORE", @@ -3474,6 +3858,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_= OTHER_CORE_FWD", @@ -3484,6 +3869,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_= OTHER_CORE_NO_FWD", @@ -3494,6 +3880,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.NO_S= NOOP_NEEDED", @@ -3504,6 +3891,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS", @@ -3514,6 +3902,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", @@ -3524,6 +3913,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_NONE", @@ -3534,6 +3924,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", @@ -3544,6 +3935,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.ANY_SNOOP", @@ -3554,6 +3946,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.HITM_OTHER_CORE", @@ -3564,6 +3957,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.HIT_OTHER_CORE_FWD", @@ -3574,6 +3968,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.HIT_OTHER_CORE_NO_FWD", @@ -3584,6 +3979,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.NO_SNOOP_NEEDED", @@ -3594,6 +3990,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.SNOOP_MISS", @@ -3604,6 +4001,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_HOP1_DRA= M.SNOOP_NONE", @@ -3614,6 +4012,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", @@ -3624,6 +4023,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HITM_OTHER_C= ORE", @@ -3634,6 +4034,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", @@ -3644,6 +4045,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", @@ -3654,6 +4056,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.NO_SNOOP_NEE= DED", @@ -3664,6 +4067,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", @@ -3674,6 +4078,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", @@ -3684,6 +4089,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS", @@ -3694,6 +4100,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_NONE", @@ -3704,6 +4111,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", @@ -3714,6 +4122,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.H= ITM_OTHER_CORE", @@ -3724,6 +4133,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", @@ -3734,6 +4144,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", @@ -3744,6 +4155,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", @@ -3754,6 +4166,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", @@ -3764,6 +4177,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -3774,6 +4188,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", @@ -3784,6 +4199,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", @@ -3794,6 +4210,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.ANY_SNOOP", @@ -3804,6 +4221,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HITM_OTHER_CORE", @@ -3814,6 +4232,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", @@ -3824,6 +4243,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", @@ -3834,6 +4254,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", @@ -3844,6 +4265,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", @@ -3854,6 +4276,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", @@ -3864,6 +4287,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", @@ -3874,6 +4298,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HITM_OTHER_CORE", @@ -3884,6 +4309,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_F= WD", @@ -3894,6 +4320,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.HIT_OTHER_CORE_N= O_FWD", @@ -3904,6 +4331,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.NO_SNOOP_NEEDED", @@ -3914,6 +4342,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", @@ -3924,6 +4353,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", @@ -3934,6 +4364,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS", @@ -3944,6 +4375,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_NONE", @@ -3954,6 +4386,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", @@ -3964,6 +4397,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HITM_= OTHER_CORE", @@ -3974,6 +4408,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_FWD", @@ -3984,6 +4419,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_NO_FWD", @@ -3994,6 +4430,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.NO_SN= OOP_NEEDED", @@ -4004,6 +4441,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", @@ -4014,6 +4452,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", @@ -4024,6 +4463,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", @@ -4034,6 +4474,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", @@ -4044,6 +4485,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .ANY_SNOOP", @@ -4054,6 +4496,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HITM_OTHER_CORE", @@ -4064,6 +4507,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_FWD", @@ -4074,6 +4518,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_NO_FWD", @@ -4084,6 +4529,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .NO_SNOOP_NEEDED", @@ -4094,6 +4540,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_MISS", @@ -4104,6 +4551,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_NONE", @@ -4114,6 +4562,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_SNOOP", @@ -4124,6 +4573,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HITM_OTHER_CORE", @@ -4134,6 +4584,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_FW= D", @@ -4144,6 +4595,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.HIT_OTHER_CORE_NO= _FWD", @@ -4154,6 +4606,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.NO_SNOOP_NEEDED", @@ -4164,6 +4617,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HITM", @@ -4174,6 +4628,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.REMOTE_HIT_FORWAR= D", @@ -4184,6 +4639,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_MISS", @@ -4194,6 +4650,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.SNOOP_NONE", @@ -4204,6 +4661,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", @@ -4214,6 +4672,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HITM_O= THER_CORE", @@ -4224,6 +4683,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", @@ -4234,6 +4694,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", @@ -4244,6 +4705,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", @@ -4254,6 +4716,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", @@ -4264,6 +4727,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", @@ -4274,6 +4738,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", @@ -4284,6 +4749,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", @@ -4294,6 +4760,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= ANY_SNOOP", @@ -4304,6 +4771,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= HITM_OTHER_CORE", @@ -4314,6 +4782,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", @@ -4324,6 +4793,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", @@ -4334,6 +4804,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", @@ -4344,6 +4815,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", @@ -4354,6 +4826,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", @@ -4364,6 +4837,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", @@ -4374,6 +4848,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HITM_OTHER_CORE", @@ -4384,6 +4859,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_FWD", @@ -4394,6 +4870,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.HIT_OTHER_CORE_NO_F= WD", @@ -4404,6 +4881,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.NO_SNOOP_NEEDED", @@ -4414,6 +4892,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", @@ -4424,6 +4903,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", @@ -4434,6 +4914,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS", @@ -4444,6 +4925,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_NONE", @@ -4454,6 +4936,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOO= P", @@ -4464,6 +4947,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HITM_OTH= ER_CORE", @@ -4474,6 +4958,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHE= R_CORE_FWD", @@ -4484,6 +4969,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHE= R_CORE_NO_FWD", @@ -4494,6 +4980,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP= _NEEDED", @@ -4504,6 +4991,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS", @@ -4514,6 +5002,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS_OR_NO_FWD", @@ -4524,6 +5013,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NO= NE", @@ -4534,6 +5024,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_M= ISS_OR_NO_FWD", @@ -4544,6 +5035,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.AN= Y_SNOOP", @@ -4554,6 +5046,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HI= TM_OTHER_CORE", @@ -4564,6 +5057,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HI= T_OTHER_CORE_FWD", @@ -4574,6 +5068,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.HI= T_OTHER_CORE_NO_FWD", @@ -4584,6 +5079,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO= _SNOOP_NEEDED", @@ -4594,6 +5090,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SN= OOP_MISS", @@ -4604,6 +5101,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_HOP1_DRAM.SN= OOP_NONE", @@ -4614,6 +5112,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", @@ -4624,6 +5123,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HITM_OTHER_C= ORE", @@ -4634,6 +5134,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", @@ -4644,6 +5145,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", @@ -4654,6 +5156,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.NO_SNOOP_NEE= DED", @@ -4664,6 +5167,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", @@ -4674,6 +5178,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_F= ORWARD", @@ -4684,6 +5189,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", @@ -4694,6 +5200,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", @@ -4704,6 +5211,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", @@ -4714,6 +5222,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.H= ITM_OTHER_CORE", @@ -4724,6 +5233,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", @@ -4734,6 +5244,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", @@ -4744,6 +5255,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", @@ -4754,6 +5266,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", @@ -4764,6 +5277,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -4774,6 +5288,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", @@ -4784,6 +5299,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", @@ -4794,6 +5310,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.ANY_SNOOP", @@ -4804,6 +5321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.HITM_OTHER_CORE", @@ -4814,6 +5332,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", @@ -4824,6 +5343,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", @@ -4834,6 +5354,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", @@ -4844,6 +5365,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", @@ -4854,6 +5376,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", @@ -4864,6 +5387,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", @@ -4874,6 +5398,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HITM_OTHER_C= ORE", @@ -4884,6 +5409,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_FWD", @@ -4894,6 +5420,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.HIT_OTHER_CO= RE_NO_FWD", @@ -4904,6 +5431,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.NO_SNOOP_NEE= DED", @@ -4914,6 +5442,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", @@ -4924,6 +5453,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", @@ -4934,6 +5464,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", @@ -4944,6 +5475,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", @@ -4954,6 +5486,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", @@ -4964,6 +5497,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.H= ITM_OTHER_CORE", @@ -4974,6 +5508,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_FWD", @@ -4984,6 +5519,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.H= IT_OTHER_CORE_NO_FWD", @@ -4994,6 +5530,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.N= O_SNOOP_NEEDED", @@ -5004,6 +5541,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", @@ -5014,6 +5552,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -5024,6 +5563,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", @@ -5034,6 +5574,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", @@ -5044,6 +5585,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.ANY_SNOOP", @@ -5054,6 +5596,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HITM_OTHER_CORE", @@ -5064,6 +5607,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_FWD", @@ -5074,6 +5618,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.HIT_OTHER_CORE_NO_FWD", @@ -5084,6 +5629,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.NO_SNOOP_NEEDED", @@ -5094,6 +5640,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_MISS", @@ -5104,6 +5651,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_HOP1_= DRAM.SNOOP_NONE", @@ -5114,6 +5662,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", @@ -5124,6 +5673,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HITM_OTHER_CORE", @@ -5134,6 +5684,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_F= WD", @@ -5144,6 +5695,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.HIT_OTHER_CORE_N= O_FWD", @@ -5154,6 +5706,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.NO_SNOOP_NEEDED", @@ -5164,6 +5717,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", @@ -5174,6 +5728,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", @@ -5184,6 +5739,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", @@ -5194,6 +5750,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", @@ -5204,6 +5761,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", @@ -5214,6 +5772,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HITM_= OTHER_CORE", @@ -5224,6 +5783,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_FWD", @@ -5234,6 +5794,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.HIT_O= THER_CORE_NO_FWD", @@ -5244,6 +5805,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.NO_SN= OOP_NEEDED", @@ -5254,6 +5816,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", @@ -5264,6 +5827,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", @@ -5274,6 +5838,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", @@ -5284,6 +5849,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", @@ -5294,6 +5860,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .ANY_SNOOP", @@ -5304,6 +5871,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HITM_OTHER_CORE", @@ -5314,6 +5882,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_FWD", @@ -5324,6 +5893,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .HIT_OTHER_CORE_NO_FWD", @@ -5334,6 +5904,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .NO_SNOOP_NEEDED", @@ -5344,6 +5915,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_MISS", @@ -5354,6 +5926,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_HOP1_DRAM= .SNOOP_NONE", @@ -5364,6 +5937,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", @@ -5374,6 +5948,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HITM_OTHER_CORE", @@ -5384,6 +5959,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_FWD", @@ -5394,6 +5970,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.HIT_OTHER_CORE_NO_FWD= ", @@ -5404,6 +5981,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.NO_SNOOP_NEEDED", @@ -5414,6 +5992,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HITM", @@ -5424,6 +6003,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.REMOTE_HIT_FORWARD", @@ -5434,6 +6014,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", @@ -5444,6 +6025,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", @@ -5454,6 +6036,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", @@ -5464,6 +6047,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HITM_OTHER= _CORE", @@ -5474,6 +6058,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_FWD", @@ -5484,6 +6069,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.HIT_OTHER_= CORE_NO_FWD", @@ -5494,6 +6080,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.NO_SNOOP_N= EEDED", @@ -5504,6 +6091,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", @@ -5514,6 +6102,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= _OR_NO_FWD", @@ -5524,6 +6113,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", @@ -5534,6 +6124,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_DRAM.SNOOP_MIS= S_OR_NO_FWD", @@ -5544,6 +6135,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.ANY_= SNOOP", @@ -5554,6 +6146,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HITM= _OTHER_CORE", @@ -5564,6 +6157,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_FWD", @@ -5574,6 +6168,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.HIT_= OTHER_CORE_NO_FWD", @@ -5584,6 +6179,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.NO_S= NOOP_NEEDED", @@ -5594,6 +6190,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_MISS", @@ -5604,6 +6201,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_REMOTE_HOP1_DRAM.SNOO= P_NONE", @@ -5614,6 +6212,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", @@ -5624,6 +6223,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HITM_OTHER_CO= RE", @@ -5634,6 +6234,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_COR= E_FWD", @@ -5644,6 +6245,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.HIT_OTHER_COR= E_NO_FWD", @@ -5654,6 +6256,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.NO_SNOOP_NEED= ED", @@ -5664,6 +6267,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", @@ -5674,6 +6278,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FO= RWARD", @@ -5684,6 +6289,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS", @@ -5694,6 +6300,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_NONE", @@ -5704,6 +6311,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", @@ -5714,6 +6322,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HI= TM_OTHER_CORE", @@ -5724,6 +6333,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", @@ -5734,6 +6344,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", @@ -5744,6 +6355,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", @@ -5754,6 +6366,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", @@ -5764,6 +6377,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", @@ -5774,6 +6388,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", @@ -5784,6 +6399,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -5794,6 +6410,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.ANY_SNOOP", @@ -5804,6 +6421,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.HITM_OTHER_CORE", @@ -5814,6 +6432,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", @@ -5824,6 +6443,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", @@ -5834,6 +6454,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", @@ -5844,6 +6465,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", @@ -5854,6 +6476,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", @@ -5864,6 +6487,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", @@ -5874,6 +6498,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HITM_OTHER_CO= RE", @@ -5884,6 +6509,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_COR= E_FWD", @@ -5894,6 +6520,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.HIT_OTHER_COR= E_NO_FWD", @@ -5904,6 +6531,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.NO_SNOOP_NEED= ED", @@ -5914,6 +6542,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", @@ -5924,6 +6553,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", @@ -5934,6 +6564,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS", @@ -5944,6 +6575,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_NONE", @@ -5954,6 +6586,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", @@ -5964,6 +6597,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HI= TM_OTHER_CORE", @@ -5974,6 +6608,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", @@ -5984,6 +6619,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", @@ -5994,6 +6630,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", @@ -6004,6 +6641,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", @@ -6014,6 +6652,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", @@ -6024,6 +6663,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", @@ -6034,6 +6674,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -6044,6 +6685,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.ANY_SNOOP", @@ -6054,6 +6696,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HITM_OTHER_CORE", @@ -6064,6 +6707,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", @@ -6074,6 +6718,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", @@ -6084,6 +6729,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", @@ -6094,6 +6740,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", @@ -6104,6 +6751,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", @@ -6114,6 +6762,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", @@ -6124,6 +6773,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HITM_OTHER_CORE", @@ -6134,6 +6784,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_FW= D", @@ -6144,6 +6795,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.HIT_OTHER_CORE_NO= _FWD", @@ -6154,6 +6806,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.NO_SNOOP_NEEDED", @@ -6164,6 +6817,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", @@ -6174,6 +6828,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", @@ -6184,6 +6839,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS", @@ -6194,6 +6850,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_NONE", @@ -6204,6 +6861,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", @@ -6214,6 +6872,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HITM_O= THER_CORE", @@ -6224,6 +6883,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", @@ -6234,6 +6894,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", @@ -6244,6 +6905,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", @@ -6254,6 +6916,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", @@ -6264,6 +6927,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", @@ -6274,6 +6938,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", @@ -6284,6 +6949,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", @@ -6294,6 +6960,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= ANY_SNOOP", @@ -6304,6 +6971,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HITM_OTHER_CORE", @@ -6314,6 +6982,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", @@ -6324,6 +6993,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", @@ -6334,6 +7004,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", @@ -6344,6 +7015,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", @@ -6354,6 +7026,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", @@ -6364,6 +7037,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", @@ -6374,6 +7048,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HITM_OTHER_CO= RE", @@ -6384,6 +7059,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_COR= E_FWD", @@ -6394,6 +7070,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.HIT_OTHER_COR= E_NO_FWD", @@ -6404,6 +7081,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.NO_SNOOP_NEED= ED", @@ -6414,6 +7092,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", @@ -6424,6 +7103,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", @@ -6434,6 +7114,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS", @@ -6444,6 +7125,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_NONE", @@ -6454,6 +7136,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.AN= Y_SNOOP", @@ -6464,6 +7147,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HI= TM_OTHER_CORE", @@ -6474,6 +7158,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_FWD", @@ -6484,6 +7169,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.HI= T_OTHER_CORE_NO_FWD", @@ -6494,6 +7180,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.NO= _SNOOP_NEEDED", @@ -6504,6 +7191,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS", @@ -6514,6 +7202,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", @@ -6524,6 +7213,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_NONE", @@ -6534,6 +7224,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", @@ -6544,6 +7235,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.ANY_SNOOP", @@ -6554,6 +7246,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HITM_OTHER_CORE", @@ -6564,6 +7257,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_FWD", @@ -6574,6 +7268,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.HIT_OTHER_CORE_NO_FWD", @@ -6584,6 +7279,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.NO_SNOOP_NEEDED", @@ -6594,6 +7290,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_MISS", @@ -6604,6 +7301,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_HOP1_D= RAM.SNOOP_NONE", @@ -6614,6 +7312,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", @@ -6624,6 +7323,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HITM_OTHER_CORE", @@ -6634,6 +7334,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_FW= D", @@ -6644,6 +7345,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.HIT_OTHER_CORE_NO= _FWD", @@ -6654,6 +7356,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.NO_SNOOP_NEEDED", @@ -6664,6 +7367,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.REMOTE_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", @@ -6674,6 +7378,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWARD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", @@ -6684,6 +7389,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS", @@ -6694,6 +7400,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_NONE", @@ -6704,6 +7411,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.ANY_SN= OOP", @@ -6714,6 +7422,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HITM_O= THER_CORE", @@ -6724,6 +7433,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_FWD", @@ -6734,6 +7444,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.HIT_OT= HER_CORE_NO_FWD", @@ -6744,6 +7455,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.NO_SNO= OP_NEEDED", @@ -6754,6 +7466,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS", @@ -6764,6 +7477,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", @@ -6774,6 +7488,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= NONE", @@ -6784,6 +7499,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP_MISS_OR_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", @@ -6794,6 +7510,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.ANY_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= ANY_SNOOP", @@ -6804,6 +7521,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HITM_OTHER_CORE", @@ -6814,6 +7532,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_FWD", @@ -6824,6 +7543,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= HIT_OTHER_CORE_NO_FWD", @@ -6834,6 +7554,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= NO_SNOOP_NEEDED", @@ -6844,6 +7565,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_MISS", @@ -6854,6 +7576,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.SNOOP_NONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_HOP1_DRAM.= SNOOP_NONE", @@ -6864,6 +7587,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "2", @@ -6873,6 +7597,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -6881,6 +7606,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -6889,6 +7615,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", @@ -6897,6 +7624,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -6904,6 +7632,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", @@ -6912,6 +7641,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -6920,6 +7650,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", @@ -6928,6 +7659,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -6935,6 +7667,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", @@ -6943,6 +7676,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -6951,6 +7685,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -6959,6 +7694,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", @@ -6967,6 +7703,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", @@ -6974,6 +7711,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -6982,6 +7720,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -6990,6 +7729,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -6998,6 +7738,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -7006,6 +7747,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -7014,6 +7756,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/metricgroups.json = b/tools/perf/pmu-events/arch/x86/cascadelakex/metricgroups.json index 904d299c95a3..cccfcab3425e 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json b/tools= /perf/pmu-events/arch/x86/cascadelakex/other.json index 95d42ac36717..f25693b17b8b 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for baseline license level 0. This includes non-AVX codes, = SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 1. This includes high current AVX 256-bit= instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Core cycles the core was throttled due to a p= ending power level request.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.THROTTLE", "PublicDescription": "Core cycles the out-of-order engine was thro= ttled due to a pending power level request.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "SampleAfterValue": "2000003", @@ -40,6 +45,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "SampleAfterValue": "2000003", @@ -47,6 +53,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "SampleAfterValue": "2000003", @@ -54,6 +61,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "SampleAfterValue": "2000003", @@ -61,6 +69,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "SampleAfterValue": "2000003", @@ -68,6 +77,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "SampleAfterValue": "2000003", @@ -75,6 +85,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "SampleAfterValue": "2000003", @@ -82,6 +93,7 @@ }, { "BriefDescription": "Number of hardware interrupts received by the= processor.", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Counts number of cache lines that are dropped= and not written back to L3 as they are deemed to be less likely to be reus= ed shortly", + "Counter": "0,1,2,3", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_DOWNGRADE", "PublicDescription": "Counts number of cache lines that are droppe= d and not written back to L3 as they are deemed to be less likely to be reu= sed shortly.", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Counts number of cache lines that are allocat= ed and written back to L3 with the intention that they are more likely to b= e reused shortly", + "Counter": "0,1,2,3", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_UPGRADE", "PublicDescription": "Counts number of cache lines that are alloca= ted and written back to L3 with the intention that they are more likely to = be reused shortly.", @@ -106,6 +120,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.ANY_RESPONSE have any respons= e type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -115,6 +130,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP O= CR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -124,6 +140,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE = OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -133,6 +150,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_N= EEDED OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -142,6 +160,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP OCR.= ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -151,6 +170,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE= OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -160,6 +180,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_= FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -169,6 +190,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_= NO_FWD OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +200,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED= OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +210,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +220,7 @@ }, { "BriefDescription": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +230,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE have any resp= onse type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +240,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOO= P OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +250,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NO= NE OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +260,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NO= T_NEEDED OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +270,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP O= CR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -250,6 +280,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_C= ORE OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -259,6 +290,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CO= RE_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -268,6 +300,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CO= RE_NO_FWD OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -277,6 +310,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEE= DED OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -286,6 +320,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -295,6 +330,7 @@ }, { "BriefDescription": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +340,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.ANY_RESPONSE have any response= type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -313,6 +350,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OC= R.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -322,6 +360,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE O= CR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -331,6 +370,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NE= EDED OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -340,6 +380,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.A= LL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -349,6 +390,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE = OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -358,6 +400,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_F= WD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -367,6 +410,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_N= O_FWD OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -376,6 +420,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED = OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -385,6 +430,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -394,6 +440,7 @@ }, { "BriefDescription": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_PF_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -403,6 +450,7 @@ }, { "BriefDescription": "OCR.ALL_READS.ANY_RESPONSE have any response = type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -412,6 +460,7 @@ }, { "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR= .ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -421,6 +470,7 @@ }, { "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE OC= R.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -430,6 +480,7 @@ }, { "BriefDescription": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEE= DED OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -439,6 +490,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP OCR.AL= L_READS.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -448,6 +500,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE = OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -457,6 +510,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FW= D OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -466,6 +520,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO= _FWD OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -475,6 +530,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED = OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -484,6 +540,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -493,6 +550,7 @@ }, { "BriefDescription": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_READS.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -502,6 +560,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.ANY_RESPONSE have any response ty= pe.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -511,6 +570,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP OCR.A= LL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -520,6 +580,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE OCR.= ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -529,6 +590,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -538,6 +600,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP OCR.ALL_= RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -547,6 +610,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE OC= R.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -556,6 +620,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD = OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -565,6 +630,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +640,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED OC= R.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -583,6 +650,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -592,6 +660,7 @@ }, { "BriefDescription": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ALL_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -601,6 +670,7 @@ }, { "BriefDescription": "Counts all demand code reads have any respons= e type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -610,6 +680,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -619,6 +690,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -628,6 +700,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE_= RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -637,6 +710,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -646,6 +720,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -655,6 +730,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -664,6 +740,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -673,6 +750,7 @@ }, { "BriefDescription": "Counts all demand code reads OCR.DEMAND_CODE= _RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -682,6 +760,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -691,6 +770,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -700,6 +780,7 @@ }, { "BriefDescription": "Counts demand data reads have any response ty= pe.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -709,6 +790,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.P= MM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -718,6 +800,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.P= MM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -727,6 +810,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.P= MM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -736,6 +820,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -745,6 +830,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -754,6 +840,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -763,6 +850,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -772,6 +860,7 @@ }, { "BriefDescription": "Counts demand data reads OCR.DEMAND_DATA_RD.= SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -781,6 +870,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -790,6 +880,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -799,6 +890,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) have any= response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -808,6 +900,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -817,6 +910,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -826,6 +920,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEMA= ND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -835,6 +930,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -844,6 +940,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -853,6 +950,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -862,6 +960,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -871,6 +970,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) OCR.DEM= AND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -880,6 +980,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -889,6 +990,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -898,6 +1000,7 @@ }, { "BriefDescription": "Counts any other requests have any response t= ype.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -907,6 +1010,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_L= OCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -916,6 +1020,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_L= OCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -925,6 +1030,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.PMM_HIT_L= OCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -934,6 +1040,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER= _NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -943,6 +1050,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER= _NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -952,6 +1060,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER= _NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -961,6 +1070,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER= _NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -970,6 +1080,7 @@ }, { "BriefDescription": "Counts any other requests OCR.OTHER.SUPPLIER= _NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -979,6 +1090,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -988,6 +1100,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -997,6 +1110,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1006,6 +1120,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_S= NOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1015,6 +1130,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP= _NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1024,6 +1140,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP= _NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -1033,6 +1150,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOO= P", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1042,6 +1160,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTH= ER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1051,6 +1170,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHE= R_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1060,6 +1180,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHE= R_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1069,6 +1190,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP= _NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1078,6 +1200,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1087,6 +1210,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L1D_AND_SW.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1096,6 +1220,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1105,6 +1230,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1114,6 +1240,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1123,6 +1250,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -1132,6 +1260,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1141,6 +1270,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1150,6 +1280,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1159,6 +1290,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1168,6 +1300,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1177,6 +1310,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1186,6 +1320,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1195,6 +1330,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1204,6 +1340,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1213,6 +1350,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1222,6 +1360,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1231,6 +1370,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1240,6 +1380,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1249,6 +1390,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1258,6 +1400,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1267,6 +1410,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1276,6 +1420,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1285,6 +1430,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L2_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1294,6 +1440,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1303,6 +1450,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1312,6 +1460,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1321,6 +1470,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -1330,6 +1480,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1339,6 +1490,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1348,6 +1500,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1357,6 +1510,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1366,6 +1520,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1375,6 +1530,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1384,6 +1540,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_DATA_RD.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1393,6 +1550,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1402,6 +1560,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1411,6 +1570,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1420,6 +1580,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.PMM_HIT_LOCAL_PMM.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1429,6 +1590,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1438,6 +1600,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1447,6 +1610,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1456,6 +1620,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.HIT_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1465,6 +1630,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1474,6 +1640,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1483,6 +1650,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PF_L3_RFO.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json b/to= ols/perf/pmu-events/arch/x86/cascadelakex/pipeline.json index c50ddf5b40dd..3dd296ab4d78 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -9,6 +10,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", @@ -17,6 +19,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.CONDITIONAL]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.COND", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.COND]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", @@ -75,6 +83,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", @@ -85,6 +94,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -95,6 +105,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -112,6 +124,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -120,6 +133,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -162,6 +180,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -171,6 +190,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -178,6 +198,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -186,6 +207,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -207,6 +231,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -215,6 +240,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x3C", @@ -231,6 +258,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", @@ -239,12 +267,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -253,12 +283,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -267,6 +299,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -275,6 +308,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -283,6 +317,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -291,6 +326,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -299,6 +335,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "20", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -307,6 +344,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -315,6 +353,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -323,6 +362,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -331,6 +371,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -339,6 +380,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -347,6 +389,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "SampleAfterValue": "2000003", @@ -354,6 +397,7 @@ }, { "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", @@ -362,6 +406,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -370,6 +415,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -378,6 +424,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", @@ -385,6 +432,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -393,15 +441,17 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.NOP", - "PEBS": "2", + "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -412,6 +462,7 @@ }, { "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", + "Counter": "0,2,3", "CounterMask": "10", "Errata": "SKL091, SKL044", "EventCode": "0xC0", @@ -424,6 +475,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -434,6 +486,7 @@ }, { "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", @@ -441,6 +494,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", @@ -450,6 +504,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", @@ -457,6 +512,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -465,6 +521,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -473,6 +530,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", @@ -481,6 +539,7 @@ }, { "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -489,6 +548,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -498,6 +558,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -507,6 +568,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_OK", @@ -516,6 +578,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", @@ -524,6 +587,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -533,6 +597,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -541,6 +606,7 @@ }, { "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", @@ -548,6 +614,7 @@ }, { "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", @@ -556,6 +623,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Counts resource-related stall cycles.", @@ -564,6 +632,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -572,6 +641,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -580,6 +650,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.PAUSE_INST", "SampleAfterValue": "2000003", @@ -587,6 +658,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", @@ -595,6 +667,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -606,6 +679,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -614,6 +688,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -622,6 +697,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", @@ -630,6 +706,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", @@ -638,6 +715,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", @@ -646,6 +724,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -654,6 +733,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -662,6 +742,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", @@ -670,6 +751,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -678,6 +760,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -686,6 +769,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -694,6 +778,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -702,6 +787,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -710,6 +796,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -719,6 +806,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -728,6 +816,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -737,6 +826,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -746,6 +836,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -755,6 +846,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -765,6 +857,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -773,6 +866,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -781,6 +875,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -789,6 +884,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -796,6 +892,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -806,6 +903,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -814,6 +912,7 @@ }, { "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", @@ -822,6 +921,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PublicDescription": "Counts the retirement slots used.", @@ -830,6 +930,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -840,6 +941,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json = b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json index 2c880535cc82..c9596e18ec09 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.= ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_READ", "Filter": "config1=3D0x40040e33", @@ -11,6 +12,7 @@ }, { "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts= .ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "config1=3D0x40041e33", @@ -21,6 +23,7 @@ }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "config1=3D0x40e33", @@ -31,6 +34,7 @@ }, { "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "config1=3D0x41833", @@ -42,6 +46,7 @@ }, { "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "config1=3D0x41a33", @@ -53,8 +58,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -62,8 +69,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -71,8 +80,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -80,8 +91,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -89,8 +102,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -98,8 +113,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -107,8 +124,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -116,8 +135,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -125,8 +146,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -134,8 +157,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -143,8 +168,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -152,8 +179,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -161,8 +190,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -170,8 +201,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -179,8 +212,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -188,8 +223,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -197,8 +234,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -206,8 +245,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -215,8 +256,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -224,8 +267,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -233,8 +278,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -242,8 +289,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -251,8 +300,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -260,8 +311,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -269,8 +322,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -278,8 +333,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -287,8 +344,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -296,8 +355,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -305,8 +366,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -314,8 +377,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -323,8 +388,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -332,8 +399,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -341,8 +410,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -350,8 +421,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -359,8 +432,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -368,8 +443,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -377,8 +454,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -386,8 +465,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -395,8 +476,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -404,8 +487,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -413,8 +498,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -422,8 +509,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -431,8 +520,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -440,8 +531,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -449,8 +542,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -458,8 +553,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -467,8 +564,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -476,8 +575,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -485,8 +586,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the intermediate bypass.", "UMask": "0x2", @@ -494,8 +597,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that could not take the bypass, and issues a read to memory.= Note that transactions that did not take the bypass but did not issue read= to memory will not be counted.", "UMask": "0x4", @@ -503,8 +608,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the full bypass.", "UMask": "0x1", @@ -512,6 +619,7 @@ }, { "BriefDescription": "Uncore cache clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts clockticks of the clock controlling t= he uncore caching and home agent (CHA).", @@ -519,55 +627,69 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C1 State", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C1 Transition", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C6 State", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C6 Transition", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; GV", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.GV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Mult= iple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe2", @@ -575,8 +697,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe1", @@ -584,8 +708,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote= Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe4", @@ -593,6 +719,7 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple Core Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", @@ -602,8 +729,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single Core Request= s", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x41", @@ -611,8 +740,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Core Request to Rem= ote Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x44", @@ -620,6 +751,7 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", @@ -629,8 +761,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x81", @@ -638,8 +772,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote = Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x84", @@ -647,8 +783,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple External S= noops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x22", @@ -656,8 +794,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single External Sno= ops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x21", @@ -665,8 +805,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; External Snoop to R= emote Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x24", @@ -674,14 +816,17 @@ }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", "PerPkg": "1", @@ -691,6 +836,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", "PerPkg": "1", @@ -700,6 +846,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", @@ -709,6 +856,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", @@ -718,8 +866,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -727,8 +877,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -736,6 +888,7 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", "PerPkg": "1", @@ -745,8 +898,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -754,6 +909,7 @@ }, { "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", "PerPkg": "1", @@ -763,80 +919,100 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared = hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF= /LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; op is= RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LL= C HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Deallocate HitME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Received RspFwdI* for a local request, but c= onverted HitME$ to SF entry", "UMask": "0x1", @@ -844,16 +1020,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E r= eceived for a remote request", "UMask": "0x2", @@ -861,16 +1041,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -878,8 +1062,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -887,8 +1073,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -896,8 +1084,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -905,8 +1095,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -914,8 +1106,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -923,8 +1117,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -932,8 +1128,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -941,8 +1139,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -950,8 +1150,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -959,8 +1161,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -968,8 +1172,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -977,8 +1183,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -986,8 +1194,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -995,6 +1205,7 @@ }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -1004,8 +1215,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count of the number of reads issued to any o= f the memory controller channels. This can be filtered by the priority of = the reads.", "UMask": "0x2", @@ -1013,6 +1226,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -1022,8 +1236,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Full Line= MIG", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x10", @@ -1031,8 +1247,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Ful= l Line", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x4", @@ -1040,8 +1258,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Partial N= on-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x2", @@ -1049,8 +1269,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Partial M= IG", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory c= ontroller 5 only.", "UMask": "0x20", @@ -1058,8 +1280,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Par= tial", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x8", @@ -1067,64 +1291,80 @@ }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations dropped due to IODC Full", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IDOC allocation dropped due to OSB gate", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to any reason", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to conflicting transaction", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoE", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbPushMtoI", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Moved to Cbo section", "UMask": "0x4", @@ -1132,8 +1372,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x11", @@ -1141,8 +1383,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", @@ -1150,8 +1394,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", "UMask": "0x31", @@ -1159,8 +1405,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", "UMask": "0x91", @@ -1168,8 +1416,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; External Snoo= p Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for only snoop requests c= oming from the remote socket(s) through the IPQ.", "UMask": "0x9", @@ -1177,8 +1427,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Write Request= s", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to= the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", @@ -1186,35 +1438,43 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2f", @@ -1222,8 +1482,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x22", @@ -1231,8 +1493,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x28", @@ -1240,8 +1504,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x21", @@ -1249,8 +1515,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x24", @@ -1258,26 +1526,32 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8f", @@ -1285,8 +1559,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x82", @@ -1294,8 +1570,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x88", @@ -1303,8 +1581,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x81", @@ -1312,8 +1592,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x84", @@ -1321,15 +1603,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", "PerPkg": "1", @@ -1339,6 +1624,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", "PerPkg": "1", @@ -1348,6 +1634,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", "PerPkg": "1", @@ -1357,6 +1644,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", "PerPkg": "1", @@ -1366,8 +1654,10 @@ }, { "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x20", @@ -1375,8 +1665,10 @@ }, { "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x10", @@ -1384,6 +1676,7 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", @@ -1393,8 +1686,10 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times when a Snoop hit in FSE states and triggered a silent evic= tion. This is useful because this information is lost in the PRE encodings= .", "UMask": "0x1", @@ -1402,8 +1697,10 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times that a USWC write (WCIL(F)) transaction hit in the LLC in = M state, triggering a WBMtoI followed by the USWC write. This occurs when = there is WC aliasing.", "UMask": "0x2", @@ -1411,16 +1708,20 @@ }, { "BriefDescription": "OSB Snoop Broadcast", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", "Unit": "CHA" }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw NM Set conflict in IODC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.IODC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "2LM related events; Counts the number of tim= es CHA saw NM Set conflict in IODC", "UMask": "0x10", @@ -1428,8 +1729,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "NM evictions due to another read to the same= near memory set in the LLC.", "UMask": "0x2", @@ -1437,8 +1740,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "NM evictions due to another read to the same= near memory set in the SF.", "UMask": "0x1", @@ -1446,8 +1751,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw NM Set conflict in TOR", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Reject in the CHA due to a pending read t= o the same near memory set in the TOR.", "UMask": "0x4", @@ -1455,8 +1762,10 @@ }, { "BriefDescription": "Memory mode related events; Counts the number= of times CHA saw NM Set conflict in TOR and the transaction was rejected", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR_REJECT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Rejects in the CHA due to a pending read to = the same near memory set in the TOR.", "UMask": "0x8", @@ -1464,8 +1773,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", "UMask": "0x4", @@ -1473,8 +1784,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", "UMask": "0x8", @@ -1482,8 +1795,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", "UMask": "0x10", @@ -1491,8 +1806,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", "UMask": "0x20", @@ -1500,8 +1817,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", "UMask": "0x1", @@ -1509,8 +1828,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", "UMask": "0x2", @@ -1518,6 +1839,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -1527,6 +1849,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -1536,6 +1859,7 @@ }, { "BriefDescription": "Read requests", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -1545,6 +1869,7 @@ }, { "BriefDescription": "Read requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -1554,6 +1879,7 @@ }, { "BriefDescription": "Read requests from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -1563,6 +1889,7 @@ }, { "BriefDescription": "Write requests", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -1572,6 +1899,7 @@ }, { "BriefDescription": "Write Requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -1581,6 +1909,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes Remote", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -1590,8 +1919,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -1599,8 +1930,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -1608,8 +1941,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -1617,8 +1952,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -1626,8 +1963,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -1635,8 +1974,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -1644,8 +1985,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -1653,8 +1996,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -1662,87 +2007,109 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x4", @@ -1750,6 +2117,7 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", @@ -1759,8 +2127,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x2", @@ -1768,8 +2138,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x10", @@ -1777,8 +2149,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x20", @@ -1786,8 +2160,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x40", @@ -1795,8 +2171,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x80", @@ -1804,238 +2182,297 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Merging these tw= o together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Mer= ging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", @@ -2044,24 +2481,30 @@ }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2069,8 +2512,10 @@ }, { "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2078,8 +2523,10 @@ }, { "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x40", @@ -2087,8 +2534,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x10", @@ -2096,8 +2545,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x20", @@ -2105,8 +2556,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x4", @@ -2114,8 +2567,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x8", @@ -2123,8 +2578,10 @@ }, { "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x80", @@ -2132,8 +2589,10 @@ }, { "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2141,8 +2600,10 @@ }, { "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2150,8 +2611,10 @@ }, { "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x40", @@ -2159,8 +2622,10 @@ }, { "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x10", @@ -2168,8 +2633,10 @@ }, { "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x20", @@ -2177,8 +2644,10 @@ }, { "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x4", @@ -2186,8 +2655,10 @@ }, { "BriefDescription": "ISMQ Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x8", @@ -2195,8 +2666,10 @@ }, { "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x80", @@ -2204,8 +2677,10 @@ }, { "BriefDescription": "ISMQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2213,8 +2688,10 @@ }, { "BriefDescription": "ISMQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2222,8 +2699,10 @@ }, { "BriefDescription": "ISMQ Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2231,8 +2710,10 @@ }, { "BriefDescription": "ISMQ Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2240,8 +2721,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x4", @@ -2249,6 +2732,7 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", "PerPkg": "1", @@ -2258,8 +2742,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x40", @@ -2267,8 +2753,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x80", @@ -2276,8 +2764,10 @@ }, { "BriefDescription": "Other Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x1", @@ -2285,8 +2775,10 @@ }, { "BriefDescription": "Other Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x2", @@ -2294,8 +2786,10 @@ }, { "BriefDescription": "Other Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x40", @@ -2303,8 +2797,10 @@ }, { "BriefDescription": "Other Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x10", @@ -2312,8 +2808,10 @@ }, { "BriefDescription": "Other Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x20", @@ -2321,8 +2819,10 @@ }, { "BriefDescription": "Other Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x4", @@ -2330,8 +2830,10 @@ }, { "BriefDescription": "Other Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x8", @@ -2339,8 +2841,10 @@ }, { "BriefDescription": "Other Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x80", @@ -2348,8 +2852,10 @@ }, { "BriefDescription": "Other Retries; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x40", @@ -2357,8 +2863,10 @@ }, { "BriefDescription": "Other Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x1", @@ -2366,8 +2874,10 @@ }, { "BriefDescription": "Other Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x2", @@ -2375,8 +2885,10 @@ }, { "BriefDescription": "Other Retries; Merging these two together to = make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x20", @@ -2384,8 +2896,10 @@ }, { "BriefDescription": "Other Retries; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x4", @@ -2393,8 +2907,10 @@ }, { "BriefDescription": "Other Retries; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x80", @@ -2402,8 +2918,10 @@ }, { "BriefDescription": "Other Retries; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x8", @@ -2411,8 +2929,10 @@ }, { "BriefDescription": "Other Retries; Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x10", @@ -2420,136 +2940,170 @@ }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x1", @@ -2557,8 +3111,10 @@ }, { "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x2", @@ -2566,8 +3122,10 @@ }, { "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x40", @@ -2575,8 +3133,10 @@ }, { "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", @@ -2584,8 +3144,10 @@ }, { "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", @@ -2593,8 +3155,10 @@ }, { "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x4", @@ -2602,8 +3166,10 @@ }, { "BriefDescription": "Request Queue Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x8", @@ -2611,8 +3177,10 @@ }, { "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x80", @@ -2620,8 +3188,10 @@ }, { "BriefDescription": "Request Queue Retries; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x40", @@ -2629,8 +3199,10 @@ }, { "BriefDescription": "Request Queue Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x1", @@ -2638,8 +3210,10 @@ }, { "BriefDescription": "Request Queue Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x2", @@ -2647,8 +3221,10 @@ }, { "BriefDescription": "Request Queue Retries; Merging these two toge= ther to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", @@ -2656,8 +3232,10 @@ }, { "BriefDescription": "Request Queue Retries; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x4", @@ -2665,8 +3243,10 @@ }, { "BriefDescription": "Request Queue Retries; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x80", @@ -2674,8 +3254,10 @@ }, { "BriefDescription": "Request Queue Retries; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x8", @@ -2683,8 +3265,10 @@ }, { "BriefDescription": "Request Queue Retries; Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", @@ -2692,8 +3276,10 @@ }, { "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x1", @@ -2701,8 +3287,10 @@ }, { "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2710,8 +3298,10 @@ }, { "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x40", @@ -2719,8 +3309,10 @@ }, { "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x10", @@ -2728,8 +3320,10 @@ }, { "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x20", @@ -2737,8 +3331,10 @@ }, { "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x4", @@ -2746,8 +3342,10 @@ }, { "BriefDescription": "RRQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x8", @@ -2755,8 +3353,10 @@ }, { "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x80", @@ -2764,8 +3364,10 @@ }, { "BriefDescription": "RRQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x40", @@ -2773,8 +3375,10 @@ }, { "BriefDescription": "RRQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x1", @@ -2782,8 +3386,10 @@ }, { "BriefDescription": "RRQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2791,8 +3397,10 @@ }, { "BriefDescription": "RRQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x20", @@ -2800,8 +3408,10 @@ }, { "BriefDescription": "RRQ Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x4", @@ -2809,8 +3419,10 @@ }, { "BriefDescription": "RRQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x80", @@ -2818,8 +3430,10 @@ }, { "BriefDescription": "RRQ Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x8", @@ -2827,8 +3441,10 @@ }, { "BriefDescription": "RRQ Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x10", @@ -2836,8 +3452,10 @@ }, { "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x1", @@ -2845,8 +3463,10 @@ }, { "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2854,8 +3474,10 @@ }, { "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x40", @@ -2863,8 +3485,10 @@ }, { "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2872,8 +3496,10 @@ }, { "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x20", @@ -2881,8 +3507,10 @@ }, { "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x4", @@ -2890,8 +3518,10 @@ }, { "BriefDescription": "WBQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x8", @@ -2899,8 +3529,10 @@ }, { "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x80", @@ -2908,8 +3540,10 @@ }, { "BriefDescription": "WBQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x40", @@ -2917,8 +3551,10 @@ }, { "BriefDescription": "WBQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x1", @@ -2926,8 +3562,10 @@ }, { "BriefDescription": "WBQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2935,8 +3573,10 @@ }, { "BriefDescription": "WBQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x20", @@ -2944,8 +3584,10 @@ }, { "BriefDescription": "WBQ Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x4", @@ -2953,8 +3595,10 @@ }, { "BriefDescription": "WBQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x80", @@ -2962,8 +3606,10 @@ }, { "BriefDescription": "WBQ Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x8", @@ -2971,8 +3617,10 @@ }, { "BriefDescription": "WBQ Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2980,8 +3628,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -2989,8 +3639,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -2998,8 +3650,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -3007,8 +3661,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -3016,8 +3672,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -3025,8 +3683,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -3034,8 +3694,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -3043,8 +3705,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -3052,8 +3716,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -3061,8 +3727,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -3070,8 +3738,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -3079,8 +3749,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -3088,8 +3760,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -3097,8 +3771,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -3106,8 +3782,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -3115,8 +3793,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -3124,8 +3804,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -3133,8 +3815,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -3142,8 +3826,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -3151,8 +3837,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -3160,8 +3848,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -3169,8 +3859,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -3178,8 +3870,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -3187,8 +3881,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -3196,8 +3892,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -3205,8 +3903,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -3214,8 +3914,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -3223,8 +3925,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -3232,8 +3936,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -3241,6 +3947,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", @@ -3250,6 +3957,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", @@ -3259,6 +3967,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", @@ -3268,8 +3977,10 @@ }, { "BriefDescription": "Snoops Sent; All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .", "UMask": "0x1", @@ -3277,8 +3988,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast snoop for Local Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA. This filter incl= udes only requests coming from local sockets.", "UMask": "0x10", @@ -3286,8 +3999,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA.This filter inclu= des only requests coming from remote sockets.", "UMask": "0x20", @@ -3295,8 +4010,10 @@ }, { "BriefDescription": "Snoops Sent; Directed snoops for Local Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from local sockets.", "UMask": "0x40", @@ -3304,8 +4021,10 @@ }, { "BriefDescription": "Snoops Sent; Directed snoops for Remote Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from remote sockets.", "UMask": "0x80", @@ -3313,8 +4032,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the local socket.", "UMask": "0x4", @@ -3322,8 +4043,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the remote socket.", "UMask": "0x8", @@ -3331,6 +4054,7 @@ }, { "BriefDescription": "RspCnflct* Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "PerPkg": "1", @@ -3340,8 +4064,10 @@ }, { "BriefDescription": "Snoop Responses Received; RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspFwd to a CA request. This snoop response = is only possible for RdCur when a snoop HITM/E in a remote caching agent an= d it directly forwards data to a requestor without changing the requestor's= cache line state.", "UMask": "0x80", @@ -3349,6 +4075,7 @@ }, { "BriefDescription": "RspI Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -3358,6 +4085,7 @@ }, { "BriefDescription": "RspIFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -3367,8 +4095,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RspS : Counts the= total number of RspI snoop responses received. Whenever a snoops are issu= ed, one or more snoop responses will be returned depending on the topology = of the system. In systems larger than 2s, when multiple snoops are return= ed this will count all the snoops that are received. For example, if 3 sno= ops were issued and returned RspI, RspS, and RspSFwd; then each of these su= b-events would increment by 1. : Filters for snoop responses of RspS. RspS= is returned when a remote cache has data but is not forwarding it. It is = a way to let the requesting socket know that it cannot allocate the data in= E state. No data is sent with S RspS.", "UMask": "0x2", @@ -3376,6 +4106,7 @@ }, { "BriefDescription": "RspSFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -3385,6 +4116,7 @@ }, { "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -3394,6 +4126,7 @@ }, { "BriefDescription": "Rsp*WB Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", @@ -3403,8 +4136,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspConflict to local CA reques= ts. This is returned when a snoop finds an existing outstanding transactio= n in a remote caching agent when it CAMs that caching agent. This triggers= conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI= .", "UMask": "0x40", @@ -3412,8 +4147,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspFwd to local CA requests. = This snoop response is only possible for RdCur when a snoop HITM/E in a rem= ote caching agent and it directly forwards data to a requestor without chan= ging the requestor's cache line state.", "UMask": "0x80", @@ -3421,8 +4158,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspI to local CA requests. Rs= pI is returned when the remote cache does not have the data, or when the re= mote cache silently evicts data (such as when an RFO hits non-modified data= ).", "UMask": "0x1", @@ -3430,8 +4169,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspIFwd to local CA requests. = This is returned when a remote caching agent forwards data and the requesti= ng agent is able to acquire the data in E or M states. This is commonly re= turned with RFO transactions. It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -3439,8 +4180,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspS to local CA requests. Rsp= S is returned when a remote cache has data but is not forwarding it. It is= a way to let the requesting socket know that it cannot allocate the data i= n E state. No data is sent with S RspS.", "UMask": "0x2", @@ -3448,8 +4191,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd to local CA requests. = This is returned when a remote caching agent forwards data but holds on to= its current copy. This is common for data and code reads that hit in a re= mote socket in E or F state.", "UMask": "0x8", @@ -3457,8 +4202,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of Rsp*Fwd*WB to local CA request= s. This snoop response is only used in 4s systems. It is used when a snoo= p HITM's in a remote caching agent and it directly forwards data to a reque= stor, and simultaneously returns data to the home to be written back to mem= ory.", "UMask": "0x20", @@ -3466,8 +4213,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspIWB or RspSWB to local CA r= equests. This is returned when a non-RFO request hits in M state. Data an= d Code Reads can return either RspIWB or RspSWB depending on how the system= has been configured. InvItoE transactions will also return RspIWB because= they must acquire ownership.", "UMask": "0x10", @@ -3475,8 +4224,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3484,8 +4235,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3493,8 +4246,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3502,8 +4257,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3511,8 +4268,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3520,8 +4279,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3529,8 +4290,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3538,8 +4301,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3547,8 +4312,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3556,8 +4323,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3565,8 +4334,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3574,8 +4345,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3583,8 +4356,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3592,8 +4367,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3601,8 +4378,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3610,8 +4389,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3619,8 +4400,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3628,8 +4411,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3637,8 +4422,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3646,8 +4433,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3655,8 +4444,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3664,8 +4455,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3673,8 +4466,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3682,8 +4477,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3691,8 +4488,10 @@ }, { "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0xff", @@ -3700,8 +4499,10 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x15", @@ -3709,8 +4510,10 @@ }, { "BriefDescription": "TOR Inserts; All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally initiated requests", "UMask": "0x35", @@ -3718,8 +4521,10 @@ }, { "BriefDescription": "TOR Inserts; Misses from Local", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x25", @@ -3727,8 +4532,10 @@ }, { "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; T= OR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)= ", "UMask": "0x2", @@ -3736,8 +4543,10 @@ }, { "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; H= ITs (hit is defined to be not a miss [see below], as a result for any reque= st allocated into the TOR, one of either HIT or MISS must be true)", "UMask": "0x10", @@ -3745,6 +4554,7 @@ }, { "BriefDescription": "TOR Inserts; All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -3754,6 +4564,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -3763,6 +4574,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "Filter": "config1=3D0x40233", @@ -3773,6 +4585,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", "Filter": "config1=3D0x40433", @@ -3783,6 +4596,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -3792,6 +4606,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -3801,6 +4616,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -3811,6 +4627,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "Filter": "config1=3D0x40033", @@ -3821,6 +4638,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -3830,6 +4648,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "Filter": "config1=3D0x40233", @@ -3840,6 +4659,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", "Filter": "config1=3D0x40433", @@ -3850,6 +4670,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -3859,6 +4680,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -3868,6 +4690,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -3878,6 +4701,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "Filter": "config1=3D0x40033", @@ -3888,8 +4712,10 @@ }, { "BriefDescription": "TOR Inserts; All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally generated IO traffic", "UMask": "0x34", @@ -3897,6 +4723,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -3906,6 +4733,7 @@ }, { "BriefDescription": "TOR Inserts; Misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -3915,8 +4743,10 @@ }, { "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Experimental": "1", "Filter": "config1=3D0x49033", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO ItoM requests that mis= s the LLC. An ItoM request is used by IIO to request a data write without f= irst reading the data for ownership.", @@ -3925,8 +4755,10 @@ }, { "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Experimental": "1", "Filter": "config1=3D0x43C33", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RdCur requests and mis= s the LLC. A RdCur request is used by IIO to read data without changing sta= te.", @@ -3935,8 +4767,10 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Experimental": "1", "Filter": "config1=3D0x40033", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RFO requests that miss= the LLC. A read for ownership (RFO) requests a cache line to be cached in = E state with the intent to modify.", @@ -3945,8 +4779,10 @@ }, { "BriefDescription": "TOR Inserts; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x8", @@ -3954,26 +4790,32 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x1", @@ -3981,17 +4823,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; Miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; M= isses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IP= Q or (in the victim case) the ISMQ, that required the CHA to spawn a new UP= I/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to = a local memory controller, in the event that the CHA is the home node)). B= asically, if the LLC/SF/MLC complex were not able to service the request wi= thout involving another agent...it is a miss. If only IDI snoops were requ= ired, it is not a miss (that means the SF/MLC com", "UMask": "0x20", @@ -3999,8 +4845,10 @@ }, { "BriefDescription": "TOR Inserts; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x4", @@ -4008,6 +4856,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", @@ -4017,44 +4866,54 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x60", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. Does not include addressless requests= such as locks and interrupts.", "UMask": "0xff", @@ -4062,8 +4921,10 @@ }, { "BriefDescription": "TOR Occupancy; All from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely= generated requests", "UMask": "0x37", @@ -4071,8 +4932,10 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x17", @@ -4080,8 +4943,10 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x27", @@ -4089,8 +4954,10 @@ }, { "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; TOR allocation occurred as a result of SF/LLC evictions (c= ame from the ISMQ)", "UMask": "0x2", @@ -4098,8 +4965,10 @@ }, { "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; HITs (hit is defined to be not a miss [see below], as a re= sult for any request allocated into the TOR, one of either HIT or MISS must= be true)", "UMask": "0x10", @@ -4107,6 +4976,7 @@ }, { "BriefDescription": "TOR Occupancy; All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4116,6 +4986,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4125,6 +4996,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "Filter": "config1=3D0x40233", @@ -4135,6 +5007,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "Filter": "config1=3D0x40433", @@ -4145,6 +5018,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -4154,6 +5028,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -4163,6 +5038,7 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -4173,6 +5049,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "Filter": "config1=3D0x40033", @@ -4183,6 +5060,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -4192,6 +5070,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "Filter": "config1=3D0x40233", @@ -4202,6 +5081,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "Filter": "config1=3D0x40433", @@ -4212,6 +5092,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -4221,6 +5102,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -4230,6 +5112,7 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -4240,6 +5123,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "Filter": "config1=3D0x40033", @@ -4250,8 +5134,10 @@ }, { "BriefDescription": "TOR Occupancy; All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; All locally generated IO traffic", "UMask": "0x34", @@ -4259,8 +5145,10 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x14", @@ -4268,8 +5156,10 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x24", @@ -4277,8 +5167,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Experimental": "1", "Filter": "config1=3D0x49033", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO ItoM req= uests that miss the LLC. An ItoM is used by IIO to request a data write wit= hout first reading the data for ownership.", @@ -4287,8 +5179,10 @@ }, { "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Experimental": "1", "Filter": "config1=3D0x43C33", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RdCur re= quests that miss the LLC. A RdCur request is used by IIO to read data witho= ut changing state.", @@ -4297,8 +5191,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "Filter": "config1=3D0x40033", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RFO requ= ests that miss the LLC. A read for ownership (RFO) requests data to be cach= ed in E state with the intent to modify.", @@ -4307,8 +5203,10 @@ }, { "BriefDescription": "TOR Occupancy; IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x8", @@ -4316,26 +5214,32 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; IRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x1", @@ -4343,17 +5247,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; Misses. (a miss is defined to be any transaction from the= IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA= to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops an= d/or any RD/WR to a local memory controller, in the event that the CHA is t= he home node)). Basically, if the LLC/SF/MLC complex were not able to serv= ice the request without involving another agent...it is a miss. If only ID= I snoops were required, it is not a miss (that means the SF/MLC com", "UMask": "0x20", @@ -4361,8 +5269,10 @@ }, { "BriefDescription": "TOR Occupancy; PRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x4", @@ -4370,8 +5280,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4379,8 +5291,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4388,8 +5302,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4397,8 +5313,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4406,8 +5324,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4415,8 +5335,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4424,8 +5346,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4433,8 +5357,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4442,8 +5368,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4451,8 +5379,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4460,8 +5390,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -4469,8 +5401,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4478,8 +5412,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4487,8 +5423,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4496,8 +5434,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4505,8 +5445,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4514,8 +5456,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4523,8 +5467,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4532,8 +5478,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4541,8 +5489,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4550,8 +5500,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4559,8 +5511,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4568,8 +5522,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4577,8 +5533,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4586,8 +5544,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4595,8 +5555,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4604,8 +5566,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4613,8 +5577,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4622,8 +5588,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4631,8 +5599,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -4640,8 +5610,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -4649,8 +5621,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -4658,8 +5632,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -4667,8 +5643,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -4676,8 +5654,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -4685,8 +5665,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4694,8 +5676,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4703,8 +5687,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4712,8 +5698,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4721,8 +5709,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4730,8 +5720,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4739,8 +5731,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -4748,8 +5742,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -4757,8 +5753,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -4766,8 +5764,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -4775,8 +5775,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4784,8 +5786,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4793,8 +5797,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4802,8 +5808,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -4811,8 +5819,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4820,8 +5830,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4829,8 +5841,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4838,8 +5852,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4847,8 +5863,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4856,8 +5874,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -4865,8 +5885,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4874,8 +5896,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4883,8 +5907,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -4892,8 +5918,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -4901,8 +5929,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4910,8 +5940,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4919,8 +5951,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -4928,8 +5962,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -4937,8 +5973,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -4946,8 +5984,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -4955,8 +5995,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -4964,8 +6006,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4973,8 +6017,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4982,8 +6028,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -4991,8 +6039,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -5000,8 +6050,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -5009,8 +6061,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5018,8 +6072,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -5027,8 +6083,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -5036,8 +6094,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5045,8 +6105,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -5054,8 +6116,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -5063,8 +6127,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -5072,8 +6138,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5081,8 +6149,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -5090,8 +6160,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -5099,8 +6171,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -5108,8 +6182,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -5117,8 +6193,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -5126,8 +6204,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -5135,8 +6215,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -5144,8 +6226,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -5153,8 +6237,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -5162,8 +6248,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5171,8 +6259,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -5180,8 +6270,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -5189,8 +6281,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -5198,8 +6292,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5207,8 +6303,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -5216,8 +6314,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -5225,8 +6325,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -5234,8 +6336,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -5243,8 +6347,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -5252,8 +6358,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -5261,8 +6369,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -5270,8 +6380,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x4", @@ -5279,8 +6391,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Cr= edits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x8", @@ -5288,8 +6402,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x40", @@ -5297,8 +6413,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x80", @@ -5306,8 +6424,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x10", @@ -5315,8 +6435,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x20", @@ -5324,8 +6446,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x2", @@ -5333,8 +6457,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x1", @@ -5342,8 +6468,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x4", @@ -5351,8 +6479,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x8", @@ -5360,8 +6490,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x40", @@ -5369,6 +6501,7 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", "PerPkg": "1", @@ -5378,8 +6511,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x10", @@ -5387,8 +6522,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x20", @@ -5396,8 +6533,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Cre= dits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x1", @@ -5405,8 +6544,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Cre= dits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x2", @@ -5414,8 +6555,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -5423,8 +6566,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -5432,8 +6577,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -5441,8 +6588,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -5450,8 +6599,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -5459,8 +6610,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -5468,8 +6621,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -5477,8 +6632,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -5486,8 +6643,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -5495,8 +6654,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -5504,8 +6665,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -5513,8 +6676,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -5522,8 +6687,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -5531,8 +6698,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -5540,8 +6709,10 @@ }, { "BriefDescription": "WbPushMtoI; Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was able to pu= sh WbPushMToI to LLC", "UMask": "0x1", @@ -5549,8 +6720,10 @@ }, { "BriefDescription": "WbPushMtoI; Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was unable to = push WbPushMToI to LLC (hence pushed it to MEM)", "UMask": "0x2", @@ -5558,8 +6731,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", "UMask": "0x4", @@ -5567,8 +6742,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", "UMask": "0x8", @@ -5576,8 +6753,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", "UMask": "0x10", @@ -5585,8 +6764,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", "UMask": "0x20", @@ -5594,8 +6775,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", "UMask": "0x1", @@ -5603,8 +6786,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", "UMask": "0x2", @@ -5612,8 +6797,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd F/E", "UMask": "0xe4", @@ -5621,8 +6808,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd M", "UMask": "0xf0", @@ -5630,8 +6819,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd F/E", "UMask": "0xe2", @@ -5639,8 +6830,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd M", "UMask": "0xe8", @@ -5648,8 +6841,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response any to Hit F/S/E= ", "UMask": "0xe1", @@ -5657,8 +6852,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd F/E", "UMask": "0x44", @@ -5666,8 +6863,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd M", "UMask": "0x50", @@ -5675,8 +6874,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd F/E", "UMask": "0x42", @@ -5684,8 +6885,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd M", "UMask": "0x48", @@ -5693,8 +6896,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response any to Hit F/S/= E", "UMask": "0x41", @@ -5702,8 +6907,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd F/= E", "UMask": "0x84", @@ -5711,8 +6918,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd M", "UMask": "0x90", @@ -5720,8 +6929,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd F/= E", "UMask": "0x82", @@ -5729,8 +6940,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd M", "UMask": "0x88", @@ -5738,8 +6951,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response any to Hit = F/S/E", "UMask": "0x81", @@ -5747,8 +6962,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspIFwdF= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd F/= E", "UMask": "0x24", @@ -5756,8 +6973,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd M", "UMask": "0x30", @@ -5765,8 +6984,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspSFwdF= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd F/= E", "UMask": "0x22", @@ -5774,8 +6995,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd M", "UMask": "0x28", @@ -5783,8 +7006,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspHitFS= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response any to Hit = F/S/E", "UMask": "0x21", @@ -5792,6 +7017,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", @@ -5799,6 +7025,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA5", "EventName": "UNC_C_FAST_ASSERTED", @@ -5808,15 +7035,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.ANY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", @@ -5826,24 +7056,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x91", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", @@ -5853,15 +7088,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", @@ -5871,6 +7109,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.F_STATE", @@ -5880,15 +7119,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2f", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", @@ -5898,15 +7140,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.S_STATE", @@ -5916,59 +7161,72 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SRC_THRTL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA4", "EventName": "UNC_C_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.EVICT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IPQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ", @@ -5978,6 +7236,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", @@ -5987,6 +7246,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", @@ -5996,51 +7256,62 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x34", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.PRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", @@ -6050,6 +7321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", @@ -6059,6 +7331,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REM_ALL", @@ -6068,87 +7341,106 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x60", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.EVICT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IPQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", @@ -6158,6 +7450,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", @@ -6167,6 +7460,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", @@ -6176,608 +7470,743 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x34", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.PRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CMS_CLOCKTICKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_H_CLOCK", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C1_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_TRANSITION", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C6_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_TRANSITION", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.GV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.GV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_GTONE", @@ -6787,24 +8216,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x41", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", @@ -6814,59 +8248,72 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_COUNTER0_OCCUPANCY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x1F", "EventName": "UNC_H_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x53", "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", @@ -6876,6 +8323,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x53", "EventName": "UNC_H_DIR_LOOKUP.SNP", @@ -6885,6 +8333,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x54", "EventName": "UNC_H_DIR_UPDATE.HA", @@ -6894,6 +8343,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x54", "EventName": "UNC_H_DIR_UPDATE.TOR", @@ -6903,24 +8353,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.EX_RDS", @@ -6930,411 +8385,502 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5E", "EventName": "UNC_H_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.WRITE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5E", "EventName": "UNC_H_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.READ_OR_INV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.SHARED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.NORMAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x59", "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x59", "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.INVITOM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.INVITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.IODCFULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.IODCFULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.OSBGATED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.OSBGATED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.SNPOUT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_VIC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.RFO_HIT_S", @@ -7344,86 +8890,105 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RSPI_WAS_FSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.WC_ALIASING", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_OSB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x55", "EventName": "UNC_H_OSB", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", @@ -7433,6 +8998,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", @@ -7442,6 +9008,7 @@ }, { "BriefDescription": "read requests from home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS", @@ -7451,6 +9018,7 @@ }, { "BriefDescription": "read requests from local home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS_LOCAL", @@ -7460,15 +9028,18 @@ }, { "BriefDescription": "read requests from remote home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "write requests from home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES", @@ -7478,6 +9049,7 @@ }, { "BriefDescription": "write requests from local home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", @@ -7487,177 +9059,216 @@ }, { "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IPQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IRQ", @@ -7667,276 +9278,337 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.RRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.WBQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", @@ -7946,177 +9618,216 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x25", "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x25", "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2D", "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2D", "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IPQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", @@ -8126,1005 +9837,1228 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.RRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.WBQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IFV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.E_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.E_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.M_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.M_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.S_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.S_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", @@ -9134,24 +11068,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", @@ -9161,15 +11100,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", @@ -9179,6 +11121,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", @@ -9188,1575 +11131,1925 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.LLC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x56", "EventName": "UNC_H_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.MEM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x56", "EventName": "UNC_H_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf0", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x42", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x48", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x41", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x82", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x30", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "CHA" diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnec= t.json b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.js= on index 3fe9ce483bbe..91889e447bd1 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests f= rom any source port.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Snoops", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", "UMask": "0x2", @@ -19,6 +23,7 @@ }, { "BriefDescription": "Total IRP occupancy of inbound read and write= requests.", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", @@ -28,15 +33,19 @@ }, { "BriefDescription": "IRP Clocks", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x80", @@ -44,8 +53,10 @@ }, { "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x2", @@ -53,8 +64,10 @@ }, { "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.DRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x4", @@ -62,8 +75,10 @@ }, { "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x20", @@ -71,8 +86,10 @@ }, { "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x1", @@ -80,6 +97,7 @@ }, { "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -89,6 +107,7 @@ }, { "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", @@ -98,8 +117,10 @@ }, { "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x40", @@ -107,13 +128,16 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -122,6 +146,7 @@ }, { "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -130,95 +155,119 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.UNKNOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1; Lost Forward", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.LOST_FWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop pulled away ownership before a write w= as committed", "UMask": "0x10", @@ -226,8 +275,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", "UMask": "0x20", @@ -235,8 +286,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", "UMask": "0x40", @@ -244,8 +297,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", "UMask": "0x4", @@ -253,8 +308,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", "UMask": "0x1", @@ -262,8 +319,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", "UMask": "0x8", @@ -271,8 +330,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", "UMask": "0x2", @@ -280,88 +341,110 @@ }, { "BriefDescription": "P2P Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_P2P_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P requests from the ITC", "Unit": "IRP" }, { "BriefDescription": "P2P Occupancy", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_P2P_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P B & S Queue Occupancy", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P completions", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if local only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if local and target m= atches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P Message", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P reads", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; Match if remote only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if remote and target = matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P Writes", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -369,8 +452,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -378,8 +463,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -387,8 +474,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M line in the IIO cache", "UMask": "0x78", @@ -396,8 +485,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -405,64 +496,80 @@ }, { "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of atomic = transactions", "UMask": "0x10", @@ -470,8 +577,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of 'other'= kinds of transactions.", "UMask": "0x20", @@ -479,8 +588,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of read pr= efetches.", "UMask": "0x4", @@ -488,8 +599,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.READS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only read requests (n= ot including read prefetches).", "UMask": "0x1", @@ -497,8 +610,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WRITES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only write requests. = Each write request should have a prefetch, so there is no need to explicit= ly track these requests. For writes that are tickled and have to retry, th= e counter will be incremented for each retry.", "UMask": "0x2", @@ -506,6 +621,7 @@ }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -515,118 +631,150 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0xB", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1B", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xC", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of outstanding outbou= nd requests from the IRP to the switch (towards the devices). This can be = used in conjunction with the allocations event in order to calculate averag= e latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -634,8 +782,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -643,8 +793,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -652,8 +804,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -661,8 +815,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -670,8 +826,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -679,8 +837,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -688,8 +848,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -697,8 +859,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -706,8 +870,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -715,8 +881,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -724,8 +892,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -733,8 +903,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -742,8 +914,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -751,8 +925,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -760,8 +936,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -769,8 +947,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -778,8 +958,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -787,8 +969,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -796,8 +980,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -805,8 +991,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -814,8 +1002,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -823,8 +1013,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -832,8 +1024,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -841,8 +1035,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -850,8 +1046,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -859,8 +1057,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -868,8 +1068,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -877,8 +1079,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -886,8 +1090,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -895,8 +1101,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -904,8 +1112,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -913,8 +1123,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -922,8 +1134,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -931,8 +1145,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -940,8 +1156,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -949,8 +1167,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -958,8 +1178,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -967,8 +1189,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -976,8 +1200,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -985,8 +1211,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -994,8 +1222,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -1003,8 +1233,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -1012,8 +1244,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -1021,8 +1255,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -1030,8 +1266,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -1039,8 +1277,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -1048,8 +1288,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -1057,6 +1299,7 @@ }, { "BriefDescription": "Traffic in which the M2M to iMC Bypass was no= t taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", "PerPkg": "1", @@ -1066,43 +1309,54 @@ }, { "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", "EventName": "UNC_M2M_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", "PerPkg": "1", @@ -1111,6 +1365,7 @@ }, { "BriefDescription": "Messages sent direct to core (bypassing the C= HA)", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", "PerPkg": "1", @@ -1119,6 +1374,7 @@ }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1127,6 +1383,7 @@ }, { "BriefDescription": "Number of reads in which direct to Intel(R) U= PI transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", @@ -1135,6 +1392,7 @@ }, { "BriefDescription": "Cycles when direct to Intel(R) UPI was disabl= ed", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", @@ -1143,6 +1401,7 @@ }, { "BriefDescription": "Messages sent direct to the Intel(R) UPI", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", "PerPkg": "1", @@ -1151,6 +1410,7 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel(R) UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", @@ -1159,70 +1419,87 @@ }, { "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -1232,6 +1509,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -1241,6 +1519,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -1250,6 +1529,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -1259,70 +1539,87 @@ }, { "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", "PerPkg": "1", @@ -1332,6 +1629,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", "PerPkg": "1", @@ -1341,6 +1639,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1350,6 +1649,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", "PerPkg": "1", @@ -1359,6 +1659,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", "PerPkg": "1", @@ -1368,6 +1669,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", "PerPkg": "1", @@ -1377,6 +1679,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", "PerPkg": "1", @@ -1386,8 +1689,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -1395,8 +1700,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -1404,8 +1711,10 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x2", @@ -1413,8 +1722,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -1422,8 +1733,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -1431,8 +1744,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -1440,8 +1755,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -1449,8 +1766,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -1458,8 +1777,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -1467,8 +1788,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -1476,8 +1799,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -1485,8 +1810,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -1494,8 +1821,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -1503,8 +1832,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -1512,8 +1843,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -1521,8 +1854,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -1530,8 +1865,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -1539,8 +1876,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -1548,6 +1887,7 @@ }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ALL", "PerPkg": "1", @@ -1557,22 +1897,27 @@ }, { "BriefDescription": "M2M Reads Issued to iMC; All, regardless of p= riority.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Reads to iMC issued at Normal Priority (Non-I= sochronous)", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.NORMAL", "PerPkg": "1", @@ -1582,6 +1927,7 @@ }, { "BriefDescription": "Read requests to Intel(R) Optane(TM) DC persi= stent memory issued to the iMC from M2M", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.TO_PMM", "PerPkg": "1", @@ -1591,6 +1937,7 @@ }, { "BriefDescription": "Writes to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.ALL", "PerPkg": "1", @@ -1600,30 +1947,37 @@ }, { "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH= ", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI", "PerPkg": "1", @@ -1632,6 +1986,7 @@ }, { "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -1641,14 +1996,17 @@ }, { "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write requests to Intel(R) Optane(TM) DC pers= istent memory issued to the iMC from M2M", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", "PerPkg": "1", @@ -1658,84 +2016,105 @@ }, { "BriefDescription": "Number Packet Header Matches; MC Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches; Mesh Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_PMM_RPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_PMM_WPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch requests that got turn into a demand= request", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", @@ -1744,6 +2123,7 @@ }, { "BriefDescription": "Inserts into the Memory Controller Prefetch Q= ueue", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", @@ -1752,15 +2132,19 @@ }, { "BriefDescription": "Prefetch CAM Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -1768,8 +2152,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -1777,8 +2163,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -1786,8 +2174,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -1795,8 +2185,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -1804,8 +2196,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -1813,8 +2207,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -1822,8 +2218,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -1831,174 +2229,217 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 0", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 1", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 2", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M2M_RxC_AD_INSERTS", "PerPkg": "1", @@ -2007,6 +2448,7 @@ }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", "PerPkg": "1", @@ -2014,20 +2456,25 @@ }, { "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M2M_RxC_BL_INSERTS", "PerPkg": "1", @@ -2035,6 +2482,7 @@ }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", "PerPkg": "1", @@ -2042,8 +2490,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -2051,8 +2501,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -2060,8 +2512,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -2069,8 +2523,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -2078,8 +2534,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -2087,8 +2545,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -2096,8 +2556,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -2105,8 +2567,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -2114,8 +2578,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -2123,8 +2589,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -2132,8 +2600,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -2141,8 +2611,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -2150,8 +2622,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -2159,8 +2633,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -2168,8 +2644,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -2177,8 +2655,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -2186,8 +2666,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -2195,8 +2677,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -2204,8 +2688,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -2213,8 +2699,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -2222,8 +2710,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -2231,8 +2721,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -2240,8 +2732,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -2249,8 +2743,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -2258,8 +2754,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -2267,8 +2765,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -2276,8 +2776,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -2285,8 +2787,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -2294,8 +2798,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -2303,8 +2809,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2312,8 +2820,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2321,8 +2831,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2330,8 +2842,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2339,8 +2853,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2348,8 +2864,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2357,8 +2875,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2366,8 +2886,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2375,8 +2897,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2384,8 +2908,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2393,8 +2919,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2402,8 +2930,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2411,8 +2941,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2420,8 +2952,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2429,8 +2963,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2438,8 +2974,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2447,8 +2985,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2456,8 +2996,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2465,8 +3007,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2474,8 +3018,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2483,8 +3029,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2492,8 +3040,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2501,8 +3051,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2510,8 +3062,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2519,8 +3073,10 @@ }, { "BriefDescription": "Clean line read hits(Regular and RFO) to Near= Memory(DRAM cache) in Memory Mode and regular reads to DRAM in 1LM", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit; Read Hit from NearMem, Clean Line", "UMask": "0x1", @@ -2528,6 +3084,7 @@ }, { "BriefDescription": "Dirty line read hits(Regular and RFO) to Near= Memory(DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", "PerPkg": "1", @@ -2537,6 +3094,7 @@ }, { "BriefDescription": "Clean line underfill read hits to Near Memory= (DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", "PerPkg": "1", @@ -2546,6 +3104,7 @@ }, { "BriefDescription": "Dirty line underfill read hits to Near Memory= (DRAM cache) in Memory Mode", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", "PerPkg": "1", @@ -2555,151 +3114,190 @@ }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Pending Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M2M_TxC_AD_INSERTS", "PerPkg": "1", @@ -2707,20 +3305,25 @@ }, { "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", "PerPkg": "1", @@ -2728,430 +3331,537 @@ }, { "BriefDescription": "Outbound Ring Transactions on AK; CRD Transac= tions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK; NDR Transac= tions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.NDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; All", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare R= equest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read= Cam Hit", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit R= equest", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare= Request", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit = Request", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare R= equest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; All", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", "PerPkg": "1", @@ -3160,54 +3870,67 @@ }, { "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", "PerPkg": "1", @@ -3216,24 +3939,30 @@ }, { "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3241,8 +3970,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3250,8 +3981,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3259,8 +3992,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3268,8 +4003,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3277,8 +4014,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3286,8 +4025,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3295,8 +4036,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3304,8 +4047,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3313,8 +4058,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3322,8 +4069,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -3331,8 +4080,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3340,8 +4091,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3349,8 +4102,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3358,8 +4113,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3367,8 +4124,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3376,8 +4135,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3385,8 +4146,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3394,8 +4157,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3403,8 +4168,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3412,8 +4179,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3421,8 +4190,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3430,8 +4201,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3439,8 +4212,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3448,8 +4223,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3457,8 +4234,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3466,8 +4245,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3475,8 +4256,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3484,8 +4267,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3493,8 +4278,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -3502,8 +4289,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -3511,8 +4300,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -3520,8 +4311,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -3529,8 +4322,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -3538,8 +4333,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -3547,8 +4344,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3556,8 +4355,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3565,8 +4366,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3574,8 +4377,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3583,8 +4388,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3592,8 +4399,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3601,8 +4410,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -3610,8 +4421,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -3619,8 +4432,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -3628,8 +4443,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -3637,8 +4454,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3646,8 +4465,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3655,8 +4476,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3664,8 +4487,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -3673,8 +4498,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3682,8 +4509,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3691,8 +4520,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3700,8 +4531,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3709,8 +4542,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3718,8 +4553,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -3727,8 +4564,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3736,8 +4575,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3745,8 +4586,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -3754,8 +4597,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -3763,8 +4608,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3772,8 +4619,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3781,8 +4630,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -3790,8 +4641,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -3799,8 +4652,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -3808,8 +4663,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3817,8 +4674,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -3826,8 +4685,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3835,8 +4696,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3844,8 +4707,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -3853,8 +4718,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -3862,8 +4729,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -3871,8 +4740,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3880,8 +4751,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -3889,8 +4762,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3898,8 +4773,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3907,8 +4784,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -3916,8 +4795,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -3925,8 +4806,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -3934,8 +4817,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3943,8 +4828,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -3952,8 +4839,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -3961,8 +4850,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -3970,8 +4861,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -3979,8 +4872,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -3988,8 +4883,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -3997,8 +4894,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -4006,8 +4905,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -4015,8 +4916,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4024,8 +4927,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4033,8 +4938,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -4042,8 +4949,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -4051,8 +4960,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -4060,8 +4971,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -4069,8 +4982,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -4078,8 +4993,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -4087,8 +5004,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -4096,8 +5015,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -4105,8 +5026,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -4114,8 +5037,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -4123,8 +5048,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -4132,8 +5059,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -4141,8 +5070,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -4150,8 +5081,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -4159,8 +5092,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -4168,8 +5103,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -4177,8 +5114,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -4186,8 +5125,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -4195,8 +5136,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -4204,8 +5147,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -4213,8 +5158,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -4222,8 +5169,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -4231,8 +5180,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -4240,8 +5191,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -4249,8 +5202,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -4258,179 +5213,223 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4438,8 +5437,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4447,8 +5448,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4456,8 +5459,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4465,8 +5470,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4474,8 +5481,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4483,8 +5492,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4492,8 +5503,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4501,8 +5514,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4510,8 +5525,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4519,8 +5536,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4528,8 +5547,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4537,8 +5558,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4546,8 +5569,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4555,8 +5580,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4564,8 +5591,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4573,8 +5602,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4582,8 +5613,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4591,8 +5624,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4600,8 +5635,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4609,8 +5646,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4618,8 +5657,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4627,8 +5668,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4636,8 +5679,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4645,8 +5690,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4654,8 +5701,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4663,8 +5712,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4672,8 +5723,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4681,8 +5734,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4690,8 +5745,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4699,8 +5756,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4708,8 +5767,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4717,8 +5778,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4726,8 +5789,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4735,8 +5800,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4744,8 +5811,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4753,8 +5822,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4762,8 +5833,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4771,8 +5844,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4780,8 +5855,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4789,8 +5866,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4798,8 +5877,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4807,8 +5888,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4816,8 +5899,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4825,8 +5910,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4834,8 +5921,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4843,8 +5932,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4852,8 +5943,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4861,8 +5954,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Requests", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x4", @@ -4870,8 +5965,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Snoops", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x8", @@ -4879,8 +5976,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x1", @@ -4888,8 +5987,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Writebacks", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x2", @@ -4897,39 +5998,49 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_M3UPI_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the M3 uclk do= main. This could be slightly different than the count in the Ubox because = of enable/freeze delays. However, because the M3 is close to the Ubox, the= y generally should not diverge by more than a handful of cycles.", "Unit": "M3UPI" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2", "EventCode": "0xC0", "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "D2C Sent", + "Counter": "0,1,2", "EventCode": "0x2B", "EventName": "UNC_M3UPI_D2C_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases BL sends direct to core", "Unit": "M3UPI" }, { "BriefDescription": "D2U Sent", + "Counter": "0,1,2", "EventCode": "0x2A", "EventName": "UNC_M3UPI_D2U_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cases where SMI3 sends D2U command", "Unit": "M3UPI" }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2", "EventCode": "0xAE", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -4937,8 +6048,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2", "EventCode": "0xAE", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -4946,8 +6059,10 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2", "EventCode": "0xA5", "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x2", @@ -4955,8 +6070,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2", "EventCode": "0xA5", "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -4964,8 +6081,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -4973,8 +6092,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -4982,8 +6103,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -4991,8 +6114,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -5000,8 +6125,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -5009,8 +6136,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -5018,8 +6147,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -5027,8 +6158,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -5036,8 +6169,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -5045,8 +6180,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -5054,8 +6191,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -5063,8 +6202,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -5072,8 +6213,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2", "EventCode": "0xAD", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -5081,8 +6224,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2", "EventCode": "0xAD", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -5090,8 +6235,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the = same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x1", @@ -5099,8 +6246,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO2", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x2", @@ -5108,8 +6257,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO3", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x4", @@ -5117,8 +6268,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO4", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x8", @@ -5126,8 +6279,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO5", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x10", @@ -5135,8 +6290,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS = are in single mask. ORs them together", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x20", @@ -5144,8 +6301,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS cred= its", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x40", @@ -5153,8 +6312,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x1", @@ -5162,8 +6323,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x2", @@ -5171,8 +6334,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x4", @@ -5180,8 +6345,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x10", @@ -5189,8 +6356,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x20", @@ -5198,8 +6367,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x8", @@ -5207,8 +6378,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -5216,8 +6389,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -5225,8 +6400,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -5234,8 +6411,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -5243,8 +6422,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -5252,8 +6433,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -5261,8 +6444,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -5270,8 +6455,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -5279,87 +6466,109 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2", "EventCode": "0xA4", "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Lost Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -5367,8 +6576,10 @@ }, { "BriefDescription": "Lost Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -5376,8 +6587,10 @@ }, { "BriefDescription": "Lost Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5385,8 +6598,10 @@ }, { "BriefDescription": "Lost Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -5394,8 +6609,10 @@ }, { "BriefDescription": "Lost Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5403,8 +6620,10 @@ }, { "BriefDescription": "Lost Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -5412,8 +6631,10 @@ }, { "BriefDescription": "Lost Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -5421,8 +6642,10 @@ }, { "BriefDescription": "Lost Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -5430,8 +6653,10 @@ }, { "BriefDescription": "Lost Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -5439,8 +6664,10 @@ }, { "BriefDescription": "Lost Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5448,8 +6675,10 @@ }, { "BriefDescription": "Lost Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -5457,8 +6686,10 @@ }, { "BriefDescription": "Lost Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5466,8 +6697,10 @@ }, { "BriefDescription": "Lost Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -5475,8 +6708,10 @@ }, { "BriefDescription": "Lost Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -5484,8 +6719,10 @@ }, { "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD and BL messages won arbitration concurren= tly / in parallel", "UMask": "0x40", @@ -5493,8 +6730,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn0 messages because slotting stage cannot accept new message", "UMask": "0x4", @@ -5502,8 +6741,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn1 messages because slotting stage cannot accept new message", "UMask": "0x8", @@ -5511,8 +6752,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn0 messages because slotting stage cannot accept new message", "UMask": "0x10", @@ -5520,8 +6763,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn1 messages because slotting stage cannot accept new message", "UMask": "0x20", @@ -5529,8 +6774,10 @@ }, { "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", "UMask": "0x1", @@ -5538,8 +6785,10 @@ }, { "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", "UMask": "0x2", @@ -5547,8 +6796,10 @@ }, { "BriefDescription": "Can't Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", "UMask": "0x1", @@ -5556,8 +6807,10 @@ }, { "BriefDescription": "Can't Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", "UMask": "0x4", @@ -5565,8 +6818,10 @@ }, { "BriefDescription": "Can't Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5574,8 +6829,10 @@ }, { "BriefDescription": "Can't Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", "UMask": "0x20", @@ -5583,8 +6840,10 @@ }, { "BriefDescription": "Can't Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", "UMask": "0x40", @@ -5592,8 +6851,10 @@ }, { "BriefDescription": "Can't Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", "UMask": "0x8", @@ -5601,8 +6862,10 @@ }, { "BriefDescription": "Can't Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", "UMask": "0x10", @@ -5610,8 +6873,10 @@ }, { "BriefDescription": "Can't Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", "UMask": "0x1", @@ -5619,8 +6884,10 @@ }, { "BriefDescription": "Can't Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", "UMask": "0x4", @@ -5628,8 +6895,10 @@ }, { "BriefDescription": "Can't Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5637,8 +6906,10 @@ }, { "BriefDescription": "Can't Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", "UMask": "0x20", @@ -5646,8 +6917,10 @@ }, { "BriefDescription": "Can't Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", "UMask": "0x40", @@ -5655,8 +6928,10 @@ }, { "BriefDescription": "Can't Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", "UMask": "0x8", @@ -5664,8 +6939,10 @@ }, { "BriefDescription": "Can't Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", "UMask": "0x10", @@ -5673,8 +6950,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5682,8 +6961,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -5691,8 +6972,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -5700,8 +6983,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -5709,8 +6994,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -5718,8 +7005,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -5727,8 +7016,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -5736,8 +7027,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5745,8 +7038,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -5754,8 +7049,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -5763,8 +7060,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -5772,8 +7071,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -5781,8 +7082,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -5790,8 +7093,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -5799,8 +7104,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Ar= b", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while b= l message is in arbitration", "UMask": "0x2", @@ -5808,8 +7115,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while p= ipeline is idle", "UMask": "0x1", @@ -5817,8 +7126,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl = message in same flit", "UMask": "0x4", @@ -5826,8 +7137,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl = message in same flit", "UMask": "0x8", @@ -5835,8 +7148,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5844,8 +7159,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x4", @@ -5853,8 +7170,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", "UMask": "0x2", @@ -5862,8 +7181,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", "UMask": "0x20", @@ -5871,8 +7192,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5880,8 +7203,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", "UMask": "0x8", @@ -5889,8 +7214,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -5898,8 +7225,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5907,8 +7236,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x4", @@ -5916,8 +7247,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", "UMask": "0x2", @@ -5925,8 +7258,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", "UMask": "0x20", @@ -5934,8 +7269,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5943,8 +7280,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", "UMask": "0x8", @@ -5952,8 +7291,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -5961,8 +7302,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf (fifo only)", "UMask": "0x1", @@ -5970,8 +7313,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf path (i.e. pipe to fifo)", "UMask": "0x2", @@ -5979,8 +7324,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 or VN1 BL RSP message was blocked from a= rbitration request due to lack of D2K CMP credits", "UMask": "0x4", @@ -5988,8 +7335,10 @@ }, { "BriefDescription": "Credit Occupancy; D2K Credits", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2K completion fifo credit occupancy (credit= s in use), accumulated across all cycles", "UMask": "0x10", @@ -5997,8 +7346,10 @@ }, { "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer= bgf; packets (flits) in fifo", "UMask": "0x2", @@ -6006,8 +7357,10 @@ }, { "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer= bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", "UMask": "0x4", @@ -6015,8 +7368,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "count of bl messages in pump-1-pending state= , in completion fifo only", "UMask": "0x40", @@ -6024,8 +7379,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "count of bl messages in pump-1-pending state= , in marker table and in fifo", "UMask": "0x20", @@ -6033,8 +7390,10 @@ }, { "BriefDescription": "Credit Occupancy; Transmit Credits", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Link layer transmit queue credit occupancy (= credits in use), accumulated across all cycles", "UMask": "0x8", @@ -6042,8 +7401,10 @@ }, { "BriefDescription": "Credit Occupancy; VNA In Use", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote UPI VNA credit occupancy (number of c= redits in use), accumulated across all cycles", "UMask": "0x1", @@ -6051,8 +7412,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -6060,8 +7423,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -6069,8 +7434,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6078,8 +7445,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6087,8 +7456,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6096,8 +7467,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6105,8 +7478,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6114,8 +7489,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -6123,8 +7500,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -6132,8 +7511,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6141,8 +7522,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6150,8 +7533,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6159,8 +7544,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6168,8 +7555,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6177,8 +7566,10 @@ }, { "BriefDescription": "Data Flit Not Sent; All", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x1", @@ -6186,8 +7577,10 @@ }, { "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x2", @@ -6195,8 +7588,10 @@ }, { "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x4", @@ -6204,8 +7599,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 0", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 0", "UMask": "0x1", @@ -6213,8 +7610,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is at capacity (pending= table plus completion fifo at limit)", "UMask": "0x10", @@ -6222,8 +7621,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is tracking at least on= e message", "UMask": "0x8", @@ -6231,8 +7632,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending completion fifo is full", "UMask": "0x40", @@ -6240,8 +7643,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is at or near capacity,= such that pump-0-only bl messages are getting stalled in slotting stage", "UMask": "0x20", @@ -6249,8 +7654,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "a bl message finished but is in limbo and mo= ved to pump-1-pending logic", "UMask": "0x4", @@ -6258,8 +7665,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 1", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 1", "UMask": "0x2", @@ -6267,15 +7676,19 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "Counter": "0,1,2", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit; One Message", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "One message in flit; VNA or non-VNA flit", "UMask": "0x1", @@ -6283,8 +7696,10 @@ }, { "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "One message in flit; non-VNA flit", "UMask": "0x8", @@ -6292,8 +7707,10 @@ }, { "BriefDescription": "Sent Header Flit; Two Messages", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Two messages in flit; VNA flit", "UMask": "0x2", @@ -6301,8 +7718,10 @@ }, { "BriefDescription": "Sent Header Flit; Three Messages", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Three messages in flit; VNA flit", "UMask": "0x4", @@ -6310,40 +7729,50 @@ }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit; All", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit; Needs D= ata Flit", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL message requires data flit sequence", "UMask": "0x2", @@ -6351,8 +7780,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 0", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Waiting for header pump 0", "UMask": "0x4", @@ -6360,8 +7791,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit", "UMask": "0x10", @@ -6369,8 +7802,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Bubble", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit but f= lit transmission delayed", "UMask": "0x20", @@ -6378,8 +7813,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Not Avail", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit and n= ot available", "UMask": "0x40", @@ -6387,8 +7824,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 1", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Waiting for header pump 1", "UMask": "0x8", @@ -6396,8 +7835,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting control state machine is in any accumulate state= ; multi-message flit may be assembled over multiple cycles", "UMask": "0x1", @@ -6405,8 +7846,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; header flit slotting control state machine is in accum_ready state; f= lit is ready to send but transmission is blocked; more messages may be slot= ted into flit", "UMask": "0x2", @@ -6414,8 +7857,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Flit is being assembled over multiple cycles, but no additional messa= ge is being slotted into flit in current cycle; accumulate cycle is wasted", "UMask": "0x4", @@ -6423,8 +7868,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting entered run-ahead state; new header flit is star= ted while transmission of prior, fully assembled flit is blocked", "UMask": "0x8", @@ -6432,8 +7879,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting is in run-ahead to start new flit, and message i= s actually slotted into new flit", "UMask": "0x10", @@ -6441,8 +7890,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; New header flit construction may proceed in parallel with data flit s= equence", "UMask": "0x20", @@ -6450,8 +7901,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit finished assembly in parallel with data flit sequence", "UMask": "0x80", @@ -6459,8 +7912,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Message is slotted into header flit in parallel with data flit sequen= ce", "UMask": "0x40", @@ -6468,8 +7923,10 @@ }, { "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "Counter": "0,1,2", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate-matching stall injected", "UMask": "0x1", @@ -6477,8 +7934,10 @@ }, { "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No= Message", + "Counter": "0,1,2", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate matching stall injected, but no additional message slotted durin= g stall cycle", "UMask": "0x2", @@ -6486,8 +7945,10 @@ }, { "BriefDescription": "Header Not Sent; All", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent", "UMask": "0x1", @@ -6495,8 +7956,10 @@ }, { "BriefDescription": "Header Not Sent; No BGF Credits", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available", "UMask": "0x2", @@ -6504,8 +7967,10 @@ }, { "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Me= ssage Slotted", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available; no additional message slotted in= to flit", "UMask": "0x8", @@ -6513,8 +7978,10 @@ }, { "BriefDescription": "Header Not Sent; No TxQ Credits", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available", "UMask": "0x4", @@ -6522,8 +7989,10 @@ }, { "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Me= ssage Slotted", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available; no additional message slotted in= to flit", "UMask": "0x10", @@ -6531,8 +8000,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only one slot taken (two slots fr= ee)", "UMask": "0x20", @@ -6540,8 +8011,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with three slots taken (no slots free)= ", "UMask": "0x80", @@ -6549,8 +8022,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only two slots taken (one slots f= ree)", "UMask": "0x40", @@ -6558,8 +8033,10 @@ }, { "BriefDescription": "Message Held; Can't Slot AD", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some AD message could not be slotted (logica= l OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", "UMask": "0x40", @@ -6567,8 +8044,10 @@ }, { "BriefDescription": "Message Held; Can't Slot BL", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some BL message could not be slotted (logica= l OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", "UMask": "0x80", @@ -6576,8 +8055,10 @@ }, { "BriefDescription": "Message Held; Parallel AD Lost", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some AD message lost contest for slot 0 (log= ical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x10", @@ -6585,8 +8066,10 @@ }, { "BriefDescription": "Message Held; Parallel Attempt", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ad and bl messages attempted to slot into th= e same flit in parallel", "UMask": "0x4", @@ -6594,8 +8077,10 @@ }, { "BriefDescription": "Message Held; Parallel BL Lost", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some BL message lost contest for slot 0 (log= ical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x20", @@ -6603,8 +8088,10 @@ }, { "BriefDescription": "Message Held; Parallel Success", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ad and bl messages were actually slotted int= o the same flit in parallel", "UMask": "0x8", @@ -6612,8 +8099,10 @@ }, { "BriefDescription": "Message Held; VN0", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "vn0 message(s) that couldn't be slotted into= last vn0 flit are held in slotting stage while processing vn1 flit", "UMask": "0x1", @@ -6621,8 +8110,10 @@ }, { "BriefDescription": "Message Held; VN1", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "vn1 message(s) that couldn't be slotted into= last vn1 flit are held in slotting stage while processing vn0 flit", "UMask": "0x2", @@ -6630,8 +8121,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Home (REQ) = messages on AD. REQ is generally used to send requests, request responses,= and snoop responses.", "UMask": "0x1", @@ -6639,8 +8132,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on AD. RSP packets are used to transmit a variety of protocol= flits including grants and completions (CMP).", "UMask": "0x4", @@ -6648,8 +8143,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Snoops (SNP= ) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6657,8 +8154,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Broadcast (NCB) messages on BL. NCB is generally used to transmit data w= ithout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6666,8 +8165,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6675,8 +8176,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on BL. RSP packets are used to transmit a variety of protocol = flits including grants and completions (CMP).", "UMask": "0x8", @@ -6684,8 +8187,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on= BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Data Respon= se (WB) messages on BL. WB is generally used to transmit data with coheren= cy. For example, remote reads and writes, or cache to cache transfers will= transmit their data using WB.", "UMask": "0x10", @@ -6693,8 +8198,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -6702,8 +8209,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -6711,8 +8220,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6720,8 +8231,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6729,8 +8242,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6738,8 +8253,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6747,8 +8264,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on= BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6756,8 +8275,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6765,8 +8286,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", "UMask": "0x4", @@ -6774,8 +8297,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", "UMask": "0x2", @@ -6783,8 +8308,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", "UMask": "0x20", @@ -6792,8 +8319,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", "UMask": "0x40", @@ -6801,8 +8330,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", "UMask": "0x8", @@ -6810,8 +8341,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", "UMask": "0x10", @@ -6819,8 +8352,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6828,8 +8363,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", "UMask": "0x4", @@ -6837,8 +8374,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", "UMask": "0x2", @@ -6846,8 +8385,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", "UMask": "0x20", @@ -6855,8 +8396,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", "UMask": "0x40", @@ -6864,8 +8407,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", "UMask": "0x8", @@ -6873,8 +8418,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", "UMask": "0x10", @@ -6882,8 +8429,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6891,8 +8440,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -6900,8 +8451,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -6909,8 +8462,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -6918,8 +8473,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -6927,8 +8484,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -6936,8 +8495,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -6945,8 +8506,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6954,8 +8517,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -6963,8 +8528,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -6972,8 +8539,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -6981,8 +8550,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -6990,8 +8561,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -6999,8 +8572,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -7008,32 +8583,40 @@ }, { "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Dropped because it was overwritten by new me= ssage while prefetch queue was full", "UMask": "0x10", @@ -7041,16 +8624,20 @@ }, { "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Remote VNA Credits; Any In Use", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "At least one remote vna credit is in use", "UMask": "0x20", @@ -7058,8 +8645,10 @@ }, { "BriefDescription": "Remote VNA Credits; Corrected", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of remote vna credits corrected (loca= l return) per cycle", "UMask": "0x2", @@ -7067,8 +8656,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 1", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 1 (i.e.= no vna credits available)", "UMask": "0x4", @@ -7076,8 +8667,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 4", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 4; bl (= or ad requiring 4 vna) cannot arb on vna", "UMask": "0x8", @@ -7085,8 +8678,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 5", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 5; para= llel ad/bl arb on vna not possible", "UMask": "0x10", @@ -7094,8 +8689,10 @@ }, { "BriefDescription": "Remote VNA Credits; Used", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of remote vna credits consumed per cy= cle", "UMask": "0x1", @@ -7103,8 +8700,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -7112,8 +8711,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -7121,8 +8722,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -7130,8 +8733,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -7139,8 +8744,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -7148,8 +8755,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -7157,8 +8766,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -7166,8 +8777,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -7175,8 +8788,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -7184,8 +8799,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -7193,8 +8810,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -7202,8 +8821,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -7211,8 +8832,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -7220,8 +8843,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -7229,8 +8854,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -7238,8 +8865,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -7247,8 +8876,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -7256,8 +8887,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -7265,8 +8898,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -7274,8 +8909,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -7283,8 +8920,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -7292,8 +8931,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -7301,8 +8942,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -7310,8 +8953,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -7319,8 +8964,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -7328,8 +8975,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -7337,8 +8986,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -7346,8 +8997,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -7355,8 +9008,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -7364,8 +9019,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7373,8 +9030,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7382,8 +9041,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7391,8 +9052,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7400,8 +9063,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7409,8 +9074,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7418,8 +9085,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7427,8 +9096,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7436,8 +9107,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7445,8 +9118,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7454,8 +9129,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7463,8 +9140,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7472,8 +9151,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7481,8 +9162,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7490,8 +9173,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7499,8 +9184,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7508,8 +9195,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7517,8 +9206,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7526,8 +9217,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7535,8 +9228,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7544,8 +9239,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7553,8 +9250,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7562,8 +9261,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7571,8 +9272,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7580,8 +9283,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x1", @@ -7589,8 +9294,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x4", @@ -7598,8 +9305,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x2", @@ -7607,8 +9316,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x8", @@ -7616,8 +9327,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x10", @@ -7625,8 +9338,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x40", @@ -7634,8 +9349,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x20", @@ -7643,8 +9360,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x80", @@ -7652,8 +9371,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x1", @@ -7661,8 +9382,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x2", @@ -7670,8 +9393,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x4", @@ -7679,8 +9404,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x8", @@ -7688,8 +9415,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x1", @@ -7697,8 +9426,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x4", @@ -7706,8 +9437,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x2", @@ -7715,8 +9448,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x8", @@ -7724,8 +9459,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x10", @@ -7733,8 +9470,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x40", @@ -7742,8 +9481,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x20", @@ -7751,8 +9492,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x80", @@ -7760,8 +9503,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x1", @@ -7769,8 +9514,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x4", @@ -7778,8 +9525,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x2", @@ -7787,8 +9536,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x8", @@ -7796,8 +9547,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x10", @@ -7805,8 +9558,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x40", @@ -7814,8 +9569,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x20", @@ -7823,64 +9580,80 @@ }, { "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to CHA", "UMask": "0x4", @@ -7888,8 +9661,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn0 Snpf", "UMask": "0x40", @@ -7897,8 +9672,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI0", "UMask": "0x1", @@ -7906,8 +9683,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI1", "UMask": "0x2", @@ -7915,8 +9694,10 @@ }, { "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to CHA", "UMask": "0x20", @@ -7924,8 +9705,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn1 Snpf", "UMask": "0x80", @@ -7933,8 +9716,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI0", "UMask": "0x8", @@ -7942,8 +9727,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI1", "UMask": "0x10", @@ -7951,8 +9738,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn0", "UMask": "0x1", @@ -7960,8 +9749,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n0 SnpF issued when SnpF pending on Vn1", "UMask": "0x4", @@ -7969,8 +9760,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn1", "UMask": "0x2", @@ -7978,8 +9771,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n1 SnpF issued when SnpF pending on Vn0", "UMask": "0x8", @@ -7987,8 +9782,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x1", @@ -7996,8 +9793,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x2", @@ -8005,8 +9804,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x8", @@ -8014,8 +9815,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x10", @@ -8023,8 +9826,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x20", @@ -8032,8 +9837,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x80", @@ -8041,8 +9848,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 RE= Q Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x1", @@ -8050,8 +9859,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 SN= P Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x2", @@ -8059,8 +9870,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x8", @@ -8068,8 +9881,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 RE= Q Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x10", @@ -8077,8 +9892,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 SN= P Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x20", @@ -8086,8 +9903,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x80", @@ -8095,8 +9914,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x1", @@ -8104,8 +9925,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x4", @@ -8113,8 +9936,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x2", @@ -8122,8 +9947,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB M= essages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x8", @@ -8131,8 +9958,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x10", @@ -8140,8 +9969,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x40", @@ -8149,8 +9980,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", @@ -8158,8 +9991,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB M= essages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x80", @@ -8167,22 +10002,28 @@ }, { "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2", "EventCode": "0x2F", "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Occupancy", + "Counter": "0", "EventCode": "0x1E", "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x4", @@ -8190,8 +10031,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x8", @@ -8199,8 +10042,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x1", @@ -8208,8 +10053,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x2", @@ -8217,8 +10064,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x40", @@ -8226,8 +10075,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x80", @@ -8235,8 +10086,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x10", @@ -8244,8 +10097,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x20", @@ -8253,8 +10108,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x1", @@ -8262,8 +10119,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x4", @@ -8271,8 +10130,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x2", @@ -8280,8 +10141,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x8", @@ -8289,8 +10152,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x10", @@ -8298,8 +10163,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x40", @@ -8307,8 +10174,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x20", @@ -8316,8 +10185,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x80", @@ -8325,8 +10196,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x1", @@ -8334,8 +10207,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x2", @@ -8343,8 +10218,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x8", @@ -8352,8 +10229,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x4", @@ -8361,8 +10240,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x10", @@ -8370,8 +10251,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x20", @@ -8379,8 +10262,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x80", @@ -8388,8 +10273,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x40", @@ -8397,72 +10284,90 @@ }, { "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x2", @@ -8470,8 +10375,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 NC= S Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x8", @@ -8479,8 +10386,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x1", @@ -8488,8 +10397,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x20", @@ -8497,8 +10408,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 NC= B Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x80", @@ -8506,8 +10419,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 RS= P Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x10", @@ -8515,8 +10430,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x4", @@ -8524,8 +10441,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x8", @@ -8533,8 +10452,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x1", @@ -8542,8 +10463,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x2", @@ -8551,8 +10474,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x40", @@ -8560,8 +10485,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x80", @@ -8569,8 +10496,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x10", @@ -8578,8 +10507,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", @@ -8587,8 +10518,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8596,8 +10529,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8605,8 +10540,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8614,8 +10551,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8623,8 +10562,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8632,8 +10573,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8641,8 +10584,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8650,8 +10595,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8659,8 +10606,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8668,8 +10617,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8677,8 +10628,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -8686,8 +10639,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8695,8 +10650,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8704,8 +10661,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8713,8 +10672,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8722,8 +10683,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8731,8 +10694,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8740,8 +10705,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8749,8 +10716,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8758,8 +10727,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8767,8 +10738,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8776,8 +10749,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8785,8 +10760,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8794,8 +10771,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8803,8 +10782,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8812,8 +10793,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8821,8 +10804,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8830,8 +10815,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8839,8 +10826,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8848,8 +10837,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -8857,8 +10848,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -8866,8 +10859,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -8875,8 +10870,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -8884,8 +10881,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -8893,8 +10892,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -8902,8 +10903,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8911,8 +10914,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8920,8 +10925,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8929,8 +10936,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8938,8 +10947,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8947,8 +10958,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8956,8 +10969,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -8965,8 +10980,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -8974,8 +10991,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -8983,8 +11002,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -8992,8 +11013,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -9001,8 +11024,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -9010,8 +11035,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -9019,8 +11046,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -9028,8 +11057,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -9037,8 +11068,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -9046,8 +11079,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -9055,8 +11090,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -9064,8 +11101,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -9073,8 +11112,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -9082,8 +11123,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -9091,8 +11134,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -9100,8 +11145,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -9109,8 +11156,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -9118,8 +11167,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9127,8 +11178,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9136,8 +11189,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -9145,8 +11200,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -9154,8 +11211,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -9163,8 +11222,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9172,8 +11233,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -9181,8 +11244,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9190,8 +11255,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9199,8 +11266,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -9208,8 +11277,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -9217,8 +11288,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -9226,8 +11299,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9235,8 +11310,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -9244,8 +11321,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9253,8 +11332,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9262,8 +11343,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -9271,8 +11354,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -9280,8 +11365,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -9289,8 +11376,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9298,8 +11387,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -9307,8 +11398,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -9316,8 +11409,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -9325,8 +11420,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -9334,8 +11431,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -9343,8 +11442,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -9352,8 +11453,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -9361,8 +11464,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -9370,8 +11475,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9379,8 +11486,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9388,8 +11497,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -9397,8 +11508,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -9406,8 +11519,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -9415,8 +11530,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9424,8 +11541,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -9433,8 +11552,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -9442,8 +11563,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -9451,8 +11574,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -9460,8 +11585,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -9469,8 +11596,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -9478,8 +11607,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -9487,8 +11618,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x2", @@ -9496,8 +11629,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x8", @@ -9505,8 +11640,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x4", @@ -9514,8 +11651,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x10", @@ -9523,8 +11662,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x40", @@ -9532,8 +11673,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x20", @@ -9541,8 +11684,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VNA", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x1", @@ -9550,8 +11695,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x4", @@ -9559,8 +11706,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x2", @@ -9568,8 +11717,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x8", @@ -9577,8 +11728,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x20", @@ -9586,8 +11739,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x10", @@ -9595,8 +11750,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x40", @@ -9604,8 +11761,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VNA", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x1", @@ -9613,6 +11772,7 @@ }, { "BriefDescription": "Prefetches generated by the flow control queu= e of the M3UPI unit.", + "Counter": "0,1,2", "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "PerPkg": "1", @@ -9621,8 +11781,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -9630,8 +11792,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -9639,8 +11803,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -9648,8 +11814,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -9657,8 +11825,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -9666,8 +11836,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -9675,8 +11847,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -9684,8 +11858,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -9693,8 +11869,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -9702,8 +11880,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -9711,8 +11891,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -9720,8 +11902,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -9729,8 +11913,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2", "EventCode": "0xAC", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -9738,8 +11924,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2", "EventCode": "0xAC", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -9747,8 +11935,10 @@ }, { "BriefDescription": "VN0 Credit Used; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Data Response (WB) messages on BL. WB is generally used to tran= smit data with coherency. For example, remote reads and writes, or cache t= o cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9756,8 +11946,10 @@ }, { "BriefDescription": "VN0 Credit Used; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally u= sed to transmit data without coherency. For example, non-coherent read dat= a returns.", "UMask": "0x20", @@ -9765,8 +11957,10 @@ }, { "BriefDescription": "VN0 Credit Used; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Home (REQ) messages on AD. REQ is generally used to send reques= ts, request responses, and snoop responses.", "UMask": "0x1", @@ -9774,8 +11968,10 @@ }, { "BriefDescription": "VN0 Credit Used; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on AD. RSP packets are used to transmit= a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9783,8 +11979,10 @@ }, { "BriefDescription": "VN0 Credit Used; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9792,8 +11990,10 @@ }, { "BriefDescription": "VN0 Credit Used; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on BL. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9801,8 +12001,10 @@ }, { "BriefDescription": "VN0 No Credits; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -9810,8 +12012,10 @@ }, { "BriefDescription": "VN0 No Credits; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -9819,8 +12023,10 @@ }, { "BriefDescription": "VN0 No Credits; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -9828,8 +12034,10 @@ }, { "BriefDescription": "VN0 No Credits; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9837,8 +12045,10 @@ }, { "BriefDescription": "VN0 No Credits; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9846,8 +12056,10 @@ }, { "BriefDescription": "VN0 No Credits; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9855,8 +12067,10 @@ }, { "BriefDescription": "VN1 Credit Used; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Data Response (WB) messages on BL. WB is generally used to trans= mit data with coherency. For example, remote reads and writes, or cache to= cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9864,8 +12078,10 @@ }, { "BriefDescription": "VN1 Credit Used; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally us= ed to transmit data without coherency. For example, non-coherent read data= returns.", "UMask": "0x20", @@ -9873,8 +12089,10 @@ }, { "BriefDescription": "VN1 Credit Used; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Home (REQ) messages on AD. REQ is generally used to send request= s, request responses, and snoop responses.", "UMask": "0x1", @@ -9882,8 +12100,10 @@ }, { "BriefDescription": "VN1 Credit Used; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on AD. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9891,8 +12111,10 @@ }, { "BriefDescription": "VN1 Credit Used; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9900,8 +12122,10 @@ }, { "BriefDescription": "VN1 Credit Used; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a= variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9909,8 +12133,10 @@ }, { "BriefDescription": "VN1 No Credits; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -9918,8 +12144,10 @@ }, { "BriefDescription": "VN1 No Credits; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -9927,8 +12155,10 @@ }, { "BriefDescription": "VN1 No Credits; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -9936,8 +12166,10 @@ }, { "BriefDescription": "VN1 No Credits; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9945,8 +12177,10 @@ }, { "BriefDescription": "VN1 No Credits; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9954,8 +12188,10 @@ }, { "BriefDescription": "VN1 No Credits; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9963,15 +12199,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_TxC_BL.DRS_UPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x40", "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnec= t (UPI)", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -9980,6 +12219,7 @@ }, { "BriefDescription": "Data Response packets that go direct to core", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", "PerPkg": "1", @@ -9989,6 +12229,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", @@ -9998,6 +12239,7 @@ }, { "BriefDescription": "Data Response packets that go direct to Intel= (R) UPI", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", "PerPkg": "1", @@ -10007,70 +12249,87 @@ }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shut= down)", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", @@ -10079,164 +12338,205 @@ }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_UPI_POWER_L1_NACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqNAck. When the UPI links would like to change power state, t= he Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wi= th an Ack, the power mode will change. If it replies with NAck, no change = will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNA= ck refers to receiving an NAck (meaning this agent's Tx originally requeste= d the power change). A Tx LinkReqNAck refers to sending this command (mean= ing the peer agent's Tx originally requested the power change and this agen= t accepted it).", "Unit": "UPI" }, { "BriefDescription": "L1 Req (same as L1 Ack).", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_UPI_POWER_L1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqAck. When the UPI links would like to change power state, th= e Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wit= h an Ack, the power mode will change. If it replies with NAck, no change w= ill take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck= refers to receiving an Ack (meaning this agent's Tx originally requested t= he power change). A Tx LinkReqAck refers to sending this command (meaning = the peer agent's Tx originally requested the power change and this agent ac= cepted it).", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p p= ower mode", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -10245,16 +12545,20 @@ }, { "BriefDescription": "Cycles in L0. Receive side.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0xe", @@ -10262,8 +12566,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0x10e", @@ -10271,8 +12577,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0xf", @@ -10280,8 +12588,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0x10f", @@ -10289,8 +12599,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQ Message Class", "UMask": "0x8", @@ -10298,8 +12610,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t Opcode", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", "UMask": "0x108", @@ -10307,24 +12621,30 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xc", @@ -10332,8 +12652,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10c", @@ -10341,8 +12663,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0xa", @@ -10350,8 +12674,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0x10a", @@ -10359,8 +12685,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "SNP Message Class", "UMask": "0x9", @@ -10368,8 +12696,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Snoop = Opcode", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", "UMask": "0x109", @@ -10377,8 +12707,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xd", @@ -10386,8 +12718,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10d", @@ -10395,6 +12729,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", @@ -10404,6 +12739,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", @@ -10413,6 +12749,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", @@ -10422,30 +12759,37 @@ }, { "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VNA c= redit was consumed (i.e. message uses a VNA credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "Valid data FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -10455,6 +12799,7 @@ }, { "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -10464,8 +12809,10 @@ }, { "BriefDescription": "Valid Flits Received; Data", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Data Flits (which consume all slots), but how much to count= is based on Slot0-2 mask, so count can be 0-3 depending on which slots are= enabled for counting..", "UMask": "0x8", @@ -10473,8 +12820,10 @@ }, { "BriefDescription": "Valid Flits Received; Idle", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).", "UMask": "0x47", @@ -10482,8 +12831,10 @@ }, { "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", "UMask": "0x10", @@ -10491,8 +12842,10 @@ }, { "BriefDescription": "Valid Flits Received; LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", "UMask": "0x40", @@ -10500,6 +12853,7 @@ }, { "BriefDescription": "Protocol header and credit FLITs received fro= m any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -10509,6 +12863,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.NULL", @@ -10518,8 +12873,10 @@ }, { "BriefDescription": "Valid Flits Received; Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", "UMask": "0x80", @@ -10527,17 +12884,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", "UMask": "0x1", @@ -10545,8 +12906,10 @@ }, { "BriefDescription": "Valid Flits Received; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", "UMask": "0x2", @@ -10554,8 +12917,10 @@ }, { "BriefDescription": "Valid Flits Received; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", "UMask": "0x4", @@ -10563,62 +12928,76 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "UPI" }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x1", @@ -10626,8 +13005,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x2", @@ -10635,8 +13016,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x4", @@ -10644,8 +13027,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x1", @@ -10653,8 +13038,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x2", @@ -10662,8 +13049,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x4", @@ -10671,118 +13060,147 @@ }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra = Path Interconnect (UPI) is in L0p power mode", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -10791,30 +13209,38 @@ }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0. Transmit side.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0xe", @@ -10822,8 +13248,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0x10e", @@ -10831,8 +13259,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0xf", @@ -10840,8 +13270,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0x10f", @@ -10849,8 +13281,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQ Message Class", "UMask": "0x8", @@ -10858,8 +13292,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st Opcode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", "UMask": "0x108", @@ -10867,24 +13303,30 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xc", @@ -10892,8 +13334,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10c", @@ -10901,8 +13345,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0xa", @@ -10910,8 +13356,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0x10a", @@ -10919,8 +13367,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= ", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "SNP Message Class", "UMask": "0x9", @@ -10928,8 +13378,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= Opcode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", "UMask": "0x109", @@ -10937,8 +13389,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xd", @@ -10946,8 +13400,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10d", @@ -10955,6 +13411,7 @@ }, { "BriefDescription": "FLITs that bypassed the TxL Buffer", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", "PerPkg": "1", @@ -10963,6 +13420,7 @@ }, { "BriefDescription": "Valid data FLITs transmitted via any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -10972,6 +13430,7 @@ }, { "BriefDescription": "Null FLITs transmitted from any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -10981,6 +13440,7 @@ }, { "BriefDescription": "Valid Flits Sent; Data", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.DATA", "PerPkg": "1", @@ -10990,6 +13450,7 @@ }, { "BriefDescription": "Idle FLITs transmitted", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.IDLE", "PerPkg": "1", @@ -10999,8 +13460,10 @@ }, { "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", "UMask": "0x10", @@ -11008,8 +13471,10 @@ }, { "BriefDescription": "Valid Flits Sent; LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", "UMask": "0x40", @@ -11017,6 +13482,7 @@ }, { "BriefDescription": "Protocol header and credit FLITs transmitted = across any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -11026,6 +13492,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.NULL", @@ -11035,8 +13502,10 @@ }, { "BriefDescription": "Valid Flits Sent; Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", "UMask": "0x80", @@ -11044,17 +13513,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", "UMask": "0x1", @@ -11062,8 +13535,10 @@ }, { "BriefDescription": "Valid Flits Sent; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", "UMask": "0x2", @@ -11071,8 +13546,10 @@ }, { "BriefDescription": "Valid Flits Sent; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", "UMask": "0x4", @@ -11080,157 +13557,195 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Tx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = TxQ and pass directly to the link. However, the TxQ will be used with L0p = and when LLR occurs, increasing latency to transfer out to the link. This = event can be used in conjunction with the Flit Buffer Occupancy event in or= der to calculate the average flit buffer lifetime.", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of flits in the TxQ. = Generally, when data is transmitted across UPI, it will bypass the TxQ and= pass directly to the link. However, the TxQ will be used with L0p and whe= n LLR occurs, increasing latency to transfer out to the link. This can be u= sed with the cycles not empty event to track average occupancy, or the allo= cations event to track average lifetime in the TxQ.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of VNA credits in the Rx side that ar= e waitng to be returned back across the link.", "Unit": "UPI" }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "UBOX" }, { "BriefDescription": "Message Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x8", @@ -11238,8 +13753,10 @@ }, { "BriefDescription": "Message Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x10", @@ -11247,8 +13764,10 @@ }, { "BriefDescription": "Message Received; IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Inter Processor Interrupts", "UMask": "0x4", @@ -11256,8 +13775,10 @@ }, { "BriefDescription": "Message Received; MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Message Signaled Interrupts - interrupts sent by devi= ces (including PCIe via IOxAPIC) (Socket Mode only)", "UMask": "0x2", @@ -11265,8 +13786,10 @@ }, { "BriefDescription": "Message Received; VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x1", @@ -11274,16 +13797,20 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times an IDI Lock/SplitLock sequen= ce was started", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PHOLD cycles.", "UMask": "0x1", @@ -11291,38 +13818,47 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number outstanding register requests within = message channel tracker", "Unit": "UBOX" }, { "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UPI_DATA_BANDWIDTH_TX", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json b/t= ools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json index 743c91f3d2f0..bce46dd4f395 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_READ", "FCMask": "0x07", @@ -16,6 +17,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_WRITE", "FCMask": "0x07", @@ -31,6 +33,7 @@ }, { "BriefDescription": "Clockticks of the IIO Traffic Controller", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -39,6 +42,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", "FCMask": "0x4", @@ -49,6 +53,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", "FCMask": "0x4", @@ -59,6 +64,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", "FCMask": "0x4", @@ -69,6 +75,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", "FCMask": "0x4", @@ -79,6 +86,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", "FCMask": "0x4", @@ -89,8 +97,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x01", @@ -99,8 +109,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x02", @@ -109,8 +121,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x04", @@ -119,8 +133,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x08", @@ -129,6 +145,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -138,6 +155,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", "FCMask": "0x04", @@ -147,6 +165,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 1", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", "FCMask": "0x04", @@ -156,6 +175,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 2", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", "FCMask": "0x04", @@ -165,6 +185,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 3", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", "FCMask": "0x04", @@ -174,8 +195,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -185,8 +208,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -196,8 +221,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -207,8 +234,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -218,8 +247,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -229,8 +260,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -240,8 +273,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -251,8 +286,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -262,8 +299,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -273,8 +312,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -284,8 +325,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -295,8 +338,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -306,8 +351,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -317,8 +364,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -328,8 +377,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -339,8 +390,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -350,8 +403,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -361,8 +416,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -372,8 +429,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -383,8 +442,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -394,8 +455,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -405,8 +468,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -416,8 +481,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -427,8 +494,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -438,6 +507,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -449,6 +519,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -460,6 +531,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -471,6 +543,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -482,8 +555,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -493,8 +568,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -504,6 +581,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -515,6 +593,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -526,6 +605,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -537,6 +617,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -548,8 +629,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -559,8 +642,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -570,6 +655,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -581,6 +667,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part1", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -592,6 +679,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part2", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -603,6 +691,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part3", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -614,8 +703,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -625,8 +716,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -636,6 +729,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -647,6 +741,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part1 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -658,6 +753,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part2 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -669,6 +765,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part3 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -680,8 +777,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -691,8 +790,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -702,8 +803,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -713,8 +816,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -724,8 +829,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -735,8 +842,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -746,8 +855,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -757,8 +868,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -768,8 +881,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -779,8 +894,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -790,8 +907,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -801,8 +920,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -812,6 +933,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -823,6 +945,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -834,6 +957,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -845,6 +969,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -856,8 +981,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -867,8 +994,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -878,6 +1007,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -889,6 +1019,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -900,6 +1031,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -911,6 +1043,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -922,8 +1055,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -933,8 +1068,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -944,8 +1081,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -955,8 +1094,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -966,8 +1107,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -977,8 +1120,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -988,8 +1133,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -999,8 +1146,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1010,6 +1159,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -1021,6 +1171,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part1 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -1032,6 +1183,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part2 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -1043,6 +1195,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part3 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -1054,8 +1207,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1065,8 +1220,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1076,6 +1233,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -1087,6 +1245,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -1098,6 +1257,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -1109,6 +1269,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -1120,8 +1281,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1131,8 +1294,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1142,29 +1307,37 @@ }, { "BriefDescription": "Num Link Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Num Link Retries", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Number packets that passed the Mask/Match Fil= ter", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_IIO_MASK_MATCH", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x1", @@ -1172,8 +1345,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x8", @@ -1181,8 +1356,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x4", @@ -1190,8 +1367,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x2", @@ -1199,8 +1378,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x10", @@ -1208,8 +1389,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x20", @@ -1217,8 +1400,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x1", @@ -1226,8 +1411,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x8", @@ -1235,8 +1422,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x4", @@ -1244,8 +1433,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x2", @@ -1253,8 +1444,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x10", @@ -1262,8 +1455,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x20", @@ -1271,15 +1466,19 @@ }, { "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", "EventName": "UNC_IIO_NOTHING", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1288,9 +1487,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1299,9 +1500,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1310,9 +1513,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1321,9 +1526,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1332,9 +1539,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1343,9 +1552,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1354,9 +1565,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1365,9 +1578,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1376,9 +1591,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1387,6 +1604,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", @@ -1398,6 +1616,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", @@ -1409,6 +1628,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", @@ -1420,6 +1640,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", @@ -1431,9 +1652,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1442,9 +1665,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1453,6 +1678,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", @@ -1464,6 +1690,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", @@ -1475,6 +1702,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", @@ -1486,6 +1714,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", @@ -1497,9 +1726,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1508,9 +1739,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1519,9 +1752,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1530,9 +1765,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1541,9 +1778,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1552,9 +1791,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1563,9 +1804,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1574,9 +1817,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1585,9 +1830,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1596,9 +1843,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1607,9 +1856,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1618,9 +1869,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1629,9 +1882,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1640,9 +1895,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1651,9 +1908,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1662,9 +1921,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1673,9 +1934,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1684,9 +1947,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1695,9 +1960,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1706,9 +1973,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1717,9 +1986,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1728,9 +1999,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1739,9 +2012,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1750,9 +2025,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1761,9 +2038,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1772,9 +2051,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1783,9 +2064,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1794,9 +2077,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1805,9 +2090,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1816,9 +2103,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1827,9 +2116,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1838,9 +2129,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1849,9 +2142,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1860,9 +2155,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1871,9 +2168,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1882,9 +2181,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1893,9 +2194,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1904,9 +2207,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1915,9 +2220,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1926,9 +2233,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1937,9 +2246,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1948,9 +2259,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1959,9 +2272,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1970,9 +2285,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1981,9 +2298,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1992,9 +2311,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2003,9 +2324,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2014,9 +2337,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2025,9 +2350,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2036,9 +2363,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2047,9 +2376,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2058,9 +2389,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2069,9 +2402,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2080,9 +2415,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2091,9 +2428,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2102,9 +2441,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2113,9 +2454,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2124,9 +2467,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2135,9 +2480,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2146,9 +2493,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2157,9 +2506,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2168,9 +2519,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2179,9 +2532,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2190,9 +2545,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2201,9 +2558,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2212,9 +2571,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2223,9 +2584,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2234,9 +2597,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2245,17 +2610,21 @@ }, { "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_IIO_SYMBOL_TIMES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - incr= ement once every 2nS, Gen3 - increment once every 1nS", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2264,9 +2633,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2275,9 +2646,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2286,9 +2659,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2297,9 +2672,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2308,9 +2685,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2319,9 +2698,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2330,9 +2711,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2341,9 +2724,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2352,9 +2737,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2363,9 +2750,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2374,9 +2763,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2385,9 +2776,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2396,9 +2789,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2407,9 +2802,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2418,9 +2815,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2429,9 +2828,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2440,9 +2841,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2451,9 +2854,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2462,9 +2867,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2473,9 +2880,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2484,9 +2893,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2495,9 +2906,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2506,9 +2919,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2517,9 +2932,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2528,9 +2945,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2539,9 +2958,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2550,9 +2971,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2561,9 +2984,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2572,9 +2997,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2583,9 +3010,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2594,9 +3023,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2605,9 +3036,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2616,9 +3049,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2627,9 +3062,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2638,9 +3075,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2649,9 +3088,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2660,9 +3101,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2671,9 +3114,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2682,9 +3127,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2693,9 +3140,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2704,9 +3153,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2715,9 +3166,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2726,9 +3179,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2737,9 +3192,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2748,9 +3205,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2759,9 +3218,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2770,9 +3231,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2781,9 +3244,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2792,9 +3257,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2803,9 +3270,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2814,9 +3283,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2825,9 +3296,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2836,9 +3309,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2847,9 +3322,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2858,9 +3335,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2869,9 +3348,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2880,9 +3361,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2891,9 +3374,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2902,9 +3387,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2913,9 +3400,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2924,9 +3413,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2935,9 +3426,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2946,9 +3439,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2957,9 +3452,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2968,9 +3465,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2979,9 +3478,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2990,9 +3491,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3001,9 +3504,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3012,9 +3517,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3023,9 +3530,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3034,9 +3543,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3045,9 +3556,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3056,9 +3569,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3067,9 +3582,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3078,9 +3595,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3089,9 +3608,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3100,9 +3621,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3111,9 +3634,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3122,9 +3647,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3133,9 +3660,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3144,9 +3673,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3155,9 +3686,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3166,9 +3699,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3177,9 +3712,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3188,9 +3725,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3199,9 +3738,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3210,8 +3751,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3221,8 +3764,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3232,8 +3777,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3243,8 +3790,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3254,8 +3803,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3265,8 +3816,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3276,8 +3829,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3287,8 +3842,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3298,8 +3855,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3309,8 +3868,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3320,8 +3881,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3331,8 +3894,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3342,8 +3907,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3353,8 +3920,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3364,8 +3933,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3375,8 +3946,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3386,8 +3959,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3397,8 +3972,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3408,8 +3985,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3419,8 +3998,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3430,8 +4011,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3441,8 +4024,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3452,8 +4037,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3463,8 +4050,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3474,6 +4063,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3485,6 +4075,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3496,6 +4087,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3507,6 +4099,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3518,8 +4111,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3529,8 +4124,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3540,6 +4137,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3551,6 +4149,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3562,6 +4161,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3573,6 +4173,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3584,8 +4185,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3595,8 +4198,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3606,6 +4211,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -3617,6 +4223,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -3628,6 +4235,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -3639,6 +4247,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -3650,8 +4259,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3661,8 +4272,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3672,6 +4285,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part0 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -3683,6 +4297,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part1 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -3694,6 +4309,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part2 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -3705,6 +4321,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part3 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -3716,8 +4333,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3727,8 +4346,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3738,8 +4359,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3749,8 +4372,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3760,8 +4385,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3771,8 +4398,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3782,8 +4411,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3793,8 +4424,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3804,8 +4437,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3815,8 +4450,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3826,8 +4463,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3837,8 +4476,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3848,6 +4489,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3859,6 +4501,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3870,6 +4513,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3881,6 +4525,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3892,8 +4537,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3903,8 +4550,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3914,6 +4563,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3925,6 +4575,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3936,6 +4587,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3947,6 +4599,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3958,8 +4611,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3969,8 +4624,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3980,8 +4637,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3991,8 +4650,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4002,8 +4663,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4013,8 +4676,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4024,8 +4689,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4035,8 +4702,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4046,6 +4715,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -4057,6 +4727,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -4068,6 +4739,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -4079,6 +4751,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -4090,8 +4763,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4101,8 +4776,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4112,6 +4789,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -4123,6 +4801,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -4134,6 +4813,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -4145,6 +4825,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -4156,8 +4837,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4167,8 +4850,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4178,72 +4863,90 @@ }, { "BriefDescription": "VTd Access; context cache miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L1 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L2 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L3 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "VTd Access; Vtd hit", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB is full", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IIO" }, { "BriefDescription": "VTd Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_VTD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" } diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json= b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json index d82d2cca6f0a..265cdf334f6a 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,8 +23,10 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Bypass", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", "UMask": "0x8", @@ -30,8 +34,10 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", "UMask": "0x1", @@ -39,6 +45,7 @@ }, { "BriefDescription": "DRAM Page Activate commands sent due to a wri= te request", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -48,30 +55,37 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "All DRAM CAS Commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -81,6 +95,7 @@ }, { "BriefDescription": "All DRAM Read CAS Commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -90,14 +105,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Read ISOCH Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "All DRAM Read CAS Commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -107,14 +125,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -124,14 +145,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "All DRAM Write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -141,16 +165,20 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Write ISOCH Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of Opportunistic DRA= M Write CAS commands issued on this channel while in Read-Major-Mode.", "UMask": "0x8", @@ -158,6 +186,7 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -167,6 +196,7 @@ }, { "BriefDescription": "Memory controller clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts clockticks of the fixed frequency clo= ck of the memory controller using one of the programmable counters.", @@ -174,63 +204,79 @@ }, { "BriefDescription": "Clockticks in the Memory Controller using a d= edicated 48-bit Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_F", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "Unit": "iMC" }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { "BriefDescription": "UNC_M_MAJMODE2.DRAM_CYC", + "Counter": "0,1,2,3", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.DRAM_CYC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "UNC_M_MAJMODE2.DRAM_ENTER", + "Counter": "0,1,2,3", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.DRAM_ENTER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Major Mode 2 : Cycles in PMM major mode", + "Counter": "0,1,2,3", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.PMM_CYC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Major Mode 2 : Entered PMM major mode", + "Counter": "0,1,2,3", "EventCode": "0xED", "EventName": "UNC_M_MAJMODE2.PMM_ENTER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; We group these tw= o modes together so that we can use four counters to track each of the majo= r modes at one time. These major modes are used whenever there is an ISOCH= txn in the memory controller. In these mode, only ISOCH transactions are = processed.", "UMask": "0x8", @@ -238,8 +284,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode i= s used to drain starved underfill reads. Regular reads and writes are bloc= ked and only underfill reads will be processed.", "UMask": "0x4", @@ -247,8 +295,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode i= s the default mode for the iMC, as reads are generally more critical to for= ward progress than writes.", "UMask": "0x1", @@ -256,8 +306,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is trig= gered when the WPQ hits high occupancy and causes writes to be higher prior= ity than reads. This can cause blips in the available read bandwidth in th= e system and temporarily increase read latencies in order to achieve better= bus utilizations and higher bandwidth.", "UMask": "0x2", @@ -265,6 +317,7 @@ }, { "BriefDescription": "Intel Optane DC persistent memory bandwidth r= ead (MB/sec). Derived from unc_m_pmm_rpq_inserts", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M_PMM_BANDWIDTH.READ", "PerPkg": "1", @@ -273,6 +326,7 @@ }, { "BriefDescription": "Intel Optane DC persistent memory bandwidth t= otal (MB/sec). Derived from unc_m_pmm_rpq_inserts", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M_PMM_BANDWIDTH.TOTAL", "MetricExpr": "UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS", @@ -283,6 +337,7 @@ }, { "BriefDescription": "Intel Optane DC persistent memory bandwidth w= rite (MB/sec). Derived from unc_m_pmm_wpq_inserts", + "Counter": "0,1,2,3", "EventCode": "0xE7", "EventName": "UNC_M_PMM_BANDWIDTH.WRITE", "PerPkg": "1", @@ -291,6 +346,7 @@ }, { "BriefDescription": "All commands for Intel(R) Optane(TM) DC persi= stent memory", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.ALL", "PerPkg": "1", @@ -299,22 +355,27 @@ }, { "BriefDescription": "Misc Commands (error, flow ACKs)", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.MISC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Misc GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.MISC_GNT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Regular reads(RPQ) commands for Intel(R) Opta= ne(TM) DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.RD", "PerPkg": "1", @@ -324,14 +385,17 @@ }, { "BriefDescription": "RPQ GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Underfill read commands for Intel(R) Optane(T= M) DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.UFILL_RD", "PerPkg": "1", @@ -341,14 +405,17 @@ }, { "BriefDescription": "Underfill GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Write commands for Intel(R) Optane(TM) DC per= sistent memory", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.WR", "PerPkg": "1", @@ -358,102 +425,127 @@ }, { "BriefDescription": "Expected No data packet (ERID matched NDP enc= oding)", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Unexpected No data packet (ERID matched a Rea= d, but data was a NDP)", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Opportunistic Reads", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.OPP_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "PMM ECC Errors", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "PMM ERID detectable parity error", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Read Requests - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Read Requests - Slot 1", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "PMM Major Mode; Cycles PMM is in Partial Writ= e Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xEC", "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_CYC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "PMM Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xEC", "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_ENTER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "PMM Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xEC", "EventName": "UNC_M_PMM_MAJMODE1.PARTIAL_WR_EXIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "PMM Major Mode; Cycles PMM is in Read Major M= ode", + "Counter": "0,1,2,3", "EventCode": "0xEC", "EventName": "UNC_M_PMM_MAJMODE1.RD_CYC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "PMM Major Mode; Cycles PMM is in Write Major = Mode", + "Counter": "0,1,2,3", "EventCode": "0xEC", "EventName": "UNC_M_PMM_MAJMODE1.WR_CYC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Intel Optane DC persistent memory read latenc= y (ns). Derived from unc_m_pmm_rpq_occupancy.all", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_READ_LATENCY", "MetricExpr": "UNC_M_PMM_RPQ_OCCUPANCY.ALL / UNC_M_PMM_RPQ_INSERTS= / UNC_M_CLOCKTICKS", @@ -465,20 +557,25 @@ }, { "BriefDescription": "PMM Read Queue Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Read Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Write requests allocated in the PMM Write Pen= ding Queue for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M_PMM_RPQ_INSERTS", "PerPkg": "1", @@ -486,6 +583,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy of all read requ= ests for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -494,28 +592,35 @@ }, { "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "PMM Write Queue Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Write requests allocated in the PMM Write Pen= ding Queue for Intel Optane DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xE7", "EventName": "UNC_M_PMM_WPQ_INSERTS", "PerPkg": "1", @@ -523,6 +628,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy of all write re= quests for Intel(R) Optane(TM) DC persistent memory", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -531,44 +637,55 @@ }, { "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "PMM Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "UNC_M_PMM_WPQ_PCOMMIT", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PMM_WPQ_PCOMMIT_CYC", + "Counter": "0,1,2,3", "EventCode": "0xE9", "EventName": "UNC_M_PMM_WPQ_PCOMMIT_CYC", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", "Unit": "iMC" }, { "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode+C37", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100", @@ -579,8 +696,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x1", @@ -588,8 +707,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x2", @@ -597,8 +718,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x4", @@ -606,8 +729,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x8", @@ -615,8 +740,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x10", @@ -624,8 +751,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x20", @@ -633,8 +762,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x40", @@ -642,8 +773,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x80", @@ -651,21 +784,26 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Cycles Memory is in self refresh power mode", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", @@ -676,8 +814,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.; Thermal throttling is performed= per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by= ID.", "UMask": "0x1", @@ -685,8 +825,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x2", @@ -694,8 +836,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x4", @@ -703,8 +847,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x8", @@ -712,8 +858,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x10", @@ -721,8 +869,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x20", @@ -730,8 +880,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x40", @@ -739,8 +891,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x80", @@ -748,8 +902,10 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts another read.", "UMask": "0x1", @@ -757,8 +913,10 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts a write.", "UMask": "0x2", @@ -766,8 +924,10 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x10", @@ -775,8 +935,10 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of the page close counter expiring. This does n= ot include implicit precharge commands sent in auto-precharge mode.", "UMask": "0x2", @@ -784,6 +946,7 @@ }, { "BriefDescription": "Pre-charges due to page misses", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -793,6 +956,7 @@ }, { "BriefDescription": "Pre-charge for reads", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -802,8 +966,10 @@ }, { "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x8", @@ -811,1390 +977,1739 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the Read Pe= nding Queue is full. When the RPQ is full, the HA will not be able to issu= e any additional read requests into the iMC. This count should be similar = count in the HA which tracks the number of cycles that the HA has no RPQ cr= edits, just somewhat smaller to account for the credit return overhead. We= generally do not expect to see RPQ become full except for potentially duri= ng Write Major Mode or while running with slow DRAM. This event only track= s non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -2203,6 +2718,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY", "PerPkg": "1", @@ -2211,452 +2727,565 @@ }, { "BriefDescription": "Scoreboard Accesses; Write Accepts", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; Write Rejects", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; FM read completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; FM write completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; Read Accepts", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; Read Rejects", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; NM read completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses; NM write completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Alloc", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.ALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Dealloc", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Far Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Far Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Near Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Near Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Reject", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Valid", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.VLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M_SB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M_SB_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Dealloc all commands (for= error flows)", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Patrol inserts", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.PATROL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts; Writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Patrol", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.PATROL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy; Writes", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected; FM re= quests rejected due to full address conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected; NM re= quests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected; Patro= l requests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Far Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_CLR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FMRD_SET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Far Mem Write - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_CLR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FMWR_SET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_CLR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NMRD_SET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Near Mem Write - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_CLR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NMWR_SET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Far Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.FMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Far Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.FMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Near Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.NMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Near Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.NEW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.OCC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "All hits to Near Memory(DRAM cache) in Memory= Mode", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", @@ -2666,6 +3295,7 @@ }, { "BriefDescription": "All Clean line misses to Near Memory(DRAM cac= he) in Memory Mode", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", @@ -2675,6 +3305,7 @@ }, { "BriefDescription": "All dirty line misses to Near Memory(DRAM cac= he) in Memory Mode", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", @@ -2684,46 +3315,57 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional write requests into the iMC. This count should be simila= r count in the CHA which tracks the number of cycles that the CHA has no WP= Q credits, just somewhat smaller to account for the credit return overhead.= ", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the CHA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of th= e rest of the system) as soon they have posted to the iMC. This is not to = be confused with actually performing the write to DRAM. Therefore, the ave= rage latency for this queue is actually not useful for deconstruction inter= mediate write latencies.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS", "PerPkg": "1", @@ -2732,6 +3374,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", @@ -2740,1359 +3383,1701 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json = b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json index ceef46046488..809b86dde933 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/uncore-power.json @@ -1,147 +1,185 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 0= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 1= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 2= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 3= ", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_MCP_PROCHOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C0. This event can be used in conjunction with edge detect to coun= t C0 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C2E. This event can be used in conjunction with edge detect to cou= nt C2E entrances (or exits using invert). Residency events do not include = transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C3. This event can be used in conjunction with edge detect to coun= t C3 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C6. This event can be used in conjunction with edge detect to coun= t C6 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0x40", @@ -149,8 +187,10 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0x80", @@ -158,8 +198,10 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0xc0", @@ -167,32 +209,40 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that we are in I= nternal PROCHOT mode. This mode is triggered when a sensor on the die dete= rmines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json index 73feadaf7674..ad33fff57c03 100644 --- a/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/cascadelakex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -162,6 +182,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -171,6 +192,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -179,6 +201,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -187,6 +210,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake microarchitecture.", @@ -211,6 +237,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -219,6 +246,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 519842e52fcb..220570cb2e66 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -5,7 +5,7 @@ GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core GenuineIntel-6-(3D|47),v29,broadwell,core GenuineIntel-6-56,v11,broadwellde,core GenuineIntel-6-4F,v22,broadwellx,core -GenuineIntel-6-55-[56789ABCDEF],v1.21,cascadelakex,core +GenuineIntel-6-55-[56789ABCDEF],v1.22,cascadelakex,core GenuineIntel-6-9[6C],v1.04,elkhartlake,core GenuineIntel-6-CF,v1.06,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B9E5381B8 for ; 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Thu, 20 Jun 2024 11:19:31 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:22 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-9-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 08/37] perf vendor events: Update elkhartlake events From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.04 to v1.05. Bring in event updates from: https://github.com/intel/perfmon/commit/fb91e1851ca40a5b443e2c3cd79bc7fc34c= 8237e The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/elkhartlake/cache.json | 101 ++++++++++++++++++ .../arch/x86/elkhartlake/counter.json | 7 ++ .../arch/x86/elkhartlake/floating-point.json | 3 + .../arch/x86/elkhartlake/frontend.json | 9 ++ .../arch/x86/elkhartlake/memory.json | 40 +++++++ .../arch/x86/elkhartlake/other.json | 61 +++++++++++ .../arch/x86/elkhartlake/pipeline.json | 60 +++++++++++ .../arch/x86/elkhartlake/virtual-memory.json | 31 ++++++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 9 files changed, 313 insertions(+), 1 deletion(-) create mode 100644 tools/perf/pmu-events/arch/x86/elkhartlake/counter.json diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/cache.json index c6be60584522..7882dca9d5e1 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", "PublicDescription": "Counts the number of L1D cacheline (dirty) e= victions caused by load misses, stores, and prefetches. Does not count evi= ctions or dirty writebacks caused by snoops. Does not count a replacement = unless a (dirty) line was written back.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ANY", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the total number of L2 Cache accesses.= Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts the total number of L2 Cache Accesses= , includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/= L2 Prefetches only. Counts on a per core basis.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a hit. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.HIT", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a hit from a front door request only (does not include rejects = or recycles), Counts on a per core basis.", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a miss. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a miss from a front door request only (does not include rejects= or recycles). Counts on a per core basis.", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that m= iss the L2 and get rejected. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.REJECTS", "PublicDescription": "Counts the number of L2 Cache accesses that = miss the L2 and get BBL reject short and long rejects (includes those coun= ted in L2_reject_XQ.any). Counts on a per core basis.", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -94,6 +106,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", "SampleAfterValue": "200003", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", "SampleAfterValue": "200003", @@ -116,6 +131,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "SampleAfterValue": "200003", @@ -123,6 +139,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", @@ -131,6 +148,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a store buffer being full.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", "SampleAfterValue": "200003", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -147,6 +166,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache, in which a snoop was required and modified data was for= warded from another core or module.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", @@ -156,6 +176,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -165,6 +186,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -183,6 +206,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", @@ -201,6 +226,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL", @@ -211,6 +237,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -231,6 +259,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", @@ -249,6 +279,7 @@ }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -258,6 +289,7 @@ }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -267,6 +299,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -276,6 +309,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -285,6 +319,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -303,6 +339,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -312,6 +349,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -321,6 +359,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -330,6 +369,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -339,6 +379,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -348,6 +389,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -357,6 +399,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -366,6 +409,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -375,6 +419,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -384,6 +429,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -393,6 +439,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -402,6 +449,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -411,6 +459,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -420,6 +469,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -429,6 +479,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -438,6 +489,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", @@ -448,6 +500,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", @@ -458,6 +511,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", @@ -468,6 +522,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -478,6 +533,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", @@ -488,6 +544,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", @@ -498,6 +555,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -507,6 +565,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -516,6 +575,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -525,6 +585,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -543,6 +605,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -552,6 +615,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -561,6 +625,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -570,6 +635,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -579,6 +645,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -588,6 +655,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -597,6 +665,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -606,6 +675,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -615,6 +685,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +695,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -633,6 +705,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -642,6 +715,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -651,6 +725,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -660,6 +735,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -669,6 +745,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -678,6 +755,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -687,6 +765,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -696,6 +775,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -705,6 +785,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +795,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -723,6 +805,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -732,6 +815,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -741,6 +825,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -750,6 +835,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -759,6 +845,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -768,6 +855,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -777,6 +865,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -786,6 +875,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -795,6 +885,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -804,6 +895,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -813,6 +905,7 @@ }, { "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -822,6 +915,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -831,6 +925,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -840,6 +935,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -849,6 +945,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -858,6 +955,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -867,6 +965,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +975,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -885,6 +985,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/counter.json b/tool= s/perf/pmu-events/arch/x86/elkhartlake/counter.json new file mode 100644 index 000000000000..aa443347b694 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json= b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json index 88522244b760..79a4beba4b78 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.FPDIV", "PublicDescription": "Counts the number of cycles the floating poi= nt divider is busy. Does not imply a stall waiting for the divider.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json b/too= ls/perf/pmu-events/arch/x86/elkhartlake/frontend.json index 5ba998e06592..6d131ed90242 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a condit= ional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to an indir= ect branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.INDIRECT", "SampleAfterValue": "200003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a return= branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.UNCOND", "SampleAfterValue": "200003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of times a decode restricti= on reduces the decode throughput due to wrong instruction length prediction= .", + "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "SampleAfterValue": "200003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", @@ -52,6 +59,7 @@ }, { "BriefDescription": "Counts the number of instruction cache hits.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts the number of instruction cache misses= .", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json b/tools= /perf/pmu-events/arch/x86/elkhartlake/memory.json index c02eb0e836ad..34306ec24e9b 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of misaligned load uops tha= t are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of misaligned store uops th= at are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", @@ -106,6 +118,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json b/tools/= perf/pmu-events/arch/x86/elkhartlake/other.json index fefbc383b840..57613207f7ad 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/other.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.SELF_LOCKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EdgeDetect": "1", "EventCode": "0x63", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock issued by other cores.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.BLOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock issued by other cores. Counts on a per c= ore basis.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.BLOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", @@ -25,6 +28,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.LOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock it issued.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.LOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock it issued. Counts on a per core basis.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of bus locks a core issued = its self (e.g. lock to UC or Split Lock) and does not include cache locks.", + "Counter": "0,1,2,3", "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.SELF_LOCKS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_DRAM_HIT", @@ -57,6 +64,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_L2_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_L2_HIT", @@ -65,6 +73,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_LLC_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_LLC_HIT", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.MASKED", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= there are pending interrupts while interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of hardware interrupts rece= ived by the processor.", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.RECEIVED", "SampleAfterValue": "203", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Counts all code reads that have any type of r= esponse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -141,6 +158,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.OUTSTANDING", "MSRIndex": "0x1a6", @@ -150,6 +168,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -159,6 +178,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -168,6 +188,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -177,6 +198,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -186,6 +208,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -213,6 +238,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", @@ -223,6 +249,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", @@ -233,6 +260,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", @@ -243,6 +271,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", @@ -253,6 +282,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +292,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +302,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +312,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -289,6 +322,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +332,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +342,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +352,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -325,6 +362,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +372,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -343,6 +382,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +392,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +402,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +412,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +422,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +432,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +442,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -406,6 +452,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +462,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +472,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +482,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +492,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +502,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +512,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +522,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +532,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.OUTSTANDING", "MSRIndex": "0x1a6", @@ -487,6 +542,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +552,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +572,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +582,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -532,6 +592,7 @@ }, { "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json b/too= ls/perf/pmu-events/arch/x86/elkhartlake/pipeline.json index c483c0838e08..e4e7902c1162 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "Counts the total number of BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", @@ -142,6 +160,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -165,6 +186,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", @@ -172,6 +194,7 @@ }, { "BriefDescription": "Counts the number of cycles the integer divid= er is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", "PublicDescription": "Counts the number of cycles the integer divi= der is busy. Does not imply a stall waiting for the divider.", @@ -180,6 +203,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", @@ -188,6 +212,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed.", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -196,6 +221,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "1", @@ -204,6 +230,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked for any of the following reasons: DTLB miss, address alias, store f= orward or data unknown (includes memory disambiguation blocks and ESP consu= ming load blocks).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL", "PEBS": "1", @@ -212,6 +239,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", @@ -220,6 +248,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "1", @@ -228,12 +257,14 @@ }, { "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", "SampleAfterValue": "20003" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -241,6 +272,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -248,6 +280,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -255,6 +288,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", @@ -263,6 +297,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -270,6 +305,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -277,6 +313,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -284,6 +321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", @@ -292,12 +330,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -305,6 +345,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -312,6 +353,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -319,6 +361,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -326,6 +369,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -333,6 +377,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -340,6 +385,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", @@ -348,12 +394,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", @@ -362,6 +410,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", @@ -370,6 +419,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -377,6 +427,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -384,6 +435,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", @@ -392,6 +444,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -399,6 +452,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -406,6 +460,7 @@ }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", @@ -413,6 +468,7 @@ }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -420,6 +476,7 @@ }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -427,6 +484,7 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", @@ -435,6 +493,7 @@ }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", @@ -444,6 +503,7 @@ }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json index cabe29e70e79..f9a6caed8776 100644 --- a/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/elkhartlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of page walks due to loads = that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccount for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for demand loads every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for demand loads every cycle. A page walk i= s outstanding from start till PMH becomes idle again (ready to serve next w= alk). Includes EPT-walk intervals.", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Counts the number of page walks due to stores= that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", @@ -85,6 +96,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -101,6 +114,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_HIT", "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", @@ -117,6 +132,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_MISS", "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", @@ -125,6 +141,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_HIT", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", @@ -133,6 +150,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_MISS", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", @@ -149,6 +168,7 @@ }, { "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.FILLS", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -164,6 +185,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -171,6 +193,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -179,6 +202,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", @@ -187,6 +211,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -195,6 +220,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -203,6 +229,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for instruction fetches every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", @@ -211,6 +238,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked due to a first level TLB miss.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DTLB_MISS", "PEBS": "1", @@ -219,6 +247,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= missed in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", @@ -228,6 +257,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the second Level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Counts the number of store uops retired that = miss in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 220570cb2e66..2da7a845784a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -6,7 +6,7 @@ GenuineIntel-6-(3D|47),v29,broadwell,core GenuineIntel-6-56,v11,broadwellde,core GenuineIntel-6-4F,v22,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.22,cascadelakex,core -GenuineIntel-6-9[6C],v1.04,elkhartlake,core +GenuineIntel-6-9[6C],v1.05,elkhartlake,core GenuineIntel-6-CF,v1.06,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:23 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A4FA1B29C6 for ; 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Thu, 20 Jun 2024 11:19:34 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:23 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-10-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 09/37] perf vendor events: Add/update emeraldrapids events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.06 to v1.09. Add TMA metrics v4.8. Bring in the event updates v1.09: https://github.com/intel/perfmon/commit/3fd5892bb4aece9c1e5c17630570d046283= 8e85d v1.08: https://github.com/intel/perfmon/commit/54525c4508f4a1ce4a8b854aa808a4ee2fb= 5930b The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 New events are: EXE_ACTIVITY.2_3_PORTS_UTIL, ICACHE_DATA.STALL_PERIODS, L2_TRANS.L2_WB, MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024, OFFCORE_REQUESTS.DEMAND_CODE_RD, OFFCORE_REQUESTS.DEMAND_RFO, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD, OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD, RS.EMPTY_RESOURCE, SW_PREFETCH_ACCESS.ANY, UNC_IIO_BANDWIDTH_OUT.PART[0-7]_FREERUN, UOPS_ISSUED.CYCLES. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/emeraldrapids/cache.json | 159 +- .../arch/x86/emeraldrapids/counter.json | 82 + .../arch/x86/emeraldrapids/emr-metrics.json | 2186 +++++++++++++++++ .../x86/emeraldrapids/floating-point.json | 28 + .../arch/x86/emeraldrapids/frontend.json | 50 + .../arch/x86/emeraldrapids/memory.json | 50 + .../arch/x86/emeraldrapids/metricgroups.json | 137 ++ .../arch/x86/emeraldrapids/other.json | 43 + .../arch/x86/emeraldrapids/pipeline.json | 133 + .../arch/x86/emeraldrapids/uncore-cache.json | 1288 ++++++++++ .../arch/x86/emeraldrapids/uncore-cxl.json | 110 + .../emeraldrapids/uncore-interconnect.json | 1427 +++++++++++ .../arch/x86/emeraldrapids/uncore-io.json | 743 ++++++ .../arch/x86/emeraldrapids/uncore-memory.json | 742 ++++++ .../arch/x86/emeraldrapids/uncore-power.json | 49 + .../x86/emeraldrapids/virtual-memory.json | 20 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 17 files changed, 7247 insertions(+), 2 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/counter.js= on create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metric= s.json create mode 100644 tools/perf/pmu-events/arch/x86/emeraldrapids/metricgrou= ps.json diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tool= s/perf/pmu-events/arch/x86/emeraldrapids/cache.json index ab09bd9fb409..21d5d96b8a6d 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.HWPF_MISS", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -34,6 +38,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L1D_PEND_MISS.L2_STALLS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALLS", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -67,6 +75,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -74,14 +83,17 @@ "UMask": "0x1f" }, { - "BriefDescription": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.NON_SILENT", + "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", @@ -98,6 +111,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_RQSTS.REFERENCES]", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_RQSTS.MISS]", @@ -114,6 +129,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -122,6 +138,7 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", @@ -130,6 +147,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts demand requests to L2 cache.", @@ -146,6 +165,7 @@ }, { "BriefDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_HWPF", "SampleAfterValue": "200003", @@ -153,6 +173,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -161,6 +182,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -169,6 +191,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -177,6 +200,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -185,6 +209,7 @@ }, { "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", @@ -193,6 +218,7 @@ }, { "BriefDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.HWPF_MISS", "SampleAfterValue": "200003", @@ -200,6 +226,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_REQUEST.MISS]", @@ -208,6 +235,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_REQUEST.ALL]", @@ -216,6 +244,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -224,6 +253,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -232,6 +262,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -240,14 +271,25 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", "SampleAfterValue": "200003", "UMask": "0x28" }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -256,6 +298,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -264,6 +307,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -274,6 +318,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -284,6 +329,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -294,6 +340,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -304,6 +351,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -314,6 +362,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -324,6 +373,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -334,6 +384,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -344,6 +395,7 @@ }, { "BriefDescription": "Completed demand load uops that miss the L1 d= -cache.", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "PublicDescription": "Number of completed demand load requests tha= t missed the L1 data cache including shadow misses (FB hits, merge to an on= going L1D miss)", @@ -352,6 +404,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -362,6 +415,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -372,6 +426,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -382,6 +437,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -392,6 +448,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -402,6 +459,7 @@ }, { "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -411,6 +469,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -421,6 +480,7 @@ }, { "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -430,6 +490,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -440,6 +501,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -450,6 +512,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -460,6 +523,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -470,6 +534,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -480,6 +545,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -490,6 +556,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -500,6 +567,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -510,6 +578,7 @@ }, { "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "MEM_STORE_RETIRED.L2_HIT", "SampleAfterValue": "200003", @@ -517,6 +586,7 @@ }, { "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe5", "EventName": "MEM_UOP_RETIRED.ANY", "PublicDescription": "Number of retired micro-operations (uops) fo= r load or store memory accesses", @@ -525,6 +595,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit in the L3 or were snooped from another co= re's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +605,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that resulted in a snoop hit a modified line in an= other core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -543,6 +615,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a modified line in a distant L3 Cache or = were snooped from a distant core's L1/L2 caches on this socket when the sys= tem is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -552,6 +625,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that either hit a non-modified line in a distant L= 3 Cache or were snooped from a distant core's L1/L2 caches on this socket w= hen the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -561,6 +635,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 o= r were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -570,6 +645,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit a modified line in another core's caches which forwarded the data.= ", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -579,6 +655,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -588,6 +665,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another core's caches which forwarded the unmodified data to th= e requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -597,6 +675,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit a modified line in another c= ore's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -606,6 +685,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit in another core's caches whi= ch forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -615,6 +695,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a modified = line in a distant L3 Cache or were snooped from a distant core's L1/L2 cach= es on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +705,7 @@ }, { "BriefDescription": "Counts demand data reads that either hit a no= n-modified line in a distant L3 Cache or were snooped from a distant core's= L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) m= ode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -633,6 +715,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit in= the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -642,6 +725,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that result= ed in a snoop hit a modified line in another core's caches which forwarded = the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -651,6 +735,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = modified line in a distant L3 Cache or were snooped from a distant core's L= 1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mod= e.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -660,6 +745,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that either= hit a non-modified line in a distant L3 Cache or were snooped from a dista= nt core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA c= luster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -669,6 +755,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit in the L3 or were snooped from another core's caches on the same sock= et.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -678,6 +765,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit in the L3 or were snooped from another core's caches on the sa= me socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -687,6 +775,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit a modified line in another core's caches w= hich forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -696,6 +785,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop that hit in another core, which did not forwar= d the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -705,6 +795,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit in another core's caches which forwarded t= he unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +805,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop was sent= and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -723,6 +815,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit a mo= dified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -732,6 +825,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit in a= nother core's caches which forwarded the unmodified data to the requesting = core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -741,6 +835,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit a modified line in a distant L3 Cache or were snooped from a d= istant core's L1/L2 caches on this socket when the system is in SNC (sub-NU= MA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -750,6 +845,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that either hit a non-modified line in a distant L3 Cache or were snoop= ed from a distant core's L1/L2 caches on this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -759,6 +855,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO), hard= ware prefetch RFOs (which bring data to L2), and software prefetches for ex= clusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 = or snoop filter.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", "MSRIndex": "0x1a6,0x1a7", @@ -768,6 +865,7 @@ }, { "BriefDescription": "Counts streaming stores that hit in the L3 or= were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -777,6 +875,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "SampleAfterValue": "100003", @@ -784,22 +883,43 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", "SampleAfterValue": "100003", "UMask": "0x8" }, + { + "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, { "BriefDescription": "This event is deprecated. Refer to new event = OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -808,14 +928,26 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA= _RD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "SampleAfterValue": "1000003", "UMask": "0x8" }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, { "BriefDescription": "Cycles where at least 1 outstanding demand da= ta read request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -824,6 +956,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMA= ND_RFO", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -832,13 +965,24 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "SampleAfterValue": "1000003", "UMask": "0x8" }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -847,14 +991,24 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", "SampleAfterValue": "100003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -863,6 +1017,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -871,6 +1026,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -879,6 +1035,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json b/to= ols/perf/pmu-events/arch/x86/emeraldrapids/counter.json new file mode 100644 index 000000000000..088d5954747c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/counter.json @@ -0,0 +1,82 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M3UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CXLCM", + "CountersNumFixed": "0", + "CountersNumGeneric": "8" + }, + { + "Unit": "CXLDP", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "MCHBM", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2HBM", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "MDF", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json = b/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json new file mode 100644 index 000000000000..ee288099a8d3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/emr-metrics.json @@ -0,0 +1,2186 @@ +[ + { + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C2 residency percent per package", + "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C2_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore frequency per die [GHZ]", + "MetricExpr": "tma_info_system_socket_clks / #num_dies / duration_= time / 1e9", + "MetricGroup": "SoC", + "MetricName": "UNCORE_FREQ" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC = * #SYSTEM_TSC_FREQ / 1e9", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "tma_info_system_cpus_utilized", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte page sizes) caused by demand data loads to the total number of = completed instructions. This implies it missed in the Data Translation Look= aside Buffer (DTLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "dtlb_2nd_level_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data loads to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricName": "dtlb_2nd_level_store_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic controller (IIO) of IO reads that are initiated by end device controlle= rs that are requesting memory from the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e= 6 / duration_time", + "MetricName": "iio_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic controller (IIO) of IO writes that are initiated by end device controll= ers that are writing memory to the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1= e6 / duration_time", + "MetricName": "iio_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / durati= on_time", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the local CPU socket.= ", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / = duration_time", + "MetricName": "io_bandwidth_read_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from a remote CPU socket.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 /= duration_time", + "MetricName": "io_bandwidth_read_remote", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.= IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the local CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_IN= SERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to a remote CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_I= NSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_remote", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Percentage of inbound full cacheline writes i= nitiated by end device controllers that miss the L3 cache.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSE= RTS.IO_ITOM", + "MetricName": "io_percent_of_inbound_full_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound partial cacheline write= s initiated by end device controllers that miss the L3 cache.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR + UNC_CH= A_TOR_INSERTS.IO_MISS_RFO) / (UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR + UNC_CH= A_TOR_INSERTS.IO_RFO)", + "MetricName": "io_percent_of_inbound_partial_writes_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of inbound reads initiated by end = device controllers that miss the L3 cache.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR / UNC_CHA_TOR_= INSERTS.IO_PCIRDCUR", + "MetricName": "io_percent_of_inbound_reads_that_miss_l3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricName": "itlb_2nd_level_large_page_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total = number of completed instructions. This implies it missed in the Instruction= Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "itlb_2nd_level_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by a code fetch to the total number of completed in= structions. This implies it missed in the ITLB (Instruction TLB) and furthe= r levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "L2_RQSTS.ALL_CODE_RD / INST_RETIRED.ANY", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L1 data c= ache (includes data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L1D.REPLACEMENT / INST_RETIRED.ANY", + "MetricName": "l1d_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read request missing = L2 cache to the total number of completed instructions", + "MetricExpr": "L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_code_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "L2_LINES_IN.ALL / INST_RETIRED.ANY", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD / INST_RETIRED.ANY", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA + UNC_CHA_= TOR_INSERTS.IA_MISS_DRD + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF) / INST_RETI= RED.ANY", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) in nano seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_= TOR_INSERTS.IA_MISS_DRD) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_TOR_= OCCUPANCY.IA_MISS_DRD) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to local memory in nano= seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL / UN= C_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL) / (UNC_CHA_CLOCKTICKS / (source_count(= UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_latency_for_local_request= s", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to remote memory in nan= o seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE / U= NC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE) / (UNC_CHA_CLOCKTICKS / (source_coun= t(UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE) * #num_packages)) * duration_ti= me", + "MetricName": "llc_demand_data_read_miss_latency_for_remote_reques= ts", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to DRAM in nano seconds= ", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_= CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_to_dram_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) addressed to Intel(R) Optane(TM) = Persistent Memory(PMEM) in nano seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_= CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_to_pmem_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_= time", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to remote memory.", + "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duratio= n_time", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "The ratio of number of completed memory load = instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricName": "loads_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "UNC_M_CAS_COUNT.RD * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) * 64 / 1e= 6 / duration_time", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "UNC_M_CAS_COUNT.WR * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Memory write bandwidth (MB/sec) caused by dir= ectory updates; includes DDR and Intel(R) Optane(TM) Persistent Memory(PMEM= ).", + "MetricExpr": "(UNC_CHA_DIR_UPDATE.HA + UNC_CHA_DIR_UPDATE.TOR + U= NC_M2M_DIRECTORY_UPDATE.ANY) * 64 / 1e6 / duration_time", + "MetricName": "memory_extra_write_bw_due_to_directory_updates", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL + UNC_CHA_TO= R_INSERTS.IA_MISS_DRD_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL = + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_= DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE + UNC_CHA_T= OR_INSERTS.IA_MISS_DRD_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCA= L + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL + UNC_CHA_TOR_INSERTS.IA_MIS= S_DRD_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE)", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from decoded instruction cache= (decoded stream buffer or DSB) as a percent of total uops delivered to Ins= truction Decode Queue", + "MetricExpr": "IDQ.DSB_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.= MS_UOPS + LSD.UOPS)", + "MetricName": "percent_uops_delivered_from_decoded_icache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from legacy decode pipeline (M= icro-instruction Translation Engine or MITE) as a percent of total uops del= ivered to Instruction Decode Queue", + "MetricExpr": "IDQ.MITE_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ= .MS_UOPS + LSD.UOPS)", + "MetricName": "percent_uops_delivered_from_legacy_decode_pipeline", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uops delivered from microcode sequencer (MS) = as a percent of total uops delivered to Instruction Decode Queue", + "MetricExpr": "IDQ.MS_UOPS / (IDQ.DSB_UOPS + IDQ.MITE_UOPS + IDQ.M= S_UOPS + LSD.UOPS)", + "MetricName": "percent_uops_delivered_from_microcode_sequencer", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory read bandwidth (MB/sec)", + "MetricExpr": "UNC_M_PMM_RPQ_INSERTS * 64 / 1e6 / duration_time", + "MetricName": "pmem_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_PMM_RPQ_INSERTS + UNC_M_PMM_WPQ_INSERTS) * 6= 4 / 1e6 / duration_time", + "MetricName": "pmem_memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Optane(TM) Persistent Memory(PMEM) m= emory write bandwidth (MB/sec)", + "MetricExpr": "UNC_M_PMM_WPQ_INSERTS * 64 / 1e6 / duration_time", + "MetricName": "pmem_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Percentage of cycles spent in System Manageme= nt Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0= else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" + }, + { + "BriefDescription": "The ratio of number of completed memory store= instructions to the total number completed instructions", + "MetricExpr": "MEM_INST_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricName": "stores_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution ports for ALU operations.", + "MetricExpr": "(UOPS_DISPATCHED.PORT_0 + UOPS_DISPATCHED.PORT_1 + = UOPS_DISPATCHED.PORT_5_11 + UOPS_DISPATCHED.PORT_6) / (5 * tma_info_core_co= re_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_alu_op_utilization", + "MetricThreshold": "tma_alu_op_utilization > 0.4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles wher= e the Advanced Matrix eXtensions (AMX) execution engine was busy with tile = (arithmetic) operations", + "MetricExpr": "EXE.AMX_BUSY / tma_info_core_core_clks", + "MetricGroup": "BvCB;Compute;HPC;Server;TopdownL3;tma_L3_group;tma= _core_bound_group", + "MetricName": "tma_amx_busy", + "MetricThreshold": "tma_amx_busy > 0.5 & (tma_core_bound > 0.1 & t= ma_backend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", + "MetricExpr": "78 * ASSISTS.ANY / tma_info_thread_slots", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", + "MetricName": "tma_assists", + "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops as a result of handing SSE to AVX* or AVX* to SSE transitio= n Assists.", + "MetricExpr": "63 * ASSISTS.SSE_AVX_MIX / tma_info_thread_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_avx_assists", + "MetricThreshold": "tma_avx_assists > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_inf= o_thread_slots", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1;Default", + "PublicDescription": "This category represents fraction of slots w= here no uops are being delivered due to a lack of required resources for ac= cepting new uops in the Backend. Backend is the portion of the processor co= re where the out-of-order scheduler dispatches ready uops into their respec= tive execution units; and once completed these uops get retired according t= o program order. For example; stalls due to data-cache misses or stalls due= to the divider unit being overloaded are both categorized under Backend Bo= und. Backend Bound is further divided into two main categories: Memory Boun= d and Core Bound. Sample with: TOPDOWN.BACKEND_BOUND_SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wa= sted due to incorrect speculations", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "max(1 - (tma_frontend_bound + tma_backend_bound + t= ma_retiring), 0)", + "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1;Default", + "PublicDescription": "This category represents fraction of slots w= asted due to incorrect speculations. This include slots used to issue uops = that do not eventually get retired and slots for which the issue-pipeline w= as blocked due to recovery from earlier incorrect speculation. For example;= wasted work due to miss-predicted branches are categorized under Bad Specu= lation category. Incorrect data speculation followed by Memory Ordering Nuk= es is another example.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tm= a_info_thread_slots", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;Default;TmaL2;TopdownL2= ;tma_L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Branch Misprediction. These slots are either wasted= by uops fetched from an incorrectly speculated program path; or stalls whe= n the out-of-order part of the machine needs to recover its state from a sp= eculative path. Sample with: TOPDOWN.BR_MISPREDICT_SLOTS. Related metrics: = tma_info_bad_spec_branch_misprediction_cost, tma_info_bottleneck_mispredict= ions, tma_mispredicts_resteers", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers", + "MetricExpr": "INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clk= s + tma_unknown_branches", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group", + "MetricName": "tma_branch_resteers", + "MetricThreshold": "tma_branch_resteers > 0.05 & (tma_fetch_latenc= y > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers. Branch Resteers estimates the Fro= ntend delay in fetching operations from corrected path; following all sorts= of miss-predicted branches. For example; branchy code with lots of miss-pr= edictions might get categorized under Branch Resteers. Note the value of th= is node may overlap with its siblings. Sample with: BR_MISP_RETIRED.ALL_BRA= NCHES", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due staying in C0.1 power-performance optimized state (Fas= ter wakeup time; Smaller power savings).", + "MetricExpr": "CPU_CLK_UNHALTED.C01 / tma_info_thread_clks", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_oper= ation_group", + "MetricName": "tma_c01_wait", + "MetricThreshold": "tma_c01_wait > 0.05 & (tma_serializing_operati= on > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due staying in C0.2 power-performance optimized state (Slo= wer wakeup time; Larger power savings).", + "MetricExpr": "CPU_CLK_UNHALTED.C02 / tma_info_thread_clks", + "MetricGroup": "C0Wait;TopdownL4;tma_L4_group;tma_serializing_oper= ation_group", + "MetricName": "tma_c02_wait", + "MetricThreshold": "tma_c02_wait > 0.05 & (tma_serializing_operati= on > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU retired uops originated from CISC (complex instruction set computer) in= struction", + "MetricExpr": "max(0, tma_microcode_sequencer - tma_assists)", + "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.1 & (tma_microcode_sequencer > 0.= 05 & tma_heavy_operations > 0.1)", + "PublicDescription": "This metric estimates fraction of cycles the= CPU retired uops originated from CISC (complex instruction set computer) i= nstruction. A CISC instruction has multiple uops that are required to perfo= rm the instruction's functionality as in the case of read-modify-write as a= n example. Since these instructions require multiple uops they may or may n= ot imply sub-optimal use of machine resources.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Machine Clears", + "MetricExpr": "(1 - tma_branch_mispredicts / tma_bad_speculation) = * INT_MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", + "MetricGroup": "BadSpec;MachineClears;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueMC", + "MetricName": "tma_clears_resteers", + "MetricThreshold": "tma_clears_resteers > 0.05 & (tma_branch_reste= ers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Machine Clears. Sam= ple with: INT_MISC.CLEAR_RESTEER_CYCLES. Related metrics: tma_l1_bound, tma= _machine_clears, tma_microcode_sequencer, tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", + "MetricExpr": "(76.6 * tma_info_system_core_frequency * (MEM_LOAD_= L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMA= ND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD= ))) + 74.6 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_= MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_= info_thread_clks", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", + "MetricName": "tma_contested_accesses", + "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related m= etrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote= _cache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e Core non-memory issues were of a bottleneck", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "max(0, tma_backend_bound - tma_memory_bound)", + "MetricGroup": "Backend;Compute;Default;TmaL2;TopdownL2;tma_L2_gro= up;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.2= ", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots whe= re Core non-memory issues were of a bottleneck. Shortage in hardware compu= te resources; or dependencies in software's instructions are both categoriz= ed under Core Bound. Hence it may indicate the machine ran out of an out-of= -order resource; certain execution units are overloaded or dependencies in = program's data- or instruction-flow are limiting the performance (e.g. FP-c= hained long-latency arithmetic operations).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", + "MetricExpr": "74.6 * tma_info_system_core_frequency * (MEM_LOAD_L= 3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEM= AND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR= .DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT= / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", + "MetricName": "tma_data_sharing", + "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re decoder-0 was the only active decoder", + "MetricExpr": "(cpu@INST_DECODED.DECODERS\\,cmask\\=3D1@ - cpu@INS= T_DECODED.DECODERS\\,cmask\\=3D2@) / tma_info_core_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL4;tma_L4_group;tma_issueD0= ;tma_mite_group", + "MetricName": "tma_decoder0_alone", + "MetricThreshold": "tma_decoder0_alone > 0.1 & (tma_mite > 0.1 & t= ma_fetch_bandwidth > 0.2)", + "PublicDescription": "This metric represents fraction of cycles wh= ere decoder-0 was the only active decoder. Related metrics: tma_few_uops_in= structions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", + "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_thread_clks", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_divider", + "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled on accesses to external memory (DRAM) by loads", + "MetricExpr": "( MEMORY_ACTIVITY.STALLS_L3_MISS / tma_info_thread_= clks )", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", + "MetricName": "tma_dram_bound", + "MetricThreshold": "tma_dram_bound > 0.1 & (tma_memory_bound > 0.2= & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was = stalled on accesses to external memory (DRAM) by loads. Better caching can = improve the latency and increase performance. Sample with: MEM_LOAD_RETIRED= .L3_MISS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to DSB (decoded uop cache) fetch pipe= line", + "MetricExpr": "(IDQ.DSB_CYCLES_ANY - IDQ.DSB_CYCLES_OK) / tma_info= _core_core_clks / 2", + "MetricGroup": "DSB;FetchBW;TopdownL3;tma_L3_group;tma_fetch_bandw= idth_group", + "MetricName": "tma_dsb", + "MetricThreshold": "tma_dsb > 0.15 & tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to DSB (decoded uop cache) fetch pip= eline. For example; inefficient utilization of the DSB cache structure or = bank conflict when reading from it; are categorized here.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to switches from DSB to MITE pipelines", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / tma_info_thread_= clks", + "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", + "MetricName": "tma_dsb_switches", + "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", + "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMOR= Y_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", + "MetricName": "tma_dtlb_load", + "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", + "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", + "MetricName": "tma_dtlb_store", + "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", + "MetricExpr": "81 * tma_info_system_core_frequency * OCR.DEMAND_RF= O.L3_HIT.SNOOP_HITM / tma_info_thread_clks", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", + "MetricName": "tma_false_sharing", + "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", + "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricName": "tma_fb_full", + "MetricThreshold": "tma_fb_full > 0.3", + "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend bandwidth issues", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "max(0, tma_frontend_bound - tma_fetch_latency)", + "MetricGroup": "Default;FetchBW;Frontend;TmaL2;TopdownL2;tma_L2_gr= oup;tma_frontend_bound_group;tma_issueFB", + "MetricName": "tma_fetch_bandwidth", + "MetricThreshold": "tma_fetch_bandwidth > 0.2", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was stalled due to Frontend latency issues", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "topdown\\-fetch\\-lat / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.U= OP_DROPPING / tma_info_thread_slots", + "MetricGroup": "Default;Frontend;TmaL2;TopdownL2;tma_L2_group;tma_= frontend_bound_group", + "MetricName": "tma_fetch_latency", + "MetricThreshold": "tma_fetch_latency > 0.1 & tma_frontend_bound >= 0.15", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend latency issues. For example; instruction-= cache misses; iTLB misses or fetch stalls after a branch misprediction are = categorized under Frontend Latency. In such cases; the Frontend eventually = delivers no uops for some period. Sample with: FRONTEND_RETIRED.LATENCY_GE_= 16_PS;FRONTEND_RETIRED.LATENCY_GE_8_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", + "MetricExpr": "max(0, tma_heavy_operations - tma_microcode_sequenc= er)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;= tma_issueD0", + "MetricName": "tma_few_uops_instructions", + "MetricThreshold": "tma_few_uops_instructions > 0.05 & tma_heavy_o= perations > 0.1", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring instructions that that are decoder into two or up t= o ([SNB+] four; [ADL+] five) uops. This highly-correlates with the number o= f uops in such instructions. Related metrics: tma_decoder0_alone", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents overall arithmetic flo= ating-point (FP) operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_x87_use + tma_fp_scalar + tma_fp_vector", + "MetricGroup": "HPC;TopdownL3;tma_L3_group;tma_light_operations_gr= oup", + "MetricName": "tma_fp_arith", + "MetricThreshold": "tma_fp_arith > 0.2 & tma_light_operations > 0.= 6", + "PublicDescription": "This metric represents overall arithmetic fl= oating-point (FP) operations fraction the CPU has executed (retired). Note = this metric's value may exceed its parent due to use of \"Uops\" CountDomai= n and FMA double-counting.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Floating Point (FP) Assists", + "MetricExpr": "30 * ASSISTS.FP / tma_info_thread_slots", + "MetricGroup": "HPC;TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_fp_assists", + "MetricThreshold": "tma_fp_assists > 0.1", + "PublicDescription": "This metric roughly estimates fraction of sl= ots the CPU retired uops as a result of handing Floating Point (FP) Assists= . FP Assist may apply when working with very small floating point values (s= o-called Denormals).", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED2.SCALAR) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", + "MetricName": "tma_fp_scalar", + "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating= -point (FP) scalar uops fraction the CPU has retired. May overcount due to = FMA double counting. Related metrics: tma_fp_vector, tma_fp_vector_128b, tm= a_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vector_2= 56b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", + "MetricExpr": "(FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIR= ED2.VECTOR) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", + "MetricName": "tma_fp_vector", + "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", + "PublicDescription": "This metric approximates arithmetic floating= -point (FP) vector uops fraction the CPU has retired aggregated across all = vector widths. May overcount due to FMA double counting. Related metrics: t= ma_fp_scalar, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, t= ma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5= , tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 128-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.128B_PACKED_HALF= ) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", + "MetricName": "tma_fp_vector_128b", + "MetricThreshold": "tma_fp_vector_128b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 128-bit wide vectors. May overcount= due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector,= tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vecto= r_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_= 2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 256-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.256B_PACKED_HALF= ) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", + "MetricName": "tma_fp_vector_256b", + "MetricThreshold": "tma_fp_vector_256b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 256-bit wide vectors. May overcount= due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector,= tma_fp_vector_128b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_vecto= r_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_= 2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric approximates arithmetic FP vector= uops fraction the CPU has retired for 512-bit wide vectors", + "MetricExpr": "(FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE + FP_ARIT= H_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRED2.512B_PACKED_HALF= ) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;Flops;TopdownL5;tma_L5_group;tma_fp_vector= _group;tma_issue2P", + "MetricName": "tma_fp_vector_512b", + "MetricThreshold": "tma_fp_vector_512b > 0.1 & (tma_fp_vector > 0.= 1 & (tma_fp_arith > 0.2 & tma_light_operations > 0.6))", + "PublicDescription": "This metric approximates arithmetic FP vecto= r uops fraction the CPU has retired for 512-bit wide vectors. May overcount= due to FMA double counting. Related metrics: tma_fp_scalar, tma_fp_vector,= tma_fp_vector_128b, tma_fp_vector_256b, tma_int_vector_128b, tma_int_vecto= r_256b, tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_= 2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.15", + "MetricgroupNoGroup": "TopdownL1;Default", + "PublicDescription": "This category represents fraction of slots w= here the processor's Frontend undersupplies its Backend. Frontend denotes t= he first part of the processor core responsible to fetch operations that ar= e executed later on by the Backend part. Within the Frontend; a branch pred= ictor predicts the next address to fetch; cache-lines are fetched from the = memory subsystem; parsed into instructions; and lastly decoded into micro-o= perations (uops). Ideally the Frontend can issue Pipeline_Width uops every = cycle to the Backend. Frontend Bound denotes unutilized issue-slots when th= ere is no Backend stall; i.e. bubbles where Frontend delivered no uops whil= e Backend could have accepted them. For example; stalls due to instruction-= cache misses would be categorized under Frontend Bound. Sample with: FRONTE= ND_RETIRED.LATENCY_GE_4_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (= tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", + "MetricName": "tma_fused_instructions", + "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring heavy-weight operations -- instructions that require= two or more uops or micro-coded sequences", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "topdown\\-heavy\\-ops / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_in= fo_thread_slots", + "MetricGroup": "Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_re= tiring_group", + "MetricName": "tma_heavy_operations", + "MetricThreshold": "tma_heavy_operations > 0.1", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring heavy-weight operations -- instructions that requir= e two or more uops or micro-coded sequences. This highly-correlates with th= e uop length of these instructions/sequences. ([ICL+] Note this may overcou= nt due to approximation using indirect events; [ADL+] .)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", + "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Branch Misprediction Cost: Fraction of TMA sl= ots wasted per non-speculative branch misprediction (retired JEClear)", + "MetricExpr": "tma_info_bottleneck_mispredictions * tma_info_threa= d_slots / BR_MISP_RETIRED.ALL_BRANCHES / 100", + "MetricGroup": "Bad;BrMispredicts;tma_issueBM", + "MetricName": "tma_info_bad_spec_branch_misprediction_cost", + "PublicDescription": "Branch Misprediction Cost: Fraction of TMA s= lots wasted per non-speculative branch misprediction (retired JEClear). Rel= ated metrics: tma_branch_mispredicts, tma_info_bottleneck_mispredictions, t= ma_mispredicts_resteers" + }, + { + "BriefDescription": "Instructions per retired mispredicts for cond= itional non-taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_NTAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_cond_ntaken", + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_ntaken < 200" + }, + { + "BriefDescription": "Instructions per retired mispredicts for cond= itional taken branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_cond_taken", + "MetricThreshold": "tma_info_bad_spec_ipmisp_cond_taken < 200" + }, + { + "BriefDescription": "Instructions per retired mispredicts for indi= rect CALL or JMP branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_indirect", + "MetricThreshold": "tma_info_bad_spec_ipmisp_indirect < 1e3" + }, + { + "BriefDescription": "Instructions per retired mispredicts for retu= rn branches (lower number means higher occurrence rate).", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RET", + "MetricGroup": "Bad;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmisp_ret", + "MetricThreshold": "tma_info_bad_spec_ipmisp_ret < 500" + }, + { + "BriefDescription": "Number of Instructions per non-speculative Br= anch Misprediction (JEClear) (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;BadSpec;BrMispredicts", + "MetricName": "tma_info_bad_spec_ipmispredict", + "MetricThreshold": "tma_info_bad_spec_ipmispredict < 200" + }, + { + "BriefDescription": "Speculative to Retired ratio of all clears (c= overing mispredicts and nukes)", + "MetricExpr": "INT_MISC.CLEARS_COUNT / (BR_MISP_RETIRED.ALL_BRANCH= ES + MACHINE_CLEARS.COUNT)", + "MetricGroup": "BrMispredicts", + "MetricName": "tma_info_bad_spec_spec_clears_ratio" + }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t= _utilization > 0.5 else 0)", + "MetricGroup": "Cor;SMT", + "MetricName": "tma_info_botlnk_l0_core_bound_likely", + "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", + "MetricGroup": "DSBmiss;Fed;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_misses", + "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma= _branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses += tma_lcp + tma_ms_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;tma_issueFL", + "MetricName": "tma_info_botlnk_l2_ic_misses", + "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", + "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", + "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", + "MetricName": "tma_info_bottleneck_big_code", + "MetricThreshold": "tma_info_bottleneck_big_code > 20" + }, + { + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", + "MetricName": "tma_info_bottleneck_branching_overhead", + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", + "MetricExpr": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( t= ma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_boun= d ) ) * ( tma_mem_bandwidth / ( tma_mem_bandwidth + tma_mem_latency ) ) ) += ( tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_sq_full / ( tma_con= tested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full ) ) )= + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bound + tm= a_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_fb_full / ( tma_d= tlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_= split_loads + tma_fb_full ) ) ) )", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", + "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", + "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", + "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" + }, + { + "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", + "MetricExpr": "100 * ( ( tma_memory_bound * ( tma_dram_bound / ( t= ma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_boun= d ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) ) + (= tma_memory_bound * ( tma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l3_hit_latency / ( tm= a_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_full = ) ) ) + ( tma_memory_bound * tma_l2_bound / ( tma_l1_bound + tma_l2_bound += tma_l3_bound + tma_dram_bound + tma_store_bound ) ) + ( tma_memory_bound *= ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dra= m_bound + tma_store_bound ) ) * ( tma_store_latency / ( tma_store_latency += tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtlb_sto= re ) ) ) + ( tma_memory_bound * ( tma_l1_bound / ( tma_l1_bound + tma_l2_bo= und + tma_l3_bound + tma_dram_bound + tma_store_bound ) ) * ( tma_l1_hit_la= tency / ( tma_dtlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock= _latency + tma_split_loads + tma_fb_full ) ) ) )", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", + "MetricName": "tma_info_bottleneck_cache_memory_latency", + "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", + "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" + }, + { + "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", + "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_amx_busy= + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_c= ore_bound * tma_amx_busy / (tma_amx_busy + tma_divider + tma_ports_utilizat= ion + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization = / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_ope= ration)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utili= zed_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", + "MetricGroup": "BvCB;Cor;tma_issueComp", + "MetricName": "tma_info_bottleneck_compute_bound_est", + "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", + "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " + }, + { + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", + "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - I= NST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=3D1@) * (tma_fetc= h_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers += tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts)= / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches))= / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_m= isses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", + "MetricName": "tma_info_bottleneck_instruction_fetch_bw", + "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" + }, + { + "BriefDescription": "Total pipeline cost of irregular execution (e= .g", + "MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_R= ETIRED.MS\\,cmask\\=3D1@) * (tma_fetch_latency * (tma_ms_switches + tma_bra= nch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_= mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredi= cts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_swit= ches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + = 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredic= ts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_ot= her_nukes + tma_core_bound * (tma_serializing_operation + cpu@RS.EMPTY\\,um= ask\\=3D1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_amx_busy += tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_mic= rocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * = (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", + "MetricName": "tma_info_bottleneck_irregular_overhead", + "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", + "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" + }, + { + "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", + "MetricExpr": "100 * ( tma_memory_bound * ( tma_l1_bound / max( tm= a_memory_bound , ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bo= und + tma_store_bound ) ) ) * ( tma_dtlb_load / max( tma_l1_bound , ( tma_d= tlb_load + tma_store_fwd_blk + tma_l1_hit_latency + tma_lock_latency + tma_= split_loads + tma_fb_full ) ) ) + ( tma_memory_bound * ( tma_store_bound / = ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_b= ound ) ) * ( tma_dtlb_store / ( tma_store_latency + tma_false_sharing + tma= _split_stores + tma_streaming_stores + tma_dtlb_store ) ) ) )", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricName": "tma_info_bottleneck_memory_data_tlbs", + "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", + "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" + }, + { + "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", + "MetricExpr": "100 * ( tma_memory_bound * ( ( tma_dram_bound / ( t= ma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound + tma_store_boun= d ) ) * ( tma_mem_latency / ( tma_mem_bandwidth + tma_mem_latency ) ) * tma= _remote_cache / ( tma_local_mem + tma_remote_mem + tma_remote_cache ) + ( t= ma_l3_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_dram_bound= + tma_store_bound ) ) * ( tma_contested_accesses + tma_data_sharing ) / ( = tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq_ful= l ) + ( tma_store_bound / ( tma_l1_bound + tma_l2_bound + tma_l3_bound + tm= a_dram_bound + tma_store_bound ) ) * tma_false_sharing / ( ( tma_store_late= ncy + tma_false_sharing + tma_split_stores + tma_streaming_stores + tma_dtl= b_store ) - tma_store_latency ) ) + tma_machine_clears * ( 1 - tma_other_nu= kes / ( tma_other_nukes ) ) )", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", + "MetricName": "tma_info_bottleneck_memory_synchronization", + "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", + "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" + }, + { + "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", + "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", + "MetricName": "tma_info_bottleneck_mispredictions", + "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", + "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" + }, + { + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", + "MetricName": "tma_info_bottleneck_other_bottlenecks", + "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" + }, + { + "BriefDescription": "Fraction of branches that are CALL or RET", + "MetricExpr": "(BR_INST_RETIRED.NEAR_CALL + BR_INST_RETIRED.NEAR_R= ETURN) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_callret" + }, + { + "BriefDescription": "Fraction of branches that are non-taken condi= tionals", + "MetricExpr": "BR_INST_RETIRED.COND_NTAKEN / BR_INST_RETIRED.ALL_B= RANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_branches_cond_nt" + }, + { + "BriefDescription": "Fraction of branches that are taken condition= als", + "MetricExpr": "BR_INST_RETIRED.COND_TAKEN / BR_INST_RETIRED.ALL_BR= ANCHES", + "MetricGroup": "Bad;Branches;CodeGen;PGO", + "MetricName": "tma_info_branches_cond_tk" + }, + { + "BriefDescription": "Fraction of branches that are unconditional (= direct or indirect) jumps", + "MetricExpr": "(BR_INST_RETIRED.NEAR_TAKEN - BR_INST_RETIRED.COND_= TAKEN - 2 * BR_INST_RETIRED.NEAR_CALL) / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_jump" + }, + { + "BriefDescription": "Fraction of branches of other types (not indi= vidually covered by other metrics in Info.Branches group)", + "MetricExpr": "1 - (tma_info_branches_cond_nt + tma_info_branches_= cond_tk + tma_info_branches_callret + tma_info_branches_jump)", + "MetricGroup": "Bad;Branches", + "MetricName": "tma_info_branches_other_branches" + }, + { + "BriefDescription": "Core actual clocks when any Logical Processor= is active on the Physical Core", + "MetricExpr": "(CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else tma_i= nfo_thread_clks)", + "MetricGroup": "SMT", + "MetricName": "tma_info_core_core_clks" + }, + { + "BriefDescription": "Instructions Per Cycle across hyper-threads (= per physical core)", + "MetricExpr": "INST_RETIRED.ANY / tma_info_core_core_clks", + "MetricGroup": "Ret;SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_core_coreipc" + }, + { + "BriefDescription": "uops Executed per Cycle", + "MetricExpr": "UOPS_EXECUTED.THREAD / tma_info_thread_clks", + "MetricGroup": "Power", + "MetricName": "tma_info_core_epc" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_= INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 = * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS)= + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.51= 2B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / tma_inf= o_core_core_clks", + "MetricGroup": "Flops;Ret", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", + "MetricExpr": "(FP_ARITH_DISPATCHED.PORT_0 + FP_ARITH_DISPATCHED.P= ORT_1 + FP_ARITH_DISPATCHED.PORT_5) / (2 * tma_info_core_core_clks)", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_core_fp_arith_utilization", + "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per thread (logical-processor)", + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,c= mask\\=3D1@", + "MetricGroup": "Backend;Cor;Pipeline;PortsUtil", + "MetricName": "tma_info_core_ilp" + }, + { + "BriefDescription": "Fraction of Uops delivered by the DSB (aka De= coded ICache; or Uop Cache)", + "MetricExpr": "IDQ.DSB_UOPS / UOPS_ISSUED.ANY", + "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", + "MetricName": "tma_info_frontend_dsb_coverage", + "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 6 > 0.35", + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" + }, + { + "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", + "MetricExpr": "DSB2MITE_SWITCHES.PENALTY_CYCLES / cpu@DSB2MITE_SWI= TCHES.PENALTY_CYCLES\\,cmask\\=3D1\\,edge@", + "MetricGroup": "DSBmiss", + "MetricName": "tma_info_frontend_dsb_switch_cost" + }, + { + "BriefDescription": "Average number of Uops issued by front-end wh= en it issued something", + "MetricExpr": "UOPS_ISSUED.ANY / cpu@UOPS_ISSUED.ANY\\,cmask\\=3D1= @", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_frontend_fetch_upc" + }, + { + "BriefDescription": "Average Latency for L1 instruction cache miss= es", + "MetricExpr": "ICACHE_DATA.STALLS / cpu@ICACHE_DATA.STALLS\\,cmask= \\=3D1\\,edge@", + "MetricGroup": "Fed;FetchLat;IcMiss", + "MetricName": "tma_info_frontend_icache_miss_latency" + }, + { + "BriefDescription": "Instructions per non-speculative DSB miss (lo= wer number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FRONTEND_RETIRED.ANY_DSB_MISS", + "MetricGroup": "DSBmiss;Fed", + "MetricName": "tma_info_frontend_ipdsb_miss_ret", + "MetricThreshold": "tma_info_frontend_ipdsb_miss_ret < 50" + }, + { + "BriefDescription": "Instructions per speculative Unknown Branch M= isprediction (BAClear) (lower number means higher occurrence rate)", + "MetricExpr": "tma_info_inst_mix_instructions / BACLEARS.ANY", + "MetricGroup": "Fed", + "MetricName": "tma_info_frontend_ipunknown_branch" + }, + { + "BriefDescription": "L2 cache true code cacheline misses per kilo = instruction", + "MetricExpr": "1e3 * FRONTEND_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_frontend_l2mpki_code" + }, + { + "BriefDescription": "L2 cache speculative code cacheline misses pe= r kilo instruction", + "MetricExpr": "1e3 * L2_RQSTS.CODE_RD_MISS / INST_RETIRED.ANY", + "MetricGroup": "IcMiss", + "MetricName": "tma_info_frontend_l2mpki_code_all" + }, + { + "BriefDescription": "Average number of cycles the front-end was de= layed due to an Unknown Branch detection", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / cpu@INT_MISC.UNKNO= WN_BRANCH_CYCLES\\,cmask\\=3D1\\,edge@", + "MetricGroup": "Fed", + "MetricName": "tma_info_frontend_unknown_branch_cost", + "PublicDescription": "Average number of cycles the front-end was d= elayed due to an Unknown Branch detection. See Unknown_Branches node." + }, + { + "BriefDescription": "Branch instructions per taken branch.", + "MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR= _TAKEN", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_inst_mix_bptkbranch" + }, + { + "BriefDescription": "Total number of retired Instructions", + "MetricExpr": "INST_RETIRED.ANY", + "MetricGroup": "Summary;TmaL1;tma_L1_group", + "MetricName": "tma_info_inst_mix_instructions", + "PublicDescription": "Total number of retired Instructions. Sample= with: INST_RETIRED.PREC_DIST" + }, + { + "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_IN= ST_RETIRED2.VECTOR))", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_inst_mix_iparith", + "MetricThreshold": "tma_info_inst_mix_iparith < 10", + "PublicDescription": "Instructions per FP Arithmetic instruction (= lower number means higher occurrence rate). Values < 1 are possible due to = intentional FMA double counting. Approximated prior to BDW." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.128B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRE= D2.128B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_iparith_avx128", + "MetricThreshold": "tma_info_inst_mix_iparith_avx128 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-b= it instruction (lower number means higher occurrence rate). Values < 1 are = possible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit i= nstruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.256B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE + FP_ARITH_INST_RETIRE= D2.256B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_iparith_avx256", + "MetricThreshold": "tma_info_inst_mix_iparith_avx256 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit = instruction (lower number means higher occurrence rate). Values < 1 are pos= sible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX 512-bit in= struction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.512B_PACK= ED_DOUBLE + FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE + FP_ARITH_INST_RETIRE= D2.512B_PACKED_HALF)", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_iparith_avx512", + "MetricThreshold": "tma_info_inst_mix_iparith_avx512 < 10", + "PublicDescription": "Instructions per FP Arithmetic AVX 512-bit i= nstruction (lower number means higher occurrence rate). Values < 1 are poss= ible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOU= BLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_inst_mix_iparith_scalar_dp", + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_dp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Double= -Precision instruction (lower number means higher occurrence rate). Values = < 1 are possible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Half-Pr= ecision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED2.SCALAR", + "MetricGroup": "Flops;FpScalar;InsType;Server", + "MetricName": "tma_info_inst_mix_iparith_scalar_hp", + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_hp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Half-P= recision instruction (lower number means higher occurrence rate). Values < = 1 are possible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SIN= GLE", + "MetricGroup": "Flops;FpScalar;InsType", + "MetricName": "tma_info_inst_mix_iparith_scalar_sp", + "MetricThreshold": "tma_info_inst_mix_iparith_scalar_sp < 10", + "PublicDescription": "Instructions per FP Arithmetic Scalar Single= -Precision instruction (lower number means higher occurrence rate). Values = < 1 are possible due to intentional FMA double counting." + }, + { + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricGroup": "Branches;Fed;InsType", + "MetricName": "tma_info_inst_mix_ipbranch", + "MetricThreshold": "tma_info_inst_mix_ipbranch < 8" + }, + { + "BriefDescription": "Instructions per (near) call (lower number me= ans higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricGroup": "Branches;Fed;PGO", + "MetricName": "tma_info_inst_mix_ipcall", + "MetricThreshold": "tma_info_inst_mix_ipcall < 200" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED= _DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_R= ETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_IN= ST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_AR= ITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PAC= KED_HALF)", + "MetricGroup": "Flops;InsType", + "MetricName": "tma_info_inst_mix_ipflop", + "MetricThreshold": "tma_info_inst_mix_ipflop < 10" + }, + { + "BriefDescription": "Instructions per Load (lower number means hig= her occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_LOADS", + "MetricGroup": "InsType", + "MetricName": "tma_info_inst_mix_ipload", + "MetricThreshold": "tma_info_inst_mix_ipload < 3" + }, + { + "BriefDescription": "Instructions per PAUSE (lower number means hi= gher occurrence rate)", + "MetricExpr": "tma_info_inst_mix_instructions / CPU_CLK_UNHALTED.P= AUSE_INST", + "MetricGroup": "Flops;FpVector;InsType", + "MetricName": "tma_info_inst_mix_ippause" + }, + { + "BriefDescription": "Instructions per Store (lower number means hi= gher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / MEM_INST_RETIRED.ALL_STORES", + "MetricGroup": "InsType", + "MetricName": "tma_info_inst_mix_ipstore", + "MetricThreshold": "tma_info_inst_mix_ipstore < 8" + }, + { + "BriefDescription": "Instructions per Software prefetch instructio= n (of any type: NTA/T0/T1/T2/Prefetch) (lower number means higher occurrenc= e rate)", + "MetricExpr": "INST_RETIRED.ANY / cpu@SW_PREFETCH_ACCESS.T0\\,umas= k\\=3D0xF@", + "MetricGroup": "Prefetches", + "MetricName": "tma_info_inst_mix_ipswpf", + "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" + }, + { + "BriefDescription": "Instructions per taken branch", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", + "MetricName": "tma_info_inst_mix_iptb", + "MetricThreshold": "tma_info_inst_mix_iptb < 13", + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "tma_info_memory_l1d_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l1d_cache_fill_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l2_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l2_cache_fill_bw_2t" + }, + { + "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", + "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / tma_info_inst_mix_i= nstructions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_memory_core_l2_evictions_nonsilent_pki" + }, + { + "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", + "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / tma_info_inst_mix_instr= uctions", + "MetricGroup": "L2Evicts;Mem;Server", + "MetricName": "tma_info_memory_core_l2_evictions_silent_pki" + }, + { + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_access_bw", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_core_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_fill_bw", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" + }, + { + "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_fb_hpki" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", + "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l1d_cache_fill_bw" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l1mpki" + }, + { + "BriefDescription": "L1 cache true misses per kilo instruction for= all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.ALL_DEMAND_DATA_RD / INST_RETIRED.AN= Y", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l1mpki_load" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", + "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l2_cache_fill_bw" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", + "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2hpki_all" + }, + { + "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2hpki_load" + }, + { + "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricGroup": "Backend;CacheHits;Mem", + "MetricName": "tma_info_memory_l2mpki" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all request types (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheHits;Mem;Offcore", + "MetricName": "tma_info_memory_l2mpki_all" + }, + { + "BriefDescription": "L2 cache ([RKL+] true) misses per kilo instru= ction for all demand loads (including speculative)", + "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.A= NY", + "MetricGroup": "CacheHits;Mem", + "MetricName": "tma_info_memory_l2mpki_load" + }, + { + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", + "MetricGroup": "Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_l3_cache_access_bw" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", + "MetricGroup": "Mem;MemoryBW", + "MetricName": "tma_info_memory_l3_cache_fill_bw" + }, + { + "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", + "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_l3mpki" + }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD / OFFCORE_REQU= ESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_memory_latency_data_l2_mlp" + }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Load= s", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_memory_latency_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@O= FFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=3D1@", + "MetricGroup": "Memory_BW;Offcore", + "MetricName": "tma_info_memory_latency_load_l2_mlp" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Load= s", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD= / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Memory_Lat;Offcore", + "MetricName": "tma_info_memory_latency_load_l3_miss_latency" + }, + { + "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", + "MetricExpr": "L1D_PEND_MISS.PENDING / MEM_LOAD_COMPLETED.L1_MISS_= ANY", + "MetricGroup": "Mem;MemoryBound;MemoryLat", + "MetricName": "tma_info_memory_load_miss_real_latency" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_mix_bus_lock_pki" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for mo= dified write requests", + "MetricExpr": "1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / tma_info_in= st_mix_instructions", + "MetricGroup": "Offcore", + "MetricName": "tma_info_memory_mix_offcore_mwrite_any_pki" + }, + { + "BriefDescription": "Off-core accesses per kilo instruction for re= ads-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / tma_info_ins= t_mix_instructions", + "MetricGroup": "CacheHits;Offcore", + "MetricName": "tma_info_memory_mix_offcore_read_any_pki" + }, + { + "BriefDescription": "L3 cache misses per kilo instruction for read= s-to-core requests (speculative; including in-core HW prefetches)", + "MetricExpr": "1e3 * OCR.READS_TO_CORE.L3_MISS / tma_info_inst_mix= _instructions", + "MetricGroup": "Offcore", + "MetricName": "tma_info_memory_mix_offcore_read_l3m_pki" + }, + { + "BriefDescription": "Un-cacheable retired load per kilo instructio= n", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem", + "MetricName": "tma_info_memory_mix_uc_load_pki" + }, + { + "BriefDescription": "Memory-Level-Parallelism (average number of L= 1 miss demand load when there is at least one such miss", + "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLE= S", + "MetricGroup": "Mem;MemoryBW;MemoryBound", + "MetricName": "tma_info_memory_mlp", + "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" + }, + { + "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) cover= ing for memory attached to local- and remote-socket", + "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / duration_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "tma_info_memory_soc_r2c_dram_bw", + "PublicDescription": "Average DRAM BW for Reads-to-Core (R2C) cove= ring for memory attached to local- and remote-socket. See R2C_Offcore_BW." + }, + { + "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R= 2C)", + "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / duration_tim= e", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "tma_info_memory_soc_r2c_l3m_bw", + "PublicDescription": "Average L3-cache miss BW for Reads-to-Core (= R2C). This covering going to DRAM or other memory off-chip memory tears. Se= e R2C_Offcore_BW." + }, + { + "BriefDescription": "Average Off-core access BW for Reads-to-Core = (R2C)", + "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / duratio= n_time", + "MetricGroup": "HPC;Mem;MemoryBW;SoC", + "MetricName": "tma_info_memory_soc_r2c_offcore_bw", + "PublicDescription": "Average Off-core access BW for Reads-to-Core= (R2C). R2C account for demand or prefetch load/RFO/code access that fill d= ata into the Core caches." + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricGroup": "Fed;MemoryTLB", + "MetricName": "tma_info_memory_tlb_code_stlb_mpki" + }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", + "MetricExpr": "1e3 * DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRE= D.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_load_stlb_mpki" + }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * tma_info_core_core_clks)", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_page_walks_utilization", + "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", + "MetricExpr": "1e3 * DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIR= ED.ANY", + "MetricGroup": "Mem;MemoryTLB", + "MetricName": "tma_info_memory_tlb_store_stlb_mpki" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", + "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", + "MetricName": "tma_info_pipeline_execute" + }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, + { + "BriefDescription": "Instructions per a microcode Assist invocatio= n", + "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", + "MetricGroup": "MicroSeq;Pipeline;Ret;Retire", + "MetricName": "tma_info_pipeline_ipassist", + "MetricThreshold": "tma_info_pipeline_ipassist < 100e3", + "PublicDescription": "Instructions per a microcode Assist invocati= on. See Assists tree node for details (lower number means higher occurrence= rate)" + }, + { + "BriefDescription": "Average number of Uops retired in cycles wher= e at least one uop has retired.", + "MetricExpr": "tma_retiring * tma_info_thread_slots / cpu@UOPS_RET= IRED.SLOTS\\,cmask\\=3D1@", + "MetricGroup": "Pipeline;Ret", + "MetricName": "tma_info_pipeline_retire" + }, + { + "BriefDescription": "Estimated fraction of retirement-cycles deali= ng with repeat instructions", + "MetricExpr": "INST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.SLOTS= \\,cmask\\=3D1@", + "MetricGroup": "MicroSeq;Pipeline;Ret", + "MetricName": "tma_info_pipeline_strings_cycles", + "MetricThreshold": "tma_info_pipeline_strings_cycles > 0.1" + }, + { + "BriefDescription": "Fraction of cycles the processor is waiting y= et unhalted; covering legacy PAUSE instruction, as well as C0.1 / C0.2 powe= r-performance optimized states", + "MetricExpr": "CPU_CLK_UNHALTED.C0_WAIT / tma_info_thread_clks", + "MetricGroup": "C0Wait", + "MetricName": "tma_info_system_c0_wait", + "MetricThreshold": "tma_info_system_c0_wait > 0.05" + }, + { + "BriefDescription": "Measured Average Core Frequency for unhalted = processors [GHz]", + "MetricExpr": "tma_info_system_turbo_utilization * TSC / 1e9 / dur= ation_time", + "MetricGroup": "Power;Summary", + "MetricName": "tma_info_system_core_frequency" + }, + { + "BriefDescription": "Average CPU Utilization (percentage)", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", + "MetricGroup": "HPC;Summary", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Average number of utilized CPUs", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_cpus_utilized" + }, + { + "BriefDescription": "Average external Memory Bandwidth Use for rea= ds and writes [GB / sec]", + "MetricExpr": "64 * (UNC_M_CAS_COUNT.RD + UNC_M_CAS_COUNT.WR) / 1e= 9 / duration_time", + "MetricGroup": "HPC;MemOffcore;MemoryBW;SoC;tma_issueBW", + "MetricName": "tma_info_system_dram_bw_use", + "PublicDescription": "Average external Memory Bandwidth Use for re= ads and writes [GB / sec]. Related metrics: tma_fb_full, tma_info_bottlenec= k_cache_memory_bandwidth, tma_mem_bandwidth, tma_sq_full" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_= INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 = * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS)= + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.51= 2B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / 1e9 / d= uration_time", + "MetricGroup": "Cor;Flops;HPC", + "MetricName": "tma_info_system_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Reads [GB / sec]", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e9 / durati= on_time", + "MetricGroup": "IoBW;MemOffcore;Server;SoC", + "MetricName": "tma_info_system_io_read_bw", + "PublicDescription": "Average IO (network or disk) Bandwidth Use f= or Reads [GB / sec]. Bandwidth of IO reads that are initiated by end device= controllers that are requesting memory from the CPU" + }, + { + "BriefDescription": "Average IO (network or disk) Bandwidth Use fo= r Writes [GB / sec]", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.= IO_ITOMCACHENEAR) * 64 / 1e9 / duration_time", + "MetricGroup": "IoBW;MemOffcore;Server;SoC", + "MetricName": "tma_info_system_io_write_bw", + "PublicDescription": "Average IO (network or disk) Bandwidth Use f= or Writes [GB / sec]. Bandwidth of IO writes that are initiated by end devi= ce controllers that are writing memory to the CPU" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricGroup": "Branches;OS", + "MetricName": "tma_info_system_ipfarbranch", + "MetricThreshold": "tma_info_system_ipfarbranch < 1e6" + }, + { + "BriefDescription": "Cycles Per Instruction for the Operating Syst= em (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k", + "MetricGroup": "OS", + "MetricName": "tma_info_system_kernel_cpi" + }, + { + "BriefDescription": "Fraction of cycles spent in the Operating Sys= tem (OS) Kernel mode", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THRE= AD", + "MetricGroup": "OS", + "MetricName": "tma_info_system_kernel_utilization", + "MetricThreshold": "tma_info_system_kernel_utilization > 0.05" + }, + { + "BriefDescription": "Average latency of data read request to exter= nal DRAM memory [in nanoseconds]", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_DDR) / uncore_cha_0@event\\=3D0x1@", + "MetricGroup": "MemOffcore;MemoryLat;Server;SoC", + "MetricName": "tma_info_system_mem_dram_read_latency", + "PublicDescription": "Average latency of data read request to exte= rnal DRAM memory [in nanoseconds]. Accounts for demand loads and L1/L2 data= -read prefetches" + }, + { + "BriefDescription": "Average number of parallel data read requests= to external memory", + "MetricExpr": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_TOR_OCC= UPANCY.IA_MISS_DRD@thresh\\=3D1@", + "MetricGroup": "Mem;MemoryBW;SoC", + "MetricName": "tma_info_system_mem_parallel_reads", + "PublicDescription": "Average number of parallel data read request= s to external memory. Accounts for demand loads and L1/L2 prefetches" + }, + { + "BriefDescription": "Average latency of data read request to exter= nal 3D X-Point memory [in nanoseconds]", + "MetricExpr": "(1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM / UNC= _CHA_TOR_INSERTS.IA_MISS_DRD_PMM) / uncore_cha_0@event\\=3D0x1@ if #has_pme= m > 0 else 0)", + "MetricGroup": "MemOffcore;MemoryLat;Server;SoC", + "MetricName": "tma_info_system_mem_pmm_read_latency", + "PublicDescription": "Average latency of data read request to exte= rnal 3D X-Point memory [in nanoseconds]. Accounts for demand loads and L1/L= 2 data-read prefetches" + }, + { + "BriefDescription": "Average latency of data read request to exter= nal memory (in nanoseconds)", + "MetricConstraint": "NO_GROUP_EVENTS", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD / UNC_CHA_= TOR_INSERTS.IA_MISS_DRD) / (tma_info_system_socket_clks / duration_time)", + "MetricGroup": "Mem;MemoryLat;SoC", + "MetricName": "tma_info_system_mem_read_latency", + "PublicDescription": "Average latency of data read request to exte= rnal memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetche= s. ([RKL+]memory-controller only)" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for reads [= GB / sec]", + "MetricExpr": "(64 * UNC_M_PMM_RPQ_INSERTS / 1e9 / duration_time i= f #has_pmem > 0 else 0)", + "MetricGroup": "MemOffcore;MemoryBW;Server;SoC", + "MetricName": "tma_info_system_pmm_read_bw" + }, + { + "BriefDescription": "Average 3DXP Memory Bandwidth Use for Writes = [GB / sec]", + "MetricExpr": "(64 * UNC_M_PMM_WPQ_INSERTS / 1e9 / duration_time i= f #has_pmem > 0 else 0)", + "MetricGroup": "MemOffcore;MemoryBW;Server;SoC", + "MetricName": "tma_info_system_pmm_write_bw" + }, + { + "BriefDescription": "Fraction of cycles where both hardware Logica= l Processors were active", + "MetricExpr": "(1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_U= NHALTED.REF_DISTRIBUTED if #SMT_on else 0)", + "MetricGroup": "SMT", + "MetricName": "tma_info_system_smt_2t_utilization" + }, + { + "BriefDescription": "Socket actual clocks when any core is active = on that socket", + "MetricExpr": "uncore_cha_0@event\\=3D0x1@", + "MetricGroup": "SoC", + "MetricName": "tma_info_system_socket_clks" + }, + { + "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "tma_info_thread_clks / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Measured Average Uncore Frequency for the SoC= [GHz]", + "MetricExpr": "tma_info_system_socket_clks / 1e9 / duration_time", + "MetricGroup": "SoC", + "MetricName": "tma_info_system_uncore_frequency" + }, + { + "BriefDescription": "Cross-socket Ultra Path Interconnect (UPI) da= ta transmit bandwidth for data only [MB / sec]", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 64 / 9 / 1e6", + "MetricGroup": "Server;SoC", + "MetricName": "tma_info_system_upi_data_transmit_bw" + }, + { + "BriefDescription": "Per-Logical Processor actual clocks when the = Logical Processor is active.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD", + "MetricGroup": "Pipeline", + "MetricName": "tma_info_thread_clks" + }, + { + "BriefDescription": "Cycles Per Instruction (per Logical Processor= )", + "MetricExpr": "1 / tma_info_thread_ipc", + "MetricGroup": "Mem;Pipeline", + "MetricName": "tma_info_thread_cpi" + }, + { + "BriefDescription": "The ratio of Executed- by Issued-Uops", + "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY", + "MetricGroup": "Cor;Pipeline", + "MetricName": "tma_info_thread_execute_per_issue", + "PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio= > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate o= f \"execute\" at rename stage." + }, + { + "BriefDescription": "Instructions Per Cycle (per Logical Processor= )", + "MetricExpr": "INST_RETIRED.ANY / tma_info_thread_clks", + "MetricGroup": "Ret;Summary", + "MetricName": "tma_info_thread_ipc" + }, + { + "BriefDescription": "Total issue-pipeline slots (per-Physical Core= till ICL; per-Logical Processor ICL onward)", + "MetricExpr": "TOPDOWN.SLOTS", + "MetricGroup": "TmaL1;tma_L1_group", + "MetricName": "tma_info_thread_slots" + }, + { + "BriefDescription": "Fraction of Physical Core issue-slots utilize= d by this Logical Processor", + "MetricExpr": "(tma_info_thread_slots / (TOPDOWN.SLOTS / 2) if #SM= T_on else 1)", + "MetricGroup": "SMT;TmaL1;tma_L1_group", + "MetricName": "tma_info_thread_slots_utilization" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "tma_retiring * tma_info_thread_slots / INST_RETIRED= .ANY", + "MetricGroup": "Pipeline;Ret;Retire", + "MetricName": "tma_info_thread_uoppi", + "MetricThreshold": "tma_info_thread_uoppi > 1.05" + }, + { + "BriefDescription": "Uops per taken branch", + "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", + "MetricGroup": "Branches;Fed;FetchBW", + "MetricName": "tma_info_thread_uptb", + "MetricThreshold": "tma_info_thread_uptb < 9" + }, + { + "BriefDescription": "This metric represents overall Integer (Int) = select operations fraction the CPU has executed (retired)", + "MetricExpr": "tma_int_vector_128b + tma_int_vector_256b", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_int_operations", + "MetricThreshold": "tma_int_operations > 0.1 & tma_light_operation= s > 0.6", + "PublicDescription": "This metric represents overall Integer (Int)= select operations fraction the CPU has executed (retired). Vector/Matrix I= nt operations and shuffles are counted. Note this metric's value may exceed= its parent due to use of \"Uops\" CountDomain.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 128-bit vector Integer= ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction the= CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_128 + INT_VEC_RETIRED.VNNI_128= ) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_128b", + "MetricThreshold": "tma_int_vector_128b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 128-bit vector Intege= r ADD/SUB/SAD or VNNI (Vector Neural Network Instructions) uops fraction th= e CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_ve= ctor_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_256b, tma= _port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents 256-bit vector Integer= ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fraction= the CPU has retired", + "MetricExpr": "(INT_VEC_RETIRED.ADD_256 + INT_VEC_RETIRED.MUL_256 = + INT_VEC_RETIRED.VNNI_256) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Compute;IntVector;Pipeline;TopdownL4;tma_L4_group;= tma_int_operations_group;tma_issue2P", + "MetricName": "tma_int_vector_256b", + "MetricThreshold": "tma_int_vector_256b > 0.1 & (tma_int_operation= s > 0.1 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents 256-bit vector Intege= r ADD/SUB/SAD/MUL or VNNI (Vector Neural Network Instructions) uops fractio= n the CPU has retired. Related metrics: tma_fp_scalar, tma_fp_vector, tma_f= p_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b,= tma_port_0, tma_port_1, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", + "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled without loads missing the L1 data cache", + "MetricExpr": "max((EXE_ACTIVITY.BOUND_ON_LOADS - MEMORY_ACTIVITY.= STALLS_L1D_MISS) / tma_info_thread_clks, 0)", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_issueL1;tma_issueMC;tma_memory_bound_group", + "MetricName": "tma_l1_bound", + "MetricThreshold": "tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 &= tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.= STALLS_L2_MISS) / tma_info_thread_clks", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", + "MetricName": "tma_l2_bound", + "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often the CPU was s= talled due to loads accesses to L3 cache or contended with a sibling Core", + "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L2_MISS - MEMORY_ACTIVITY.S= TALLS_L3_MISS) / tma_info_thread_clks", + "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricName": "tma_l3_bound", + "MetricThreshold": "tma_l3_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often the CPU was = stalled due to loads accesses to L3 cache or contended with a sibling Core.= Avoiding cache misses (i.e. L2 misses/L3 hits) can improve the latency an= d increase performance. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", + "MetricExpr": "32.6 * tma_info_system_core_frequency * (MEM_LOAD_R= ETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2= )) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", + "MetricName": "tma_l3_hit_latency", + "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= was stalled due to Length Changing Prefixes (LCPs)", + "MetricExpr": "DECODE.LCP / tma_info_thread_clks", + "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", + "MetricName": "tma_lcp", + "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring light-weight operations -- instructions that require= no more than one uop (micro-operation)", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "max(0, tma_retiring - tma_heavy_operations)", + "MetricGroup": "Default;Retire;TmaL2;TopdownL2;tma_L2_group;tma_re= tiring_group", + "MetricName": "tma_light_operations", + "MetricThreshold": "tma_light_operations > 0.6", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring light-weight operations -- instructions that requir= e no more than one uop (micro-operation). This correlates with total number= of instructions used by the program. A uops-per-instruction (see UopPI met= ric) ratio of 1 or less should be expected for decently optimized code runn= ing on Intel Core/Xeon products. While this often indicates efficient X86 i= nstructions were executed; high value does not necessarily mean better perf= ormance cannot be achieved. ([ICL+] Note this may undercount due to approxi= mation using indirect events; [ADL+] .). Sample with: INST_RETIRED.PREC_DIS= T", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Load operations", + "MetricExpr": "UOPS_DISPATCHED.PORT_2_3_10 / (3 * tma_info_core_co= re_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_load_op_utilization", + "MetricThreshold": "tma_load_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycl= es CPU dispatched uops on execution port for Load operations. Sample with: = UOPS_DISPATCHED.PORT_2_3_10", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the (first level) DTLB was missed by load accesses, that late= r on hit in second-level TLB (STLB)", + "MetricExpr": "tma_dtlb_load - tma_load_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_gro= up", + "MetricName": "tma_load_stlb_hit", + "MetricThreshold": "tma_load_stlb_hit > 0.05 & (tma_dtlb_load > 0.= 1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2= )))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = where the Second-level TLB (STLB) was missed by load accesses, performing a= hardware page walk", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_ACTIVE / tma_info_thread_clks= ", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_load_gro= up", + "MetricName": "tma_load_stlb_miss", + "MetricThreshold": "tma_load_stlb_miss > 0.05 & (tma_dtlb_load > 0= .1 & (tma_l1_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.= 2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from local memory", + "MetricExpr": "72 * tma_info_system_core_frequency * MEM_LOAD_L3_M= ISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1= _MISS / 2) / tma_info_thread_clks", + "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", + "MetricName": "tma_local_mem", + "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 &= (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)= ))", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU spent handling cache misses due to lock operations", + "MetricExpr": "(16 * max(0, MEM_INST_RETIRED.LOCK_LOADS - L2_RQSTS= .ALL_RFO) + MEM_INST_RETIRED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES * (10= * L2_RQSTS.RFO_HIT + min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTSTAN= DING.CYCLES_WITH_DEMAND_RFO))) / tma_info_thread_clks", + "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", + "MetricName": "tma_lock_latency", + "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", + "MetricGroup": "BadSpec;BvMS;Default;MachineClears;TmaL2;TopdownL2= ;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots the= CPU has wasted due to Machine Clears. These slots are either wasted by uo= ps fetched prior to the clear; or stalls the out-of-order portion of the ma= chine needs to recover its state after the clear. For example; this can hap= pen due to memory ordering Nukes (e.g. Memory Disambiguation) or Self-Modif= ying-Code (SMC) nukes. Sample with: MACHINE_CLEARS.COUNT. Related metrics: = tma_clears_resteers, tma_contested_accesses, tma_data_sharing, tma_false_sh= aring, tma_l1_bound, tma_microcode_sequencer, tma_ms_switches, tma_remote_c= ache", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to memory bandwidth Allocation= feature (RDT's memory bandwidth throttling).", + "MetricExpr": "INT_MISC.MBA_STALLS / tma_info_thread_clks", + "MetricGroup": "MemoryBW;Offcore;Server;TopdownL5;tma_L5_group;tma= _mem_bandwidth_group", + "MetricName": "tma_mba_stalls", + "MetricThreshold": "tma_mba_stalls > 0.1 & (tma_mem_bandwidth > 0.= 2 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0= .2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", + "MetricName": "tma_mem_bandwidth", + "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", + "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", + "MetricName": "tma_mem_latency", + "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = Memory subsystem within the Backend was a bottleneck", + "DefaultMetricgroupName": "TopdownL2", + "MetricExpr": "topdown\\-mem\\-bound / (topdown\\-fe\\-bound + top= down\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_in= fo_thread_slots", + "MetricGroup": "Backend;Default;TmaL2;TopdownL2;tma_L2_group;tma_b= ackend_bound_group", + "MetricName": "tma_memory_bound", + "MetricThreshold": "tma_memory_bound > 0.2 & tma_backend_bound > 0= .2", + "MetricgroupNoGroup": "TopdownL2;Default", + "PublicDescription": "This metric represents fraction of slots the= Memory subsystem within the Backend was a bottleneck. Memory Bound estima= tes fraction of slots where pipeline is likely stalled due to demand load o= r store instructions. This accounts mainly for (1) non-completed in-flight = memory demand loads which coincides with execution units starvation; in add= ition to (2) cases where stores could impose backpressure on the pipeline w= hen many of them get buffered at the same time (less common out of the two)= .", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to LFENCE Instructions.", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "13 * MISC2_RETIRED.LFENCE / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_g= roup", + "MetricName": "tma_memory_fence", + "MetricThreshold": "tma_memory_fence > 0.05 & (tma_serializing_ope= ration > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring memory operations -- uops for memory load or store a= ccesses.", + "MetricExpr": "tma_light_operations * MEM_UOP_RETIRED.ANY / (tma_r= etiring * tma_info_thread_slots)", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_memory_operations", + "MetricThreshold": "tma_memory_operations > 0.1 & tma_light_operat= ions > 0.6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricExpr": "UOPS_RETIRED.MS / tma_info_thread_slots", + "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operatio= ns_group;tma_issueMC;tma_issueMS", + "MetricName": "tma_microcode_sequencer", + "MetricThreshold": "tma_microcode_sequencer > 0.05 & tma_heavy_ope= rations > 0.1", + "PublicDescription": "This metric represents fraction of slots the= CPU was retiring uops fetched by the Microcode Sequencer (MS) unit. The M= S is used for CISC instructions not supported by the default decoders (like= repeat move strings; or CPUID); or by microcode assists used to address so= me operation modes (like in Floating Point assists). These cases can often = be avoided. Sample with: UOPS_RETIRED.MS. Related metrics: tma_clears_reste= ers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_clea= rs, tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", + "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_= MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", + "MetricName": "tma_mispredicts_resteers", + "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s in which CPU was likely limited due to the MITE pipeline (the legacy deco= de pipeline)", + "MetricExpr": "(IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / tma_in= fo_core_core_clks / 2", + "MetricGroup": "DSBmiss;FetchBW;TopdownL3;tma_L3_group;tma_fetch_b= andwidth_group", + "MetricName": "tma_mite", + "MetricThreshold": "tma_mite > 0.1 & tma_fetch_bandwidth > 0.2", + "PublicDescription": "This metric represents Core fraction of cycl= es in which CPU was likely limited due to the MITE pipeline (the legacy dec= ode pipeline). This pipeline is used for code that was not pre-cached in th= e DSB or LSD. For example; inefficiencies due to asymmetric decoders; use o= f long immediate or LCP can manifest as MITE fetch bandwidth bottleneck. Sa= mple with: FRONTEND_RETIRED.ANY_DSB_MISS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates penalty in terms of per= centage of([SKL+] injected blend uops out of all Uops Issued -- the Count D= omain; [ADL+] cycles)", + "MetricExpr": "160 * ASSISTS.SSE_AVX_MIX / tma_info_thread_clks", + "MetricGroup": "TopdownL5;tma_L5_group;tma_issueMV;tma_ports_utili= zed_0_group", + "MetricName": "tma_mixing_vectors", + "MetricThreshold": "tma_mixing_vectors > 0.05", + "PublicDescription": "This metric estimates penalty in terms of pe= rcentage of([SKL+] injected blend uops out of all Uops Issued -- the Count = Domain; [ADL+] cycles). Usually a Mixing_Vectors over 5% is worth investiga= ting. Read more in Appendix B1 of the Optimizations Guide for this topic. R= elated metrics: tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = when the CPU was stalled due to switches of uop delivery to the Microcode S= equencer (MS)", + "MetricExpr": "3 * cpu@UOPS_RETIRED.MS\\,cmask\\=3D1\\,edge@ / (UO= PS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / tma_info_thread_clks", + "MetricGroup": "FetchLat;MicroSeq;TopdownL3;tma_L3_group;tma_fetch= _latency_group;tma_issueMC;tma_issueMS;tma_issueMV;tma_issueSO", + "MetricName": "tma_ms_switches", + "MetricThreshold": "tma_ms_switches > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", + "PublicDescription": "This metric estimates the fraction of cycles= when the CPU was stalled due to switches of uop delivery to the Microcode = Sequencer (MS). Commonly used instructions are optimized for delivery by th= e DSB (decoded i-cache) or MITE (legacy instruction decode) pipelines. Cert= ain operations cannot be handled natively by the execution pipeline; and mu= st be performed by microcode (small programs injected into the execution st= ream). Switching to the MS too often can negatively impact performance. The= MS is designated to deliver long uop flows required by CISC instructions l= ike CPUID; or uncommon conditions like Floating Point Assists when dealing = with Denormals. Sample with: IDQ.MS_SWITCHES. Related metrics: tma_clears_r= esteers, tma_info_bottleneck_irregular_overhead, tma_l1_bound, tma_machine_= clears, tma_microcode_sequencer, tma_mixing_vectors, tma_serializing_operat= ion", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", + "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots)", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", + "MetricName": "tma_non_fused_branches", + "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", + "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", + "MetricName": "tma_nop_instructions", + "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents the remaining light uo= ps fraction the CPU has executed - remaining means not covered by other sib= ling nodes", + "MetricExpr": "max(0, tma_light_operations - (tma_fp_arith + tma_i= nt_operations + tma_memory_operations + tma_fused_instructions + tma_non_fu= sed_branches))", + "MetricGroup": "Pipeline;TopdownL3;tma_L3_group;tma_light_operatio= ns_group", + "MetricName": "tma_other_light_ops", + "MetricThreshold": "tma_other_light_ops > 0.3 & tma_light_operatio= ns > 0.6", + "PublicDescription": "This metric represents the remaining light u= ops fraction the CPU has executed - remaining means not covered by other si= bling nodes. May undercount due to FMA double counting", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", + "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", + "MetricName": "tma_other_mispredicts", + "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", + "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", + "MetricName": "tma_other_nukes", + "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of slo= ts the CPU retired uops as a result of handing Page Faults", + "MetricExpr": "99 * ASSISTS.PAGE_FAULT / tma_info_thread_slots", + "MetricGroup": "TopdownL5;tma_L5_group;tma_assists_group", + "MetricName": "tma_page_faults", + "MetricThreshold": "tma_page_faults > 0.05", + "PublicDescription": "This metric roughly estimates fraction of sl= ots the CPU retired uops as a result of handing Page Faults. A Page Fault m= ay apply on first application access to a memory page. Note operating syste= m handling of page faults accounts for the majority of its cost.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd b= ranch)", + "MetricExpr": "UOPS_DISPATCHED.PORT_0 / tma_info_core_core_clks", + "MetricGroup": "Compute;TopdownL6;tma_L6_group;tma_alu_op_utilizat= ion_group;tma_issue2P", + "MetricName": "tma_port_0", + "MetricThreshold": "tma_port_0 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycl= es CPU dispatched uops on execution port 0 ([SNB+] ALU; [HSW+] ALU and 2nd = branch). Sample with: UOPS_DISPATCHED.PORT_0. Related metrics: tma_fp_scala= r, tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512= b, tma_int_vector_128b, tma_int_vector_256b, tma_port_1, tma_port_5, tma_po= rt_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 1 (ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_1 / tma_info_core_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_grou= p;tma_issue2P", + "MetricName": "tma_port_1", + "MetricThreshold": "tma_port_1 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycl= es CPU dispatched uops on execution port 1 (ALU). Sample with: UOPS_DISPATC= HED.PORT_1. Related metrics: tma_fp_scalar, tma_fp_vector, tma_fp_vector_12= 8b, tma_fp_vector_256b, tma_fp_vector_512b, tma_int_vector_128b, tma_int_ve= ctor_256b, tma_port_0, tma_port_5, tma_port_6, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simple= ALU)", + "MetricExpr": "UOPS_DISPATCHED.PORT_6 / tma_info_core_core_clks", + "MetricGroup": "TopdownL6;tma_L6_group;tma_alu_op_utilization_grou= p;tma_issue2P", + "MetricName": "tma_port_6", + "MetricThreshold": "tma_port_6 > 0.6", + "PublicDescription": "This metric represents Core fraction of cycl= es CPU dispatched uops on execution port 6 ([HSW+] Primary Branch and simpl= e ALU). Sample with: UOPS_DISPATCHED.PORT_6. Related metrics: tma_fp_scalar= , tma_fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b= , tma_int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_por= t_5, tma_ports_utilized_2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU performance was potentially limited due to Core computation issues (non= divider-related)", + "MetricExpr": "((tma_ports_utilized_0 * tma_info_thread_clks + (EX= E_ACTIVITY.1_PORTS_UTIL + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,um= ask\\=3D0xc@)) / tma_info_thread_clks if ARITH.DIV_ACTIVE < CYCLE_ACTIVITY.= STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_UTIL = + tma_retiring * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,umask\\=3D0xc@) / tma_info= _thread_clks)", + "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup", + "MetricName": "tma_ports_utilization", + "MetricThreshold": "tma_ports_utilization > 0.15 & (tma_core_bound= > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates fraction of cycles the= CPU performance was potentially limited due to Core computation issues (no= n divider-related). Two distinct categories can be attributed into this me= tric: (1) heavy data-dependency among contiguous instructions would manifes= t in this metric - such cases are often referred to as low Instruction Leve= l Parallelism (ILP). (2) Contention on some hardware execution unit other t= han Divider. For example; when there are too many multiply operations.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", + "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + max(cpu@RS.EMPTY\= \,umask\\=3D1@ - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (= CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_threa= d_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricName": "tma_ports_utilized_0", + "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CP= U executed no uops on any execution port (Logical Processor cycles since IC= L, Physical Core cycles otherwise). Long-latency instructions like divides = may contribute to this metric.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles whe= re the CPU executed total of 1 uop per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricExpr": "EXE_ACTIVITY.1_PORTS_UTIL / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issueL1;tma_p= orts_utilization_group", + "MetricName": "tma_ports_utilized_1", + "MetricThreshold": "tma_ports_utilized_1 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles wh= ere the CPU executed total of 1 uop per cycle on all execution ports (Logic= al Processor cycles since ICL, Physical Core cycles otherwise). This can be= due to heavy data-dependency among software instructions; or over oversubs= cribing a particular hardware resource. In some other cases with high 1_Por= t_Utilized and L1_Bound; this metric can point to L1 data-cache latency bot= tleneck that may not necessarily manifest with complete execution starvatio= n (due to the short L1 latency e.g. walking a linked list) - looking at the= assembly can be helpful. Sample with: EXE_ACTIVITY.1_PORTS_UTIL. Related m= etrics: tma_l1_bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 2 uops per cycle on all execution ports (Logical Process= or cycles since ICL, Physical Core cycles otherwise)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "EXE_ACTIVITY.2_PORTS_UTIL / tma_info_thread_clks", + "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_issue2P;tma_p= orts_utilization_group", + "MetricName": "tma_ports_utilized_2", + "MetricThreshold": "tma_ports_utilized_2 > 0.15 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 2 uops per cycle on all execution ports (Logical Proces= sor cycles since ICL, Physical Core cycles otherwise). Loop Vectorization = -most compilers feature auto-Vectorization options today- reduces pressure = on the execution ports as multiple elements are calculated with same uop. S= ample with: EXE_ACTIVITY.2_PORTS_UTIL. Related metrics: tma_fp_scalar, tma_= fp_vector, tma_fp_vector_128b, tma_fp_vector_256b, tma_fp_vector_512b, tma_= int_vector_128b, tma_int_vector_256b, tma_port_0, tma_port_1, tma_port_5, t= ma_port_6", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", + "MetricName": "tma_ports_utilized_3m", + "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote cache in other socket= s including synchronizations issues", + "MetricExpr": "(133 * tma_info_system_core_frequency * MEM_LOAD_L3= _MISS_RETIRED.REMOTE_HITM + 133 * tma_info_system_core_frequency * MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS / 2) / tma_info_thread_clks", + "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_is= sueSyncxn;tma_mem_latency_group", + "MetricName": "tma_remote_cache", + "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0= .1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > = 0.2)))", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote cache in other socke= ts including synchronizations issues. This is caused often due to non-optim= al NUMA allocations. #link to NUMA article. Sample with: MEM_LOAD_L3_MISS_R= ETIRED.REMOTE_HITM_PS;MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD_PS. Related metri= cs: tma_contested_accesses, tma_data_sharing, tma_false_sharing, tma_machin= e_clears", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote memory", + "MetricExpr": "153 * tma_info_system_core_frequency * MEM_LOAD_L3_= MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.= L1_MISS / 2) / tma_info_thread_clks", + "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latenc= y_group", + "MetricName": "tma_remote_mem", + "MetricThreshold": "tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 = & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2= )))", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from remote memory. This is caus= ed often due to non-optimal NUMA allocations. #link to NUMA article. Sample= with: MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", + "DefaultMetricgroupName": "TopdownL1", + "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", + "MetricgroupNoGroup": "TopdownL1;Default", + "PublicDescription": "This category represents fraction of slots u= tilized by useful work i.e. issued uops that eventually get retired. Ideall= y; all pipeline slots would be attributed to the Retiring category. Retiri= ng of 100% would indicate the maximum Pipeline_Width throughput was achieve= d. Maximizing Retiring typically increases the Instructions-per-cycle (see= IPC metric). Note that a high Retiring value does not necessary mean there= is no room for more performance. For example; Heavy-operations or Microco= de Assists are categorized under Retiring. They often indicate suboptimal p= erformance and can often be optimized or avoided. Sample with: UOPS_RETIRED= .SLOTS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", + "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks += tma_c02_wait", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", + "MetricName": "tma_serializing_operation", + "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring Shuffle operations of 256-bit vector size (FP or Int= eger)", + "MetricExpr": "tma_light_operations * INT_VEC_RETIRED.SHUFFLES / (= tma_retiring * tma_info_thread_slots)", + "MetricGroup": "HPC;Pipeline;TopdownL4;tma_L4_group;tma_other_ligh= t_ops_group", + "MetricName": "tma_shuffles_256b", + "MetricThreshold": "tma_shuffles_256b > 0.1 & (tma_other_light_ops= > 0.3 & tma_light_operations > 0.6)", + "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring Shuffle operations of 256-bit vector size (FP or In= teger). Shuffles may incur slow cross \"vector lane\" data transfers.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to PAUSE Instructions", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", + "MetricExpr": "CPU_CLK_UNHALTED.PAUSE / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_serializing_operation_g= roup", + "MetricName": "tma_slow_pause", + "MetricThreshold": "tma_slow_pause > 0.05 & (tma_serializing_opera= tion > 0.1 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to PAUSE Instructions. Sample with: CPU_CLK_UNHALTED.= PAUSE_INST", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles hand= ling memory load split accesses - load that cross 64-byte cache line bounda= ry", + "MetricExpr": "tma_info_memory_load_miss_real_latency * LD_BLOCKS.= NO_SR / tma_info_thread_clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_split_loads", + "MetricThreshold": "tma_split_loads > 0.2 & (tma_l1_bound > 0.1 & = (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles han= dling memory load split accesses - load that cross 64-byte cache line bound= ary. Sample with: MEM_INST_RETIRED.SPLIT_LOADS_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents rate of split store ac= cesses", + "MetricExpr": "MEM_INST_RETIRED.SPLIT_STORES / tma_info_core_core_= clks", + "MetricGroup": "TopdownL4;tma_L4_group;tma_issueSpSt;tma_store_bou= nd_group", + "MetricName": "tma_split_stores", + "MetricThreshold": "tma_split_stores > 0.2 & (tma_store_bound > 0.= 2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric represents rate of split store a= ccesses. Consider aligning your data to the 64-byte cache line granularity= . Sample with: MEM_INST_RETIRED.SPLIT_STORES_PS. Related metrics: tma_port_= 4", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", + "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_in= fo_thread_clks", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", + "MetricName": "tma_sq_full", + "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to RFO store memory accesses; RFO store issue a read-for-ownership = request before the write", + "MetricExpr": "EXE_ACTIVITY.BOUND_ON_STORES / tma_info_thread_clks= ", + "MetricGroup": "MemoryBound;TmaL3mem;TopdownL3;tma_L3_group;tma_me= mory_bound_group", + "MetricName": "tma_store_bound", + "MetricThreshold": "tma_store_bound > 0.2 & (tma_memory_bound > 0.= 2 & tma_backend_bound > 0.2)", + "PublicDescription": "This metric estimates how often CPU was stal= led due to RFO store memory accesses; RFO store issue a read-for-ownership= request before the write. Even though store accesses do not typically stal= l out-of-order CPUs; there are few cases where stores can lead to actual st= alls. This metric will be flagged should RFO stores be a bottleneck. Sample= with: MEM_INST_RETIRED.ALL_STORES_PS", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les when the memory subsystem had loads blocked since they could not forwar= d data from earlier (in program order) overlapping stores", + "MetricExpr": "13 * LD_BLOCKS.STORE_FORWARD / tma_info_thread_clks= ", + "MetricGroup": "TopdownL4;tma_L4_group;tma_l1_bound_group", + "MetricName": "tma_store_fwd_blk", + "MetricThreshold": "tma_store_fwd_blk > 0.1 & (tma_l1_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles when the memory subsystem had loads blocked since they could not forwa= rd data from earlier (in program order) overlapping stores. To streamline m= emory operations in the pipeline; a load can avoid waiting for memory if a = prior in-flight store is writing the data that the load wants to read (stor= e forwarding process). However; in some cases the load may be blocked for a= significant time pending the store forward. For example; when the prior st= ore is writing a smaller region than the load is reading.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", + "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETI= RED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE= _REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", + "MetricName": "tma_store_latency", + "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents Core fraction of cycle= s CPU dispatched uops on execution port for Store operations", + "MetricExpr": "(UOPS_DISPATCHED.PORT_4_9 + UOPS_DISPATCHED.PORT_7_= 8) / (4 * tma_info_core_core_clks)", + "MetricGroup": "TopdownL5;tma_L5_group;tma_ports_utilized_3m_group= ", + "MetricName": "tma_store_op_utilization", + "MetricThreshold": "tma_store_op_utilization > 0.6", + "PublicDescription": "This metric represents Core fraction of cycl= es CPU dispatched uops on execution port for Store operations. Sample with:= UOPS_DISPATCHED.PORT_7_8", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric roughly estimates the fraction of= cycles where the TLB was missed by store accesses, hitting in the second-l= evel TLB (STLB)", + "MetricExpr": "tma_dtlb_store - tma_store_stlb_miss", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_gr= oup", + "MetricName": "tma_store_stlb_hit", + "MetricThreshold": "tma_store_stlb_hit > 0.05 & (tma_dtlb_store > = 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound= > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates the fraction of cycles = where the STLB was missed by store accesses, performing a hardware page wal= k", + "MetricExpr": "DTLB_STORE_MISSES.WALK_ACTIVE / tma_info_core_core_= clks", + "MetricGroup": "MemoryTLB;TopdownL5;tma_L5_group;tma_dtlb_store_gr= oup", + "MetricName": "tma_store_stlb_miss", + "MetricThreshold": "tma_store_stlb_miss > 0.05 & (tma_dtlb_store >= 0.05 & (tma_store_bound > 0.2 & (tma_memory_bound > 0.2 & tma_backend_boun= d > 0.2)))", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric estimates how often CPU was stall= ed due to Streaming store memory accesses; Streaming store optimize out a = read request required by RFO stores", + "MetricExpr": "9 * OCR.STREAMING_WR.ANY_RESPONSE / tma_info_thread= _clks", + "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueS= mSt;tma_store_bound_group", + "MetricName": "tma_streaming_stores", + "MetricThreshold": "tma_streaming_stores > 0.2 & (tma_store_bound = > 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric estimates how often CPU was stal= led due to Streaming store memory accesses; Streaming store optimize out a= read request required by RFO stores. Even though store accesses do not typ= ically stall out-of-order CPUs; there are few cases where stores can lead t= o actual stalls. This metric will be flagged should Streaming stores be a b= ottleneck. Sample with: OCR.STREAMING_WR.ANY_RESPONSE. Related metrics: tma= _fb_full", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", + "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_cl= ks", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", + "MetricName": "tma_unknown_branches", + "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "This metric serves as an approximation of leg= acy x87 usage", + "MetricExpr": "tma_retiring * UOPS_EXECUTED.X87 / UOPS_EXECUTED.TH= READ", + "MetricGroup": "Compute;TopdownL4;tma_L4_group;tma_fp_arith_group", + "MetricName": "tma_x87_use", + "MetricThreshold": "tma_x87_use > 0.1 & (tma_fp_arith > 0.2 & tma_= light_operations > 0.6)", + "PublicDescription": "This metric serves as an approximation of le= gacy x87 usage. It accounts for instructions beyond X87 FP arithmetic opera= tions; hence may be used as a thermometer to avoid X87 high usage and prefe= rably upgrade to modern ISA. See Tip under Tuning Hint.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles in aborted transactions.= ", + "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_e= vent(cycles\\-t) else 0)", + "MetricGroup": "transaction", + "MetricName": "tsx_aborted_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of cycles within a transaction divided= by the number of transactions.", + "MetricExpr": "(cycles\\-t / tx\\-start if has_event(cycles\\-t) e= lse 0)", + "MetricGroup": "transaction", + "MetricName": "tsx_cycles_per_transaction", + "ScaleUnit": "1cycles / transaction" + }, + { + "BriefDescription": "Percentage of cycles within a transaction reg= ion.", + "MetricExpr": "(cycles\\-t / cycles if has_event(cycles\\-t) else = 0)", + "MetricGroup": "transaction", + "MetricName": "tsx_transactional_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTIC= KS) * #num_packages) / 1e9 / duration_time", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data r= eceive bandwidth (MB/sec)", + "MetricExpr": "UNC_UPI_RxL_FLITS.ALL_DATA * 7.111111111111111 / 1e= 6 / duration_time", + "MetricName": "upi_data_receive_bw", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e= 6 / duration_time", + "MetricName": "upi_data_transmit_bw", + "ScaleUnit": "1MB/s" + } +] diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.js= on b/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json index 1bdefaf96287..bc475e163227 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.FPDIV_ACTIVE", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -17,6 +19,7 @@ }, { "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.SSE_AVX_MIX", "SampleAfterValue": "1000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is ali= as to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_0", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is ali= as to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_1", "SampleAfterValue": "2000003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is ali= as to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_5", "SampleAfterValue": "2000003", @@ -45,6 +51,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V0", "SampleAfterValue": "2000003", @@ -52,6 +59,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V1", "SampleAfterValue": "2000003", @@ -59,6 +67,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V2", "SampleAfterValue": "2000003", @@ -66,6 +75,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -82,6 +93,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -114,6 +129,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -122,6 +138,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -130,6 +147,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -146,6 +165,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -154,6 +174,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "PublicDescription": "Number of any Vector retired FP arithmetic i= nstructions. The DAZ and FTZ flags in the MXCSR register need to be set wh= en using these events.", @@ -162,6 +183,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", "SampleAfterValue": "100003", @@ -169,6 +191,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", "SampleAfterValue": "100003", @@ -176,6 +199,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", "SampleAfterValue": "100003", @@ -183,6 +207,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", "SampleAfterValue": "100003", @@ -190,6 +215,7 @@ }, { "BriefDescription": "Number of all Scalar Half-Precision FP arithm= etic instructions(1) retired - regular and complex.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", @@ -198,6 +224,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", "SampleAfterValue": "100003", @@ -205,6 +232,7 @@ }, { "BriefDescription": "Number of all Vector (also called packed) Hal= f-Precision FP arithmetic instructions(1) retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json b/t= ools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json index 93d99318a623..f6e3e40a3b20 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clears due to Unknown Branches.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of times the front-end is resteered w= hen it finds a branch instruction in a fetch line. This is called Unknown B= ranch which occurs for the first time a branch instruction is fetched or wh= en the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.MS_BUSY", "SampleAfterValue": "500009", @@ -24,6 +27,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -87,6 +96,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -98,6 +108,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -109,6 +120,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -120,6 +132,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -131,6 +144,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -142,6 +156,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -153,6 +168,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -164,6 +180,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -175,6 +192,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -186,6 +204,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -197,6 +216,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -208,6 +228,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.MS_FLOWS", "MSRIndex": "0x3F7", @@ -218,6 +239,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -229,6 +251,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "MSRIndex": "0x3F7", @@ -239,14 +262,26 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The decode pipeline works at a 32= Byte granularity.", "SampleAfterValue": "500009", "UMask": "0x4" }, + { + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "SampleAfterValue": "500009", + "UMask": "0x4" + }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", @@ -255,6 +290,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -264,6 +300,7 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -273,6 +310,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -281,6 +319,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -290,6 +329,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -299,6 +339,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -307,6 +348,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -316,6 +358,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -326,6 +369,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS).", @@ -334,6 +378,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE= ]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", @@ -342,6 +387,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", @@ -351,6 +397,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", @@ -361,6 +408,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_BUBBLES.CORE]", @@ -369,6 +417,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -378,6 +427,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json b/too= ls/perf/pmu-events/arch/x86/emeraldrapids/memory.json index 5420f529f491..2ea19539291b 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "9", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", @@ -49,8 +55,22 @@ "SampleAfterValue": "1000003", "UMask": "0x9" }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 1024 cycles. Reporte= d latency may be longer than just the memory latency.", + "SampleAfterValue": "53", + "UMask": "0x1" + }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -63,6 +83,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -75,6 +96,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -87,6 +109,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -99,6 +122,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -111,6 +135,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -123,6 +148,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -135,6 +161,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -147,6 +174,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -157,6 +185,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -166,6 +195,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -175,6 +205,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -184,6 +215,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -193,6 +225,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -202,6 +235,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -211,6 +245,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and t= he cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -220,6 +255,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that missed the L3 Cache and were supplied by the local socket (DRAM or= PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PM= M or DRAM accesses that are controlled by the close or distant SNC Cluster.= It does not count misses to the L3 which go to Local CXL Type 2 Memory or= Local Non DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", "MSRIndex": "0x1a6,0x1a7", @@ -229,6 +265,7 @@ }, { "BriefDescription": "Counts streaming stores that missed the local= socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -238,6 +275,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the local socket's L1, L2, or L3 caches and the cacheline is homed loc= ally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -247,6 +285,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -254,6 +293,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known by the requesti= ng core to have missed the L3 cache.", @@ -262,6 +302,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -271,6 +312,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -279,6 +321,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -287,6 +330,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -295,6 +339,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -303,6 +348,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -311,6 +357,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -319,6 +366,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -327,6 +375,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -335,6 +384,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json= b/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json new file mode 100644 index 000000000000..e1de6c2675c4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/metricgroups.json @@ -0,0 +1,137 @@ +{ + "Backend": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "Bad": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "BadSpec": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", + "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", + "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", + "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "DSBmiss": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "DataSharing": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", + "Fed": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "FetchBW": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "FetchLat": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "FpScalar": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "FpVector": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "Frontend": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "HPC": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "IcMiss": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "InsType": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "IntVector": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "IoBW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "L2Evicts": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "LSD": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "MachineClears": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", + "Machine_Clears": "Grouping from Top-down Microarchitecture Analysis M= etrics spreadsheet", + "Mem": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "MemOffcore": "Grouping from Top-down Microarchitecture Analysis Metri= cs spreadsheet", + "MemoryBW": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "MemoryBound": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", + "MemoryLat": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "MemoryTLB": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "Memory_BW": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "Memory_Lat": "Grouping from Top-down Microarchitecture Analysis Metri= cs spreadsheet", + "MicroSeq": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "OS": "Grouping from Top-down Microarchitecture Analysis Metrics sprea= dsheet", + "Offcore": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "PGO": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "Pipeline": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "PortsUtil": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Prefetches": "Grouping from Top-down Microarchitecture Analysis Metri= cs spreadsheet", + "Ret": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "Retire": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "SMT": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "Server": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "Snoop": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "SoC": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "TmaL1": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "TmaL2": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "TmaL3mem": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "TopdownL1": "Metrics for top-down breakdown at level 1", + "TopdownL2": "Metrics for top-down breakdown at level 2", + "TopdownL3": "Metrics for top-down breakdown at level 3", + "TopdownL4": "Metrics for top-down breakdown at level 4", + "TopdownL5": "Metrics for top-down breakdown at level 5", + "TopdownL6": "Metrics for top-down breakdown at level 6", + "tma_L1_group": "Metrics for top-down breakdown at level 1", + "tma_L2_group": "Metrics for top-down breakdown at level 2", + "tma_L3_group": "Metrics for top-down breakdown at level 3", + "tma_L4_group": "Metrics for top-down breakdown at level 4", + "tma_L5_group": "Metrics for top-down breakdown at level 5", + "tma_L6_group": "Metrics for top-down breakdown at level 6", + "tma_alu_op_utilization_group": "Metrics contributing to tma_alu_op_ut= ilization category", + "tma_assists_group": "Metrics contributing to tma_assists category", + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound = category", + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculat= ion category", + "tma_branch_mispredicts_group": "Metrics contributing to tma_branch_mi= spredicts category", + "tma_branch_resteers_group": "Metrics contributing to tma_branch_reste= ers category", + "tma_core_bound_group": "Metrics contributing to tma_core_bound catego= ry", + "tma_dram_bound_group": "Metrics contributing to tma_dram_bound catego= ry", + "tma_dtlb_load_group": "Metrics contributing to tma_dtlb_load category= ", + "tma_dtlb_store_group": "Metrics contributing to tma_dtlb_store catego= ry", + "tma_fetch_bandwidth_group": "Metrics contributing to tma_fetch_bandwi= dth category", + "tma_fetch_latency_group": "Metrics contributing to tma_fetch_latency = category", + "tma_fp_arith_group": "Metrics contributing to tma_fp_arith category", + "tma_fp_vector_group": "Metrics contributing to tma_fp_vector category= ", + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_boun= d category", + "tma_heavy_operations_group": "Metrics contributing to tma_heavy_opera= tions category", + "tma_int_operations_group": "Metrics contributing to tma_int_operation= s category", + "tma_issue2P": "Metrics related by the issue $issue2P", + "tma_issueBM": "Metrics related by the issue $issueBM", + "tma_issueBW": "Metrics related by the issue $issueBW", + "tma_issueComp": "Metrics related by the issue $issueComp", + "tma_issueD0": "Metrics related by the issue $issueD0", + "tma_issueFB": "Metrics related by the issue $issueFB", + "tma_issueFL": "Metrics related by the issue $issueFL", + "tma_issueL1": "Metrics related by the issue $issueL1", + "tma_issueLat": "Metrics related by the issue $issueLat", + "tma_issueMC": "Metrics related by the issue $issueMC", + "tma_issueMS": "Metrics related by the issue $issueMS", + "tma_issueMV": "Metrics related by the issue $issueMV", + "tma_issueRFO": "Metrics related by the issue $issueRFO", + "tma_issueSL": "Metrics related by the issue $issueSL", + "tma_issueSO": "Metrics related by the issue $issueSO", + "tma_issueSmSt": "Metrics related by the issue $issueSmSt", + "tma_issueSpSt": "Metrics related by the issue $issueSpSt", + "tma_issueSyncxn": "Metrics related by the issue $issueSyncxn", + "tma_issueTLB": "Metrics related by the issue $issueTLB", + "tma_l1_bound_group": "Metrics contributing to tma_l1_bound category", + "tma_l3_bound_group": "Metrics contributing to tma_l3_bound category", + "tma_light_operations_group": "Metrics contributing to tma_light_opera= tions category", + "tma_load_op_utilization_group": "Metrics contributing to tma_load_op_= utilization category", + "tma_machine_clears_group": "Metrics contributing to tma_machine_clear= s category", + "tma_mem_bandwidth_group": "Metrics contributing to tma_mem_bandwidth = category", + "tma_mem_latency_group": "Metrics contributing to tma_mem_latency cate= gory", + "tma_memory_bound_group": "Metrics contributing to tma_memory_bound ca= tegory", + "tma_microcode_sequencer_group": "Metrics contributing to tma_microcod= e_sequencer category", + "tma_mite_group": "Metrics contributing to tma_mite category", + "tma_other_light_ops_group": "Metrics contributing to tma_other_light_= ops category", + "tma_ports_utilization_group": "Metrics contributing to tma_ports_util= ization category", + "tma_ports_utilized_0_group": "Metrics contributing to tma_ports_utili= zed_0 category", + "tma_ports_utilized_3m_group": "Metrics contributing to tma_ports_util= ized_3m category", + "tma_retiring_group": "Metrics contributing to tma_retiring category", + "tma_serializing_operation_group": "Metrics contributing to tma_serial= izing_operation category", + "tma_store_bound_group": "Metrics contributing to tma_store_bound cate= gory", + "tma_store_op_utilization_group": "Metrics contributing to tma_store_o= p_utilization category" +} diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json b/tool= s/perf/pmu-events/arch/x86/emeraldrapids/other.json index 2f375a6badcd..c424facf1b95 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.PAGE_FAULT", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the cycles where the AMX (Advance Matr= ix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb7", "EventName": "EXE.AMX_BUSY", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM attached to this socket= , unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM= accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM on a distant memory con= troller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S= NC Mode counts only those DRAM accesses that are controlled by the close SN= C Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM on a distant memory controller of this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -105,6 +117,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -114,6 +127,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mo= de. In SNC Mode counts only those DRAM accesses that are controlled by the= close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM on a distant memory controller of this socket when the syst= em is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -132,6 +147,7 @@ }, { "BriefDescription": "Counts data load hardware prefetch requests t= o the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -141,6 +157,7 @@ }, { "BriefDescription": "Counts hardware prefetches (which bring data = to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L2.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -159,6 +177,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline was homed in a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -168,6 +187,7 @@ }, { "BriefDescription": "Counts writebacks of modified cachelines and = streaming stores that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -186,6 +207,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -195,6 +217,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA = Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are co= ntrolled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +227,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, whether or not in S= ub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are contr= olled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -213,6 +237,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -222,6 +247,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -231,6 +257,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", "MSRIndex": "0x1a6,0x1a7", @@ -240,6 +267,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM on a distant memory controller of this socke= t when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -249,6 +277,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -258,6 +287,7 @@ }, { "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hard= ware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted = in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.WRITE_ESTIMATE.MEMORY", "MSRIndex": "0x1a6,0x1a7", @@ -267,6 +297,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", "EventName": "RS.EMPTY", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -275,6 +306,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xa5", @@ -284,8 +316,17 @@ "SampleAfterValue": "100003", "UMask": "0x7" }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty= due to a resource in the back-end", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_RESOURCE", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY_COUNT", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EdgeDetect": "1", @@ -297,6 +338,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xa5", "EventName": "RS_EMPTY.CYCLES", @@ -305,6 +347,7 @@ }, { "BriefDescription": "Cycles the uncore cannot take further request= s", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json b/t= ools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json index e2086bedeca8..5d5811f26151 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.DIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.DIV_ACTIVE", @@ -19,6 +21,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -28,6 +31,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divi= der is busy.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", @@ -36,6 +40,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.IDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware. Examples include AD (page Access Dirt= y), FP and AVX related assists.", @@ -53,6 +59,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -70,6 +78,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -79,6 +88,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -88,6 +98,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -141,6 +157,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -159,6 +177,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -168,6 +187,7 @@ }, { "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -186,6 +207,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -195,6 +217,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -204,6 +227,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 li= ght-weight slower wakeup time but more power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C01", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 light-weight slower wakeup time but more power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -212,6 +236,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.2 li= ght-weight faster wakeup time but less power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C02", "PublicDescription": "Counts core clocks when the thread is in the= C0.2 light-weight faster wakeup time but less power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -220,6 +245,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 or= C0.2 or running a PAUSE in C0 ACPI state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C0_WAIT", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions)= or running the PAUSE instruction.", @@ -228,6 +254,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -236,6 +263,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -244,6 +272,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.PAUSE", "SampleAfterValue": "2000003", @@ -251,6 +280,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xec", @@ -260,6 +290,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -268,6 +299,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the eight programmable counte= rs available for other events. Note: On all current platforms this event st= ops counting during 'throttling (TM)' states duty off periods the processor= is 'halted'. The counter update is done at a lower clock rate then the co= re clock the overflow status bit for this counter may appear 'sticky'. Aft= er the counter has overflowed and software clears the overflow status bit a= nd resets the counter to less than MAX. The reset value to the counter is n= ot clocked immediately so the overflow status bit will flip 'high (1)' and = generate another PMI (if enabled) after which the reset value gets clocked = into the counter. Therefore, software will get the interrupt, read the over= flow status bit '1 for bit 34 while the counter value is less than MAX. Sof= tware should ignore this case.", "SampleAfterValue": "2000003", @@ -275,6 +307,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", @@ -283,6 +316,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -290,6 +324,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -297,6 +332,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -305,6 +341,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -313,6 +350,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -321,6 +359,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -329,6 +368,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -337,6 +377,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -345,14 +386,24 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Cycles total of 2 or 3 uops are executed on a= ll ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -361,6 +412,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -369,6 +421,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -377,6 +430,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", @@ -385,6 +439,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -394,6 +449,7 @@ }, { "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", @@ -402,6 +458,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -410,6 +467,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -418,6 +476,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -426,6 +485,7 @@ }, { "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -434,6 +494,7 @@ }, { "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = precise distribution of samples across instructions retired. It utilizes th= e Precise Distribution of Instructions Retired (PDIR++) feature to fix bias= in how retired instructions get sampled. Use on Fixed Counter 0.", @@ -451,6 +513,7 @@ }, { "BriefDescription": "Iterations of Repeat string retired instructi= ons.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", "PEBS": "1", @@ -460,6 +523,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xad", @@ -470,6 +534,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -478,6 +543,7 @@ }, { "BriefDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.MBA_STALLS", "SampleAfterValue": "1000003", @@ -485,6 +551,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -493,6 +560,7 @@ }, { "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", "MSRIndex": "0x3F7", @@ -502,6 +570,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -510,6 +579,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.128BIT", "SampleAfterValue": "1000003", @@ -517,6 +587,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.256BIT", "SampleAfterValue": "1000003", @@ -524,6 +595,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_128", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 128-bit vector instructions.", @@ -532,6 +604,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_256", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 256-bit vector instructions.", @@ -540,6 +613,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.MUL_256", "SampleAfterValue": "1000003", @@ -547,6 +621,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.SHUFFLES", "SampleAfterValue": "1000003", @@ -554,6 +629,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_128", "SampleAfterValue": "1000003", @@ -561,6 +637,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_256", "SampleAfterValue": "1000003", @@ -568,6 +645,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", @@ -576,6 +654,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -584,6 +663,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -592,6 +672,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -600,6 +681,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", @@ -609,6 +691,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -618,6 +701,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -626,6 +710,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -636,6 +721,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -644,6 +730,7 @@ }, { "BriefDescription": "LFENCE instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", "PublicDescription": "number of LFENCE retired instructions", @@ -652,6 +739,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -660,6 +748,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -668,6 +757,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -675,6 +765,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Number of slots in TMA method where no micro= -operations were being issued from front-end to back-end of the machine due= to lack of back-end resources.", @@ -683,6 +774,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= s.", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BAD_SPEC_SLOTS", "PublicDescription": "Number of slots of TMA method that were wast= ed due to incorrect speculation. It covers all types of control-flow or dat= a-related mis-speculations.", @@ -691,6 +783,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by (any type of) branch mispredictions. This event es= timates number of speculative operations that were issued but not retired a= s well as the out-of-order engine recovery past a branch misprediction.", @@ -699,6 +792,7 @@ }, { "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", "SampleAfterValue": "10000003", @@ -706,6 +800,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -713,6 +808,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -721,6 +817,7 @@ }, { "BriefDescription": "UOPS_DECODED.DEC0_UOPS", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UOPS_DECODED.DEC0_UOPS", "SampleAfterValue": "1000003", @@ -728,6 +825,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Number of uops dispatch to execution port 0= .", @@ -736,6 +834,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Number of uops dispatch to execution port 1= .", @@ -744,6 +843,7 @@ }, { "BriefDescription": "Uops executed on ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_2_3_10", "PublicDescription": "Number of uops dispatch to execution ports 2= , 3 and 10", @@ -752,6 +852,7 @@ }, { "BriefDescription": "Uops executed on ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Number of uops dispatch to execution ports 4= and 9", @@ -760,6 +861,7 @@ }, { "BriefDescription": "Uops executed on ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_5_11", "PublicDescription": "Number of uops dispatch to execution ports 5= and 11", @@ -768,6 +870,7 @@ }, { "BriefDescription": "Uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Number of uops dispatch to execution port 6= .", @@ -776,6 +879,7 @@ }, { "BriefDescription": "Uops executed on ports 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Number of uops dispatch to execution ports = 7 and 8.", @@ -784,6 +888,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -801,6 +907,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -810,6 +917,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -819,6 +927,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -828,6 +937,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -837,6 +947,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -846,6 +957,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -855,6 +967,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -864,6 +977,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.STALLS", @@ -874,6 +988,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_EXECUTED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb1", @@ -884,6 +999,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -891,6 +1007,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -899,14 +1016,25 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xae", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", "SampleAfterValue": "2000003", "UMask": "0x1" }, + { + "BriefDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Cycles with retired uop(s).", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.CYCLES", @@ -916,6 +1044,7 @@ }, { "BriefDescription": "Retired uops except the last uop of each inst= ruction.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.HEAVY", "PublicDescription": "Counts the number of retired micro-operation= s (uops) except the last uop of each instruction. An instruction that is de= coded into less than two uops does not contribute to the count.", @@ -924,6 +1053,7 @@ }, { "BriefDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "MSRIndex": "0x3F7", @@ -933,6 +1063,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -941,6 +1072,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALLS", @@ -951,6 +1083,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_RETIRED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xc2", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json= b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json index 141dab46682e..f453202d80c2 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cache.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", "UMask": "0x2", @@ -10,8 +12,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", "UMask": "0x4", @@ -19,8 +23,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", "UMask": "0x1", @@ -28,6 +34,7 @@ }, { "BriefDescription": "CHA Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", @@ -36,6 +43,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", @@ -43,8 +51,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0xf2", @@ -52,8 +62,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", "UMask": "0xf1", @@ -61,8 +73,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", @@ -70,8 +84,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", "UMask": "0x41", @@ -79,8 +95,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", @@ -88,8 +106,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", "UMask": "0x81", @@ -97,8 +117,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x22", @@ -106,8 +128,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x21", @@ -115,8 +139,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Tar= gets from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Ta= rgets from Remote : Counts the number of transactions that trigger a config= urable number of cross snoops. Cores are snooped if the transaction looks = up the cache and determines that it is necessary based on the operation typ= e and what CoreValid bits are set. For example, if 2 CV bits are set on a = data read, the cores must have the data in S state so it is not necessary t= o snoop them. However, if only 1 CV bit is set the core my have modified t= he data. If the transaction was an RFO, it would need to invalidate the li= nes. This event can be filtered based on who triggered the initial snoop(s= ).", "UMask": "0x12", @@ -124,8 +150,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Snoop Targe= t from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Snoop Targ= et from Remote : Counts the number of transactions that trigger a configura= ble number of cross snoops. Cores are snooped if the transaction looks up = the cache and determines that it is necessary based on the operation type a= nd what CoreValid bits are set. For example, if 2 CV bits are set on a dat= a read, the cores must have the data in S state so it is not necessary to s= noop them. However, if only 1 CV bit is set the core my have modified the = data. If the transaction was an RFO, it would need to invalidate the lines= . This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x11", @@ -133,96 +161,120 @@ }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts transactions that looked into the mul= ti-socket cacheline Directory state, and therefore did not send a snoop bec= ause the Directory indicated it was not needed.", "UMask": "0x2", @@ -230,8 +282,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts transactions that looked into the mu= lti-socket cacheline Directory state, and sent one or more snoops, because = the Directory indicated it was needed.", "UMask": "0x1", @@ -239,6 +293,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", @@ -248,6 +303,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", @@ -257,8 +313,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -266,8 +324,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -275,8 +335,10 @@ }, { "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts read requests from a remote socket wh= ich hit in the HitME cache (used to cache the multi-socket Directory state)= to a line in the E(Exclusive) state. This includes the following read opc= odes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", "UMask": "0x1", @@ -284,80 +346,100 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : Shared= hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : op is = WbMtoE", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : op is = WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : No S= F/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : op i= s RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : SF/L= LC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Deallocate HitME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI= * for a local request, but converted HitME$ to SF entry", "UMask": "0x1", @@ -365,16 +447,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ = on RspFwdI* or local HitM/E received for a remote request", "UMask": "0x2", @@ -382,14 +468,17 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -399,8 +488,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", "UMask": "0x2", @@ -408,6 +499,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -417,8 +509,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", "UMask": "0x4", @@ -426,8 +520,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", "UMask": "0x2", @@ -435,8 +531,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", "UMask": "0x8", @@ -444,8 +542,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1fffff", @@ -453,8 +553,10 @@ }, { "BriefDescription": "Cache Lookups : All transactions from Remote = Agents", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All transactions from Remote= Agents : Counts the number of times the LLC was accessed - this includes c= ode, data, prefetches and hints coming from L2. This has numerous filters = available. Note the non-standard filtering equation. This event will coun= t requests that lookup the cache multiple times with multiple increments. = One must ALWAYS select a state or states (in the umask field) to match. Ot= herwise, the event will count nothing.", "UMask": "0x17e0ff", @@ -462,16 +564,20 @@ }, { "BriefDescription": "Cache Lookups : All Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Any local or remote transaction to the LLC, including pref= etch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1bd0ff", @@ -479,24 +585,30 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Local non-prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local non-prefetch requests = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Any local transaction to the LLC, not inclu= ding prefetch", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1bc1ff", @@ -504,8 +616,10 @@ }, { "BriefDescription": "Cache Lookups : Data Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1fc1ff", @@ -513,16 +627,20 @@ }, { "BriefDescription": "Cache Lookups : Data Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Request : Counts t= he number of times the LLC was accessed - this includes code, data, prefetc= hes and hints coming from L2. This has numerous filters available. Note t= he non-standard filtering equation. This event will count requests that lo= okup the cache multiple times with multiple increments. One must ALWAYS se= t umask bit 0 and select a state or states to match. Otherwise, the event = will count nothing. : Read transactions.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Demand Data Reads, Core and L= LC prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Demand Data Reads, Core and = LLC prefetches : Counts the number of times the LLC was accessed - this inc= ludes code, data, prefetches and hints coming from L2. This has numerous f= ilters available. Note the non-standard filtering equation. This event wi= ll count requests that lookup the cache multiple times with multiple increm= ents. One must ALWAYS select a state or states (in the umask field) to mat= ch. Otherwise, the event will count nothing.", "UMask": "0x841ff", @@ -530,8 +648,10 @@ }, { "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1fc101", @@ -539,8 +659,10 @@ }, { "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Exclusive State", "UMask": "0x20", @@ -548,8 +670,10 @@ }, { "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Forward State", "UMask": "0x80", @@ -557,8 +681,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a44ff", @@ -566,16 +692,20 @@ }, { "BriefDescription": "Cache Lookups : Flush", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Miss", "UMask": "0x1", @@ -583,16 +713,20 @@ }, { "BriefDescription": "Cache Lookups : Local LLC prefetch requests (= from LLC)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local LLC prefetch requests = (from LLC) : Counts the number of times the LLC was accessed - this include= s code, data, prefetches and hints coming from L2. This has numerous filte= rs available. Note the non-standard filtering equation. This event will c= ount requests that lookup the cache multiple times with multiple increments= . One must ALWAYS set umask bit 0 and select a state or states to match. = Otherwise, the event will count nothing. : Any local LLC prefetch to the LL= C", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed locally", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS set umask bit 0 and select a state or states to match. Otherwise, t= he event will count nothing. : Transaction whose address resides in the loc= al MC.", "UMask": "0xbdfff", @@ -600,8 +734,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x19d0ff", @@ -609,8 +745,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x19c1ff", @@ -618,8 +756,10 @@ }, { "BriefDescription": "Cache Lookups : Demand CRd Requests that come= from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1850ff", @@ -627,8 +767,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Demand Data R= eads that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1841ff", @@ -636,8 +778,10 @@ }, { "BriefDescription": "Cache Lookups : Demand RFO Requests that come= from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1848ff", @@ -645,16 +789,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed locally", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS set umask bit 0 and select a state or states to match. Otherwise, t= he event will count nothing. : Transaction whose address resides in the loc= al MC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests = that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1844ff", @@ -662,8 +810,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requ= ests to the LLC that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x189dff", @@ -671,8 +821,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Pre= fetches that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x199dff", @@ -680,8 +832,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Prefetches that come from= the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1910ff", @@ -689,8 +843,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Pre= fetches that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1981ff", @@ -698,8 +854,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Prefetches that come from= the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1908ff", @@ -707,8 +865,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x19c8ff", @@ -716,8 +876,10 @@ }, { "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Modified State", "UMask": "0x40", @@ -725,8 +887,10 @@ }, { "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x1fe001", @@ -734,24 +898,30 @@ }, { "BriefDescription": "Cache Lookups : Write Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Remote non-snoop requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote non-snoop requests : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS set umask bit 0 and select a state or states to match. Otherwise, th= e event will count nothing. : Remote non-snoop transactions to the LLC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed remotely", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "UMask": "0x15dfff", @@ -759,8 +929,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1a10ff", @@ -768,8 +940,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uests that come from a Remote socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1a01ff", @@ -777,16 +951,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed remotely", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Flush or Invalidate requests = that come from a Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a04ff", @@ -794,8 +972,10 @@ }, { "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache that come from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "UMask": "0x1a02ff", @@ -803,8 +983,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1a08ff", @@ -812,16 +994,20 @@ }, { "BriefDescription": "Cache Lookups : Remote snoop requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote snoop requests : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : Remote snoop transactions to the LLC.", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Request= s from a Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1c19ff", @@ -829,8 +1015,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1bc8ff", @@ -838,16 +1026,20 @@ }, { "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing. : Local or remo= te RFO transactions to the LLC. This includes RFO prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Locally HOMed RFOs - Demand a= nd Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x9c8ff", @@ -855,8 +1047,10 @@ }, { "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Shared State", "UMask": "0x10", @@ -864,8 +1058,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit Exclusive State", "UMask": "0x4", @@ -873,8 +1069,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit HitMe State", "UMask": "0x8", @@ -882,8 +1080,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit Shared State", "UMask": "0x2", @@ -891,8 +1091,10 @@ }, { "BriefDescription": "Cache Lookups : Writes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing. : Requests that= install or change a line in the LLC. Examples: Writebacks from Core L2= 's and UPI. Prefetches into the LLC.", "UMask": "0x842ff", @@ -900,8 +1102,10 @@ }, { "BriefDescription": "Cache Lookups : Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x17c2ff", @@ -909,8 +1113,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x2", @@ -918,8 +1124,10 @@ }, { "BriefDescription": "Lines Victimized : IA traffic", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : IA traffic : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "UMask": "0x20", @@ -927,8 +1135,10 @@ }, { "BriefDescription": "Lines Victimized : IO traffic", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : IO traffic : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "UMask": "0x10", @@ -936,8 +1146,10 @@ }, { "BriefDescription": "All LLC lines in E state that are victimized = on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x12", @@ -945,8 +1157,10 @@ }, { "BriefDescription": "All LLC lines in F or S state that are victim= ized on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_FS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1c", @@ -954,8 +1168,10 @@ }, { "BriefDescription": "All LLC lines in M state that are victimized = on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x11", @@ -963,8 +1179,10 @@ }, { "BriefDescription": "All LLC lines in any state that are victimize= d on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_MESF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1f", @@ -972,8 +1190,10 @@ }, { "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x200f", @@ -981,8 +1201,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2002", @@ -990,8 +1212,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2001", @@ -999,16 +1223,20 @@ }, { "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2004", @@ -1016,8 +1244,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x1", @@ -1025,8 +1255,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x800f", @@ -1034,8 +1266,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8002", @@ -1043,8 +1277,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8001", @@ -1052,16 +1288,20 @@ }, { "BriefDescription": "Lines Victimized : Remote Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote Only : Counts the = number of lines that were victimized on a fill. This can be filtered by th= e state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8004", @@ -1069,8 +1309,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x4", @@ -1078,8 +1320,10 @@ }, { "BriefDescription": "All LLC lines in E state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", @@ -1087,8 +1331,10 @@ }, { "BriefDescription": "All LLC lines in M state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", @@ -1096,8 +1342,10 @@ }, { "BriefDescription": "All LLC lines in S state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", @@ -1105,8 +1353,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", "UMask": "0x20", @@ -1114,8 +1364,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", "UMask": "0x10", @@ -1123,8 +1375,10 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x8", @@ -1132,8 +1386,10 @@ }, { "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", "UMask": "0x1", @@ -1141,8 +1397,10 @@ }, { "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", @@ -1150,8 +1408,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count = of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be b= roadcast. Does not count all the snoops generated by OSB.", "UMask": "0x1", @@ -1159,8 +1419,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OS= B snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadc= ast. Does not count all the snoops generated by OSB.", "UMask": "0x2", @@ -1168,8 +1430,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Off", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB sno= op broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. = Does not count all the snoops generated by OSB.", "UMask": "0x20", @@ -1177,8 +1441,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of O= SB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broad= cast. Does not count all the snoops generated by OSB.", "UMask": "0x4", @@ -1186,8 +1452,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Co= unt of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to = be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x8", @@ -1195,8 +1463,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadca= st : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB sno= ops to be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x10", @@ -1204,32 +1474,40 @@ }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near Memory set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Near Memory evictions due to another read to= the same Near Memory set in the LLC.", "UMask": "0x2", @@ -1237,8 +1515,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near memory set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Near Memory evictions due to another read to= the same Near Memory set in the SF", "UMask": "0x1", @@ -1246,8 +1526,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near Memory set conflict in TOR", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Reject in the CHA due to a pending read t= o the same Near Memory set in the TOR.", "UMask": "0x4", @@ -1255,88 +1537,110 @@ }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": count # of FAST TOR Request inserted to ha= _tor_req_fifo", "UMask": "0x2", @@ -1344,16 +1648,20 @@ }, { "BriefDescription": "Number of SLOW TOR Request inserted to ha_pmm= _tor_req_fifo", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", "UMask": "0x1", @@ -1361,8 +1669,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", "UMask": "0x2", @@ -1370,8 +1680,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", "UMask": "0x4", @@ -1379,8 +1691,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", "UMask": "0x8", @@ -1388,8 +1702,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", @@ -1397,8 +1713,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", @@ -1406,8 +1724,10 @@ }, { "BriefDescription": "Requests for exclusive ownership of a cache l= ine without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", "UMask": "0x30", @@ -1415,6 +1735,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -1424,6 +1745,7 @@ }, { "BriefDescription": "Remote requests for exclusive ownership of a = cache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -1433,6 +1755,7 @@ }, { "BriefDescription": "Read requests made into the CHA", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -1442,6 +1765,7 @@ }, { "BriefDescription": "Read requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -1451,6 +1775,7 @@ }, { "BriefDescription": "Read requests from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -1460,6 +1785,7 @@ }, { "BriefDescription": "Write requests made into the CHA", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -1469,6 +1795,7 @@ }, { "BriefDescription": "Write Requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -1478,6 +1805,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes Remote", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -1487,8 +1815,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", @@ -1496,8 +1826,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", @@ -1505,8 +1837,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", "UMask": "0x2", @@ -1514,8 +1848,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", @@ -1523,8 +1859,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", @@ -1532,8 +1870,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x40", @@ -1541,8 +1881,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x80", @@ -1550,8 +1892,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1559,8 +1903,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1568,8 +1914,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -1577,8 +1925,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1586,8 +1936,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1595,8 +1947,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1604,8 +1958,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1613,8 +1969,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -1622,16 +1980,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IPQ0 Reject counter was true", "UMask": "0x1", @@ -1639,16 +2001,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -1656,16 +2022,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -1673,8 +2043,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -1682,16 +2054,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1699,8 +2075,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1708,8 +2086,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -1717,8 +2097,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1726,8 +2108,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1735,8 +2119,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1744,8 +2130,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1753,8 +2141,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -1762,16 +2152,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", "UMask": "0x1", @@ -1779,16 +2173,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -1796,24 +2194,30 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -1821,16 +2225,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1838,8 +2246,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1847,8 +2257,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -1856,8 +2268,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1865,8 +2279,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1874,8 +2290,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1883,8 +2301,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1892,8 +2312,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -1901,8 +2323,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1910,8 +2334,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1919,8 +2345,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -1928,8 +2356,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1937,8 +2367,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1946,8 +2378,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1955,8 +2389,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1964,8 +2400,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -1973,8 +2411,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -1982,8 +2422,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -1991,8 +2433,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2000,8 +2444,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2009,8 +2455,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", @@ -2018,8 +2466,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x40", @@ -2027,8 +2477,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x80", @@ -2036,8 +2488,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", "UMask": "0x1", @@ -2045,8 +2499,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", "UMask": "0x2", @@ -2054,8 +2510,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", "UMask": "0x40", @@ -2063,8 +2521,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2072,8 +2532,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2081,8 +2543,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", "UMask": "0x4", @@ -2090,8 +2554,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", "UMask": "0x8", @@ -2099,8 +2565,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", "UMask": "0x80", @@ -2108,8 +2576,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", "UMask": "0x40", @@ -2117,8 +2587,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", "UMask": "0x1", @@ -2126,8 +2598,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", "UMask": "0x2", @@ -2135,8 +2609,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", "UMask": "0x20", @@ -2144,8 +2620,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", "UMask": "0x4", @@ -2153,8 +2631,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", "UMask": "0x80", @@ -2162,8 +2642,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", "UMask": "0x8", @@ -2171,8 +2653,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", "UMask": "0x10", @@ -2180,8 +2664,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2189,8 +2675,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2198,8 +2686,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2207,8 +2697,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2216,8 +2708,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2225,8 +2719,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2234,8 +2730,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2243,8 +2741,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -2252,16 +2752,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", "UMask": "0x1", @@ -2269,16 +2773,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2286,16 +2794,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -2303,8 +2815,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2312,16 +2826,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2329,8 +2847,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2338,8 +2858,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", @@ -2347,8 +2869,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2356,8 +2880,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2365,8 +2891,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2374,8 +2902,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2383,8 +2913,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", "UMask": "0x80", @@ -2392,8 +2924,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x40", @@ -2401,8 +2935,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -2410,8 +2946,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x2", @@ -2419,8 +2957,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2428,8 +2968,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x4", @@ -2437,8 +2979,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2446,8 +2990,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2455,8 +3001,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x10", @@ -2464,8 +3012,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2473,8 +3023,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2482,8 +3034,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -2491,8 +3045,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2500,8 +3056,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2509,8 +3067,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2518,8 +3078,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the RRQ (Remote Response Queue) had = to retry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2527,8 +3089,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -2536,8 +3100,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the RRQ (Remote Response Queue) had t= o retry.", "UMask": "0x40", @@ -2545,8 +3111,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the RRQ (Remote Response Queue) had to retry= . : Any condition listed in the RRQ0 Reject counter was true", "UMask": "0x1", @@ -2554,8 +3122,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2563,8 +3133,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2572,8 +3144,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the RRQ (Remote Response Queue) had to= retry.", "UMask": "0x4", @@ -2581,8 +3155,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2590,8 +3166,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the RRQ (Remote Response Queue) had to = retry. : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2599,8 +3177,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the RRQ (Remote Response Queue) had to ret= ry.", "UMask": "0x10", @@ -2608,8 +3188,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2617,8 +3199,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2626,8 +3210,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -2635,8 +3221,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2644,8 +3232,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2653,8 +3243,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2662,8 +3254,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the WBQ (Writeback Queue) had to ret= ry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2671,8 +3265,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -2680,8 +3276,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the WBQ (Writeback Queue) had to retr= y.", "UMask": "0x40", @@ -2689,8 +3287,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the WBQ (Writeback Queue) had to retry. : An= y condition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -2698,8 +3298,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2707,8 +3309,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2716,8 +3320,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the WBQ (Writeback Queue) had to retry= .", "UMask": "0x4", @@ -2725,8 +3331,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2734,8 +3342,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the WBQ (Writeback Queue) had to retry.= : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2743,8 +3353,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2752,8 +3364,10 @@ }, { "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", "UMask": "0x1", @@ -2761,8 +3375,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoop for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoop for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= broadcast snoops issued by the HA. This filter includes only requests comi= ng from local sockets.", "UMask": "0x10", @@ -2770,8 +3386,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Re= quests : Counts the number of snoops issued by the HA. : Counts the number = of broadcast snoops issued by the HA.This filter includes only requests com= ing from remote sockets.", "UMask": "0x20", @@ -2779,8 +3397,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA. This filter includes only requests comin= g from local sockets.", "UMask": "0x40", @@ -2788,8 +3408,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Remote Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Remote Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f directed snoops issued by the HA. This filter includes only requests comi= ng from remote sockets.", "UMask": "0x80", @@ -2797,8 +3419,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast or directed Snoops se= nt for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast or directed Snoops s= ent for Local Requests : Counts the number of snoops issued by the HA. : Co= unts the number of broadcast or directed snoops issued by the HA per reques= t. This filter includes only requests coming from the local socket.", "UMask": "0x4", @@ -2806,8 +3430,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast or directed Snoops se= nt for Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast or directed Snoops s= ent for Remote Requests : Counts the number of snoops issued by the HA. : C= ounts the number of broadcast or directed snoops issued by the HA per reque= st. This filter includes only requests coming from the remote socket.", "UMask": "0x8", @@ -2815,8 +3441,10 @@ }, { "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for snoops responses of RspC= onflict. This is returned when a snoop finds an existing outstanding trans= action in a remote caching agent when it CAMs that caching agent. This tri= ggers conflict resolution hardware. This covers both RspCnflct and RspCnfl= ctWbI.", "UMask": "0x40", @@ -2824,8 +3452,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RspFwd : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspFwd t= o a CA request. This snoop response is only possible for RdCur when a snoo= p HITM/E in a remote caching agent and it directly forwards data to a reque= stor without changing the requestor's cache line state.", "UMask": "0x80", @@ -2833,8 +3463,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for a snoop response of Rsp*= Fwd*WB. This snoop response is only used in 4s systems. It is used when a= snoop HITM's in a remote caching agent and it directly forwards data to a = requestor, and simultaneously returns data to the home to be written back t= o memory.", "UMask": "0x20", @@ -2842,8 +3474,10 @@ }, { "BriefDescription": "RspI Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspI Snoop Response was received which indicates the remote cache does n= ot have the data, or when the remote cache silently evicts data (such as wh= en an RFO: the Read for Ownership issued before a write hits non-modified d= ata).", "UMask": "0x1", @@ -2851,8 +3485,10 @@ }, { "BriefDescription": "RspIFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspIFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data and the requesting agent is able to acquire the dat= a in E (Exclusive) or M (modified) states. This is commonly returned with = RFO (the Read for Ownership issued before a write) transactions. The snoop= could have either been to a cacheline in the M,E,F (Modified, Exclusive or= Forward) states.", "UMask": "0x4", @@ -2860,8 +3496,10 @@ }, { "BriefDescription": "RspS Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspS Snoop Response was received which indicates when a remote cache has= data but is not forwarding it. It is a way to let the requesting socket k= now that it cannot allocate the data in E state. No data is sent with S Rs= pS.", "UMask": "0x2", @@ -2869,8 +3507,10 @@ }, { "BriefDescription": "RspSFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspSFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data but held on to its current copy. This is common fo= r data and code reads that hit in a remote socket in E (Exclusive) or F (Fo= rward) state.", "UMask": "0x8", @@ -2878,8 +3518,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspIWB o= r RspSWB. This is returned when a non-RFO request hits in M state. Data a= nd Code Reads can return either RspIWB or RspSWB depending on how the syste= m has been configured. InvItoE transactions will also return RspIWB becaus= e they must acquire ownership.", "UMask": "0x10", @@ -2887,8 +3529,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", "UMask": "0x40", @@ -2896,8 +3540,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", "UMask": "0x80", @@ -2905,8 +3551,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", "UMask": "0x20", @@ -2914,8 +3562,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", "UMask": "0x1", @@ -2923,8 +3573,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -2932,8 +3584,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", "UMask": "0x2", @@ -2941,8 +3595,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its current copy. This is com= mon for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", @@ -2950,8 +3606,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", "UMask": "0x10", @@ -2959,56 +3617,70 @@ }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0xc001ffff", @@ -3016,16 +3688,20 @@ }, { "BriefDescription": "TOR Inserts : DDR Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DDR Access : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. : TOR allocation occurred as a result of SF/= LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -3033,14 +3709,17 @@ }, { "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; All from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -3050,6 +3729,7 @@ }, { "BriefDescription": "TOR Inserts;CLFlush from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -3059,8 +3739,10 @@ }, { "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; C= LFlushOpt events that are initiated from the Core", "UMask": "0xc8d7ff01", @@ -3068,6 +3750,7 @@ }, { "BriefDescription": "TOR Inserts; CRd from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -3077,8 +3760,10 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", "UMask": "0xc88fff01", @@ -3086,6 +3771,7 @@ }, { "BriefDescription": "TOR Inserts; DRd from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", "PerPkg": "1", @@ -3095,8 +3781,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -3104,8 +3792,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t misses in the snoop filter", "UMask": "0xc827ff01", @@ -3113,8 +3803,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that misses in the snoop filter", "UMask": "0xc8a7ff01", @@ -3122,6 +3814,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", "PerPkg": "1", @@ -3131,6 +3824,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -3140,6 +3834,7 @@ }, { "BriefDescription": "TOR Inserts; CRd hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -3149,6 +3844,7 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -3158,16 +3854,20 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018101", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008101", @@ -3175,6 +3875,7 @@ }, { "BriefDescription": "TOR Inserts; DRd hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", "PerPkg": "1", @@ -3184,8 +3885,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837fd01", @@ -3193,8 +3896,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t hits in the snoop filter", "UMask": "0xc827fd01", @@ -3202,8 +3907,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that hits in the snoop filter", "UMask": "0xc8a7fd01", @@ -3211,6 +3918,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", "PerPkg": "1", @@ -3220,8 +3928,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that H= it LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -3229,8 +3939,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA that hits in the snoop filter", "UMask": "0xcccffd01", @@ -3238,8 +3950,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch data = read from local IA that hits in the snoop filter", "UMask": "0xccd7fd01", @@ -3247,6 +3961,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -3256,6 +3971,7 @@ }, { "BriefDescription": "TOR Inserts; RFO hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -3265,6 +3981,7 @@ }, { "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -3274,8 +3991,10 @@ }, { "BriefDescription": "TOR Inserts;ItoM from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; I= toM events that are initiated from the Core", "UMask": "0xcc47ff01", @@ -3283,8 +4002,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cor= es", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -3292,8 +4013,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA.", "UMask": "0xcccfff01", @@ -3301,6 +4024,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefData from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", "PerPkg": "1", @@ -3310,6 +4034,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", "PerPkg": "1", @@ -3319,6 +4044,7 @@ }, { "BriefDescription": "TOR Inserts; misses from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -3328,6 +4054,7 @@ }, { "BriefDescription": "TOR Inserts for CRd misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -3337,16 +4064,20 @@ }, { "BriefDescription": "CRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c80b8201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80efe01", @@ -3354,6 +4085,7 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -3363,8 +4095,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88efe01", @@ -3372,8 +4106,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88f7e01", @@ -3381,8 +4117,10 @@ }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80f7e01", @@ -3390,16 +4128,20 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008201", @@ -3407,6 +4149,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", "PerPkg": "1", @@ -3416,16 +4159,20 @@ }, { "BriefDescription": "DRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8138201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc837fe01", @@ -3433,16 +4180,20 @@ }, { "BriefDescription": "DRds issued from an IA core which miss the L3= and target memory in a CXL type 2 memory expander card.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8178201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8168201", @@ -3450,8 +4201,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8168201", @@ -3459,6 +4212,7 @@ }, { "BriefDescription": "TOR Inserts for DRds issued by IA Cores targe= ting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -3468,6 +4222,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA targ= eting local memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -3477,6 +4232,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", @@ -3486,6 +4242,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", "PerPkg": "1", @@ -3495,8 +4252,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t misses in the snoop filter", "UMask": "0xc827fe01", @@ -3504,8 +4263,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_L= OCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8268201", @@ -3513,8 +4274,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that misses in the snoop filter", "UMask": "0xc8a7fe01", @@ -3522,8 +4285,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_= ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOC= AL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8a68201", @@ -3531,6 +4296,7 @@ }, { "BriefDescription": "TOR Inserts for DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -3540,6 +4306,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", "PerPkg": "1", @@ -3549,16 +4316,20 @@ }, { "BriefDescription": "L2 data prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8978201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8968201", @@ -3566,8 +4337,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8968201", @@ -3575,8 +4348,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8978601", @@ -3584,6 +4359,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= targeting local memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", "PerPkg": "1", @@ -3593,8 +4369,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8968601", @@ -3602,8 +4380,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8968a01", @@ -3611,8 +4391,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8978a01", @@ -3620,6 +4402,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= targeting remote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", "PerPkg": "1", @@ -3629,8 +4412,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8970601", @@ -3638,8 +4423,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8970a01", @@ -3647,6 +4434,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA targ= eting remote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -3656,6 +4444,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", @@ -3665,6 +4454,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", "PerPkg": "1", @@ -3674,8 +4464,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that M= issed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -3683,8 +4475,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA that misses in the snoop filter", "UMask": "0xcccffe01", @@ -3692,14 +4486,17 @@ }, { "BriefDescription": "LLC Prefetch Code transactions issued from an= IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10cccf8201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -3709,16 +4506,20 @@ }, { "BriefDescription": "LLC data prefetches issued from an IA core wh= ich miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccd78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_A= CC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCA= L", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccd68201", @@ -3726,8 +4527,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_E= XP_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_EXP_LOCA= L", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20ccd68201", @@ -3735,6 +4538,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -3744,16 +4548,20 @@ }, { "BriefDescription": "L2 RFO prefetches issued from an IA core whic= h miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8878201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_AC= C_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8868201", @@ -3761,8 +4569,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EX= P_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_EXP_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8868201", @@ -3770,8 +4580,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8668601", @@ -3779,8 +4591,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8668a01", @@ -3788,8 +4602,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86e8601", @@ -3797,8 +4613,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86e8a01", @@ -3806,8 +4624,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8670601", @@ -3815,8 +4635,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8670a01", @@ -3824,8 +4646,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f0601", @@ -3833,8 +4657,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f0a01", @@ -3842,6 +4668,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -3851,24 +4678,30 @@ }, { "BriefDescription": "RFO and L2 RFO prefetches issued from an IA c= ore which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFOMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8038201", "Unit": "CHA" }, { "BriefDescription": "RFOs issued from an IA core which miss the L3= and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8078201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8068201", @@ -3876,8 +4709,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8068201", @@ -3885,6 +4720,7 @@ }, { "BriefDescription": "TOR Inserts RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -3894,6 +4730,7 @@ }, { "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -3903,16 +4740,20 @@ }, { "BriefDescription": "LLC RFO prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccc78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccc68201", @@ -3920,8 +4761,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20ccc68201", @@ -3929,6 +4772,7 @@ }, { "BriefDescription": "TOR Inserts; RFO prefetch misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -3938,6 +4782,7 @@ }, { "BriefDescription": "TOR Inserts; RFO prefetch misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -3947,6 +4792,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -3956,8 +4802,10 @@ }, { "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -3965,8 +4813,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -3974,8 +4824,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -3983,8 +4835,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678601", @@ -3992,8 +4846,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678a01", @@ -4001,8 +4857,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8601", @@ -4010,8 +4868,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8a01", @@ -4019,8 +4879,10 @@ }, { "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -4028,6 +4890,7 @@ }, { "BriefDescription": "TOR Inserts; RFO from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -4037,6 +4900,7 @@ }, { "BriefDescription": "TOR Inserts; RFO pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -4046,6 +4910,7 @@ }, { "BriefDescription": "TOR Inserts;SpecItoM from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", "PerPkg": "1", @@ -4055,8 +4920,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc3fff01", @@ -4064,8 +4931,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc37ff01", @@ -4073,8 +4942,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc2fff01", @@ -4082,8 +4953,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -4091,8 +4964,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc67ff01", @@ -4100,8 +4975,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -4109,8 +4986,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -4118,6 +4997,7 @@ }, { "BriefDescription": "TOR Inserts; All from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", @@ -4127,6 +5007,7 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", "PerPkg": "1", @@ -4136,6 +5017,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -4145,6 +5027,7 @@ }, { "BriefDescription": "TOR Inserts; ItoM hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -4154,6 +5037,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -4163,6 +5047,7 @@ }, { "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from loca= l IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -4172,6 +5057,7 @@ }, { "BriefDescription": "TOR Inserts; RFO hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", "PerPkg": "1", @@ -4181,6 +5067,7 @@ }, { "BriefDescription": "TOR Inserts for ItoM from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -4190,6 +5077,7 @@ }, { "BriefDescription": "TOR Inserts for ItoMCacheNears from IO device= s.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -4199,6 +5087,7 @@ }, { "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", "PerPkg": "1", @@ -4208,6 +5097,7 @@ }, { "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", "PerPkg": "1", @@ -4217,6 +5107,7 @@ }, { "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", "PerPkg": "1", @@ -4226,6 +5117,7 @@ }, { "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", "PerPkg": "1", @@ -4235,6 +5127,7 @@ }, { "BriefDescription": "TOR Inserts; Misses from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -4244,6 +5137,7 @@ }, { "BriefDescription": "TOR Inserts : ItoM, indicating a full cacheli= ne write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -4253,6 +5147,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -4262,6 +5157,7 @@ }, { "BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from = local IO that miss LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -4271,6 +5167,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", "PerPkg": "1", @@ -4280,6 +5177,7 @@ }, { "BriefDescription": "TOR Inserts for RdCur from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -4289,6 +5187,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", "PerPkg": "1", @@ -4298,6 +5197,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", "PerPkg": "1", @@ -4307,6 +5207,7 @@ }, { "BriefDescription": "TOR Inserts; RFO from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", "PerPkg": "1", @@ -4316,6 +5217,7 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", "PerPkg": "1", @@ -4325,8 +5227,10 @@ }, { "BriefDescription": "TOR Inserts : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IPQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x8", @@ -4334,8 +5238,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. : From an iA Core", "UMask": "0x1", @@ -4343,8 +5249,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "UMask": "0x10", @@ -4352,24 +5260,30 @@ }, { "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. : All locally initiated requests", "UMask": "0xc000ff05", @@ -4377,8 +5291,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. : All locally initiated requests from iA Co= res", "UMask": "0xc000ff01", @@ -4386,8 +5302,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. : All locally generated IO traffic", "UMask": "0xc000ff04", @@ -4395,80 +5313,100 @@ }, { "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMIO Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMIO Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PMM Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PM Access : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. : From a PCIe Device", "UMask": "0x4", @@ -4476,8 +5414,10 @@ }, { "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent.", "UMask": "0x20", @@ -4485,16 +5425,20 @@ }, { "BriefDescription": "TOR Inserts : Just Remote Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Remote Targets : Counts t= he number of entries successfully inserted into the TOR that match qualific= ations specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Remote : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. : All remote requests (e.g. snoops, writeback= s) that came from remote sockets", "UMask": "0xc001ffc8", @@ -4502,8 +5446,10 @@ }, { "BriefDescription": "TOR Inserts : All Snoops from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All Snoops from Remote : Count= s the number of entries successfully inserted into the TOR that match quali= fications specified by the subevent. : All snoops to this LLC that came fro= m remote sockets", "UMask": "0xc001ff08", @@ -4511,8 +5457,10 @@ }, { "BriefDescription": "TOR Inserts : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RRQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x40", @@ -4520,48 +5468,60 @@ }, { "BriefDescription": "TOR Inserts for INVXTOM opcodes received from= a remote socket which miss the L3 and target memory in a CXL type 3 memory= expander local to this socket.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_INVXTOM_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e87e8240", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts for RDCODE opcodes received from = a remote socket which miss the L3 and target memory in a CXL type 3 memory = expander local to this socket.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDCODE_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e80e8240", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts for RDCUR opcodes received from a= remote socket which miss the L3 and target memory in a CXL type 3 memory e= xpander local to this socket.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDCUR_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8068240", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts for RDDATA opcodes received from = a remote socket which miss the L3 and target memory in a CXL type 3 memory = expander local to this socket.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDDATA_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8168240", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts for RDINVOWN_OPT opcodes received= from a remote socket which miss the L3 and target memory in a CXL type 3 m= emory expander local to this socket.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS_RDINVOWN_OPT_CXL_EXP_LO= CAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8268240", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; All Snoops from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. Al= l snoops to this LLC that came from remote sockets.", "UMask": "0xc001ff08", @@ -4569,8 +5529,10 @@ }, { "BriefDescription": "TOR Inserts : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WBQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x80", @@ -4578,8 +5540,10 @@ }, { "BriefDescription": "TOR Occupancy : All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0xc001ffff", @@ -4587,16 +5551,20 @@ }, { "BriefDescription": "TOR Occupancy : DDR Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DDR Access : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. T : TOR allocation occurre= d as a result of SF/LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -4604,14 +5572,17 @@ }, { "BriefDescription": "TOR Occupancy : Just Hits", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; All from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4621,6 +5592,7 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", @@ -4630,8 +5602,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4639,6 +5613,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -4648,8 +5623,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4657,6 +5634,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", "PerPkg": "1", @@ -4666,8 +5644,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -4677,8 +5657,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat misses in the snoop filter", "UMask": "0xc827ff01", @@ -4686,8 +5668,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that misses in the snoop filter", "UMask": "0xc8a7ff01", @@ -4695,6 +5679,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", "PerPkg": "1", @@ -4704,6 +5689,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4713,6 +5699,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "PerPkg": "1", @@ -4722,6 +5709,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -4731,16 +5719,20 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018101", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008101", @@ -4748,6 +5740,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "PerPkg": "1", @@ -4757,8 +5750,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -4768,8 +5763,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat hits in the snoop filter", "UMask": "0xc827fd01", @@ -4777,8 +5774,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local I= A", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that hits in the snoop filter", "UMask": "0xc8a7fd01", @@ -4786,6 +5785,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", "PerPkg": "1", @@ -4795,8 +5795,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Hit LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Hit LLC : For each cycle, this event accumulates the number of valid entr= ies in the TOR that match qualifications specified by the subevent. Doe= s not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -4804,8 +5806,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch cod= e read from local IA that hits in the snoop filter", "UMask": "0xcccffd01", @@ -4813,8 +5817,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch dat= a read from local IA that hits in the snoop filter", "UMask": "0xccd7fd01", @@ -4822,6 +5828,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -4831,6 +5838,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "PerPkg": "1", @@ -4840,6 +5848,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -4849,8 +5858,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc47ff01", @@ -4858,8 +5869,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA C= ores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA = Cores : For each cycle, this event accumulates the number of valid entries = in the TOR that match qualifications specified by the subevent. Does no= t include addressless requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -4867,8 +5880,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch dat= a read from local IA.", "UMask": "0xcccfff01", @@ -4876,6 +5891,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", "PerPkg": "1", @@ -4885,6 +5901,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", "PerPkg": "1", @@ -4894,6 +5911,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -4903,6 +5921,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -4912,16 +5931,20 @@ }, { "BriefDescription": "TOR Occupancy for CRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c80b8201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed locally : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc80efe01", @@ -4929,8 +5952,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88ffe01", @@ -4938,8 +5963,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed locally : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc88efe01", @@ -4947,8 +5974,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely : For each cycle, this event accumula= tes the number of valid entries in the TOR that match qualifications specif= ied by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc88f7e01", @@ -4956,8 +5985,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed remotely : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc80f7e01", @@ -4965,16 +5996,20 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008201", @@ -4982,6 +6017,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "PerPkg": "1", @@ -4991,16 +6027,20 @@ }, { "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8138201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -5010,16 +6050,20 @@ }, { "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= memory expander card.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8178201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8168201", @@ -5027,8 +6071,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8168201", @@ -5036,6 +6082,7 @@ }, { "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -5045,6 +6092,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA ta= rgeting local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -5054,6 +6102,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", @@ -5063,6 +6112,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", "PerPkg": "1", @@ -5072,8 +6122,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat misses in the snoop filter", "UMask": "0xc827fe01", @@ -5081,8 +6133,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC= _LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8268201", @@ -5090,8 +6144,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that misses in the snoop filter", "UMask": "0xc8a7fe01", @@ -5099,8 +6155,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CX= L_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_L= OCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8a68201", @@ -5108,6 +6166,7 @@ }, { "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -5117,6 +6176,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", "PerPkg": "1", @@ -5126,16 +6186,20 @@ }, { "BriefDescription": "TOR Occupancy for L2 data prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8978201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_AC= C_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8968201", @@ -5143,8 +6207,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EX= P_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_EXP_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8968201", @@ -5152,8 +6218,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978601", @@ -5161,8 +6229,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc896fe01", @@ -5170,8 +6240,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968601", @@ -5179,8 +6251,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968a01", @@ -5188,8 +6262,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978a01", @@ -5197,6 +6273,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", "PerPkg": "1", @@ -5206,8 +6283,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970601", @@ -5215,8 +6294,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970a01", @@ -5224,6 +6305,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA ta= rgeting remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -5233,6 +6315,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", @@ -5242,6 +6325,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", "PerPkg": "1", @@ -5251,8 +6335,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Missed LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -5260,8 +6346,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local = IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch cod= e read from local IA that misses in the snoop filter", "UMask": "0xcccffe01", @@ -5269,14 +6357,17 @@ }, { "BriefDescription": "TOR Occupancy for LLC Prefetch Code transacti= ons issued from an IA core which miss the L3 and target memory in a CXL typ= e 2 accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10cccf8201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; LLCPrefData misses from local = IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -5286,16 +6377,20 @@ }, { "BriefDescription": "TOR Occupancy for LLC data prefetches issued = from an IA core which miss the L3 and target memory in a CXL type 2 acceler= ator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccd78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL= _ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LO= CAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccd68201", @@ -5303,8 +6398,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL= _EXP_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_EXP_LO= CAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20ccd68201", @@ -5312,6 +6409,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local I= A", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -5321,16 +6419,20 @@ }, { "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued fr= om an IA core which miss the L3 and target memory in a CXL type 2 accelerat= or.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8878201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_= ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOC= AL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8868201", @@ -5338,8 +6440,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_= EXP_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_EXP_LOC= AL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8868201", @@ -5347,8 +6451,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668601", @@ -5356,8 +6462,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668a01", @@ -5365,8 +6473,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8601", @@ -5374,8 +6484,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8a01", @@ -5383,8 +6495,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670601", @@ -5392,8 +6506,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670a01", @@ -5401,8 +6517,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0601", @@ -5410,8 +6528,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0a01", @@ -5419,6 +6539,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -5428,24 +6549,30 @@ }, { "BriefDescription": "TOR Occupancy for RFO and L2 RFO prefetches i= ssued from an IA core which miss the L3 and target memory in a CXL type 2 a= ccelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFOMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8038201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RFOs issued from an IA core= which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8078201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8068201", @@ -5453,8 +6580,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20c8068201", @@ -5462,6 +6591,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -5471,6 +6601,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -5480,16 +6611,20 @@ }, { "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccc78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_AC= C_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccc68201", @@ -5497,8 +6632,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EX= P_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_EXP_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20ccc68201", @@ -5506,6 +6643,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -5515,6 +6653,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -5524,6 +6663,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -5533,8 +6673,10 @@ }, { "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -5542,8 +6684,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -5551,8 +6695,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -5560,8 +6706,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678601", @@ -5569,8 +6717,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678a01", @@ -5578,8 +6728,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8601", @@ -5587,8 +6739,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8a01", @@ -5596,8 +6750,10 @@ }, { "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -5605,6 +6761,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -5614,6 +6771,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", "PerPkg": "1", @@ -5623,6 +6781,7 @@ }, { "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", "PerPkg": "1", @@ -5632,8 +6791,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -5641,8 +6802,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -5650,8 +6813,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -5659,6 +6824,7 @@ }, { "BriefDescription": "TOR Occupancy; All from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", @@ -5668,8 +6834,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -5677,6 +6845,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", @@ -5686,6 +6855,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", "PerPkg": "1", @@ -5695,6 +6865,7 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -5704,6 +6875,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from lo= cal IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -5713,8 +6885,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -5722,6 +6896,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", "PerPkg": "1", @@ -5731,8 +6906,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -5742,6 +6919,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", @@ -5751,6 +6929,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", "PerPkg": "1", @@ -5760,6 +6939,7 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -5769,8 +6949,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC and targets loca= l memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcd42fe04", @@ -5778,8 +6960,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC and targets remo= te memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcd437e04", @@ -5787,8 +6971,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO and = targets local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcc42fe04", @@ -5796,8 +6982,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO and = targets remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcc437e04", @@ -5805,6 +6993,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -5814,8 +7003,10 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO and targets local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc8f2fe04", @@ -5823,8 +7014,10 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO and targets remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc8f37e04", @@ -5832,8 +7025,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -5841,6 +7036,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local I= O", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -5850,8 +7046,10 @@ }, { "BriefDescription": "TOR Occupancy; ItoM from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -5859,8 +7057,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -5868,8 +7068,10 @@ }, { "BriefDescription": "TOR Occupancy : IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x8", @@ -5877,8 +7079,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. T : From an iA Core", "UMask": "0x1", @@ -5886,8 +7090,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "UMask": "0x10", @@ -5895,24 +7101,30 @@ }, { "BriefDescription": "TOR Occupancy : Just ISOC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Local Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. T : All locally in= itiated requests", "UMask": "0xc000ff05", @@ -5920,8 +7132,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. T : All locally initiated= requests from iA Cores", "UMask": "0xc000ff01", @@ -5929,8 +7143,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. T : All locally generated= IO traffic", "UMask": "0xc000ff04", @@ -5938,80 +7154,100 @@ }, { "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Misses", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMCFG Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMIO Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NonCoherent", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NotNearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PMM Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PMM Access : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. T : From a PCIe Device", "UMask": "0x4", @@ -6019,8 +7255,10 @@ }, { "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. T", "UMask": "0x20", @@ -6028,16 +7266,20 @@ }, { "BriefDescription": "TOR Occupancy : Just Remote Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Remote Targets : For ea= ch cycle, this event accumulates the number of valid entries in the TOR tha= t match qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Remote : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. T : All remote requests (e.= g. snoops, writebacks) that came from remote sockets", "UMask": "0xc001ffc8", @@ -6045,8 +7287,10 @@ }, { "BriefDescription": "TOR Occupancy : All Snoops from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All Snoops from Remote : For= each cycle, this event accumulates the number of valid entries in the TOR = that match qualifications specified by the subevent. T : All snoops to th= is LLC that came from remote sockets", "UMask": "0xc001ff08", @@ -6054,8 +7298,10 @@ }, { "BriefDescription": "TOR Occupancy : RRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x40", @@ -6063,48 +7309,60 @@ }, { "BriefDescription": "TOR Occupancy for INVXTOM opcodes received fr= om a remote socket which miss the L3 and target memory in a CXL type 3 memo= ry expander local to this socket.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_INVXTOM_CXL_EXP_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e87e8240", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RDCODE opcodes received fro= m a remote socket which miss the L3 and target memory in a CXL type 3 memor= y expander local to this socket.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDCODE_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e80e8240", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RDCUR opcodes received from= a remote socket which miss the L3 and target memory in a CXL type 3 memory= expander local to this socket.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDCUR_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8068240", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RDDATA opcodes received fro= m a remote socket which miss the L3 and target memory in a CXL type 3 memor= y expander local to this socket.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDDATA_CXL_EXP_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8168240", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RDINVOWN_OPT opcodes receiv= ed from a remote socket which miss the L3 and target memory in a CXL type 3= memory expander local to this socket.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ_MISS_RDINVOWN_OPT_CXL_EXP_= LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20e8268240", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; All Snoops from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. All snoops to this LLC that came from remote sockets.", "UMask": "0xc001ff08", @@ -6112,8 +7370,10 @@ }, { "BriefDescription": "TOR Occupancy : WBQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x80", @@ -6121,8 +7381,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", "UMask": "0x1", @@ -6130,8 +7392,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", "UMask": "0x2", @@ -6139,8 +7403,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", "UMask": "0x1", @@ -6148,8 +7414,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", "UMask": "0x2", @@ -6157,8 +7425,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", "UMask": "0x4", @@ -6166,8 +7436,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", "UMask": "0x8", @@ -6175,8 +7447,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", "UMask": "0x10", @@ -6184,8 +7458,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", "UMask": "0x20", @@ -6193,8 +7469,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x8", @@ -6202,8 +7480,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x4", @@ -6211,8 +7491,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x80", @@ -6220,8 +7502,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x40", @@ -6229,8 +7513,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", "UMask": "0x1", @@ -6238,8 +7524,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", "UMask": "0x10", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json b= /tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json index f3e84fd88de3..ff81f3a6426a 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-cxl.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of lfclk ticks", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x01", "EventName": "UNC_CXLCM_CLOCKTICKS", "PerPkg": "1", @@ -9,390 +10,487 @@ }, { "BriefDescription": "Number of Allocation to Mem Rxx AGF 0", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req AGF0", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req AGF 1", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with AK set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with BE set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of control flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.CTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Headerless flits received= ", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of protocol flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.PROT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with SZ set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.VALID", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of valid messages in the fli= t", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of CRC errors detected", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Init flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.INIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of LLCRD flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Retry flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data Packing bu= ffer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp Packing buf= fer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Rxx Packing buffe= r", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Data = Packing buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Req P= acking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Rsp P= acking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Mem Data Pa= cking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Mem Rxx Pac= king buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with AK set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with BE set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of control flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.CTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Headerless flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of protocol flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.PROT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with SZ set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.VALID", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp1 Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp0 Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Rxx Packing buffe= r", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Counts the number of uclk ticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CXLDP_CLOCKTICKS", "PerPkg": "1", @@ -401,48 +499,60 @@ }, { "BriefDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to M2S Req AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Data AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Req AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Rsp AGF 0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Rsp AGF 1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLDP" diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconne= ct.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.= json index 22bb490e9666..8b1ae9540066 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", "EventCode": "0x0f", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total IRP occupancy of inbound read and writ= e requests to coherent memory. This is effectively the sum of read occupan= cy and write occupancy.", "UMask": "0x4", @@ -10,6 +12,7 @@ }, { "BriefDescription": "IRP Clockticks", + "Counter": "0,1", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -18,6 +21,7 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", @@ -25,6 +29,7 @@ }, { "BriefDescription": "FAF - request insert from TC.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -32,6 +37,7 @@ }, { "BriefDescription": "FAF occupancy", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -39,6 +45,7 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", @@ -46,14 +53,17 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.EVICTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", @@ -62,78 +72,97 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -143,8 +172,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", @@ -152,8 +183,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", "UMask": "0x40", @@ -161,8 +194,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", "UMask": "0x4", @@ -170,8 +205,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", @@ -179,8 +216,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", @@ -188,8 +227,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", @@ -197,8 +238,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -206,8 +249,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -215,8 +260,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -224,6 +271,7 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", @@ -233,8 +281,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -242,62 +292,77 @@ }, { "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -307,132 +372,167 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0x0b", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x05", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x08", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x06", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x09", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x07", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x04", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x0a", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", "EventCode": "0x1c", "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count = as 2", "Unit": "IRP" }, { "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1a", "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1b", "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1d", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0d", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0e", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0x0c", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Request Queue Occupancy : Accumulat= es the number of outstanding outbound requests from the IRP to the switch (= towards the devices). This can be used in conjunction with the allocations= event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "M2M Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", @@ -441,6 +541,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", @@ -448,16 +549,20 @@ }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled : Non Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when direct to core mode, which bypas= ses the CHA, was disabled : Non Cisgress : Counts the number of time non ci= sgress D2C was not honoured by egress due to directory state constraints", "UMask": "0x2", @@ -465,39 +570,49 @@ }, { "BriefDescription": "Counts the time when FM didn't do d2c for fil= l reads (cross tile case)", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : 2LM Hit?", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.PMM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_DIRECT2UPITXN_OVERRIDE.PMM_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a direct to UPI transaction = was overridden. : Counts the number of times D2K wasn't honored even though= the incoming request had d2k set", "UMask": "0x1", @@ -505,24 +620,30 @@ }, { "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgres= s D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Cisgre= ss D2U Ignored : Counts cisgress d2K that was not honored due to directory = constraints", "UMask": "0x4", @@ -530,8 +651,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress= Ignored D2U : Counts the number of time D2K was not honoured by egress due= to directory state constraints", "UMask": "0x1", @@ -539,8 +662,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cis= gress D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Non Ci= sgress D2U Ignored : Counts non cisgress d2K that was not honored due to di= rectory constraints", "UMask": "0x2", @@ -548,8 +673,10 @@ }, { "BriefDescription": "Messages sent direct to the Intel UPI", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times egress did D2K (D= irect to KTI)", "UMask": "0x7", @@ -557,86 +684,107 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -646,6 +794,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -655,6 +804,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -664,6 +814,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -673,86 +824,107 @@ }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x320", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -761,8 +933,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from A to I to non persistent memory (DRAM or= HBM)", "UMask": "0x120", @@ -770,8 +944,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from A to I to non persistent memory (DRAM or HBM)", "UMask": "0x220", @@ -779,8 +955,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from A to S to non persistent memory (DRAM or= HBM)", "UMask": "0x140", @@ -788,8 +966,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from A to S to non persistent memory (DRAM or HBM)", "UMask": "0x240", @@ -797,8 +977,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts any 1lm or 2lm hit data return that w= ould result in directory update to non persistent memory (DRAM or HBM)", "UMask": "0x101", @@ -806,24 +988,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from I to A to non persistent memory (DRAM or= HBM)", "UMask": "0x104", @@ -831,8 +1019,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from I to A to non persistent memory (DRAM or HBM)", "UMask": "0x204", @@ -840,8 +1030,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from I to S to non persistent memory (DRAM or= HBM)", "UMask": "0x102", @@ -849,8 +1041,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would re= sult in directory update from I to S to non persistent memory (DRAM or HBM)= ", "UMask": "0x202", @@ -858,8 +1052,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts any 2lm miss data return that would r= esult in directory update to non persistent memory (DRAM or HBM)", "UMask": "0x201", @@ -867,24 +1063,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from S to A to non persistent memory (DRAM or= HBM)", "UMask": "0x110", @@ -892,8 +1094,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from S to A to non persistent memory (DRAM or HBM)", "UMask": "0x210", @@ -901,8 +1105,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from S to I to non persistent memory (DRAM or= HBM)", "UMask": "0x108", @@ -910,8 +1116,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from S to I to non persistent memory (DRAM or HBM)", "UMask": "0x208", @@ -919,8 +1127,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x80000004", @@ -928,8 +1138,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x80000001", @@ -937,40 +1149,50 @@ }, { "BriefDescription": "Count when Starve Glocab counter is at 7", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_IGR_STARVE_WINNER.MASK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -979,24 +1201,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1005,24 +1233,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1031,24 +1265,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x208", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "Experimental": "1", "PerPkg": "1", "UMask": "0x210", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1057,24 +1297,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1083,24 +1329,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x210", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x208", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1109,62 +1361,77 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x301", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_NMCACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_NMCACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_PMM", "PerPkg": "1", @@ -1173,23 +1440,29 @@ }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1810", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1198,15 +1471,19 @@ }, { "BriefDescription": "From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1215,30 +1492,38 @@ }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1247,32 +1532,40 @@ }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x840", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x820", "Unit": "M2M" }, { "BriefDescription": "PMM - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1282,15 +1575,19 @@ }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1299,15 +1596,19 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1316,30 +1617,38 @@ }, { "BriefDescription": "ISOCH Full Line - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1004", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1348,32 +1657,40 @@ }, { "BriefDescription": "ISOCH Partial - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1008", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1040", "Unit": "M2M" }, { "BriefDescription": "DDR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1020", "Unit": "M2M" }, { "BriefDescription": "PMM - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1383,75 +1700,94 @@ }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1801", "Unit": "M2M" }, { "BriefDescription": "ISOCH Full Line - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1804", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1802", "Unit": "M2M" }, { "BriefDescription": "ISOCH Partial - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1808", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1840", "Unit": "M2M" }, { "BriefDescription": "DDR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1820", "Unit": "M2M" }, { "BriefDescription": "PMM - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", "PerPkg": "1", @@ -1460,143 +1796,179 @@ }, { "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2M" }, { "BriefDescription": ": UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": ": XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", "UMask": "0x5", @@ -1604,108 +1976,135 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCE= PT", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2M_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Clean NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", "PerPkg": "1", @@ -1715,6 +2114,7 @@ }, { "BriefDescription": "Dirty NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", "PerPkg": "1", @@ -1724,8 +2124,10 @@ }, { "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit indicates when a request sent to the= iMC hit in Near Memory. : Counts clean underfill hits due to a partial wri= te", "UMask": "0x4", @@ -1733,8 +2135,10 @@ }, { "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit indicates when a request sent to the= iMC hit in Near Memory. : Counts dirty underfill read hits due to a partia= l write", "UMask": "0x8", @@ -1742,230 +2146,288 @@ }, { "BriefDescription": "UNC_M2M_TAG_MISS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2M_TAG_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CBox AD Credits Empty : Requests", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Requests : No credit= s available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x4", @@ -1973,8 +2435,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Snoops", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Snoops : No credits = available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x8", @@ -1982,8 +2446,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : VNA Messages : No cr= edits available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x1", @@ -1991,8 +2457,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Writebacks : No cred= its available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x2", @@ -2000,6 +2468,7 @@ }, { "BriefDescription": "M3UPI Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M3UPI_CLOCKTICKS", "PerPkg": "1", @@ -2008,31 +2477,39 @@ }, { "BriefDescription": "M3UPI CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "D2C Sent", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_M3UPI_D2C_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2C Sent : Count cases BL sends direct to co= re", "Unit": "M3UPI" }, { "BriefDescription": "D2U Sent", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_M3UPI_D2U_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U comman= d", "Unit": "M3UPI" }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -2040,8 +2517,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -2049,8 +2528,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the= same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share th= e same ring destination. (1 VN0 credit only) : No vn0 and vna credits avail= able to send to M2", "UMask": "0x1", @@ -2058,8 +2539,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO2", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna = credits available to send to M2", "UMask": "0x2", @@ -2067,8 +2550,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO3", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna = credits available to send to M2", "UMask": "0x4", @@ -2076,8 +2561,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO4", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna = credits available to send to M2", "UMask": "0x8", @@ -2085,8 +2572,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x10", @@ -2094,8 +2583,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS= are in single mask. ORs them together", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : All IIO targets for NC= S are in single mask. ORs them together : No vn0 and vna credits available = to send to M2", "UMask": "0x40", @@ -2103,8 +2594,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS cr= edits : No vn0 and vna credits available to send to M2", "UMask": "0x80", @@ -2112,8 +2605,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x20", @@ -2121,8 +2616,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x1", @@ -2130,8 +2627,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x2", @@ -2139,8 +2638,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x4", @@ -2148,8 +2649,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x10", @@ -2157,8 +2660,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x20", @@ -2166,8 +2671,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x8", @@ -2175,8 +2682,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -2184,8 +2693,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -2193,8 +2704,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -2202,8 +2715,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -2211,8 +2726,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -2220,8 +2737,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -2229,8 +2748,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -2238,8 +2759,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -2247,8 +2770,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -2256,8 +2781,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -2265,8 +2792,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -2274,8 +2803,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -2283,8 +2814,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -2292,8 +2825,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -2301,8 +2836,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x10", @@ -2310,8 +2847,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x20", @@ -2319,8 +2858,10 @@ }, { "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 a= nd VN1 arbitration sub-pipelines both produced AD and BL winners (maximum p= ossible parallel winners)", "UMask": "0x80", @@ -2328,8 +2869,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN0 : Arbitration stage made no progress on pending ad vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x1", @@ -2337,8 +2880,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN1 : Arbitration stage made no progress on pending ad vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x2", @@ -2346,8 +2891,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN0 : Arbitration stage made no progress on pending bl vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x4", @@ -2355,8 +2902,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN1 : Arbitration stage made no progress on pending bl vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x8", @@ -2364,8 +2913,10 @@ }, { "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : = VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD= or BL on each side)", "UMask": "0x40", @@ -2373,8 +2924,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -2382,8 +2935,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2391,8 +2946,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2400,8 +2957,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -2409,8 +2968,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2418,8 +2979,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2427,8 +2990,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -2436,8 +3001,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -2445,8 +3012,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2454,8 +3023,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2463,8 +3034,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -2472,8 +3045,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2481,8 +3056,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2490,8 +3067,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -2499,8 +3078,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -2508,8 +3089,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2517,8 +3100,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2526,8 +3111,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -2535,8 +3122,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2544,8 +3133,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2553,8 +3144,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -2562,8 +3155,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -2571,8 +3166,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2580,8 +3177,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2589,8 +3188,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -2598,8 +3199,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2607,8 +3210,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2616,8 +3221,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -2625,8 +3232,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL A= rb", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL = Arb : Number of times message is bypassed around the Ingress Queue : AD is = taking bypass to slot 0 of independent flit while bl message is in arbitrat= ion", "UMask": "0x2", @@ -2634,8 +3243,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle= ", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idl= e : Number of times message is bypassed around the Ingress Queue : AD is ta= king bypass to slot 0 of independent flit while pipeline is idle", "UMask": "0x1", @@ -2643,8 +3254,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 1 while merging with bl message in same flit", "UMask": "0x4", @@ -2652,8 +3265,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 2 while merging with bl message in same flit", "UMask": "0x8", @@ -2661,8 +3276,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO= ", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIF= O : Indication that at least one packet (flit) is in the bgf (fifo only)", "UMask": "0x1", @@ -2670,8 +3287,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path= ", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any in BGF Pat= h : Indication that at least one packet (flit) is in the bgf path (i.e. pip= e to fifo)", "UMask": "0x2", @@ -2679,8 +3298,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 1", "UMask": "0x10", @@ -2688,8 +3309,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 2", "UMask": "0x20", @@ -2697,8 +3320,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb= : VN0 BL RSP message was blocked from arbitration request due to lack of D= 2K CMP credit", "UMask": "0x4", @@ -2706,8 +3331,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP mes= sage was blocked from arbitration request due to lack of D2K CMP credits", "UMask": "0x8", @@ -2715,8 +3342,10 @@ }, { "BriefDescription": "Credit Occupancy : Credits Consumed", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Credits Consumed : number= of remote vna credits consumed per cycle", "UMask": "0x80", @@ -2724,8 +3353,10 @@ }, { "BriefDescription": "Credit Occupancy : D2K Credits", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : D2K Credits : D2K complet= ion fifo credit occupancy (credits in use), accumulated across all cycles", "UMask": "0x10", @@ -2733,8 +3364,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", "UMask": "0x2", @@ -2742,8 +3375,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e= . pipe to fifo or fifo)", "UMask": "0x4", @@ -2751,8 +3386,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in completion fifo only", "UMask": "0x40", @@ -2760,8 +3397,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in marker table and in fifo", "UMask": "0x20", @@ -2769,8 +3408,10 @@ }, { "BriefDescription": "Credit Occupancy : Transmit Credits", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Transmit Credits : Link l= ayer transmit queue credit occupancy (credits in use), accumulated across a= ll cycles", "UMask": "0x8", @@ -2778,8 +3419,10 @@ }, { "BriefDescription": "Credit Occupancy : VNA In Use", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI V= NA credit occupancy (number of credits in use), accumulated across all cycl= es", "UMask": "0x1", @@ -2787,8 +3430,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : REQ on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : REQ on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Home (REQ) me= ssages on AD. REQ is generally used to send requests, request responses, a= nd snoop responses.", "UMask": "0x1", @@ -2796,8 +3441,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on AD. RSP packets are used to transmit a variety of protocol f= lits including grants and completions (CMP).", "UMask": "0x4", @@ -2805,8 +3452,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : SNP on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : SNP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Snoops (SNP) = messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2814,8 +3463,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCB on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCB on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Broadcast (NCB) messages on BL. NCB is generally used to transmit data wit= hout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -2823,8 +3474,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCS on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCS on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2832,8 +3485,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on BL. RSP packets are used to transmit a variety of protocol fl= its including grants and completions (CMP).", "UMask": "0x8", @@ -2841,8 +3496,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : WB on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : WB on BL : Counts the number of cycles when the UPI Ingress is not em= pty. This tracks one of the three rings that are used by the UPI agent. T= his can be used in conjunction with the UPI Ingress Occupancy Accumulator e= vent in order to calculate average queue occupancy. Multiple ingress buffe= rs can be tracked at a given time using multiple counters. : Data Response = (WB) messages on BL. WB is generally used to transmit data with coherency.= For example, remote reads and writes, or cache to cache transfers will tr= ansmit their data using WB.", "UMask": "0x10", @@ -2850,8 +3507,10 @@ }, { "BriefDescription": "Data Flit Not Sent : All", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : All : Data flit is read= y for transmission but could not be sent : data flit is ready for transmiss= ion but could not be sent for any reason, e.g. low credits, low tsv, stall = injection", "UMask": "0x1", @@ -2859,8 +3518,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x8", @@ -2868,8 +3529,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x10", @@ -2877,8 +3540,10 @@ }, { "BriefDescription": "Data Flit Not Sent : TSV High", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is= ready for transmission but could not be sent : data flit is ready for tran= smission but was not sent while tsv high", "UMask": "0x2", @@ -2886,8 +3551,10 @@ }, { "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : = Data flit is ready for transmission but could not be sent : data flit is re= ady for transmission but was not sent while cycle is valid for flit transmi= ssion", "UMask": "0x4", @@ -2895,8 +3562,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 0", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 0 : generating bl data flit sequence; waiting for data pump 0", "UMask": "0x1", @@ -2904,8 +3573,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at capacity (pending table plus completion fifo at limit)", "UMask": "0x10", @@ -2913,8 +3584,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is tracking at least one message", "UMask": "0x8", @@ -2922,8 +3595,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding completion fifo is full", "UMask": "0x40", @@ -2931,8 +3606,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at or near capacity, such that pump-0-only bl messages are g= etting stalled in slotting stage", "UMask": "0x20", @@ -2940,8 +3617,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : a bl mess= age finished but is in limbo and moved to pump-1-pending logic", "UMask": "0x4", @@ -2949,8 +3628,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 1", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 1 : generating bl data flit sequence; waiting for data pump 1", "UMask": "0x2", @@ -2958,8 +3639,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request naturally serviced during h= old-off period", "UMask": "0x4", @@ -2967,8 +3650,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request forcibly serviced during se= rvice window", "UMask": "0x8", @@ -2976,8 +3661,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request received from link layer wh= ile idle (with no slot 2 request active immediately prior)", "UMask": "0x1", @@ -2985,8 +3672,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request withdrawn during hold-off p= eriod or service window", "UMask": "0x2", @@ -2994,16 +3683,20 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : All", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit : Needs = Data Flit", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Needs= Data Flit : BL message requires data flit sequence", "UMask": "0x2", @@ -3011,8 +3704,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 0", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 0 : Waiting for header pump 0", "UMask": "0x4", @@ -3020,8 +3715,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 : Header pump 1 is not required for flit", "UMask": "0x10", @@ -3029,8 +3726,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Bubble", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit tra= nsmission delayed", "UMask": "0x20", @@ -3038,8 +3737,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Not Avail", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not a= vailable", "UMask": "0x40", @@ -3047,8 +3748,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 1", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 1 : Waiting for header pump 1", "UMask": "0x8", @@ -3056,8 +3759,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events re= lated to Header Flit Generation - Set 1 : Header flit slotting control stat= e machine is in any accumulate state; multi-message flit may be assembled o= ver multiple cycles", "UMask": "0x1", @@ -3065,8 +3770,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Eve= nts related to Header Flit Generation - Set 1 : header flit slotting contro= l state machine is in accum_ready state; flit is ready to send but transmis= sion is blocked; more messages may be slotted into flit", "UMask": "0x2", @@ -3074,8 +3781,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Ev= ents related to Header Flit Generation - Set 1 : Flit is being assembled ov= er multiple cycles, but no additional message is being slotted into flit in= current cycle; accumulate cycle is wasted", "UMask": "0x4", @@ -3083,8 +3792,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : = Events related to Header Flit Generation - Set 1 : Header flit slotting ent= ered run-ahead state; new header flit is started while transmission of prio= r, fully assembled flit is blocked", "UMask": "0x8", @@ -3092,8 +3803,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: message was slotted only after= run-ahead was over; run-ahead mode definitely wasted", "UMask": "0x80", @@ -3101,8 +3814,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : = Events related to Header Flit Generation - Set 1 : run-ahead mode: one mess= age slotted during run-ahead", "UMask": "0x10", @@ -3110,8 +3825,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: second message slotted immedia= tely after run-ahead; potential run-ahead success", "UMask": "0x20", @@ -3119,8 +3836,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: two (or three) message flit se= nt immediately after run-ahead; complete run-ahead success", "UMask": "0x40", @@ -3128,8 +3847,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events r= elated to Header Flit Generation - Set 2 : new header flit construction may= proceed in parallel with data flit sequence", "UMask": "0x4", @@ -3137,8 +3858,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished= : Events related to Header Flit Generation - Set 2 : header flit finished = assembly in parallel with data flit sequence", "UMask": "0x10", @@ -3146,8 +3869,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Eve= nts related to Header Flit Generation - Set 2 : message is slotted into hea= der flit in parallel with data flit sequence", "UMask": "0x8", @@ -3155,8 +3880,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : = Events related to Header Flit Generation - Set 2 : Rate-matching stall inje= cted", "UMask": "0x1", @@ -3164,8 +3891,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - N= o Message", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - = No Message : Events related to Header Flit Generation - Set 2 : Rate matchi= ng stall injected, but no additional message slotted during stall cycle", "UMask": "0x2", @@ -3173,8 +3902,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message : One message= in flit; VNA or non-VNA flit", "UMask": "0x1", @@ -3182,8 +3913,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message in non-VNA : = One message in flit; non-VNA flit", "UMask": "0x8", @@ -3191,8 +3924,10 @@ }, { "BriefDescription": "Sent Header Flit : Two Messages", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Two Messages : Two messag= es in flit; VNA flit", "UMask": "0x2", @@ -3200,8 +3935,10 @@ }, { "BriefDescription": "Sent Header Flit : Three Messages", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Three Messages : Three me= ssages in flit; VNA flit", "UMask": "0x4", @@ -3209,32 +3946,40 @@ }, { "BriefDescription": "Sent Header Flit : One Slot Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : Two Slots Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : All Slots Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "Header Not Sent : All", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : All : header flit is ready= for transmission but could not be sent : header flit is ready for transmis= sion but could not be sent for any reason, e.g. no credits, low tsv, stall = injection", "UMask": "0x1", @@ -3242,8 +3987,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits : header fl= it is ready for transmission but could not be sent : No BGF credits availab= le", "UMask": "0x8", @@ -3251,8 +3998,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits + No Extra M= essage Slotted", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No BGF credits available; no additional message slotted into flit", "UMask": "0x20", @@ -3260,8 +4009,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits : header fl= it is ready for transmission but could not be sent : No TxQ credits availab= le", "UMask": "0x10", @@ -3269,8 +4020,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra M= essage Slotted", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No TxQ credits available; no additional message slotted into flit", "UMask": "0x40", @@ -3278,8 +4031,10 @@ }, { "BriefDescription": "Header Not Sent : TSV High", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : TSV High : header flit is = ready for transmission but could not be sent : header flit is ready for tra= nsmission but was not sent while tsv high", "UMask": "0x2", @@ -3287,8 +4042,10 @@ }, { "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : Cycle valid for Flit : hea= der flit is ready for transmission but could not be sent : header flit is r= eady for transmission but was not sent while cycle is valid for flit transm= ission", "UMask": "0x4", @@ -3296,8 +4053,10 @@ }, { "BriefDescription": "Message Held : Can't Slot AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot AD : some AD messa= ge could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x10", @@ -3305,8 +4064,10 @@ }, { "BriefDescription": "Message Held : Can't Slot BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot BL : some BL messa= ge could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x20", @@ -3314,8 +4075,10 @@ }, { "BriefDescription": "Message Held : Parallel Attempt", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Attempt : ad and bl = messages attempted to slot into the same flit in parallel", "UMask": "0x4", @@ -3323,8 +4086,10 @@ }, { "BriefDescription": "Message Held : Parallel Success", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Success : ad and bl = messages were actually slotted into the same flit in parallel", "UMask": "0x8", @@ -3332,8 +4097,10 @@ }, { "BriefDescription": "Message Held : VN0", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN0 : vn0 message(s) that cou= ldn't be slotted into last vn0 flit are held in slotting stage while proces= sing vn1 flit", "UMask": "0x1", @@ -3341,8 +4108,10 @@ }, { "BriefDescription": "Message Held : VN1", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN1 : vn1 message(s) that cou= ldn't be slotted into last vn1 flit are held in slotting stage while proces= sing vn0 flit", "UMask": "0x2", @@ -3350,8 +4119,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -3359,8 +4130,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -3368,8 +4141,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -3377,8 +4152,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -3386,8 +4163,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -3395,8 +4174,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -3404,8 +4185,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -3413,8 +4196,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -3422,8 +4207,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -3431,8 +4218,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -3440,8 +4229,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -3449,8 +4240,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -3458,8 +4251,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -3467,8 +4262,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -3476,8 +4273,10 @@ }, { "BriefDescription": "Remote VNA Credits : Any In Use", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Any In Use : At least o= ne remote vna credit is in use", "UMask": "0x20", @@ -3485,8 +4284,10 @@ }, { "BriefDescription": "Remote VNA Credits : Corrected", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Corrected : Number of r= emote vna credits corrected (local return) per cycle", "UMask": "0x1", @@ -3494,8 +4295,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 1", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna = credit level is less than 1 (i.e. no vna credits available)", "UMask": "0x2", @@ -3503,8 +4306,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 10", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna= credit level is less than 10; parallel vn0/vn1 arb not possible", "UMask": "0x10", @@ -3512,8 +4317,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 4", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna = credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", "UMask": "0x4", @@ -3521,8 +4328,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 5", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna = credit level is less than 5; parallel ad/bl arb on vna not possible", "UMask": "0x8", @@ -3530,8 +4339,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 5 an= d allocation to ad or bl messages was required", "UMask": "0x2", @@ -3539,8 +4350,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT1= 0", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 10 a= nd allocation to vn0 or vn1 was required", "UMask": "0x1", @@ -3548,8 +4361,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x10", @@ -3557,8 +4372,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x20", @@ -3566,8 +4383,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn0, not to vn1", "UMask": "0x4", @@ -3575,8 +4394,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x40", @@ -3584,8 +4405,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x80", @@ -3593,8 +4416,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn1, not to vn0", "UMask": "0x8", @@ -3602,8 +4427,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -3611,8 +4438,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -3620,8 +4449,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x2", @@ -3629,8 +4460,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x8", @@ -3638,8 +4471,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -3647,8 +4482,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -3656,8 +4493,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x20", @@ -3665,8 +4504,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x80", @@ -3674,8 +4515,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3684,8 +4527,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x1", @@ -3693,8 +4538,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x2", @@ -3702,8 +4549,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x4", @@ -3711,8 +4560,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x8", @@ -3720,8 +4571,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x1", @@ -3729,8 +4582,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x4", @@ -3738,8 +4593,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x2", @@ -3747,8 +4604,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x8", @@ -3756,8 +4615,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x10", @@ -3765,8 +4626,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x40", @@ -3774,8 +4637,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x20", @@ -3783,8 +4648,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x80", @@ -3792,8 +4659,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -3801,8 +4670,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -3810,8 +4681,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -3819,8 +4692,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -3828,8 +4703,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -3837,8 +4714,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -3846,8 +4725,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -3855,78 +4736,98 @@ }, { "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Occupancy", + "Counter": "0", "EventCode": "0x1e", "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -3934,8 +4835,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x8", @@ -3943,8 +4846,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -3952,8 +4857,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x2", @@ -3961,8 +4868,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -3970,8 +4879,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x80", @@ -3979,8 +4890,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -3988,8 +4901,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x20", @@ -3997,8 +4912,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x1", @@ -4006,8 +4923,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x4", @@ -4015,8 +4934,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x2", @@ -4024,8 +4945,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x8", @@ -4033,8 +4956,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x10", @@ -4042,8 +4967,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x40", @@ -4051,8 +4978,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x20", @@ -4060,8 +4989,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x80", @@ -4069,8 +5000,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -4078,8 +5011,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -4087,8 +5022,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -4096,8 +5033,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -4105,8 +5044,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -4114,8 +5055,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -4123,8 +5066,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x80", @@ -4132,8 +5077,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -4141,120 +5088,150 @@ }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x2", @@ -4262,8 +5239,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x8", @@ -4271,8 +5250,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x4", @@ -4280,8 +5261,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x10", @@ -4289,8 +5272,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x40", @@ -4298,8 +5283,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x20", @@ -4307,8 +5294,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VNA", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits ava= ilable to send to UPIs on the AD Ring", "UMask": "0x1", @@ -4316,8 +5305,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x4", @@ -4325,8 +5316,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x2", @@ -4334,8 +5327,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x8", @@ -4343,8 +5338,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x20", @@ -4352,8 +5349,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x10", @@ -4361,8 +5360,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x40", @@ -4370,8 +5371,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VNA", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits ava= ilable to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", "UMask": "0x1", @@ -4379,16 +5382,20 @@ }, { "BriefDescription": "FlowQ Generated Prefetch", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "FlowQ Generated Prefetch : Count cases where= FlowQ causes spawn of Prefetch to iMC/SMI3 target", "Unit": "M3UPI" }, { "BriefDescription": "VN0 Credit Used : WB on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : WB on BL : Number of times= a VN0 credit was used on the DRS message channel. In order for a request = to be transferred across UPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN0.= VNA is a shared pool used to achieve high performance. The VN0 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN0 if= they fail. This counts the number of times a VN0 credit was used. Note t= hat a single VN0 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN0 will only count a single credit ev= en though it may use multiple buffers. : Data Response (WB) messages on BL.= WB is generally used to transmit data with coherency. For example, remot= e reads and writes, or cache to cache transfers will transmit their data us= ing WB.", "UMask": "0x10", @@ -4396,8 +5403,10 @@ }, { "BriefDescription": "VN0 Credit Used : NCB on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : NCB on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -4405,8 +5414,10 @@ }, { "BriefDescription": "VN0 Credit Used : REQ on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : REQ on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4414,8 +5425,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -4423,8 +5436,10 @@ }, { "BriefDescription": "VN0 Credit Used : SNP on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : SNP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -4432,8 +5447,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -4441,8 +5458,10 @@ }, { "BriefDescription": "VN0 No Credits : WB on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles= there were no VN0 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -4450,8 +5469,10 @@ }, { "BriefDescription": "VN0 No Credits : NCB on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycle= s there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -4459,8 +5480,10 @@ }, { "BriefDescription": "VN0 No Credits : REQ on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycle= s there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4468,8 +5491,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -4477,8 +5502,10 @@ }, { "BriefDescription": "VN0 No Credits : SNP on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycle= s there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -4486,8 +5513,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -4495,8 +5524,10 @@ }, { "BriefDescription": "VN1 Credit Used : WB on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : WB on BL : Number of times= a VN1 credit was used on the WB message channel. In order for a request t= o be transferred across QPI, it must be guaranteed to have a flit buffer on= the remote socket to sink into. There are two credit pools, VNA and VN1. = VNA is a shared pool used to achieve high performance. The VN1 pool has r= eserved entries for each message class and is used to prevent deadlock. Re= quests first attempt to acquire a VNA credit, and then fall back to VN1 if = they fail. This counts the number of times a VN1 credit was used. Note th= at a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that = case uses 9 credits. A transfer on VN1 will only count a single credit eve= n though it may use multiple buffers. : Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote= reads and writes, or cache to cache transfers will transmit their data usi= ng WB.", "UMask": "0x10", @@ -4504,8 +5535,10 @@ }, { "BriefDescription": "VN1 Credit Used : NCB on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : NCB on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messa= ges on BL. NCB is generally used to transmit data without coherency. For = example, non-coherent read data returns.", "UMask": "0x20", @@ -4513,8 +5546,10 @@ }, { "BriefDescription": "VN1 Credit Used : REQ on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : REQ on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Home (REQ) messages on AD. REQ is= generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4522,8 +5557,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on AD. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x4", @@ -4531,8 +5568,10 @@ }, { "BriefDescription": "VN1 Credit Used : SNP on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : SNP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP = is used for outgoing snoops.", "UMask": "0x2", @@ -4540,8 +5579,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on BL. RSP= packets are used to transmit a variety of protocol flits including grants = and completions (CMP).", "UMask": "0x8", @@ -4549,8 +5590,10 @@ }, { "BriefDescription": "VN1 No Credits : WB on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles= there were no VN1 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -4558,8 +5601,10 @@ }, { "BriefDescription": "VN1 No Credits : NCB on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycle= s there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -4567,8 +5612,10 @@ }, { "BriefDescription": "VN1 No Credits : REQ on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycle= s there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4576,8 +5623,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -4585,8 +5634,10 @@ }, { "BriefDescription": "VN1 No Credits : SNP on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycle= s there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -4594,8 +5645,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -4603,168 +5656,210 @@ }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x82", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message is making arbitration= request", "UMask": "0x4", @@ -4772,8 +5867,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message arrived in ingress pi= peline", "UMask": "0x1", @@ -4781,8 +5878,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message took bypass path", "UMask": "0x2", @@ -4790,8 +5889,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was slotted into flit= (non bypass)", "UMask": "0x10", @@ -4799,8 +5900,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message lost arbitration", "UMask": "0x8", @@ -4808,8 +5911,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t became too old", "UMask": "0x20", @@ -4817,8 +5922,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t was overwritten by new message while prefetch queue was full", "UMask": "0x40", @@ -4826,8 +5933,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AD Bounceable)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Bounceable : Number of allocations into t= he CRS Egress", "UMask": "0x1", @@ -4835,8 +5944,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AD credited)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD credited : Number of allocations into the= CRS Egress", "UMask": "0x2", @@ -4844,8 +5955,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AK)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AK : Number of allocations into the CRS Egre= ss", "UMask": "0x10", @@ -4853,8 +5966,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AKC)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AKC : Number of allocations into the CRS Egr= ess", "UMask": "0x40", @@ -4862,8 +5977,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (BL Bounceable)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Bounceable : Number of allocations into t= he CRS Egress", "UMask": "0x4", @@ -4871,8 +5988,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (BL credited)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL credited : Number of allocations into the= CRS Egress", "UMask": "0x8", @@ -4880,8 +5999,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (IV)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IV : Number of allocations into the CRS Egre= ss", "UMask": "0x20", @@ -4889,8 +6010,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AD)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x1", @@ -4898,8 +6021,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AK)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AK : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x4", @@ -4907,8 +6032,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AKC : Number of cycles incoming messages fro= m the vertical ring that are bounced at the SBO", "UMask": "0x10", @@ -4916,8 +6043,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (BL)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x2", @@ -4925,8 +6054,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (IV)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IV : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x8", @@ -4934,8 +6065,10 @@ }, { "BriefDescription": "Counts the number of cycles when the distress= signals are asserted based on SBO Ingress threshold", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_MDF_FAST_ASSERTED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD bnc : Counts the number of cycles when th= e distress signals are asserted based on SBO Ingress threshold", "UMask": "0x1", @@ -4943,8 +6076,10 @@ }, { "BriefDescription": "Counts the number of cycles when the distress= signals are asserted based on SBO Ingress threshold", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_MDF_FAST_ASSERTED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL bnc : Counts the number of cycles when th= e distress signals are asserted based on SBO Ingress threshold", "UMask": "0x2", @@ -4952,6 +6087,7 @@ }, { "BriefDescription": "UPI Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -4960,8 +6096,10 @@ }, { "BriefDescription": "Direct packet attempts : D2C", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2C : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x1", @@ -4969,8 +6107,10 @@ }, { "BriefDescription": "Direct packet attempts : D2K", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2K : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x2", @@ -4978,70 +6118,87 @@ }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", @@ -5050,246 +6207,308 @@ }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_UPI_POWER_L1_NACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req Nack : Counts the number of times a l= ink sends/receives a LinkReqNAck. When the UPI links would like to change = power state, the Tx side initiates a request to the Rx side requesting to c= hange states. This requests can either be accepted or denied. If the Rx s= ide replies with an Ack, the power mode will change. If it replies with NA= ck, no change will take place. This can be filtered based on Rx and Tx. A= n Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx origi= nally requested the power change). A Tx LinkReqNAck refers to sending this= command (meaning the peer agent's Tx originally requested the power change= and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "L1 Req (same as L1 Ack).", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_UPI_POWER_L1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number= of times a link sends/receives a LinkReqAck. When the UPI links would lik= e to change power state, the Tx side initiates a request to the Rx side req= uesting to change states. This requests can either be accepted or denied. = If the Rx side replies with an Ack, the power mode will change. If it rep= lies with NAck, no change will take place. This can be filtered based on R= x and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent'= s Tx originally requested the power change). A Tx LinkReqAck refers to sen= ding this command (meaning the peer agent's Tx originally requested the pow= er change and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles s= pent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lane= s, decreasing our bandwidth in order to save power. It increases snoop and= data transfer latencies and decreases overall bandwidth. This mode can be= very useful in NUMA optimized workloads that largely only utilize UPI for = snoops and their responses. Use edge detect to count the number of instanc= es when the UPI link entered L0p. Link power states are per link and per d= irection, so for example the Tx direction could be in one state while Rx wa= s in another.", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.DATA", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.NULL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMa= sk specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcod= e (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Ena= ble R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enabl= e Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even un= der specific opcode match_en cases. Note: If Message Class is disabled, we = expect opcode to also be disabled.", "UMask": "0xe", @@ -5297,8 +6516,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Matc= h based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class E= nable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S= : Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single = Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, = LLCRD) even under specific opcode match_en cases. Note: If Message Class is= disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -5306,8 +6527,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard : Matches on Receive path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xf", @@ -5315,8 +6538,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -5324,8 +6549,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", @@ -5333,8 +6560,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", @@ -5342,8 +6571,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", @@ -5351,40 +6582,50 @@ }, { "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", "EventCode": "0x0b", "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CRC Errors Detected : Number of CRC errors d= etected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for err= or detection. This counts the number of flits where the CRC was able to de= tect an error. After an error has been detected, the UPI agent will send a= request to the transmitting socket to resend the flit (as well as any flit= s that came after it).", "Unit": "UPI" }, { "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "LLR Requests Sent : Number of LLR Requests w= ere transmitted. This should generally be <=3D the number of CRC errors de= tected. If multiple errors are detected before the Rx side receives a LLC_= REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs..", "Unit": "UPI" }, { "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Consumed : Counts the number of t= imes that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Consumed : Counts the number of t= imes that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -5393,6 +6634,7 @@ }, { "BriefDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -5402,6 +6644,7 @@ }, { "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -5410,8 +6653,10 @@ }, { "BriefDescription": "Valid Flits Received : Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Data : Shows legal fl= it time (hides impact of L0p and L0c). : Count Data Flits (which consume al= l slots), but how much to count is based on Slot0-2 mask, so count can be 0= -3 depending on which slots are enabled for counting..", "UMask": "0x8", @@ -5419,8 +6664,10 @@ }, { "BriefDescription": "Valid Flits Received : Idle", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Idle : Shows legal fl= it time (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5428,8 +6675,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables counting of LLC= RD (with non-zero payload). This only applies to slot 2 since LLCRD is only= allowed in slot 2", "UMask": "0x10", @@ -5437,8 +6686,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal = flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. E= nables counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -5446,6 +6697,7 @@ }, { "BriefDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -5455,8 +6707,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Emp= ty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Em= pty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all= zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dua= l slot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -5464,8 +6718,10 @@ }, { "BriefDescription": "Valid Flits Received : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Protocol Header : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables count of protoc= ol headers in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -5473,8 +6729,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits d= etermine types of headers to count.", "UMask": "0x1", @@ -5482,8 +6740,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits d= etermine types of headers to count.", "UMask": "0x2", @@ -5491,8 +6751,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits d= etermine types of headers to count.", "UMask": "0x4", @@ -5500,8 +6762,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x1", @@ -5509,8 +6773,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x2", @@ -5518,8 +6784,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x4", @@ -5527,8 +6795,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x1", @@ -5536,8 +6806,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x2", @@ -5545,8 +6817,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x4", @@ -5554,214 +6828,268 @@ }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles s= pent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lane= s, decreasing our bandwidth in order to save power. It increases snoop and= data transfer latencies and decreases overall bandwidth. This mode can be= very useful in NUMA optimized workloads that largely only utilize UPI for = snoops and their responses. Use edge detect to count the number of instanc= es when the UPI link entered L0p. Link power states are per link and per d= irection, so for example the Tx direction could be in one state while Rx wa= s in another.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.DATA", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.NULL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass : Matches on Transmit path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xe", @@ -5769,8 +7097,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -5778,8 +7108,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard : Matches on Transmit path of a UPI port. Match based on= UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: O= pcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr= Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr E= nable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) eve= n under specific opcode match_en cases. Note: If Message Class is disabled,= we expect opcode to also be disabled.", "UMask": "0xf", @@ -5787,8 +7119,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. = Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Cla= ss Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enab= le S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Sin= gle Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NU= LL, LLCRD) even under specific opcode match_en cases. Note: If Message Clas= s is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -5796,14 +7130,17 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number = of times that an incoming flit was able to bypass the Tx flit buffer and pa= ss directly out the UPI Link. Generally, when data is transmitted across UP= I, it will bypass the TxQ and pass directly to the link. However, the TxQ = will be used with L0p and when LLR occurs, increasing latency to transfer o= ut to the link.", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -5813,8 +7150,10 @@ }, { "BriefDescription": "Valid Flits Sent : All LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All Data : Shows legal fl= it time (hides impact of L0p and L0c).", "UMask": "0x17", @@ -5822,8 +7161,10 @@ }, { "BriefDescription": "Valid Flits Sent : All LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All LLCTRL : Shows legal = flit time (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5831,6 +7172,7 @@ }, { "BriefDescription": "All Null Flits", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -5839,8 +7181,10 @@ }, { "BriefDescription": "Valid Flits Sent : All Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All ProtDDR : Shows legal= flit time (hides impact of L0p and L0c).", "UMask": "0x87", @@ -5848,8 +7192,10 @@ }, { "BriefDescription": "Valid Flits Sent : Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Data : Shows legal flit t= ime (hides impact of L0p and L0c). : Count Data Flits (which consume all sl= ots), but how much to count is based on Slot0-2 mask, so count can be 0-3 d= epending on which slots are enabled for counting..", "UMask": "0x8", @@ -5857,8 +7203,10 @@ }, { "BriefDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit t= ime (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5866,8 +7214,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows l= egal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (= with non-zero payload). This only applies to slot 2 since LLCRD is only all= owed in slot 2", "UMask": "0x10", @@ -5875,8 +7225,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit= time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enabl= es counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -5884,6 +7236,7 @@ }, { "BriefDescription": "Valid Flits Sent : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -5893,8 +7246,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty = : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zer= os is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual sl= ot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -5902,8 +7257,10 @@ }, { "BriefDescription": "Valid Flits Sent : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Protocol Header : Shows l= egal flit time (hides impact of L0p and L0c). : Enables count of protocol h= eaders in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -5911,8 +7268,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits deter= mine types of headers to count.", "UMask": "0x1", @@ -5920,8 +7279,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits deter= mine types of headers to count.", "UMask": "0x2", @@ -5929,8 +7290,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits deter= mine types of headers to count.", "UMask": "0x4", @@ -5938,47 +7301,59 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Allocations : Number of alloc= ations into the UPI Tx Flit Buffer. Generally, when data is transmitted ac= ross UPI, it will bypass the TxQ and pass directly to the link. However, t= he TxQ will be used with L0p and when LLR occurs, increasing latency to tra= nsfer out to the link. This event can be used in conjunction with the Flit= Buffer Occupancy event in order to calculate the average flit buffer lifet= ime.", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the n= umber of flits in the TxQ. Generally, when data is transmitted across UPI,= it will bypass the TxQ and pass directly to the link. However, the TxQ wi= ll be used with L0p and when LLR occurs, increasing latency to transfer out= to the link. This can be used with the cycles not empty event to track ave= rage occupancy, or the allocations event to track average lifetime in the T= xQ.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VNA Credits Pending Return - Occupancy : Num= ber of VNA credits in the Rx side that are waitng to be returned back acros= s the link.", "Unit": "UPI" }, { "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", @@ -5986,8 +7361,10 @@ }, { "BriefDescription": "Message Received : IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", "UMask": "0x4", @@ -5995,8 +7372,10 @@ }, { "BriefDescription": "Message Received : MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", "UMask": "0x2", @@ -6004,8 +7383,10 @@ }, { "BriefDescription": "Message Received : VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", "UMask": "0x1", @@ -6013,152 +7394,190 @@ }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0", "EventCode": "0x4f", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0", "EventCode": "0x4f", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", "UMask": "0x1", @@ -6166,32 +7585,40 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json b/= tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json index 0761980c34a0..91013ced74aa 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-io.json @@ -1,70 +1,167 @@ [ { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x23", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x25", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x26", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x27", "Unit": "iio_free_running" }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "9", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x30", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "10", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x31", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "11", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x32", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "12", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x33", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "13", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x34", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "14", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x35", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "15", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x36", + "Unit": "iio_free_running" + }, + { + "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "16", + "EventCode": "0xff", + "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x37", + "Unit": "iio_free_running" + }, { "BriefDescription": "IIO Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -74,6 +171,7 @@ }, { "BriefDescription": "Free running counter that increments for IIO = clocktick", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", @@ -82,8 +180,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xff", @@ -93,8 +193,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -104,8 +206,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -115,8 +219,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -126,8 +232,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -137,8 +245,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -148,8 +258,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -159,8 +271,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -170,8 +284,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -181,8 +297,10 @@ }, { "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "UMask": "0xff", @@ -190,8 +308,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 0", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -201,8 +321,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 1", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -212,8 +334,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 2", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -223,8 +347,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 3", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -234,8 +360,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -245,8 +373,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 5", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -256,8 +386,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 6", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -267,8 +399,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -278,8 +412,10 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0-7", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -288,6 +424,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -299,6 +436,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -310,6 +448,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -321,6 +460,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -332,6 +472,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -343,6 +484,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -354,6 +496,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -365,6 +508,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -376,8 +520,10 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0-7 = by the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -386,8 +532,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0100", @@ -397,8 +545,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0200", @@ -408,6 +558,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -419,6 +570,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -430,6 +582,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -441,6 +594,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -452,6 +606,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -463,6 +618,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -474,6 +630,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -485,6 +642,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -496,8 +654,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -507,8 +667,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -518,8 +680,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -529,8 +693,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -540,8 +706,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -551,8 +719,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -562,8 +732,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -573,8 +745,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -584,8 +758,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -595,8 +771,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -606,8 +784,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -617,8 +797,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -628,8 +810,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -639,8 +823,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -650,8 +836,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -661,8 +849,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -672,8 +862,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xff", @@ -683,6 +875,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -694,6 +887,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -705,6 +899,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -716,6 +911,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -727,6 +923,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -738,6 +935,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -749,6 +947,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -760,6 +959,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -771,8 +971,10 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 = to Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -781,6 +983,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part0 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -792,6 +995,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part1 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -803,6 +1007,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part2 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -814,6 +1019,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part3 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -825,6 +1031,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -836,6 +1043,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -847,6 +1055,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -858,6 +1067,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -869,8 +1079,10 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 = to Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -879,6 +1091,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part0 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -890,6 +1103,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part1 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -901,6 +1115,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part2 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -912,6 +1127,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part3 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -923,6 +1139,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -934,6 +1151,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -945,6 +1163,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -956,6 +1175,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -967,8 +1187,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -978,8 +1200,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -989,8 +1213,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -1000,8 +1226,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -1011,8 +1239,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -1022,8 +1252,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -1033,8 +1265,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -1044,8 +1278,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -1055,8 +1291,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1066,8 +1304,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1077,8 +1317,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1088,8 +1330,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1099,8 +1343,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1110,8 +1356,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1121,8 +1369,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1132,8 +1382,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1143,8 +1395,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1154,8 +1408,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1165,8 +1421,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1176,8 +1434,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1187,8 +1447,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", @@ -1197,8 +1459,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", @@ -1207,8 +1471,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", @@ -1217,8 +1483,10 @@ }, { "BriefDescription": ": Context cache hits", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", @@ -1227,8 +1495,10 @@ }, { "BriefDescription": ": Context cache lookups", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", @@ -1237,8 +1507,10 @@ }, { "BriefDescription": ": IOTLB lookups first", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", @@ -1247,8 +1519,10 @@ }, { "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a tr= ansaction misses IOTLB, it does a page walk to look up memory and bring in = the relevant page translation. Counts when this page translation is written= to IOTLB.", @@ -1257,8 +1531,10 @@ }, { "BriefDescription": ": IOMMU memory access", + "Counter": "0", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", "UMask": "0xc0", @@ -1266,8 +1542,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -1275,8 +1553,10 @@ }, { "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", "UMask": "0x10", @@ -1284,8 +1564,10 @@ }, { "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", "UMask": "0x2", @@ -1293,8 +1575,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -1302,8 +1586,10 @@ }, { "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", "UMask": "0x20", @@ -1311,8 +1597,10 @@ }, { "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", "UMask": "0x1", @@ -1320,8 +1608,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -1329,8 +1619,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x10", @@ -1338,8 +1630,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -1347,8 +1641,10 @@ }, { "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", @@ -1357,8 +1653,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", @@ -1367,8 +1665,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", @@ -1377,8 +1677,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", @@ -1387,8 +1689,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", @@ -1397,8 +1701,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", @@ -1407,8 +1713,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", @@ -1417,8 +1725,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", @@ -1427,8 +1737,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", @@ -1437,8 +1749,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", @@ -1447,8 +1761,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", @@ -1457,8 +1773,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", @@ -1467,8 +1785,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", @@ -1477,6 +1797,7 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", @@ -1488,8 +1809,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1498,8 +1821,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1508,8 +1833,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1518,8 +1845,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1528,8 +1857,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1538,8 +1869,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1548,8 +1881,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1558,8 +1893,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1568,8 +1905,10 @@ }, { "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", @@ -1577,8 +1916,10 @@ }, { "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1588,8 +1929,10 @@ }, { "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1599,8 +1942,10 @@ }, { "BriefDescription": "PWT occupancy. Does not include 9th bit of o= ccupancy (will undercount if PWT is greater than 255 per cycle).", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", @@ -1609,8 +1954,10 @@ }, { "BriefDescription": "Request Ownership : PCIe Request complete", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1620,8 +1967,10 @@ }, { "BriefDescription": "Request Ownership : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1631,8 +1980,10 @@ }, { "BriefDescription": "Request Ownership : Issuing final read or wri= te of line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1642,8 +1993,10 @@ }, { "BriefDescription": "Request Ownership : Passing data to be writte= n", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1653,8 +2006,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Passing data= to be written", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1664,8 +2019,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Issuing fina= l read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1674,8 +2031,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Request Owne= rship", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1685,8 +2044,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Writing line= ", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1696,8 +2057,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1707,8 +2070,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1718,8 +2083,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1729,8 +2096,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1740,6 +2109,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1751,6 +2121,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1762,6 +2133,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1773,6 +2145,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1784,6 +2157,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1795,6 +2169,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1806,6 +2181,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1817,6 +2193,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1828,6 +2205,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1839,6 +2217,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1850,6 +2229,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1861,6 +2241,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1872,6 +2253,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1883,6 +2265,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1894,6 +2277,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1905,6 +2289,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1916,8 +2301,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -1927,8 +2314,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -1938,8 +2327,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -1949,8 +2340,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -1960,8 +2353,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -1971,8 +2366,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -1982,8 +2379,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -1993,8 +2392,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -2004,6 +2405,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -2015,6 +2417,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -2026,6 +2429,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -2037,6 +2441,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -2048,6 +2453,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -2059,6 +2465,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -2070,6 +2477,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -2081,6 +2489,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -2092,6 +2501,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -2103,6 +2513,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -2114,6 +2525,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -2125,6 +2537,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -2136,6 +2549,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -2147,6 +2561,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -2158,6 +2573,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -2169,6 +2585,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -2180,6 +2597,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -2191,6 +2609,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -2202,6 +2621,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -2213,6 +2633,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -2224,6 +2645,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -2235,6 +2657,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -2246,6 +2669,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -2257,6 +2681,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -2268,8 +2693,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -2279,8 +2706,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -2290,8 +2719,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -2301,8 +2732,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -2312,8 +2745,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -2323,8 +2758,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -2334,8 +2771,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -2345,8 +2784,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -2356,6 +2797,7 @@ }, { "BriefDescription": "M2P Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", @@ -2364,6 +2806,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", @@ -2371,8 +2814,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -2380,8 +2825,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -2389,8 +2836,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x1", @@ -2398,8 +2847,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x2", @@ -2407,8 +2858,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x4", @@ -2416,8 +2869,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x8", @@ -2425,8 +2880,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", @@ -2434,8 +2891,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", @@ -2443,8 +2902,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", "UMask": "0x8", @@ -2452,8 +2913,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", "UMask": "0x10", @@ -2461,8 +2924,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", "UMask": "0x20", @@ -2470,8 +2935,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x1", @@ -2479,8 +2946,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x2", @@ -2488,8 +2957,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x4", @@ -2497,8 +2968,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x8", @@ -2506,8 +2979,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", "UMask": "0x10", @@ -2515,8 +2990,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", "UMask": "0x20", @@ -2524,896 +3001,1120 @@ }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x80", @@ -3421,8 +4122,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x1", @@ -3430,8 +4133,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x2", @@ -3439,8 +4144,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x4", @@ -3448,8 +4155,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x20", @@ -3457,8 +4166,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x40", @@ -3466,8 +4177,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x8", @@ -3475,8 +4188,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x10", @@ -3484,8 +4199,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x80", @@ -3493,8 +4210,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x1", @@ -3502,8 +4221,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x2", @@ -3511,8 +4232,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x4", @@ -3520,8 +4243,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x20", @@ -3529,8 +4254,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x40", @@ -3538,8 +4265,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x8", @@ -3547,8 +4276,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x10", @@ -3556,24 +4287,30 @@ }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3583,8 +4320,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3594,8 +4333,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3605,8 +4346,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.jso= n b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json index 3ff9e9b722c8..aa06088dd26f 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2HBM_CLOCKTICKS", "PerPkg": "1", @@ -8,6 +9,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2HBM_CMS_CLOCKTICKS", "PerPkg": "1", @@ -15,16 +17,20 @@ }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled : Non Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRES= S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of time non cisgress D2C w= as not honoured by egress due to directory state constraints", "UMask": "0x2", @@ -32,47 +38,59 @@ }, { "BriefDescription": "Counts the time when FM didn't do d2c for fil= l reads (cross tile case)", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_CREDITS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgres= s D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -82,8 +100,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -93,8 +113,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cis= gress D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS= ", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -104,86 +126,107 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -193,6 +236,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -202,6 +246,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -211,6 +256,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -220,86 +266,107 @@ }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x320", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -308,8 +375,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -319,8 +388,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -330,8 +401,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -341,8 +414,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -352,8 +427,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -363,24 +440,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -390,8 +473,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -401,8 +486,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -412,8 +499,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -423,8 +512,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -434,24 +525,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -461,8 +558,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -472,8 +571,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -483,8 +584,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -494,64 +597,80 @@ }, { "BriefDescription": "Count distress signalled on AkAd cmp message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on any packet type", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on Bl Cmp message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.BL_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on NM fill write mes= sage", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.CROSSTILE_NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2Cha message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2CHA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2c message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2k message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x80000004", @@ -559,8 +678,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x80000001", @@ -568,8 +689,10 @@ }, { "BriefDescription": "Count when Starve Glocab counter is at 7", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2HBM_IGR_STARVE_WINNER.MASK7", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -578,32 +701,40 @@ }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -612,24 +743,30 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -638,24 +775,30 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x201", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -664,24 +807,30 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -690,64 +839,80 @@ }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x301", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1810", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x810", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x801", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x802", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -756,15 +921,19 @@ }, { "BriefDescription": "From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -773,16 +942,20 @@ }, { "BriefDescription": "ISOCH Full Line - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -790,8 +963,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -799,8 +974,10 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -809,40 +986,50 @@ }, { "BriefDescription": "ISOCH Partial - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1010", "Unit": "M2HBM" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1001", "Unit": "M2HBM" }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1002", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -851,15 +1038,19 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -868,16 +1059,20 @@ }, { "BriefDescription": "ISOCH Full Line - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1004", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -885,8 +1080,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -894,8 +1091,10 @@ }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -904,39 +1103,49 @@ }, { "BriefDescription": "ISOCH Partial - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1008", "Unit": "M2HBM" }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1801", "Unit": "M2HBM" }, { "BriefDescription": "ISOCH Full Line - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1804", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -944,8 +1153,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -953,159 +1164,199 @@ }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1802", "Unit": "M2HBM" }, { "BriefDescription": "ISOCH Partial - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1808", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2HBM" }, { "BriefDescription": ": UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": ": XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", "UMask": "0x5", @@ -1113,80 +1364,100 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1194,8 +1465,10 @@ }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2HBM_RxC_AD.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1204,23 +1477,29 @@ }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2HBM_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2HBM_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2HBM_RxC_BL.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1230,8 +1509,10 @@ }, { "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2HBM_RxC_BL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts anytime a BL packet is added to Ingre= ss", "UMask": "0x1", @@ -1239,61 +1520,77 @@ }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M2HBM_RxC_BL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M2HBM_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M2HBM_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Alloc= ations", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2HBM_TxC_AD.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1303,8 +1600,10 @@ }, { "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Alloc= ations", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2HBM_TxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts anytime a AD packet is added to Egres= s", "UMask": "0x1", @@ -1312,15 +1611,19 @@ }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "UNC_M2HBM_TxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) : Inserts - CMS0 - Near Si= de", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1330,8 +1633,10 @@ }, { "BriefDescription": "BL Egress (to CMS) : Inserts - CMS1 - Far Sid= e", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1341,160 +1646,200 @@ }, { "BriefDescription": "BL Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2HBM_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2HBM_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : = Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : = Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : = Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : = Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Activate due to read, write, underfill, or by= pass", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0xff", @@ -1502,8 +1847,10 @@ }, { "BriefDescription": "Activate due to read", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x11", @@ -1511,8 +1858,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Read in = PCH0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x1", @@ -1520,8 +1869,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Read in = PCH1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x10", @@ -1529,8 +1880,10 @@ }, { "BriefDescription": "HBM Activate Count : Underfill Read transacti= on on Page Empty or Page Miss", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x44", @@ -1538,8 +1891,10 @@ }, { "BriefDescription": "HBM Activate Count", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x4", @@ -1547,8 +1902,10 @@ }, { "BriefDescription": "HBM Activate Count", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x40", @@ -1556,8 +1913,10 @@ }, { "BriefDescription": "Activate due to write", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x22", @@ -1565,8 +1924,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Write in= PCH0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x2", @@ -1574,8 +1935,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Write in= PCH1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x20", @@ -1583,16 +1946,20 @@ }, { "BriefDescription": "All CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xff", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HBM RD_CAS and WR_CAS Commands", "UMask": "0x40", @@ -1600,8 +1967,10 @@ }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HBM RD_CAS and WR_CAS Commands", "UMask": "0x80", @@ -1609,134 +1978,167 @@ }, { "BriefDescription": "Read CAS commands issued (regular and underfi= ll)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xcf", "Unit": "MCHBM" }, { "BriefDescription": "Regular read CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "MCHBM" }, { "BriefDescription": "Underfill read CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "MCHBM" }, { "BriefDescription": "Regular read CAS commands issued (does not in= clude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "MCHBM" }, { "BriefDescription": "Underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf0", "Unit": "MCHBM" }, { "BriefDescription": "HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS = commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "MCHBM" }, { "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "MCHBM" }, { "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pse= udochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "MCHBM" }, { "BriefDescription": "Underfill Read CAS Command in Interleaved Mod= e (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "MCHBM" }, { "BriefDescription": "Underfill Read CAS Command in Regular Mode (6= 4B) in Pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS Command in Regular Mode (64B) in Ps= eudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "MCHBM" }, { "BriefDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_MCHBM_CLOCKTICKS", "PerPkg": "1", @@ -1745,8 +2147,10 @@ }, { "BriefDescription": "HBM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PREALL.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "UMask": "0x1", @@ -1754,8 +2158,10 @@ }, { "BriefDescription": "HBM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PREALL.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "UMask": "0x2", @@ -1763,8 +2169,10 @@ }, { "BriefDescription": "All Precharge Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Precharge All Commands: Counts the number of= times that the precharge all command was sent.", "UMask": "0x3", @@ -1772,15 +2180,19 @@ }, { "BriefDescription": "IMC Clockticks at HCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_MCHBM_HCLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "All precharge events", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0xff", @@ -1788,8 +2200,10 @@ }, { "BriefDescription": "Precharge from MC page table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x88", @@ -1797,8 +2211,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharges from Pag= e Table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Equivalent to PAGE_EMPTY", "UMask": "0x8", @@ -1806,8 +2222,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x80", @@ -1815,8 +2233,10 @@ }, { "BriefDescription": "Precharge due to read on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x11", @@ -1824,8 +2244,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Precharge from read bank scheduler", "UMask": "0x1", @@ -1833,8 +2255,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x10", @@ -1842,8 +2266,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x44", @@ -1851,8 +2277,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x4", @@ -1860,8 +2288,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x40", @@ -1869,8 +2299,10 @@ }, { "BriefDescription": "Precharge due to write on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x22", @@ -1878,8 +2310,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Precharge from write bank scheduler", "UMask": "0x2", @@ -1887,8 +2321,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x20", @@ -1896,46 +2332,58 @@ }, { "BriefDescription": "Counts the number of cycles where the read bu= ffer has greater than UMASK elements. NOTE: Umask must be set to the maxim= um number of elements in the queue (24 entries for SPR).", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_MCHBM_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "Counts the number of inserts into the read bu= ffer.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "MCHBM" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "MCHBM" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "MCHBM" }, { "BriefDescription": "Counts the number of elements in the read buf= fer per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_MCHBM_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Allocations: Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", "UMask": "0x1", @@ -1943,8 +2391,10 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Allocations: Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", "UMask": "0x2", @@ -1952,24 +2402,30 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Occupancy: Accumulates th= e occupancies of the Read Pending Queue each cycle. This can then be used = to calculate both the average occupancy (in conjunction with the number of = cycles not empty) and the average latency (in conjunction with the number o= f allocations). The RPQ is used to schedule reads out to the memory contro= ller and to track the requests. Requests allocate into the RPQ soon after = they enter the memory controller, and need credits for an entry in this buf= fer before being sent from the HA to the iMC. They deallocate after the CAS= command has been issued to memory.", "Unit": "MCHBM" }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Occupancy: Accumulates th= e occupancies of the Read Pending Queue each cycle. This can then be used = to calculate both the average occupancy (in conjunction with the number of = cycles not empty) and the average latency (in conjunction with the number o= f allocations). The RPQ is used to schedule reads out to the memory contro= ller and to track the requests. Requests allocate into the RPQ soon after = they enter the memory controller, and need credits for an entry in this buf= fer before being sent from the HA to the iMC. They deallocate after the CAS= command has been issued to memory.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Allocations: Counts the = number of allocations into the Write Pending Queue. This can then be used = to calculate the average queuing latency (in conjunction with the WPQ occup= ancy count). The WPQ is used to schedule write out to the memory controlle= r and to track the writes. Requests allocate into the WPQ soon after they = enter the memory controller, and need credits for an entry in this buffer b= efore being sent from the CHA to the iMC. They deallocate after being issu= ed. Write requests themselves are able to complete (from the perspective o= f the rest of the system) as soon they have posted to the iMC.", "UMask": "0x1", @@ -1977,8 +2433,10 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Allocations: Counts the = number of allocations into the Write Pending Queue. This can then be used = to calculate the average queuing latency (in conjunction with the WPQ occup= ancy count). The WPQ is used to schedule write out to the memory controlle= r and to track the writes. Requests allocate into the WPQ soon after they = enter the memory controller, and need credits for an entry in this buffer b= efore being sent from the CHA to the iMC. They deallocate after being issu= ed. Write requests themselves are able to complete (from the perspective o= f the rest of the system) as soon they have posted to the iMC.", "UMask": "0x2", @@ -1986,24 +2444,30 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Occupancy: Accumulates t= he occupancies of the Write Pending Queue each cycle. This can then be use= d to calculate both the average queue occupancy (in conjunction with the nu= mber of cycles not empty) and the average latency (in conjunction with the = number of allocations). The WPQ is used to schedule write out to the memor= y controller and to track the writes. Requests allocate into the WPQ soon = after they enter the memory controller, and need credits for an entry in th= is buffer before being sent from the HA to the iMC. They deallocate after = being issued to memory. Write requests themselves are able to complete (fr= om the perspective of the rest of the system) as soon they have posted to t= he iMC. This is not to be confused with actually performing the write. Th= erefore, the average latency for this queue is actually not useful for deco= nstruction intermediate write latencies. So, we provide filtering based on= if the request has posted or not. By using the not posted filter, we can = track how long writes spent in the iMC before completions were sent to the = HA. The posted filter, on the other hand, provides information about how m= uch queueing is actually happening in the iMC for writes before they are ac= tually issued to memory. High average occupancies will generally coincide = with high write major mode counts.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Occupancy: Accumulates t= he occupancies of the Write Pending Queue each cycle. This can then be use= d to calculate both the average queue occupancy (in conjunction with the nu= mber of cycles not empty) and the average latency (in conjunction with the = number of allocations). The WPQ is used to schedule write out to the memor= y controller and to track the writes. Requests allocate into the WPQ soon = after they enter the memory controller, and need credits for an entry in th= is buffer before being sent from the HA to the iMC. They deallocate after = being issued to memory. Write requests themselves are able to complete (fr= om the perspective of the rest of the system) as soon they have posted to t= he iMC. This is not to be confused with actually performing the write. Th= erefore, the average latency for this queue is actually not useful for deco= nstruction intermediate write latencies. So, we provide filtering based on= if the request has posted or not. By using the not posted filter, we can = track how long writes spent in the iMC before completions were sent to the = HA. The posted filter, on the other hand, provides information about how m= uch queueing is actually happening in the iMC for writes before they are ac= tually issued to memory. High average occupancies will generally coincide = with high write major mode counts.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2012,8 +2476,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -2021,8 +2487,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -2030,8 +2498,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2040,8 +2510,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -2049,8 +2521,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -2058,6 +2532,7 @@ }, { "BriefDescription": "Activate due to read, write, underfill, or by= pass", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -2067,6 +2542,7 @@ }, { "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -2076,8 +2552,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Ch= annel 0 : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x40", @@ -2085,8 +2563,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Ch= annel 1 : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x80", @@ -2094,6 +2574,7 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -2103,8 +2584,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xc2", @@ -2112,8 +2595,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xc8", @@ -2121,8 +2606,10 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the t= otal number or DRAM Read CAS commands issued on this channel. This include= s both regular RD CAS commands as well as those with implicit Precharge. = We do not filter based on major mode, as RD_CAS is not issued during WMM (w= ith the exception of underfills).", "UMask": "0xc1", @@ -2130,8 +2617,10 @@ }, { "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill= Read Issued : DRAM RD_CAS and WR_CAS Commands", "UMask": "0xc4", @@ -2139,6 +2628,7 @@ }, { "BriefDescription": "All DRAM write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -2148,8 +2638,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0xd0", @@ -2157,8 +2649,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xe0", @@ -2166,70 +2660,87 @@ }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "iMC" }, { "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pse= udochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "iMC" }, { "BriefDescription": "Underfill Read CAS Command in Interleaved Mod= e (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "iMC" }, { "BriefDescription": "Underfill Read CAS Command in Regular Mode (6= 4B) in Pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "iMC" }, { "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "iMC" }, { "BriefDescription": "Write CAS Command in Regular Mode (64B) in Ps= eudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "iMC" }, { "BriefDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -2239,8 +2750,10 @@ }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "UMask": "0x3", @@ -2248,6 +2761,7 @@ }, { "BriefDescription": "IMC Clockticks at HCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", @@ -2256,30 +2770,37 @@ }, { "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.TOTAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "PMM Read Pending Queue inserts", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M_PMM_RPQ_INSERTS", "PerPkg": "1", @@ -2288,6 +2809,7 @@ }, { "BriefDescription": "PMM Read Pending Queue occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", "PerPkg": "1", @@ -2297,6 +2819,7 @@ }, { "BriefDescription": "PMM Read Pending Queue occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", "PerPkg": "1", @@ -2306,8 +2829,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x10", @@ -2315,8 +2840,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x20", @@ -2324,8 +2851,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the per cycle occupancy of the P= MM Read Pending Queue.", "UMask": "0x4", @@ -2333,8 +2862,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the per cycle occupancy of the P= MM Read Pending Queue.", "UMask": "0x8", @@ -2342,13 +2873,16 @@ }, { "BriefDescription": "PMM (for IXP) Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Write Pending Queue inserts", + "Counter": "0,1,2,3", "EventCode": "0xe7", "EventName": "UNC_M_PMM_WPQ_INSERTS", "PerPkg": "1", @@ -2357,6 +2891,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -2366,6 +2901,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", "PerPkg": "1", @@ -2375,6 +2911,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", "PerPkg": "1", @@ -2384,8 +2921,10 @@ }, { "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy = : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP= DIMM.", "UMask": "0xc", @@ -2393,8 +2932,10 @@ }, { "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy = : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP= DIMM.", "UMask": "0x30", @@ -2402,16 +2943,20 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Channel PPD Cycles : Number of cycles when a= ll the ranks in the channel are in PPD mode. If IBT=3Doff is enabled, then= this can be used to count those cycles. If it is not enabled, then this c= an count the number of cycles when that could have been taken advantage of.= ", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x1", @@ -2419,8 +2964,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x2", @@ -2428,8 +2975,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x4", @@ -2437,8 +2986,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x8", @@ -2446,8 +2997,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -2455,8 +3008,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -2464,14 +3019,17 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Clock-Enabled Self-Refresh : Counts the numb= er of cycles when the iMC is in self-refresh and the iMC still has a clock.= This happens in some package C-states. For example, the PCU may ask the = iMC to enter self-refresh even though some of the cores are still processin= g. One use of this is for Monroe technology. Self-refresh is required dur= ing package C3 and C6, but there is no clock in the iMC at this time, so it= is not possible to count these cases.", "Unit": "iMC" }, { "BriefDescription": "Precharge due to read, write, underfill, or P= GT.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -2481,6 +3039,7 @@ }, { "BriefDescription": "DRAM Precharge commands", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -2490,8 +3049,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharges from Pa= ge Table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharges from P= age Table : Counts the number of DRAM Precharge commands sent on this chann= el. : Equivalent to PAGE_EMPTY", "UMask": "0x8", @@ -2499,8 +3060,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x80", @@ -2508,6 +3071,7 @@ }, { "BriefDescription": "Precharge due to read on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -2517,8 +3081,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to r= ead", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = read : Counts the number of DRAM Precharge commands sent on this channel. := Precharge from read bank scheduler", "UMask": "0x1", @@ -2526,8 +3092,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x10", @@ -2535,8 +3103,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x44", @@ -2544,8 +3114,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x4", @@ -2553,8 +3125,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x40", @@ -2562,6 +3136,7 @@ }, { "BriefDescription": "Precharge due to write on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -2571,8 +3146,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to w= rite", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = write : Counts the number of DRAM Precharge commands sent on this channel. = : Precharge from write bank scheduler", "UMask": "0x2", @@ -2580,8 +3157,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x20", @@ -2589,21 +3168,26 @@ }, { "BriefDescription": "Counts the number of cycles where the read bu= ffer has greater than UMASK elements. This includes reads to both DDR and = PMEM. NOTE: Umask must be set to the maximum number of elements in the que= ue (24 entries for SPR).", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Counts the number of inserts into the read bu= ffer destined for DDR. Does not count reads destined for PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.PCH0", "PerPkg": "1", @@ -2612,6 +3196,7 @@ }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.PCH1", "PerPkg": "1", @@ -2620,45 +3205,56 @@ }, { "BriefDescription": "Counts the number of cycles where there's at = least one element in the read buffer. This includes reads to both DDR and = PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Counts the number of cycles where there's at = least one element in the read buffer. This includes reads to both DDR and = PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NOT_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Counts the number of elements in the read buf= fer, including reads to both DDR and PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", @@ -2668,6 +3264,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", @@ -2677,6 +3274,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -2685,6 +3283,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -2693,294 +3292,368 @@ }, { "BriefDescription": "Scoreboard accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM read completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM write completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM read completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM write completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Alloc", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.ALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Dealloc", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": ": Valid", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Reject", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.VLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M_SB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M_SB_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : PMM", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Me= m", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2989,230 +3662,287 @@ }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.CANARY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : FM r= equests rejected due to full address conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : NM r= equests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : Patr= ol requests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.NEW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.OCC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "2LM Tag check hit in near memory cache (DDR4)= ", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", @@ -3221,6 +3951,7 @@ }, { "BriefDescription": "2LM Tag check miss, no data at this line", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", @@ -3229,6 +3960,7 @@ }, { "BriefDescription": "2LM Tag check miss, existing data may be evic= ted to PMM", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", @@ -3237,6 +3969,7 @@ }, { "BriefDescription": "2LM Tag check hit due to memory read", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.NM_RD_HIT", "PerPkg": "1", @@ -3245,6 +3978,7 @@ }, { "BriefDescription": "2LM Tag check hit due to memory write", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.NM_WR_HIT", "PerPkg": "1", @@ -3253,6 +3987,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", @@ -3262,6 +3997,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", @@ -3271,6 +4007,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -3279,6 +4016,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -3287,8 +4025,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3297,8 +4037,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json= b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json index 8948e85074f0..9482ddaea4d1 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCU PCLK Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", @@ -9,187 +10,235 @@ }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C0 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C3", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C3 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C6", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C6 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0x0a", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json index a1e3b8d2ebe7..609a9549cbf3 100644 --- a/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -156,6 +175,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 2da7a845784a..a53b88154a58 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -7,7 +7,7 @@ GenuineIntel-6-56,v11,broadwellde,core GenuineIntel-6-4F,v22,broadwellx,core GenuineIntel-6-55-[56789ABCDEF],v1.22,cascadelakex,core GenuineIntel-6-9[6C],v1.05,elkhartlake,core -GenuineIntel-6-CF,v1.06,emeraldrapids,core +GenuineIntel-6-CF,v1.09,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.02,grandridge,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 695FF1B373C for ; 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Thu, 20 Jun 2024 11:19:37 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:24 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-11-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 10/37] perf vendor events: Add goldmont counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/goldmont/cache.json | 103 ++++++++++++++++++ .../pmu-events/arch/x86/goldmont/counter.json | 7 ++ .../arch/x86/goldmont/floating-point.json | 3 + .../arch/x86/goldmont/frontend.json | 8 ++ .../pmu-events/arch/x86/goldmont/memory.json | 3 + .../pmu-events/arch/x86/goldmont/other.json | 5 + .../arch/x86/goldmont/pipeline.json | 40 +++++++ .../arch/x86/goldmont/virtual-memory.json | 7 ++ 8 files changed, 176 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/goldmont/counter.json diff --git a/tools/perf/pmu-events/arch/x86/goldmont/cache.json b/tools/per= f/pmu-events/arch/x86/goldmont/cache.json index ee47a09172a1..1a121ef47a99 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Requests rejected by the L2Q", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ALL", "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to ensure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "L1 Cache evictions for dirty data", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Requests rejected by the XQ", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ALL", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "L2 cache request misses", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -77,6 +86,7 @@ }, { "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", @@ -117,6 +130,7 @@ }, { "BriefDescription": "Memory uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Load uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -137,6 +152,7 @@ }, { "BriefDescription": "Store uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Locked load uops retired (Precise event capab= le)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", @@ -157,6 +174,7 @@ }, { "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT", @@ -167,6 +185,7 @@ }, { "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -177,6 +196,7 @@ }, { "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -187,6 +207,7 @@ }, { "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", @@ -194,6 +215,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) that hi= t the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +226,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +237,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, data forwar= ding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +248,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) that mi= ss the L2 cache with a snoop hit in the other processor module, no data for= warding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -234,6 +259,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) that tr= ue miss for the L2 cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -244,6 +270,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -254,6 +281,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -264,6 +292,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -274,6 +303,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -284,6 +314,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -294,6 +325,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +336,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +347,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -324,6 +358,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that miss the L2 cache with a sno= op hit in the other processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +369,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) that true miss for the L2 cache w= ith a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -344,6 +380,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem that = have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -354,6 +391,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem that = hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -364,6 +402,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, data forw= arding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -374,6 +413,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem that = miss the L2 cache with a snoop hit in the other processor module, no data f= orwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -384,6 +424,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem that = true miss for the L2 cache with a snoop miss in the other processor module.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -394,6 +435,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -404,6 +446,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -414,6 +457,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +468,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that miss the L2 cache with a snoop hit in the other proce= ssor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -434,6 +479,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) that true miss for the L2 cache with a snoop miss in the o= ther processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -444,6 +490,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests that = have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -454,6 +501,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", "MSRIndex": "0x1a6", @@ -464,6 +512,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6", @@ -474,6 +523,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6", @@ -484,6 +534,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that miss the L2 cache with a snoop hit i= n the other processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6", @@ -494,6 +545,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions that true miss for the L2 cache with a sn= oop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6", @@ -504,6 +556,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +567,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -524,6 +578,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that miss the L2 cache = with a snoop hit in the other processor module, no data forwarding is requi= red.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +589,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that true miss for the = L2 cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -544,6 +600,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache that are outstanding, p= er cycle, from the time of the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -554,6 +611,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -564,6 +622,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +633,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -584,6 +644,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that miss the L2 cache with a snoop hit in the other processor mo= dule, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -594,6 +655,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that true miss for the L2 cache with a snoop miss in the other pr= ocessor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -604,6 +666,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines that are outstanding, per cycle, from the time of the L2 miss to = when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -614,6 +677,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +688,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -634,6 +699,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -644,6 +710,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that miss the L2 cache wit= h a snoop hit in the other processor module, no data forwarding is required= .", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -654,6 +721,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that true miss for the L2 = cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -664,6 +732,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line that are outstanding, per = cycle, from the time of the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -674,6 +743,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -684,6 +754,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -694,6 +765,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -704,6 +776,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that miss the L2 cache with a snoop hit in the other processor modul= e, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HIT_O= THER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +787,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes that true miss for the L2 cache with a snoop miss in the other proce= ssor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -724,6 +798,7 @@ }, { "BriefDescription": "Counts demand data partial reads, including d= ata in uncacheable (UC) or uncacheable write combining (USWC) memory types = that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +809,7 @@ }, { "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -744,6 +820,7 @@ }, { "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.AN= Y", "MSRIndex": "0x1a6,0x1a7", @@ -754,6 +831,7 @@ }, { "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= TM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +842,7 @@ }, { "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that miss the L2 cache with a= snoop hit in the other processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.HI= T_OTHER_CORE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -774,6 +853,7 @@ }, { "BriefDescription": "Counts partial cache line data writes to unca= cheable write combining (USWC) memory region that true miss for the L2 cac= he with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.L2_MISS.SN= OOP_MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -784,6 +864,7 @@ }, { "BriefDescription": "Counts the number of demand write requests (R= FO) generated by a write to partial data cache line, including the writes t= o uncacheable (UC) and write through (WT), and write protected (WP) types o= f memory that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -794,6 +875,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -804,6 +886,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -814,6 +897,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +908,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that miss the L2 cache with a snoop hit in t= he other processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -834,6 +919,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher that true miss for the L2 cache with a snoop= miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -844,6 +930,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -854,6 +941,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -864,6 +952,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -874,6 +963,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that miss the L2 cache with a snoop hit in the oth= er processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -884,6 +974,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher that true miss for the L2 cache with a snoop miss = in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -894,6 +985,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -904,6 +996,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1007,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -924,6 +1018,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that miss the L2 cache with a snoop hit in the othe= r processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -934,6 +1029,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher that true miss for the L2 cache with a snoop miss i= n the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -944,6 +1040,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -954,6 +1051,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -964,6 +1062,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -974,6 +1073,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -984,6 +1084,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -994,6 +1095,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that miss the L2 cache with a snoop hit in the other = processor module, no data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1106,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions that true miss for the L2 cache with a snoop miss in = the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/counter.json b/tools/p= erf/pmu-events/arch/x86/goldmont/counter.json new file mode 100644 index 000000000000..aa443347b694 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmont/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json b/= tools/perf/pmu-events/arch/x86/goldmont/floating-point.json index a3f03855ca05..0141e214ff39 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the FP divide unit is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.FPDIV", "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Machine clears due to FP assists", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Floating point divide uops retired. (Precise = Event Capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json b/tools/= perf/pmu-events/arch/x86/goldmont/frontend.json index ace2a114b546..249a97cf3f4c 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "BACLEARs asserted for any branch type", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "BACLEARs asserted for conditional branch", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "BACLEARs asserted for return branch", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "PublicDescription": "Counts BACLEARS on return instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length", + "Counter": "0,1,2,3", "EventCode": "0xE9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "MS decode starts", + "Counter": "0,1,2,3", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/memory.json b/tools/pe= rf/pmu-events/arch/x86/goldmont/memory.json index b97642a109ee..abd0fc02afac 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Machine clears due to memory ordering issue", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved as another core is in the process= of modifying the data.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Load uops that split a page (Precise event ca= pable)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "2", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Store uops that split a page (Precise event c= apable)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/other.json b/tools/per= f/pmu-events/arch/x86/goldmont/other.json index c4fd0acb15bc..260b10740644 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles code-fetch stalled due to any reason.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Cycles hardware interrupts are masked", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.MASKED", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cycles pending interrupts are masked", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Hardware interrupts received", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json b/tools/= perf/pmu-events/arch/x86/goldmont/pipeline.json index acb897483a87..013d2d5b50df 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Retired branch instructions (Precise event ca= pable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "2", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", "PEBS": "2", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise event= capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "2", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Retired far branch instructions (Precise even= t capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "2", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "2", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "2", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "2", @@ -63,6 +70,7 @@ }, { "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "2", @@ -72,6 +80,7 @@ }, { "BriefDescription": "Retired near return instructions (Precise eve= nt capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "2", @@ -81,6 +90,7 @@ }, { "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "2", @@ -90,6 +100,7 @@ }, { "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "2", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "2", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "2", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call. (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "2", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "2", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "2", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", "SampleAfterValue": "2000003", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Core cycles when core is not halted", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", @@ -157,6 +175,7 @@ }, { "BriefDescription": "Reference cycles when core is not halted", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "Reference cycles when core is not halted. T= his event uses a programmable general purpose performance counter.", @@ -165,6 +184,7 @@ }, { "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", "SampleAfterValue": "2000003", @@ -172,6 +192,7 @@ }, { "BriefDescription": "Cycles a divider is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.ALL", "PublicDescription": "Counts core cycles if either divide unit is = busy.", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Cycles the integer divide unit is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.IDIV", "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Instructions retired (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", "SampleAfterValue": "2000003", @@ -194,6 +217,7 @@ }, { "BriefDescription": "Instructions retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", @@ -202,6 +226,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", @@ -209,6 +234,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle to recover", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", @@ -217,6 +243,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", @@ -225,6 +252,7 @@ }, { "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "2", @@ -234,6 +262,7 @@ }, { "BriefDescription": "Loads blocked (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL_BLOCK", "PEBS": "2", @@ -243,6 +272,7 @@ }, { "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "2", @@ -252,6 +282,7 @@ }, { "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "2", @@ -261,6 +292,7 @@ }, { "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.UTLB_MISS", "PEBS": "2", @@ -270,6 +302,7 @@ }, { "BriefDescription": "All machine clears", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.ALL", "PublicDescription": "Counts machine clears for any reason.", @@ -277,6 +310,7 @@ }, { "BriefDescription": "Machine clears due to memory disambiguation", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", @@ -285,6 +319,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel(R) architecture processors.", @@ -293,6 +328,7 @@ }, { "BriefDescription": "Uops issued to the back end per cycle", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", @@ -300,6 +336,7 @@ }, { "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UOPS_NOT_DELIVERED.ANY", "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", @@ -307,6 +344,7 @@ }, { "BriefDescription": "Uops retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "2", @@ -315,6 +353,7 @@ }, { "BriefDescription": "Integer divide uops retired. (Precise Event C= apable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "2", @@ -324,6 +363,7 @@ }, { "BriefDescription": "MS uops retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MS", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json index 8c4929a517fa..13b23bbe4226 100644 --- a/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmont/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ITLB misses", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.MISS", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", @@ -39,6 +43,7 @@ }, { "BriefDescription": "Duration of page-walks in cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "PAGE_WALKS.CYCLES", "PublicDescription": "Counts every core cycle a page-walk is in pr= ogress due to either a data memory operation or an instruction fetch.", @@ -47,6 +52,7 @@ }, { "BriefDescription": "Duration of D-side page-walks in cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "PublicDescription": "Counts every core cycle when a Data-side (wa= lks due to a data operation) page walk is in progress.", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Duration of I-side pagewalks in cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "PublicDescription": "Counts every core cycle when a Instruction-s= ide (walks due to an instruction fetch) page walk is in progress.", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DE231B47A9 for ; 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Thu, 20 Jun 2024 11:19:39 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:25 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-12-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 11/37] perf vendor events: Add goldmontplus counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/goldmontplus/cache.json | 101 ++++++++++++++++++ .../arch/x86/goldmontplus/counter.json | 7 ++ .../arch/x86/goldmontplus/floating-point.json | 3 + .../arch/x86/goldmontplus/frontend.json | 8 ++ .../arch/x86/goldmontplus/memory.json | 3 + .../arch/x86/goldmontplus/other.json | 5 + .../arch/x86/goldmontplus/pipeline.json | 42 ++++++++ .../arch/x86/goldmontplus/virtual-memory.json | 18 ++++ 8 files changed, 187 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/goldmontplus/counter.json diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/cache.json index a7f80fd1b1df..92086758e7ce 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Requests rejected by the L2Q", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ALL", "PublicDescription": "Counts the number of demand and L1 prefetche= r requests rejected by the L2Q due to a full or nearly full condition which= likely indicates back pressure from L2Q. It also counts requests that woul= d have gone directly to the XQ, but are rejected due to a full or nearly fu= ll condition, indicating back pressure from the IDI link. The L2Q may also = reject transactions from a core to insure fairness between cores, or to del= ay a core's dirty eviction when the address conflicts with incoming externa= l snoops.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "L1 Cache evictions for dirty data", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.REPLACEMENT", "PublicDescription": "Counts when a modified (dirty) cache line is= evicted from the data L1 cache and needs to be written back to memory. No= count will occur if the evicted line is clean, and hence does not require = a writeback.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Requests rejected by the XQ", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ALL", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the L2 XQ rejects due to a full or near full condition which= likely indicates back pressure from the intra-die interconnect (IDI) fabri= c. The XQ may reject transactions from the L2Q (non-cacheable requests), L2= misses and L2 write-back victims.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "L2 cache request misses", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts memory requests originating from the = core that miss in the L2 cache.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "L2 cache requests", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts memory requests originating from the = core that reference a cache line in the L2 cache.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "Loads retired that came from DRAM (Precise ev= ent capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Memory uop retired where cross core or cross = module HITM occurred (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Load uops retired that hit L1 data cache (Pre= cise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -77,6 +86,7 @@ }, { "BriefDescription": "Load uops retired that missed L1 data cache (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Load uops retired that hit L2 (Precise event = capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Load uops retired that missed L2 (Precise eve= nt capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Loads retired that hit WCB (Precise event cap= able)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", @@ -117,6 +130,7 @@ }, { "BriefDescription": "Memory uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Load uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -137,6 +152,7 @@ }, { "BriefDescription": "Store uops retired (Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Locked load uops retired (Precise event capab= le)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", @@ -157,6 +174,7 @@ }, { "BriefDescription": "Memory uops retired that split a cache-line (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT", @@ -167,6 +185,7 @@ }, { "BriefDescription": "Load uops retired that split a cache-line (Pr= ecise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -177,6 +196,7 @@ }, { "BriefDescription": "Stores uops retired that split a cache-line (= Precise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -187,6 +207,7 @@ }, { "BriefDescription": "Requires MSR_OFFCORE_RESP[0,1] to specify req= uest type and response. (duplicated for both MSRs)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", @@ -194,6 +215,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) have an= y transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -204,6 +226,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) hit the= L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -214,6 +237,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) miss th= e L2 cache with a snoop hit in the other processor module, data forwarding = is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", @@ -224,6 +248,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) true mi= ss for the L2 cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -234,6 +259,7 @@ }, { "BriefDescription": "Counts data reads (demand & prefetch) outstan= ding, per cycle, from the time of the L2 miss to when any response is recei= ved.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -244,6 +270,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -254,6 +281,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -264,6 +292,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", @@ -274,6 +303,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers true miss for the L2 cache with a snoop miss in the other processor = module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -284,6 +314,7 @@ }, { "BriefDescription": "Counts data reads generated by L1 or L2 prefe= tchers outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -294,6 +325,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) have any transaction responses fr= om the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -304,6 +336,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -314,6 +347,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) miss the L2 cache with a snoop hi= t in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -324,6 +358,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) true miss for the L2 cache with a= snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_MISS.SNOOP_MISS_OR_NO_S= NOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -334,6 +369,7 @@ }, { "BriefDescription": "Counts data read, code read, and read for own= ership (RFO) requests (demand & prefetch) outstanding, per cycle, from the = time of the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", @@ -344,6 +380,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem have = any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -354,6 +391,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem hit t= he L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -364,6 +402,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", @@ -374,6 +413,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem true = miss for the L2 cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -384,6 +424,7 @@ }, { "BriefDescription": "Counts requests to the uncore subsystem outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", @@ -394,6 +435,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -404,6 +446,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -414,6 +457,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) miss the L2 cache with a snoop hit in the other processor = module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -424,6 +468,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) true miss for the L2 cache with a snoop miss in the other = processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS_OR_NO_SN= OOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -434,6 +479,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests (de= mand & prefetch) outstanding, per cycle, from the time of the L2 miss to wh= en any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -444,6 +490,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests have = any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -454,6 +501,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests hit t= he L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -464,6 +512,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests miss = the L2 cache with a snoop hit in the other processor module, data forwardin= g is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -474,6 +523,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests true = miss for the L2 cache with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -484,6 +534,7 @@ }, { "BriefDescription": "Counts bus lock and split lock requests outst= anding, per cycle, from the time of the L2 miss to when any response is rec= eived.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", @@ -494,6 +545,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions have any transaction responses from the u= ncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -504,6 +556,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -514,6 +567,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions miss the L2 cache with a snoop hit in the= other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -524,6 +578,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions true miss for the L2 cache with a snoop m= iss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.SNOOP_MISS_OR_NO_SNO= OP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -534,6 +589,7 @@ }, { "BriefDescription": "Counts the number of writeback transactions c= aused by L1 or L2 cache evictions outstanding, per cycle, from the time of = the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.OUTSTANDING", "MSRIndex": "0x1a6", @@ -544,6 +600,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache have any transaction re= sponses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -554,6 +611,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -564,6 +622,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache miss the L2 cache with = a snoop hit in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", @@ -574,6 +633,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache true miss for the L2 ca= che with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -584,6 +644,7 @@ }, { "BriefDescription": "Counts demand instruction cacheline and I-sid= e prefetch requests that miss the instruction cache outstanding, per cycle,= from the time of the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -594,6 +655,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -604,6 +666,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -614,6 +677,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines miss the L2 cache with a snoop hit in the other processor module,= data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6, 0x1a7", @@ -624,6 +688,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines true miss for the L2 cache with a snoop miss in the other process= or module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS_O= R_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -634,6 +699,7 @@ }, { "BriefDescription": "Counts demand cacheable data reads of full ca= che lines outstanding, per cycle, from the time of the L2 miss to when any = response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -644,6 +710,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line have any transaction respo= nses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -654,6 +721,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -664,6 +732,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line miss the L2 cache with a s= noop hit in the other processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -674,6 +743,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line true miss for the L2 cache= with a snoop miss in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS_OR_NO= _SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -684,6 +754,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts generated by a write to full data cache line outstanding, per cycle, fr= om the time of the L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -694,6 +765,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes have any transaction responses from the uncore subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -704,6 +776,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -714,6 +787,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes miss the L2 cache with a snoop hit in the other processor module, da= ta forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.HITM_= OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -724,6 +798,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes true miss for the L2 cache with a snoop miss in the other processor = module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.L2_MISS.SNOOP= _MISS_OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -734,6 +809,7 @@ }, { "BriefDescription": "Counts full cache line data writes to uncache= able write combining (USWC) memory region and full cache-line non-temporal = writes outstanding, per cycle, from the time of the L2 miss to when any res= ponse is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.OUTSTANDING", "MSRIndex": "0x1a6", @@ -744,6 +820,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher have any transaction responses from the unco= re subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -754,6 +831,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -764,6 +842,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", @@ -774,6 +853,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher true miss for the L2 cache with a snoop miss= in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -784,6 +864,7 @@ }, { "BriefDescription": "Counts data cache line reads generated by har= dware L1 data cache prefetcher outstanding, per cycle, from the time of the= L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -794,6 +875,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher have any transaction responses from the uncore sub= system.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -804,6 +886,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -814,6 +897,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher miss the L2 cache with a snoop hit in the other pr= ocessor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6, 0x1a7", @@ -824,6 +908,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher true miss for the L2 cache with a snoop miss in th= e other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS_OR= _NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -834,6 +919,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by hard= ware L2 cache prefetcher outstanding, per cycle, from the time of the L2 mi= ss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -844,6 +930,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher have any transaction responses from the uncore subs= ystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -854,6 +941,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -864,6 +952,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher miss the L2 cache with a snoop hit in the other pro= cessor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -874,6 +963,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher true miss for the L2 cache with a snoop miss in the= other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS_OR_NO_= SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -884,6 +974,7 @@ }, { "BriefDescription": "Counts reads for ownership (RFO) requests gen= erated by L2 prefetcher outstanding, per cycle, from the time of the L2 mis= s to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -894,6 +985,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region have any transaction responses from the unco= re subsystem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -904,6 +996,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -914,6 +1007,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region miss the L2 cache with a snoop hit in the ot= her processor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.HITM_OTHER= _CORE", "MSRIndex": "0x1a6, 0x1a7", @@ -924,6 +1018,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region true miss for the L2 cache with a snoop miss= in the other processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.SNOOP_MISS= _OR_NO_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -934,6 +1029,7 @@ }, { "BriefDescription": "Counts any data writes to uncacheable write c= ombining (USWC) memory region outstanding, per cycle, from the time of the= L2 miss to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.OUTSTANDING", "MSRIndex": "0x1a6", @@ -944,6 +1040,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions have any transaction responses from the uncore subsys= tem.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6, 0x1a7", @@ -954,6 +1051,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions hit the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_HIT", "MSRIndex": "0x1a6, 0x1a7", @@ -964,6 +1062,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions miss the L2 cache with a snoop hit in the other proce= ssor module, data forwarding is required.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6, 0x1a7", @@ -974,6 +1073,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions true miss for the L2 cache with a snoop miss in the o= ther processor module.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.L2_MISS.SNOOP_MISS_OR_N= O_SNOOP_NEEDED", "MSRIndex": "0x1a6, 0x1a7", @@ -984,6 +1084,7 @@ }, { "BriefDescription": "Counts data cache lines requests by software = prefetch instructions outstanding, per cycle, from the time of the L2 miss = to when any response is received.", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.SW_PREFETCH.OUTSTANDING", "MSRIndex": "0x1a6", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/counter.json b/too= ls/perf/pmu-events/arch/x86/goldmontplus/counter.json new file mode 100644 index 000000000000..aa443347b694 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json index 822a7a6bcaeb..3d06ac1ee0cf 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the FP divide unit is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.FPDIV", "PublicDescription": "Counts core cycles the floating point divide= unit is busy.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Machine clears due to FP assists", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts machine clears due to floating point = (FP) operations needing assists. For instance, if the result was a floatin= g point denormal, the hardware clears the pipeline and reissues uops to pro= duce the correct IEEE compliant denormal result.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Floating point divide uops retired (Precise E= vent Capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/frontend.json index ace2a114b546..249a97cf3f4c 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "BACLEARs asserted for any branch type", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "PublicDescription": "Counts the number of times a BACLEAR is sign= aled for any reason, including, but not limited to indirect branch/call, J= cc (Jump on Conditional Code/Jump if Condition is Met) branch, unconditiona= l branch/call, and returns.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "BACLEARs asserted for conditional branch", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "PublicDescription": "Counts BACLEARS on Jcc (Jump on Conditional = Code/Jump if Condition is Met) branches.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "BACLEARs asserted for return branch", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "PublicDescription": "Counts BACLEARS on return instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Decode restrictions due to predicting wrong i= nstruction length", + "Counter": "0,1,2,3", "EventCode": "0xE9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "PublicDescription": "Counts the number of times the prediction (f= rom the predecode cache) for instruction length is incorrect.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "References per ICache line. This event counts= differently than Intel processors based on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line. The event strives to count = on a cache line basis, so that multiple fetches to a single cache line coun= t as one ICACHE.ACCESS. Specifically, the event counts when accesses from = straight line code crosses the cache line boundary, or when a branch target= is to a new line.\r\nThis event counts differently than Intel processors b= ased on Silvermont microarchitecture.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "References per ICache line that are available= in the ICache (hit). This event counts differently than Intel processors b= ased on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is in the= ICache (hit). The event strives to count on a cache line basis, so that m= ultiple accesses which hit in a single cache line count as one ICACHE.HIT. = Specifically, the event counts when straight line code crosses the cache l= ine boundary, or when a branch target is to a new line, and that cache line= is in the ICache. This event counts differently than Intel processors base= d on Silvermont microarchitecture.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "References per ICache line that are not avail= able in the ICache (miss). This event counts differently than Intel process= ors based on Silvermont microarchitecture", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts requests to the Instruction Cache (IC= ache) for one or more bytes in an ICache Line and that cache line is not i= n the ICache (miss). The event strives to count on a cache line basis, so = that multiple accesses which miss in a single cache line count as one ICACH= E.MISS. Specifically, the event counts when straight line code crosses the= cache line boundary, or when a branch target is to a new line, and that ca= che line is not in the ICache. This event counts differently than Intel pro= cessors based on Silvermont microarchitecture.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "MS decode starts", + "Counter": "0,1,2,3", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "PublicDescription": "Counts the number of times the Microcode Seq= uencer (MS) starts a flow of uops from the MSROM. It does not count every t= ime a uop is read from the MSROM. The most common case that this counts is= when a micro-coded instruction is encountered by the front end of the mach= ine. Other cases include when an instruction encounters a fault, trap, or = microcode assist of any sort that initiates a flow of uops. The event will= count MS startups for uops that are speculative, and subsequently cleared = by branch mispredict or a machine clear.", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json b/tool= s/perf/pmu-events/arch/x86/goldmontplus/memory.json index 7038873a5c8d..72bc2155ed00 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Machine clears due to memory ordering issue", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts machine clears due to memory ordering= issues. This occurs when a snoop request happens and the machine is uncer= tain if memory ordering will be preserved - as another core is in the proce= ss of modifying the data.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Load uops that split a page (Precise event ca= pable)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "2", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Store uops that split a page (Precise event c= apable)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json b/tools= /perf/pmu-events/arch/x86/goldmontplus/other.json index ec0ce9078c98..96bbc4fc82a1 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/other.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles code-fetch stalled due to any reason.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles the code-fetch stalls and an ITLB miss= is outstanding.", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Cycles hardware interrupts are masked", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.MASKED", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cycles pending interrupts are masked", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PublicDescription": "Counts core cycles during which there are pe= nding interrupts, but interrupts are masked (EFLAGS.IF =3D 0).", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Hardware interrupts received", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts hardware interrupts received by the p= rocessor.", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json b/to= ols/perf/pmu-events/arch/x86/goldmontplus/pipeline.json index 33ef331e77e0..8cbf253d0c30 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Retired branch instructions (Precise event ca= pable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "2", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Retired taken branch instructions (Precise ev= ent capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", "PEBS": "2", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise event= capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "2", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Retired far branch instructions (Precise even= t capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "2", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Retired near indirect call instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "2", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "2", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Retired instructions of near indirect Jmp or = call (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "2", @@ -63,6 +70,7 @@ }, { "BriefDescription": "Retired near relative call instructions (Prec= ise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "2", @@ -72,6 +80,7 @@ }, { "BriefDescription": "Retired near return instructions (Precise eve= nt capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "2", @@ -81,6 +90,7 @@ }, { "BriefDescription": "Retired conditional branch instructions that = were taken (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "2", @@ -90,6 +100,7 @@ }, { "BriefDescription": "Retired mispredicted branch instructions (Pre= cise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "2", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Retired mispredicted near indirect call instr= uctions (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "2", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Retired mispredicted conditional branch instr= uctions (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "2", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Retired mispredicted instructions of near ind= irect Jmp or near indirect call (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "2", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Retired mispredicted near return instructions= (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "2", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Retired mispredicted conditional branch instr= uctions that were taken (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "2", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Core cycles when core is not halted (Fixed e= vent)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runn= ing the HLT instruction. In mobile systems the core frequency may change fr= om time to time. For this reason this event may have a changing ratio with = regards to time. This event uses fixed counter 1. You cannot collect a PE= Bs record for this event.", "SampleAfterValue": "2000003", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Core cycles when core is not halted", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Core cycles when core is not halted. This e= vent uses a (_P)rogrammable general purpose performance counter.", @@ -157,6 +175,7 @@ }, { "BriefDescription": "Reference cycles when core is not halted", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "Reference cycles when core is not halted. T= his event uses a (_P)rogrammable general purpose performance counter.", @@ -165,6 +184,7 @@ }, { "BriefDescription": "Reference cycles when core is not halted (Fi= xed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. In mobile systems the core frequency may chang= e from time. This event is not affected by core frequency changes but coun= ts as if the core is running at the maximum frequency all the time. This e= vent uses fixed counter 2. You cannot collect a PEBs record for this event= .", "SampleAfterValue": "2000003", @@ -172,6 +192,7 @@ }, { "BriefDescription": "Cycles a divider is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.ALL", "PublicDescription": "Counts core cycles if either divide unit is = busy.", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Cycles the integer divide unit is busy", + "Counter": "0,1,2,3", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.IDIV", "PublicDescription": "Counts core cycles the integer divide unit i= s busy.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Instructions retired (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "2", "PublicDescription": "Counts the number of instructions that retir= e execution. For instructions that consist of multiple uops, this event cou= nts the retirement of the last uop of the instruction. The counter continue= s counting during hardware interrupts, traps, and inside interrupt handlers= . This event uses fixed counter 0. You cannot collect a PEBs record for t= his event.", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Instructions retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "2", @@ -203,6 +227,7 @@ }, { "BriefDescription": "Instructions retired - using Reduced Skid PEB= S feature", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", @@ -211,6 +236,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.ANY", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend due to either a full resource in= the backend (RESOURCE_FULL) or due to the processor recovering from some e= vent (RECOVERY).", @@ -218,6 +244,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle to recover", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RECOVERY", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed by the backend because allocation is stalled wai= ting for a mispredicted jump to retire or other branch-like conditions (e.g= . the event is relevant during certain microcode flows). Counts all issue= slots blocked while within this window including slots where uops were not= available in the Instruction Queue.", @@ -226,6 +253,7 @@ }, { "BriefDescription": "Unfilled issue slots per cycle because of a f= ull resource in the backend", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "ISSUE_SLOTS_NOT_CONSUMED.RESOURCE_FULL", "PublicDescription": "Counts the number of issue slots per core cy= cle that were not consumed because of a full resource in the backend. Incl= uding but not limited to resources such as the Re-order Buffer (ROB), reser= vation stations (RS), load/store buffers, physical registers, or any other = needed machine resource that is currently unavailable. Note that uops mus= t be available for consumption in order for this event to fire. If a uop i= s not available (Instruction Queue is empty), this event will not count.", @@ -234,6 +262,7 @@ }, { "BriefDescription": "Loads blocked because address has 4k partial = address false dependence (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "2", @@ -243,6 +272,7 @@ }, { "BriefDescription": "Loads blocked (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL_BLOCK", "PEBS": "2", @@ -252,6 +282,7 @@ }, { "BriefDescription": "Loads blocked due to store data not ready (Pr= ecise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "2", @@ -261,6 +292,7 @@ }, { "BriefDescription": "Loads blocked due to store forward restrictio= n (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "2", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Loads blocked because address in not in the U= TLB (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.UTLB_MISS", "PEBS": "2", @@ -279,6 +312,7 @@ }, { "BriefDescription": "All machine clears", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.ALL", "PublicDescription": "Counts machine clears for any reason.", @@ -286,6 +320,7 @@ }, { "BriefDescription": "Machine clears due to memory disambiguation", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "PublicDescription": "Counts machine clears due to memory disambig= uation. Memory disambiguation happens when a load which has been issued co= nflicts with a previous unretired store in the pipeline whose address was n= ot known at issue time, but is later resolved to be the same as the load ad= dress.", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Machines clear due to a page fault", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "PublicDescription": "Counts the number of times that the machines= clears due to a page fault. Covers both I-side and D-side(Loads/Stores) pa= ge faults. A page fault occurs when either page is not present, or an acces= s violation", @@ -302,6 +338,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts the number of times that the processo= r detects that a program is writing to a code section and has to perform a = machine clear because of that modification. Self-modifying code (SMC) caus= es a severe penalty in all Intel(R) architecture processors.", @@ -310,6 +347,7 @@ }, { "BriefDescription": "Uops issued to the back end per cycle", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts uops issued by the front end and allo= cated into the back end of the machine. This event counts uops that retire= as well as uops that were speculatively executed but didn't retire. The so= rt of speculative uops that might be counted includes, but is not limited t= o those uops issued in the shadow of a miss-predicted branch, those uops th= at are inserted during an assist (such as for a denormal floating point res= ult), and (previously allocated) uops that might be canceled during a machi= ne clear.", @@ -317,6 +355,7 @@ }, { "BriefDescription": "Uops requested but not-delivered to the back-= end per cycle", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UOPS_NOT_DELIVERED.ANY", "PublicDescription": "This event used to measure front-end ineffic= iencies. I.e. when front-end of the machine is not delivering uops to the b= ack-end and the back-end has is not stalled. This event can be used to iden= tify if the machine is truly front-end bound. When this event occurs, it i= s an indication that the front-end of the machine is operating at less than= its theoretical peak performance. Background: We can think of the processo= r pipeline as being divided into 2 broader parts: Front-end and Back-end. F= ront-end is responsible for fetching the instruction, decoding into uops in= machine understandable format and putting them into a uop queue to be cons= umed by back end. The back-end then takes these uops, allocates the require= d resources. When all resources are ready, uops are executed. If the back-= end is not ready to accept uops from the front-end, then we do not want to = count these as front-end bottlenecks. However, whenever we have bottleneck= s in the back-end, we will have allocation unit stalls and eventually forci= ng the front-end to wait until the back-end is ready to receive more uops. = This event counts only when back-end is requesting more uops and front-end = is not able to provide them. When 3 uops are requested and no uops are deli= vered, the event counts 3. When 3 are requested, and only 1 is delivered, t= he event counts 2. When only 2 are delivered, the event counts 1. Alternati= vely stated, the event will not count if 3 uops are delivered, or if the ba= ck end is stalled and not requesting any uops at all. Counts indicate miss= ed opportunities for the front-end to deliver a uop to the back end. Some e= xamples of conditions that cause front-end efficiencies are: ICache misses,= ITLB misses, and decoder restrictions that limit the front-end bandwidth. = Known Issues: Some uops require multiple allocation slots. These uops will= not be charged as a front end 'not delivered' opportunity, and will be reg= arded as a back end problem. For example, the INC instruction has one uop t= hat requires 2 issue slots. A stream of INC instructions will not count as= UOPS_NOT_DELIVERED, even though only one instruction can be issued per clo= ck. The low uop issue rate for a stream of INC instructions is considered = to be a back end issue.", @@ -324,6 +363,7 @@ }, { "BriefDescription": "Uops retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "2", @@ -332,6 +372,7 @@ }, { "BriefDescription": "Integer divide uops retired (Precise Event Ca= pable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "2", @@ -341,6 +382,7 @@ }, { "BriefDescription": "MS uops retired (Precise event capable)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MS", "PEBS": "2", diff --git a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json index 3d6feb45a50b..09208af2e0ba 100644 --- a/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Page walk completed due to a demand load to a= 1GB page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1GB", "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 1GB pages. The page walks can end with or w= ithout a page fault.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Page walk completed due to a demand load to a= 2M or 4M page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 2M or 4M pages. The page walks can end with= or without a page fault.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Page walk completed due to a demand load to a= 4K page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts page walks completed due to demand da= ta loads (including SW prefetches) whose address translations missed in all= TLB levels and were mapped to 4K pages. The page walks can end with or wi= thout a page fault.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Page walks outstanding due to a demand load e= very cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a load (demand data loads or SW prefetches). Includes cycles = spent traversing the Extended Page Table (EPT). Average cycles per walk can= be calculated by dividing by the number of walks.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1GB page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1GB", "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 1= GB pages. The page walks can end with or without a page fault.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M or 4M page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M or 4M pages. The page walks can end with or without a page fault.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Page walks outstanding due to a demand data s= tore every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts once per cycle for each page walk occ= urring due to a demand data store. Includes cycles spent traversing the Ext= ended Page Table (EPT). Average cycles per walk can be calculated by dividi= ng by the number of walks.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Page walks outstanding due to walking the EPT= every cycle", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts once per cycle for each page walk onl= y while traversing the Extended Page Table (EPT), and does not count during= the rest of the translation. The EPT is used for translating Guest-Physic= al Addresses to Physical Addresses for Virtual Machine Monitors (VMMs). Av= erage cycles per walk can be calculated by dividing the count by number of = walks.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "ITLB misses", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.MISS", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) for a linear address of an instruction fetch. It counts when new t= ranslation are filled into the ITLB. The event is speculative in nature, b= ut will not count translations (page walks) that are begun and not finished= , or translations that are finished but not filled into the ITLB.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Page walk completed due to an instruction fet= ch in a 1GB page", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1GB", "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 1GB pages. The page walks can end with or without a page fault.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Page walk completed due to an instruction fet= ch in a 2M or 4M page", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 2M or 4M pages. The page walks can end with or without a page fault.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Page walk completed due to an instruction fet= ch in a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts page walks completed due to instructi= on fetches whose address translations missed in the TLB and were mapped to = 4K pages. The page walks can end with or without a page fault.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Page walks outstanding due to an instruction = fetch every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts once per cycle for each page walk occ= urring due to an instruction fetch. Includes cycles spent traversing the Ex= tended Page Table (EPT). Average cycles per walk can be calculated by divid= ing by the number of walks.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Memory uops retired that missed the DTLB (Pre= cise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Load uops retired that missed the DTLB (Preci= se event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -133,6 +149,7 @@ }, { "BriefDescription": "Store uops retired that missed the DTLB (Prec= ise event capable)", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", @@ -143,6 +160,7 @@ }, { "BriefDescription": "STLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSHES.STLB_ANY", "PublicDescription": "Counts STLB flushes. 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Add TMA metrics v4.8. Bring in the event updates v1.03: https://github.com/intel/perfmon/commit/5ec7a252d0f6ec461f80cc397c9ac25abcd= 9184f The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 New events are: FP_INST_RETIRED.128B_DP, FP_INST_RETIRED.128B_SP, FP_INST_RETIRED.256B_DP, FP_INST_RETIRED.32B_SP, FP_INST_RETIRED.64B_DP, OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM, OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD, OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM, OCR.STREAMING_WR.ANY_RESPONSE. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/grandridge/cache.json | 97 +- .../arch/x86/grandridge/counter.json | 42 + .../arch/x86/grandridge/floating-point.json | 54 +- .../arch/x86/grandridge/frontend.json | 5 +- .../arch/x86/grandridge/grr-metrics.json | 849 ++++++++++++++++++ .../arch/x86/grandridge/memory.json | 13 +- .../arch/x86/grandridge/metricgroups.json | 23 + .../pmu-events/arch/x86/grandridge/other.json | 15 +- .../arch/x86/grandridge/pipeline.json | 97 +- .../arch/x86/grandridge/uncore-cache.json | 267 ++++++ .../x86/grandridge/uncore-interconnect.json | 30 + .../arch/x86/grandridge/uncore-io.json | 181 ++++ .../arch/x86/grandridge/uncore-memory.json | 66 ++ .../arch/x86/grandridge/uncore-power.json | 1 + .../arch/x86/grandridge/virtual-memory.json | 17 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 16 files changed, 1693 insertions(+), 66 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/counter.json create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/grr-metrics.j= son create mode 100644 tools/perf/pmu-events/arch/x86/grandridge/metricgroups.= json diff --git a/tools/perf/pmu-events/arch/x86/grandridge/cache.json b/tools/p= erf/pmu-events/arch/x86/grandridge/cache.json index f937ba0e50e1..04802e254e51 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/cache.json @@ -1,22 +1,25 @@ [ { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= core has access to an L3 cache, the LLC is the L3 cache, otherwise it is t= he L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th= e L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f" }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an instruction cache or TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", "SampleAfterValue": "1000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", "SampleAfterValue": "1000003", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which missed all the caches.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", "SampleAfterValue": "1000003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an L1 demand load miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.ALL", "SampleAfterValue": "1000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the L2 cache.", @@ -61,6 +69,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", "SampleAfterValue": "1000003", @@ -68,6 +77,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which missed all the local cache= s.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", "SampleAfterValue": "1000003", @@ -75,62 +85,63 @@ }, { "BriefDescription": "Counts the number of load ops retired that mi= ss the L3 cache and hit in DRAM", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd3", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of load ops retired that hi= t the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x40" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1c" }, { "BriefDescription": "Counts the number of loads that hit in a writ= e combining buffer (WCB), excluding the first load that caused the WCB to a= llocate.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked for any of the following reasons: load buffer, store buffer or RSV fu= ll.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ALL", "SampleAfterValue": "20003", @@ -138,6 +149,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", "SampleAfterValue": "20003", @@ -145,6 +157,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.RSV", "SampleAfterValue": "20003", @@ -152,6 +165,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", "SampleAfterValue": "20003", @@ -159,179 +173,210 @@ }, { "BriefDescription": "Counts the number of load ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x81" }, { "BriefDescription": "Counts the number of store ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x82" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", "MSRIndex": "0x3F6", "MSRValue": "0x400", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", "MSRIndex": "0x3F6", "MSRValue": "0x800", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x21" }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x43" }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x42" }, { "BriefDescription": "Counts the number of stores uops retired sam= e as MEM_UOPS_RETIRED.ALL_STORES", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x6" }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to an icache miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/counter.json b/tools= /perf/pmu-events/arch/x86/grandridge/counter.json new file mode 100644 index 000000000000..9fd5d8ad6d3b --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/counter.json @@ -0,0 +1,42 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "8" + }, + { + "Unit": "B2CMI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "CHACMS", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json = b/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json index 00c9a8ae0f53..5266eed969be 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the f= loating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.FPDIV_ACTIVE", @@ -9,48 +10,89 @@ }, { "BriefDescription": "Counts the number of all types of floating po= int operations per uop with all default weighting", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x3" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP64]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.DP", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 32 bit single precision results [This event is alias to FP_F= LOPS_RETIRED.SP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP32", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 64 bit double precision results [This event is alias to FP_F= LOPS_RETIRED.DP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP64", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP32]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.SP", - "PEBS": "1", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of floating point re= tired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 128 bit single precision floating point. This may b= e SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 256 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.256B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 32bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.32B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 64 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.64B_DP", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -59,9 +101,9 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and sse, including x87 sqrt).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x8" } diff --git a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json b/tool= s/perf/pmu-events/arch/x86/grandridge/frontend.json index 356d36aecc81..7cdf611efb23 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,14 +10,15 @@ }, { "BriefDescription": "Counts the number of instructions retired tha= t were tagged because empty issue slots were seen before the uop due to ITL= B miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x10" }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -24,6 +26,7 @@ }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump and the instruction cache registers bytes are not present= . -", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/grr-metrics.json b/t= ools/perf/pmu-events/arch/x86/grandridge/grr-metrics.json new file mode 100644 index 000000000000..07e542297e93 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/grr-metrics.json @@ -0,0 +1,849 @@ +[ + { + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per module", + "MetricExpr": "cstate_module@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Module_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC = * #SYSTEM_TSC_FREQ / 1e9", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "tma_info_system_cpu_utilization", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte page sizes) caused by demand data loads to the total number of = completed instructions. This implies it missed in the Data Translation Look= aside Buffer (DTLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "dtlb_2nd_level_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data loads to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricName": "dtlb_2nd_level_store_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / durati= on_time", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.= IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricName": "itlb_2nd_level_large_page_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total = number of completed instructions. This implies it missed in the Instruction= Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "itlb_2nd_level_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by a code fetch to the total number of completed in= structions. This implies it missed in the ITLB (Instruction TLB) and furthe= r levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "ICACHE.MISSES / INST_RETIRED.ANY", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "LONGEST_LAT_CACHE.REFERENCE / INST_RETIRED.ANY", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSE= RTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_= INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / I= NST_RETIRED.ANY", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) in nano seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_= CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Load operations retired per instruction", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricName": "loads_retired_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD)= * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD = + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_= time", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR)= * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Percentage of cycles spent in System Manageme= nt Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0= else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" + }, + { + "BriefDescription": "Store operations retired per instruction", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricName": "stores_retired_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to certain allocation restrictions", + "MetricExpr": "tma_core_bound", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_allocation_restriction", + "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_b= ound > 0.1 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend due to backend stalls", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls. Note that uops must= be available for consumption in order for this event to count. If a uop is= not available (IQ is empty), this event will not count", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL_P / (6 * CPU_CLK_UNHALT= ED.CORE)", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BACLEARS, which occurs when the Branch T= arget Buffer (BTB) prediction or lack thereof, was corrected by a later bra= nch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_branch_detect", + "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "PublicDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend. Includes BACLEARS due to all branch types i= ncluding conditional and unconditional jumps, returns, and indirect branche= s.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to branch mispredicts", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (6 * CPU_CLK_U= NHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_specul= ation > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BTCLEARS, which occurs when the Branch T= arget Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (6 * CPU_CLK_UNHA= LTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_branch_resteer", + "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latenc= y > 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / (6 * CPU_CLK_UNHALTED.CORE)= ", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 = & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are bounded by core restrictions and not attributed to an o= utstanding load or stores, or resource limitation", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (6 * CPU_CLK_= UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1= ", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (6 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_decode", + "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.= 1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that does not require the = use of microcode, classified as a fast nuke, due to memory ordering, memory= disambiguation and memory renaming", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (6 * CPU_CLK_UNH= ALTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0= .05 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (6 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend bandwidth restrictions due to d= ecode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (6 * CPU_CLK_= UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_ifetch_bandwidth", + "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_boun= d > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend latency restrictions due to ica= che misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (6 * CPU_CLK_UN= HALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_ifetch_latency", + "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound= > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n", + "MetricExpr": "INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction", + "MetricExpr": "INST_RETIRED.ANY / (FP_INST_RETIRED.128B_DP + FP_IN= ST_RETIRED.128B_SP)", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "MetricGroup": "Ifetch", + "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "tma_info_bottleneck_load_miss_bound_cycles", + "MetricGroup": "Load_Store_Miss", + "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "tma_info_bottleneck_mem_exec_bound_cycles", + "MetricGroup": "Mem_Exec", + "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT= _RET) / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Cycles", + "MetricName": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.ALL / CPU_CLK_UNHALTE= D.CORE", + "MetricGroup": "Cycles;Ifetch", + "MetricName": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.ALL / CPU_CLK_UNHALTED.= CORE", + "MetricGroup": "Cycles;Load_Store_Miss", + "MetricName": "tma_info_bottleneck_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Cycles;Mem_Exec", + "MetricName": "tma_info_bottleneck_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricName": "tma_info_br_inst_mix_ipcall" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricName": "tma_info_br_inst_mix_ipfarbranch" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per retired return Branch Mispre= diction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction= ", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipmispredict" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_= BRANCHES", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_rati= o" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unkno= wn branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_u= nknown_branch_ratio" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CO= RE", + "MetricName": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY", + "MetricName": "tma_info_core_cpi" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Flops", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE", + "MetricName": "tma_info_core_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY", + "MetricName": "tma_info_core_upi" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2h= it", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 2hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3h= it", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss subsequently misses in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_MISS / MEM_BOUND_= STALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3miss" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / MEM_BOUND_ST= ALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2h= it", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / MEM_BOUND_S= TALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3h= it", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that subsequently misses the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_MISS / MEM_BOUND_ST= ALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3mis= s" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STAL= LS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STA= LLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement", + "MetricExpr": "100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_L= OAD.ALL) / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full", + "MetricExpr": "100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_B= LOCK.ALL) * tma_mem_scheduler", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assi= st_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to page faults", + "MetricExpr": "1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fa= ult_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasin= g" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.AL= L_LOADS", + "MetricName": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", + "MetricName": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_otherpipeline= blks", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipeli= neblks" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_otherpipeline= blks", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET= ", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricName": "tma_info_mem_mix_ipstore" + }, + { + "BriefDescription": "Percentage of total non-speculative loads tha= t perform one or more locks", + "MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRE= D.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_locks_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_splits_ratio" + }, + { + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING= .ALL_P", + "MetricName": "tma_info_mem_mix_memload_ratio" + }, + { + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "tma_info_serialization_tpause_cycles", + "MetricName": "tma_info_serialization _%_tpause_cycles" + }, + { + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricName": "tma_info_serialization_tpause_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / (duration_time * 1e9)", + "MetricGroup": "Flops", + "MetricName": "tma_info_system_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are microcode op= s", + "MetricExpr": "100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_x87_uop_ratio" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB= ) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB_MISS / (6 * CPU_CLK_UNHALTED.= CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency >= 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (6 * CPU_C= LK_UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculatio= n > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to memory reservation stalls in which a sched= uler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to IEC or FPC RAT stalls, which can be due to= FIQ or IEC reservation stalls in which the integer, floating point or SIMD= scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (6 * CPU_CLK_U= NHALTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bo= und > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that requires the use of m= icrocode (slow nuke)", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / (6 * CPU_CLK_UNHALTE= D.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 &= tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to other common frontend stalls not categor= ized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > = 0.1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / (6 * CPU_CLK_UNHALTED.= CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth >= 0.1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the physical register file unable to accep= t an entry (marble stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / (6 * CPU_CLK_UNHALTED.C= ORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2= & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the reorder buffer being full (ROB stalls)= ", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / (6 * CPU_CLK_UNHA= LTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound= > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a resource limitation", + "MetricExpr": "tma_backend_bound - tma_core_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound >= 0.1", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that result = in retirement slots", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to scoreboards from the instruction queue (IQ= ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTIC= KS) * #num_packages) / 1e9 / duration_time", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + } +] diff --git a/tools/perf/pmu-events/arch/x86/grandridge/memory.json b/tools/= perf/pmu-events/arch/x86/grandridge/memory.json index e0ce2decc805..22d23077618e 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to any number of reasons, incl= uding an L1 miss, WCB full, pagewalk, store address block or store data blo= ck, on a load that retires.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ANY_AT_RET", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to a core bound stall includin= g a store address match, a DTLB miss or a page walk that detains the load f= rom retiring.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_BOUND_AT_RET", "SampleAfterValue": "1000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_MISS_AT_RET", "SampleAfterValue": "1000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", "PublicDescription": "Counts the number of cycles that the head (o= ldest load) of the load buffer and retirement are both stalled due to other= block cases such as pipeline conflicts, fences, etc.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a page= walk.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.PGWALK_AT_RET", "SampleAfterValue": "1000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a stor= e address match.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ST_ADDR_AT_RET", "SampleAfterValue": "1000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -51,22 +58,23 @@ }, { "BriefDescription": "Counts misaligned loads that are 4K page spli= ts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts misaligned stores that are 4K page spl= its.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/metricgroups.json b/= tools/perf/pmu-events/arch/x86/grandridge/metricgroups.json new file mode 100644 index 000000000000..40984c23a6c9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/grandridge/metricgroups.json @@ -0,0 +1,23 @@ +{ + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis = Metrics spreadsheet", + "Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "TopdownL1": "Metrics for top-down breakdown at level 1", + "TopdownL2": "Metrics for top-down breakdown at level 2", + "TopdownL3": "Metrics for top-down breakdown at level 3", + "load_store_bound": "Grouping from Top-down Microarchitecture Analysis= Metrics spreadsheet", + "tma_L1_group": "Metrics for top-down breakdown at level 1", + "tma_L2_group": "Metrics for top-down breakdown at level 2", + "tma_L3_group": "Metrics for top-down breakdown at level 3", + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound = category", + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculat= ion category", + "tma_core_bound_group": "Metrics contributing to tma_core_bound catego= ry", + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_boun= d category", + "tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_band= width category", + "tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latenc= y category", + "tma_machine_clears_group": "Metrics contributing to tma_machine_clear= s category", + "tma_resource_bound_group": "Metrics contributing to tma_resource_boun= d category" +} diff --git a/tools/perf/pmu-events/arch/x86/grandridge/other.json b/tools/p= erf/pmu-events/arch/x86/grandridge/other.json index 70a9da7e97df..28f9a4c3ea84 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/other.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/other.json @@ -1,15 +1,16 @@ [ { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xe4", "EventName": "LBR_INSERTS.ANY", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -19,6 +20,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -26,8 +28,19 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots in a UMWAIT = or TPAUSE instruction where no uop issues due to the instruction putting th= e CPU into the C0.1 activity state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x75", "EventName": "SERIALIZATION.C01_MS_SCB", "SampleAfterValue": "200003", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json b/tool= s/perf/pmu-events/arch/x86/grandridge/pipeline.json index 90292dc03d33..b67c0c89054d 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the d= ividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.DIV_ACTIVE", @@ -9,153 +10,157 @@ }, { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of instructions in w= hich the instruction pointer (IP) of the processor is resteered due to a br= anch instruction and the branch instruction successfully retires. All bran= ch type instructions are accounted for.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xbf" }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf9" }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of mispredicted bran= ch instructions retired. All branch type instructions are accounted for. = Prediction of the branch target address enables the processor to begin exec= uting instructions before the non-speculative execution path is known. The = branch prediction unit (BPU) predicts the target address based on the instr= uction pointer (IP) of the branch and on the execution path through which e= xecution reached this IP. A branch misprediction occurs when the predict= ion is wrong, and results in discarding all instructions executed in the sp= eculative path and re-fetching from the correct path.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of mispredicted near taken = branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -164,18 +169,21 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "SampleAfterValue": "2000003", @@ -183,37 +191,38 @@ }, { "BriefDescription": "Counts the number of instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -221,6 +230,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -228,6 +238,7 @@ }, { "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine with the use of microcode due to SMC= , MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_= TRAP.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SLOW", "SampleAfterValue": "20003", @@ -235,6 +246,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -242,14 +254,15 @@ }, { "BriefDescription": "Counts the number of Last Branch Record (LBR)= entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This= event is alias to LBR_INSERTS.ANY]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", @@ -257,6 +270,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", @@ -264,6 +278,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Fast Nukes such as Memory Ord= ering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -271,6 +286,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -278,6 +294,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -285,6 +302,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "SampleAfterValue": "1000003", @@ -292,12 +310,14 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to due to certain allocation rest= rictions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -305,12 +325,14 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL_P", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stall (sche= duler not being able to accept another uop). This could be caused by RSV f= ull or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -318,6 +340,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC and FPC RAT stalls - which= can be due to the FIQ and IEC reservation station stall (integer, FP and S= IMD scheduler not being able to accept another uop. )", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -325,6 +348,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to mrbl stall. A 'marble' refers= to a physical register file entry, also known as the physical destination = (PDST).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -332,6 +356,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -339,6 +364,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -346,18 +372,21 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_= P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL_P", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BAClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "SampleAfterValue": "1000003", @@ -365,6 +394,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "SampleAfterValue": "1000003", @@ -372,6 +402,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ms", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -379,6 +410,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -386,6 +418,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "SampleAfterValue": "1000003", @@ -393,6 +426,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to latency related stalls inclu= ding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "SampleAfterValue": "1000003", @@ -400,6 +434,7 @@ }, { "BriefDescription": "This event is deprecated. [This event is alia= s to TOPDOWN_FE_BOUND.ITLB_MISS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", @@ -408,6 +443,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to itlb miss [This event is ali= as to TOPDOWN_FE_BOUND.ITLB]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", "SampleAfterValue": "1000003", @@ -415,6 +451,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend that do not categorize into any oth= er common frontend stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -422,27 +459,29 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to predecode wrong", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", "UMask": "0x4" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L_P]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", "SampleAfterValue": "1000003" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL_P", - "PEBS": "1", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -450,32 +489,32 @@ }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in ms flows", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/grandridge/uncore-cache.json index 36614429dd72..1eaf796601b1 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clockticks for CMS units attached to CHA", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHACMS_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of CHA clock cycles while the event is= enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR o= r IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", "PerPkg": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in IRQ (= immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", "PerPkg": "1", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR (= immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", "PerPkg": "1", @@ -42,40 +47,50 @@ }, { "BriefDescription": "Counts when a normal (Non-Isochronous) full l= ine write is issued from the CHA to the any of the memory controller channe= ls.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line : Counts the total number of full line writes issued from the HA in= to the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH : Counts the total number of full line writes issued from the HA = into the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial : Counts the total number of full line writes issued from the HA into= the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups: CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1bd0ff", @@ -83,8 +98,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1bc1ff", @@ -92,8 +109,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Reads", "UMask": "0x1fc1ff", @@ -101,8 +120,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Demand Data Reads, Core and = LLC prefetches", "UMask": "0x841ff", @@ -110,8 +131,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops which miss the Cache", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses", "UMask": "0x1fc101", @@ -119,8 +142,10 @@ }, { "BriefDescription": "Cache Lookups: All Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally", "UMask": "0xbdfff", @@ -128,8 +153,10 @@ }, { "BriefDescription": "Cache Lookups: Code Read Requests and Code Re= ad Prefetches to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x19d0ff", @@ -137,8 +164,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x19c1ff", @@ -146,8 +175,10 @@ }, { "BriefDescription": "Cache Lookups: Code Read Requests to Locally = Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1850ff", @@ -155,8 +186,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1841ff", @@ -164,8 +197,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x1848ff", @@ -173,8 +208,10 @@ }, { "BriefDescription": "Cache Lookups: LLC Prefetch Requests to Local= ly Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x189dff", @@ -182,8 +219,10 @@ }, { "BriefDescription": "Cache Lookups: All Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x199dff", @@ -191,8 +230,10 @@ }, { "BriefDescription": "Cache Lookups: Code Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1910ff", @@ -200,8 +241,10 @@ }, { "BriefDescription": "Cache Lookups: Read Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1981ff", @@ -209,8 +252,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x1908ff", @@ -218,8 +263,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x19c8ff", @@ -227,8 +274,10 @@ }, { "BriefDescription": "Cache Lookups: All RFO and RFO Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All RFOs - Demand and Prefet= ches", "UMask": "0x1bc8ff", @@ -236,8 +285,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally HOMed RFOs - Demand = and Prefetches", "UMask": "0x9c8ff", @@ -245,8 +296,10 @@ }, { "BriefDescription": "Cache Lookups: Writes to Locally Homed Memory= (includes writebacks from L1/L2)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Writes", "UMask": "0x842ff", @@ -254,8 +307,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : All Lines Victimized", "UMask": "0xf", @@ -263,24 +318,30 @@ }, { "BriefDescription": "Lines Victimized : IA traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : IO traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - All Lines", "UMask": "0x200f", @@ -288,8 +349,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in E State", "UMask": "0x2002", @@ -297,8 +360,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in F State", "UMask": "0x2008", @@ -306,8 +371,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in M State", "UMask": "0x2001", @@ -315,8 +382,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in S State", "UMask": "0x2004", @@ -324,8 +393,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state", "UMask": "0x2", @@ -333,8 +404,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state", "UMask": "0x1", @@ -342,8 +415,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State", "UMask": "0x4", @@ -351,6 +426,7 @@ }, { "BriefDescription": "Counts when a RFO (the Read for Ownership iss= ued before a write) request hit a cacheline in the S (Shared) state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", @@ -360,30 +436,37 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local InvItoE : Count o= f OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be br= oadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB= snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadca= st. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Off : Count of OSB snoo= p broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. D= oes not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoo= ps to be broadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", "PerPkg": "1", @@ -392,6 +475,7 @@ }, { "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", "PerPkg": "1", @@ -401,6 +485,7 @@ }, { "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -409,6 +494,7 @@ }, { "BriefDescription": "Counts read requests made into this CHA. Read= s include all read opcodes (including RFO: the Read for Ownership issued be= fore a write) .", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -418,6 +504,7 @@ }, { "BriefDescription": "Counts read requests coming from a unit on th= is socket made into this CHA. Reads include all read opcodes (including RFO= : the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -426,6 +513,7 @@ }, { "BriefDescription": "Counts write requests made into the CHA, incl= uding streaming, evictions, HitM (Reads from another core to a Modified cac= heline), etc.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -435,6 +523,7 @@ }, { "BriefDescription": "Counts write requests coming from a unit on = this socket made into this CHA, including streaming, evictions, HitM (Reads= from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -443,8 +532,10 @@ }, { "BriefDescription": "All TOR Inserts", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All", "UMask": "0xc001ffff", @@ -452,8 +543,10 @@ }, { "BriefDescription": "All locally initiated requests from IA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from iA Cores", "UMask": "0xc001ff01", @@ -461,6 +554,7 @@ }, { "BriefDescription": "CLFlush events that are initiated from the Co= re", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -470,6 +564,7 @@ }, { "BriefDescription": "CLFlushOpt events that are initiated from the= Core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", "PerPkg": "1", @@ -479,6 +574,7 @@ }, { "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -488,6 +584,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", "PerPkg": "1", @@ -497,6 +594,7 @@ }, { "BriefDescription": "Data read opt from local IA that miss the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", "PerPkg": "1", @@ -506,6 +604,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that mis= s the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -515,8 +614,10 @@ }, { "BriefDescription": "All locally initiated requests from IA Cores = which hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Hit the LLC", "UMask": "0xc001fd01", @@ -524,6 +625,7 @@ }, { "BriefDescription": "Code read from local IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -533,6 +635,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that hit the= cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -542,6 +645,7 @@ }, { "BriefDescription": "Data read opt from local IA that hit the cach= e", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -551,6 +655,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that hit= the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -560,6 +665,7 @@ }, { "BriefDescription": "ItoM requests from local IA cores that hit th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", "PerPkg": "1", @@ -569,6 +675,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", "PerPkg": "1", @@ -578,6 +685,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", "PerPkg": "1", @@ -587,6 +695,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -596,6 +705,7 @@ }, { "BriefDescription": "Read for ownership from local IA that hit the= cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -605,6 +715,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -614,6 +725,7 @@ }, { "BriefDescription": "ItoM events that are initiated from the Core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", "PerPkg": "1", @@ -623,6 +735,7 @@ }, { "BriefDescription": "ItoMCacheNear requests from local IA cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", "PerPkg": "1", @@ -632,6 +745,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", "PerPkg": "1", @@ -641,6 +755,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", "PerPkg": "1", @@ -650,6 +765,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", "PerPkg": "1", @@ -659,6 +775,7 @@ }, { "BriefDescription": "All locally initiated requests from IA Cores = which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -668,6 +785,7 @@ }, { "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -677,6 +795,7 @@ }, { "BriefDescription": "CRDs from local IA cores to locally homed mem= ory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", "PerPkg": "1", @@ -686,6 +805,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -695,6 +815,7 @@ }, { "BriefDescription": "CRD Prefetches from local IA cores to locally= homed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", @@ -704,6 +825,7 @@ }, { "BriefDescription": "Data read opt from local IA that miss the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -713,6 +835,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRd_Opt, and which target l= ocal memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", "PerPkg": "1", @@ -722,6 +845,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that mis= s the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", @@ -731,6 +855,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target lo= cal memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", "PerPkg": "1", @@ -740,6 +865,7 @@ }, { "BriefDescription": "ItoM requests from local IA cores that miss t= he cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", "PerPkg": "1", @@ -749,6 +875,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", "PerPkg": "1", @@ -758,6 +885,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -767,6 +895,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -776,6 +905,7 @@ }, { "BriefDescription": "WCILF requests from local IA cores to locally= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", @@ -785,6 +915,7 @@ }, { "BriefDescription": "WCIL requests from local IA cores to locally = homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", @@ -794,6 +925,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -803,6 +935,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -812,6 +945,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -821,6 +955,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -830,6 +965,7 @@ }, { "BriefDescription": "UCRDF requests from local IA cores that miss = the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", @@ -839,6 +975,7 @@ }, { "BriefDescription": "WCIL requests from a local IA core that miss = the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", @@ -848,6 +985,7 @@ }, { "BriefDescription": "WCILF requests from local IA core that miss t= he cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", @@ -857,6 +995,7 @@ }, { "BriefDescription": "WCILF requests from local IA cores to DDR hom= ed addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", "PerPkg": "1", @@ -866,6 +1005,7 @@ }, { "BriefDescription": "WCIL requests from local IA cores to DDR home= d addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", "PerPkg": "1", @@ -875,6 +1015,7 @@ }, { "BriefDescription": "WIL requests from local IA cores that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", @@ -884,6 +1025,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -893,6 +1035,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -902,6 +1045,7 @@ }, { "BriefDescription": "SpecItoM events that are initiated from the C= ore", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", "PerPkg": "1", @@ -911,6 +1055,7 @@ }, { "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", "PerPkg": "1", @@ -920,6 +1065,7 @@ }, { "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified = Write Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", "PerPkg": "1", @@ -929,6 +1075,7 @@ }, { "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write= Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", "PerPkg": "1", @@ -938,6 +1085,7 @@ }, { "BriefDescription": "WbMtoI requests from local IA cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", "PerPkg": "1", @@ -947,6 +1095,7 @@ }, { "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", "PerPkg": "1", @@ -956,6 +1105,7 @@ }, { "BriefDescription": "WCIL requests from a local IA core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", "PerPkg": "1", @@ -965,6 +1115,7 @@ }, { "BriefDescription": "WCILF requests from local IA core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", "PerPkg": "1", @@ -974,8 +1125,10 @@ }, { "BriefDescription": "All TOR inserts from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from IO Devices", "UMask": "0xc001ff04", @@ -983,6 +1136,7 @@ }, { "BriefDescription": "CLFlush requests from IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", "PerPkg": "1", @@ -992,8 +1146,10 @@ }, { "BriefDescription": "All TOR inserts from local IO devices which h= it the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat hit the LLC", "UMask": "0xc001fd04", @@ -1001,6 +1157,7 @@ }, { "BriefDescription": "ItoMs from local IO devices which hit the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -1010,6 +1167,7 @@ }, { "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -1019,6 +1177,7 @@ }, { "BriefDescription": "PCIRDCURs issued by IO devices which hit the = LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -1028,6 +1187,7 @@ }, { "BriefDescription": "RFOs from local IO devices which hit the cach= e", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", "PerPkg": "1", @@ -1037,6 +1197,7 @@ }, { "BriefDescription": "All TOR ItoM inserts from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -1046,6 +1207,7 @@ }, { "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -1055,8 +1217,10 @@ }, { "BriefDescription": "All TOR inserts from local IO devices which m= iss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC", "UMask": "0xc001fe04", @@ -1064,6 +1228,7 @@ }, { "BriefDescription": "All TOR ItoM inserts from local IO devices wh= ich miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -1073,6 +1238,7 @@ }, { "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -1082,6 +1248,7 @@ }, { "BriefDescription": "PCIRDCURs issued by IO devices which miss the= LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -1091,6 +1258,7 @@ }, { "BriefDescription": "All TOR RFO inserts from local IO devices whi= ch miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", "PerPkg": "1", @@ -1100,6 +1268,7 @@ }, { "BriefDescription": "PCIRDCURs issued by IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -1109,6 +1278,7 @@ }, { "BriefDescription": "RFOs from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", "PerPkg": "1", @@ -1118,6 +1288,7 @@ }, { "BriefDescription": "WBMtoI requests from IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", "PerPkg": "1", @@ -1127,6 +1298,7 @@ }, { "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", "PerPkg": "1", @@ -1136,8 +1308,10 @@ }, { "BriefDescription": "All locally initiated requests", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO", "UMask": "0xc000ff05", @@ -1145,8 +1319,10 @@ }, { "BriefDescription": "All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA", "UMask": "0xc000ff01", @@ -1154,8 +1330,10 @@ }, { "BriefDescription": "All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO", "UMask": "0xc000ff04", @@ -1163,8 +1341,10 @@ }, { "BriefDescription": "Occupancy for all TOR entries", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All", "UMask": "0xc001ffff", @@ -1172,8 +1352,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores", "UMask": "0xc001ff01", @@ -1181,6 +1363,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlush events that are ini= tiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", @@ -1190,6 +1373,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlushOpt events that are = initiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", "PerPkg": "1", @@ -1199,6 +1383,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -1208,6 +1393,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", "PerPkg": "1", @@ -1217,8 +1403,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", "UMask": "0xc827ff01", @@ -1226,8 +1414,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores", "UMask": "0xc8a7ff01", @@ -1235,8 +1425,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Hit the LLC", "UMask": "0xc001fd01", @@ -1244,6 +1436,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "PerPkg": "1", @@ -1253,6 +1446,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -1262,8 +1456,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = that hit the LLC", "UMask": "0xc827fd01", @@ -1271,8 +1467,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that hit the LLC", "UMask": "0xc8a7fd01", @@ -1280,6 +1478,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", "PerPkg": "1", @@ -1289,6 +1488,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", "PerPkg": "1", @@ -1298,6 +1498,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", "PerPkg": "1", @@ -1307,6 +1508,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -1316,6 +1518,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "PerPkg": "1", @@ -1325,6 +1528,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -1334,6 +1538,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM events that are initia= ted from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", "PerPkg": "1", @@ -1343,6 +1548,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from= local IA cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", "PerPkg": "1", @@ -1352,6 +1558,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", "PerPkg": "1", @@ -1361,6 +1568,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", "PerPkg": "1", @@ -1370,6 +1578,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", "PerPkg": "1", @@ -1379,8 +1588,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Missed the LLC", "UMask": "0xc001fe01", @@ -1388,6 +1599,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -1397,6 +1609,7 @@ }, { "BriefDescription": "TOR Occupancy for CRDs from local IA cores to= locally homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", "PerPkg": "1", @@ -1406,6 +1619,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -1415,6 +1629,7 @@ }, { "BriefDescription": "TOR Occupancy for CRD Prefetches from local I= A cores to locally homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", @@ -1424,8 +1639,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores t= hat missed the LLC", "UMask": "0xc827fe01", @@ -1433,8 +1650,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC", "UMask": "0xc8a7fe01", @@ -1442,6 +1661,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", "PerPkg": "1", @@ -1451,6 +1671,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", "PerPkg": "1", @@ -1460,6 +1681,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -1469,6 +1691,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -1478,6 +1701,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to locally homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", @@ -1487,6 +1711,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to locally homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", @@ -1496,6 +1721,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -1505,6 +1731,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -1514,6 +1741,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -1523,6 +1751,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -1532,6 +1761,7 @@ }, { "BriefDescription": "TOR Occupancy for UCRDF requests from local I= A cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", "PerPkg": "1", @@ -1541,6 +1771,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", "PerPkg": "1", @@ -1550,6 +1781,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", "PerPkg": "1", @@ -1559,6 +1791,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to DDR homed addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", "PerPkg": "1", @@ -1568,6 +1801,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to DDR homed addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", "PerPkg": "1", @@ -1577,6 +1811,7 @@ }, { "BriefDescription": "TOR Occupancy for WIL requests from local IA = cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", "PerPkg": "1", @@ -1586,6 +1821,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -1595,6 +1831,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", "PerPkg": "1", @@ -1604,6 +1841,7 @@ }, { "BriefDescription": "TOR Occupancy for SpecItoM events that are in= itiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", "PerPkg": "1", @@ -1613,6 +1851,7 @@ }, { "BriefDescription": "TOR Occupancy for WbMtoI requests from local = IA cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", "PerPkg": "1", @@ -1622,6 +1861,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", "PerPkg": "1", @@ -1631,6 +1871,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", "PerPkg": "1", @@ -1640,8 +1881,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= ", "UMask": "0xc001ff04", @@ -1649,6 +1892,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlush requests from IO de= vices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", "PerPkg": "1", @@ -1658,8 +1902,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= that hit the LLC", "UMask": "0xc001fd04", @@ -1667,6 +1913,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMs from local IO devices= which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", "PerPkg": "1", @@ -1676,6 +1923,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -1685,6 +1933,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -1694,6 +1943,7 @@ }, { "BriefDescription": "TOR Occupancy for RFOs from local IO devices = which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", "PerPkg": "1", @@ -1703,6 +1953,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", "PerPkg": "1", @@ -1712,6 +1963,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -1721,8 +1973,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= that missed the LLC", "UMask": "0xc001fe04", @@ -1730,6 +1984,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", "PerPkg": "1", @@ -1739,6 +1994,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -1748,6 +2004,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which miss the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -1757,6 +2014,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR RFO inserts from lo= cal IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", "PerPkg": "1", @@ -1766,6 +2024,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -1775,6 +2034,7 @@ }, { "BriefDescription": "TOR Occupancy for RFOs from local IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", "PerPkg": "1", @@ -1784,6 +2044,7 @@ }, { "BriefDescription": "TOR Occupancy for WBMtoI requests from IO dev= ices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", "PerPkg": "1", @@ -1793,8 +2054,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO", "UMask": "0xc000ff05", @@ -1802,8 +2065,10 @@ }, { "BriefDescription": "TOR Occupancy for All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA", "UMask": "0xc000ff01", @@ -1811,8 +2076,10 @@ }, { "BriefDescription": "TOR Occupancy for All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO", "UMask": "0xc000ff04", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/grandridge/uncore-interconnect.json index 9091f8fde51f..6aaca4039107 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_B2CMI_CLOCKTICKS", "PerPkg": "1", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of times B2CMI egress did D= 2C (direct to core)", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of times D2C wasn't honoure= d even though the incoming request had d2c set for non cisgress txn", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts any read", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.ALL", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.NORMAL", "PerPkg": "1", @@ -40,14 +45,17 @@ }, { "BriefDescription": "Counts reads to 1lm non persistent memory reg= ions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "B2CMI" }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.ALL", "PerPkg": "1", @@ -56,6 +64,7 @@ }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.FULL", "PerPkg": "1", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -72,22 +82,27 @@ }, { "BriefDescription": "DDR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x120", "Unit": "B2CMI" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", "PerPkg": "1", @@ -97,14 +112,17 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_B2CMI_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", "PerPkg": "1", @@ -113,6 +131,7 @@ }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", @@ -121,22 +140,27 @@ }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_B2CMI_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Total Write Cache Occupancy : Mem", + "Counter": "0,1,2,3", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "IRP Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -144,6 +168,7 @@ }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -151,21 +176,26 @@ }, { "BriefDescription": "FAF occupancy", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pu= lled away ownership before a write was committed", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.LOST_FWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Inbound write (fast path) requests to coheren= t memory, received by the IRP resulting in write ownership requests issued = by IRP to the mesh.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json b/too= ls/perf/pmu-events/arch/x86/grandridge/uncore-io.json index c301ef95ae8d..33fc7b835abf 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "IIO Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -9,8 +10,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -19,8 +22,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -29,8 +34,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -39,8 +46,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -49,8 +58,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -59,8 +70,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -69,8 +82,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -79,8 +94,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -89,8 +106,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -99,8 +118,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -109,8 +130,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -119,8 +142,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -129,8 +154,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -139,8 +166,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -149,8 +178,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -159,8 +190,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -169,8 +202,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -179,8 +214,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -189,6 +226,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", "FCMask": "0x07", @@ -199,8 +237,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -209,8 +249,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -219,8 +261,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -229,8 +273,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -239,8 +285,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -249,8 +297,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -259,8 +309,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -269,8 +321,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -279,6 +333,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", "FCMask": "0x07", @@ -289,6 +344,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -299,6 +355,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -309,6 +366,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -319,6 +377,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -329,6 +388,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -339,6 +399,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -349,6 +410,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -359,6 +421,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -369,6 +432,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -379,6 +443,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -389,6 +454,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -399,6 +465,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -409,6 +476,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -419,6 +487,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -429,6 +498,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -439,6 +509,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -449,6 +520,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -459,6 +531,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -469,6 +542,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -479,6 +553,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -489,6 +564,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -499,6 +575,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -509,6 +586,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -519,6 +597,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -529,8 +608,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -539,8 +620,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -549,8 +632,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -559,8 +644,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -569,8 +656,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -579,8 +668,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -589,8 +680,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -599,8 +692,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -609,8 +704,10 @@ }, { "BriefDescription": "IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10", @@ -618,8 +715,10 @@ }, { "BriefDescription": "IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x8", @@ -627,8 +726,10 @@ }, { "BriefDescription": "IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x4", @@ -636,8 +737,10 @@ }, { "BriefDescription": "Context cache hits", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x80", @@ -645,8 +748,10 @@ }, { "BriefDescription": "Context cache lookups", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x40", @@ -654,8 +759,10 @@ }, { "BriefDescription": "IOTLB lookups first", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x1", @@ -663,8 +770,10 @@ }, { "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20", @@ -672,8 +781,10 @@ }, { "BriefDescription": "IOMMU memory access (both low and high priori= ty)", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0xc0", @@ -681,8 +792,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page= ", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x4", @@ -690,8 +803,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 256T pa= ge", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10", @@ -699,8 +814,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 512G pa= ge", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x8", @@ -708,8 +825,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -718,8 +837,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -728,8 +849,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -738,8 +861,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -748,8 +873,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -758,8 +885,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -768,8 +897,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -778,14 +909,17 @@ }, { "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -796,6 +930,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -806,6 +941,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -816,6 +952,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -826,6 +963,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -836,6 +974,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -846,6 +985,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -856,6 +996,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -866,6 +1007,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -876,6 +1018,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -886,6 +1029,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -896,6 +1040,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -906,6 +1051,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -916,6 +1062,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -926,6 +1073,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -936,6 +1084,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -946,6 +1095,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -956,6 +1106,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -966,6 +1117,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -976,6 +1128,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -986,6 +1139,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -996,6 +1150,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1006,6 +1161,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1016,6 +1172,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1026,6 +1183,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1036,6 +1194,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1046,6 +1205,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1056,6 +1216,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1066,6 +1227,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1076,6 +1238,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1086,6 +1249,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1096,6 +1260,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1106,8 +1271,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -1116,8 +1283,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -1126,8 +1295,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -1136,8 +1307,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -1146,8 +1319,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -1156,8 +1331,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -1166,8 +1343,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -1176,8 +1355,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json index a2405ed640c9..7e6e6764f181 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count : Counts the number of DR= AM Activate commands sent on this channel. Activate commands are issued to= open up a page on the DRAM devices so that it can be read or written to wi= th a CAS. One can calculate the number of Page Misses by subtracting the n= umber of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -9,30 +10,37 @@ }, { "BriefDescription": "DRAM Activate Count : Read transaction on Pag= e Empty or Page Miss : Counts the number of DRAM Activate commands sent on = this channel. Activate commands are issued to open up a page on the DRAM d= evices so that it can be read or written to with a CAS. One can calculate = the number of Page Misses by subtracting the number of Page Miss precharges= from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf1", "Unit": "IMC" }, { "BriefDescription": "DRAM Activate Count : Underfill Read transact= ion on Page Empty or Page Miss : Counts the number of DRAM Activate command= s sent on this channel. Activate commands are issued to open up a page on = the DRAM devices so that it can be read or written to with a CAS. One can = calculate the number of Page Misses by subtracting the number of Page Miss = precharges from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf4", "Unit": "IMC" }, { "BriefDescription": "DRAM Activate Count : Write transaction on Pa= ge Empty or Page Miss : Counts the number of DRAM Activate commands sent on= this channel. Activate commands are issued to open up a page on the DRAM = devices so that it can be read or written to with a CAS. One can calculate= the number of Page Misses by subtracting the number of Page Miss precharge= s from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf2", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 0, all CAS operation= s", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", "PerPkg": "1", @@ -41,6 +49,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD", "PerPkg": "1", @@ -49,6 +58,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", "PerPkg": "1", @@ -57,6 +67,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", "PerPkg": "1", @@ -65,6 +76,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR", "PerPkg": "1", @@ -73,22 +85,27 @@ }, { "BriefDescription": "CAS count for SubChannel 0 regular writes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 0 auto-precharge wri= tes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 1, all CAS operation= s", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", "PerPkg": "1", @@ -97,6 +114,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD", "PerPkg": "1", @@ -105,6 +123,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", "PerPkg": "1", @@ -113,6 +132,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", "PerPkg": "1", @@ -121,6 +141,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR", "PerPkg": "1", @@ -129,22 +150,27 @@ }, { "BriefDescription": "CAS count for SubChannel 1 regular writes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 1 auto-precharge wri= tes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "IMC" }, { "BriefDescription": "Number of DRAM DCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -154,14 +180,17 @@ }, { "BriefDescription": "Number of DRAM HCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_HCLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Clockticks", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -170,6 +199,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to (= ?) : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -178,46 +208,57 @@ }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf1", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf4", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf2", "Unit": "IMC" }, { "BriefDescription": "Read buffer inserts on subchannel 0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.SCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IMC" }, { "BriefDescription": "Read buffer inserts on subchannel 1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.SCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IMC" }, { "BriefDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", "PerPkg": "1", @@ -225,6 +266,7 @@ }, { "BriefDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", "PerPkg": "1", @@ -232,22 +274,27 @@ }, { "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "IMC" }, { "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "IMC" }, { "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", "PerPkg": "1", @@ -256,6 +303,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", "PerPkg": "1", @@ -264,6 +312,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", "PerPkg": "1", @@ -272,6 +321,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", "PerPkg": "1", @@ -280,6 +330,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", "PerPkg": "1", @@ -287,6 +338,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", "PerPkg": "1", @@ -294,6 +346,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", "PerPkg": "1", @@ -301,6 +354,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", "PerPkg": "1", @@ -308,22 +362,27 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "IMC" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "IMC" }, { "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", "PerPkg": "1", @@ -332,6 +391,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", "PerPkg": "1", @@ -340,6 +400,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", "PerPkg": "1", @@ -348,6 +409,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", "PerPkg": "1", @@ -356,6 +418,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", "PerPkg": "1", @@ -363,6 +426,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", "PerPkg": "1", @@ -370,6 +434,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", "PerPkg": "1", @@ -377,6 +442,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/uncore-power.json b/= tools/perf/pmu-events/arch/x86/grandridge/uncore-power.json index e3a66166e28c..02e59f64a544 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCU Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json index 371974c6d6c3..35cc5b6d41f2 100644 --- a/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/grandridge/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or Loads (demand or SW prefetch) in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Accounts= for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -61,6 +69,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", "SampleAfterValue": "1000003", @@ -84,6 +95,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -99,6 +112,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -107,6 +121,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -115,6 +130,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or iside in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for iside in PMH every cycle. A PMH page walk is outstanding from page wal= k start till PMH becomes idle again (ready to serve next walk). Includes EP= T-walk intervals. Walks could be counted by edge detecting on this event, = but would count restarted suspended walks.", @@ -123,6 +139,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.DTLB_MISS_AT_RET", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index a53b88154a58..53c16bb56fdf 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -10,7 +10,7 @@ GenuineIntel-6-9[6C],v1.05,elkhartlake,core GenuineIntel-6-CF,v1.09,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core -GenuineIntel-6-B6,v1.02,grandridge,core +GenuineIntel-6-B6,v1.03,grandridge,core GenuineIntel-6-A[DE],v1.01,graniterapids,core GenuineIntel-6-(3C|45|46),v35,haswell,core GenuineIntel-6-3F,v28,haswellx,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ABA0D1B3F0E for ; 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Thu, 20 Jun 2024 11:19:44 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:27 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-14-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 13/37] perf vendor events: Update graniterapids events and add counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.01 to v1.02. Bring in the event updates v1.02: https://github.com/intel/perfmon/commit/0ff9f681bd07d0e84026c52f4941d21b1cd= 4c171 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ There are over 1000 new events. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/graniterapids/cache.json | 825 ++++ .../arch/x86/graniterapids/counter.json | 77 + .../x86/graniterapids/floating-point.json | 242 ++ .../arch/x86/graniterapids/frontend.json | 469 ++- .../arch/x86/graniterapids/memory.json | 175 +- .../arch/x86/graniterapids/other.json | 150 +- .../arch/x86/graniterapids/pipeline.json | 1009 ++++- .../arch/x86/graniterapids/uncore-cache.json | 3674 +++++++++++++++++ .../arch/x86/graniterapids/uncore-cxl.json | 31 + .../graniterapids/uncore-interconnect.json | 1849 +++++++++ .../arch/x86/graniterapids/uncore-io.json | 1901 +++++++++ .../arch/x86/graniterapids/uncore-memory.json | 449 ++ .../arch/x86/graniterapids/uncore-power.json | 11 + .../x86/graniterapids/virtual-memory.json | 159 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 15 files changed, 10975 insertions(+), 48 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/counter.js= on create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/floating-p= oint.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-cac= he.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-cxl= .json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-int= erconnect.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-io.= json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-mem= ory.json create mode 100644 tools/perf/pmu-events/arch/x86/graniterapids/uncore-pow= er.json diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json b/tool= s/perf/pmu-events/arch/x86/graniterapids/cache.json index 56212827870c..b56066274813 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/cache.json @@ -1,6 +1,135 @@ [ + { + "BriefDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "L1D.HWPF_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", + "EventCode": "0x51", + "EventName": "L1D.REPLACEMENT", + "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS", + "PublicDescription": "Counts number of phases a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.L2_STALLS", + "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING", + "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x48", + "EventName": "L1D_PEND_MISS.PENDING_CYCLES", + "PublicDescription": "Counts duration of L1D miss outstanding in c= ycles.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "L2_LINES_IN.ALL", + "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", + "SampleAfterValue": "100003", + "UMask": "0x1f" + }, + { + "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.NON_SILENT", + "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.SILENT", + "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.ALL", + "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_RQSTS.REFERENCES]", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "All requests that hit L2 cache. [This event i= s alias to L2_RQSTS.HIT]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This= event is alias to L2_RQSTS.HIT]", + "SampleAfterValue": "200003", + "UMask": "0xdf" + }, + { + "BriefDescription": "Read requests with true-miss in L2 cache [Thi= s event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_REQUEST.MISS", + "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_RQSTS.MISS]", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -9,14 +138,167 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", "SampleAfterValue": "200003", "UMask": "0xe1" }, + { + "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_MISS", + "PublicDescription": "Counts demand requests that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x27" + }, + { + "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", + "PublicDescription": "Counts demand requests to L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xe7" + }, + { + "BriefDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_HWPF", + "SampleAfterValue": "200003", + "UMask": "0xf0" + }, + { + "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.ALL_RFO", + "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", + "SampleAfterValue": "200003", + "UMask": "0xe2" + }, + { + "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_HIT", + "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", + "SampleAfterValue": "200003", + "UMask": "0xc4" + }, + { + "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.CODE_RD_MISS", + "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", + "SampleAfterValue": "200003", + "UMask": "0x24" + }, + { + "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", + "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc1" + }, + { + "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", + "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", + "SampleAfterValue": "200003", + "UMask": "0x21" + }, + { + "BriefDescription": "All requests that hit L2 cache. [This event i= s alias to L2_REQUEST.HIT]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.HIT", + "PublicDescription": "Counts all requests that hit L2 cache. [This= event is alias to L2_REQUEST.HIT]", + "SampleAfterValue": "200003", + "UMask": "0xdf" + }, + { + "BriefDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.HWPF_MISS", + "SampleAfterValue": "200003", + "UMask": "0x30" + }, + { + "BriefDescription": "Read requests with true-miss in L2 cache [Thi= s event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.MISS", + "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_REQUEST.MISS]", + "SampleAfterValue": "200003", + "UMask": "0x3f" + }, + { + "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.REFERENCES", + "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_REQUEST.ALL]", + "SampleAfterValue": "200003", + "UMask": "0xff" + }, + { + "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_HIT", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0xc2" + }, + { + "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.RFO_MISS", + "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x22" + }, + { + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", + "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", + "SampleAfterValue": "200003", + "UMask": "0xc8" + }, + { + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", + "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", + "SampleAfterValue": "200003", + "UMask": "0x28" + }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -25,6 +307,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -33,6 +316,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -43,6 +327,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -50,5 +335,545 @@ "PublicDescription": "Counts all retired store instructions.", "SampleAfterValue": "1000003", "UMask": "0x82" + }, + { + "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.ANY", + "PEBS": "1", + "PublicDescription": "Counts all retired memory instructions - loa= ds and stores.", + "SampleAfterValue": "1000003", + "UMask": "0x83" + }, + { + "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.LOCK_LOADS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with locked= access.", + "SampleAfterValue": "100007", + "UMask": "0x21" + }, + { + "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions that split = across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x41" + }, + { + "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.SPLIT_STORES", + "PEBS": "1", + "PublicDescription": "Counts retired store instructions that split= across a cacheline boundary.", + "SampleAfterValue": "100003", + "UMask": "0x42" + }, + { + "BriefDescription": "Retired load instructions that hit the STLB.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS", + "PEBS": "1", + "PublicDescription": "Number of retired load instructions with a c= lean hit in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x9" + }, + { + "BriefDescription": "Retired store instructions that hit the STLB.= ", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES", + "PEBS": "1", + "PublicDescription": "Number of retired store instructions that hi= t in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0xa" + }, + { + "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", + "PEBS": "1", + "PublicDescription": "Number of retired load instructions that (st= art a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x11" + }, + { + "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd0", + "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", + "PEBS": "1", + "PublicDescription": "Number of retired store instructions that (s= tart a) miss in the 2nd-level TLB (STLB).", + "SampleAfterValue": "100003", + "UMask": "0x12" + }, + { + "BriefDescription": "Completed demand load uops that miss the L1 d= -cache.", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", + "PublicDescription": "Number of completed demand load requests tha= t missed the L1 data cache including shadow misses (FB hits, merge to an on= going L1D miss)", + "SampleAfterValue": "1000003", + "UMask": "0xfd" + }, + { + "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions whose data = sources were HitM responses from shared L3.", + "SampleAfterValue": "20011", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", + "PEBS": "1", + "PublicDescription": "Counts the retired load instructions whose d= ata sources were L3 hit and cross-core snoop missed in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions whose data = sources were hits in L3 without snoops required.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd2", + "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", + "SampleAfterValue": "20011", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", + "PEBS": "1", + "PublicDescription": "Retired load instructions which data sources= missed L3 but serviced from local DRAM.", + "SampleAfterValue": "100007", + "UMask": "0x1" + }, + { + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "PEBS": "1", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", + "PEBS": "1", + "PublicDescription": "Retired load instructions whose data sources= was forwarded from a remote cache.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd3", + "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "PEBS": "1", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd4", + "EventName": "MEM_LOAD_MISC_RETIRED.UC", + "PEBS": "1", + "PublicDescription": "Retired instructions with at least one load = to uncacheable memory-type, or at least one cache-line split locked access = (Bus Lock).", + "SampleAfterValue": "100007", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.FB_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding= miss to the same cache line with data not ready.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L1 data cache. This event includes all SW prefet= ches and lock instructions regardless of the data source.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L1_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L1 cache.", + "SampleAfterValue": "200003", + "UMask": "0x8" + }, + { + "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with L2 cac= he hits as data sources.", + "SampleAfterValue": "200003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L2_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions missed L2 c= ache as data sources.", + "SampleAfterValue": "100021", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_HIT", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that hit in the L3 cache.", + "SampleAfterValue": "100021", + "UMask": "0x4" + }, + { + "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", + "Data_LA": "1", + "EventCode": "0xd1", + "EventName": "MEM_LOAD_RETIRED.L3_MISS", + "PEBS": "1", + "PublicDescription": "Counts retired load instructions with at lea= st one uop that missed in the L3 cache.", + "SampleAfterValue": "50021", + "UMask": "0x20" + }, + { + "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", + "EventCode": "0x44", + "EventName": "MEM_STORE_RETIRED.L2_HIT", + "SampleAfterValue": "200003", + "UMask": "0x1" + }, + { + "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe5", + "EventName": "MEM_UOP_RETIRED.ANY", + "PublicDescription": "Number of retired micro-operations (uops) fo= r load or store memory accesses", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit in the L3 or were snooped from another co= re's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that resulted in a snoop hit a modified line in an= other core's caches which forwarded the data.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that hit in the L3 o= r were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a s= noop hit a modified line in another core's caches which forwarded the data.= ", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another core's caches which forwarded the unmodified data to th= e requesting core.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit in= the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F803C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that result= ed in a snoop hit a modified line in another core's caches which forwarded = the data.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit in the L3 or were snooped from another core's caches on the sa= me socket.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.L3_HIT", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F003C4477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", + "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DATA_RD", + "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cacheable and Non-Cacheable code read request= s", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and Non-Cacheable code= read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", + "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", + "PublicDescription": "Counts cycles when offcore outstanding cache= able Core Data Read transactions are present in the super queue. A transact= ion is considered to be in the Offcore outstanding state between L2 miss an= d transaction completion sent to requestor (SQ de-allocation). See correspo= nding Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 outstanding demand da= ta read request is pending.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", + "PublicDescription": "Counts the number of offcore outstanding dem= and rfo Reads transactions in the super queue every cycle. The 'Offcore out= standing' state of the transaction lasts from the L2 miss until the sending= transaction completion to requestor (SQ deallocation). See the correspondi= ng Umask under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", + "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", + "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", + "EventCode": "0x2c", + "EventName": "SQ_MISC.BUS_LOCK", + "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, + { + "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.NTA", + "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", + "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.T0", + "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.T1_T2", + "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", + "SampleAfterValue": "100003", + "UMask": "0x4" } ] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/counter.json b/to= ols/perf/pmu-events/arch/x86/graniterapids/counter.json new file mode 100644 index 000000000000..250781a8ca64 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/counter.json @@ -0,0 +1,77 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "B2CMI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "B2HOT", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "B2UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "B2CXL", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "CHACMS", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "MDF", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CXLCM", + "CountersNumFixed": "0", + "CountersNumGeneric": 8 + }, + { + "Unit": "CXLDP", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/floating-point.js= on b/tools/perf/pmu-events/arch/x86/graniterapids/floating-point.json new file mode 100644 index 000000000000..59789eee060c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/floating-point.json @@ -0,0 +1,242 @@ +[ + { + "BriefDescription": "This event counts the cycles the floating poi= nt divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.FPDIV_ACTIVE", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.FP", + "PublicDescription": "Counts all microcode Floating Point assists.= ", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.SSE_AVX_MIX", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is ali= as to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is ali= as to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is ali= as to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.PORT_5", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.V0", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.V1", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb3", + "EventName": "FP_ARITH_DISPATCHED.V2", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x18" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x40" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", + "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", + "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x60" + }, + { + "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", + "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", + "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_ARITH_INST_RETIRED.VECTOR", + "PublicDescription": "Number of any Vector retired FP arithmetic i= nstructions. The DAZ and FTZ flags in the MXCSR register need to be set wh= en using these events.", + "SampleAfterValue": "1000003", + "UMask": "0xfc" + }, + { + "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of all Scalar Half-Precision FP arithm= etic instructions(1) retired - regular and complex.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", + "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", + "SampleAfterValue": "100003", + "UMask": "0x3" + }, + { + "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of all Vector (also called packed) Hal= f-Precision FP arithmetic instructions(1) retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcf", + "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", + "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", + "SampleAfterValue": "100003", + "UMask": "0x1c" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json b/t= ools/perf/pmu-events/arch/x86/graniterapids/frontend.json index c6d5016e7337..663c1a0e55a2 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/frontend.json @@ -1,9 +1,474 @@ [ { - "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were no operation was delivered to the back-end pipeline due = to instruction fetch limitations when the back-end could have accepted more= operations. Common examples include instruction cache misses or x86 instru= ction decode limitations.", + "BriefDescription": "Clears due to Unknown Branches.", + "Counter": "0,1,2,3", + "EventCode": "0x60", + "EventName": "BACLEARS.ANY", + "PublicDescription": "Number of times the front-end is resteered w= hen it finds a branch instruction in a fetch line. This is called Unknown B= ranch which occurs for the first time a branch instruction is fetched or wh= en the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "DECODE.LCP", + "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "DECODE.MS_BUSY", + "SampleAfterValue": "500009", + "UMask": "0x2" + }, + { + "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", + "EventCode": "0x61", + "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", + "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired ANT branches", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_ANT", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "PEBS": "1", + "PublicDescription": "Always Not Taken (ANT) conditional retired b= ranches (no BTB entry and not mispredicted)", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x1", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.DSB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x11", + "PEBS": "1", + "PublicDescription": "Number of retired Instructions that experien= ced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache= ) miss. Critical means stalls were exposed to the back-end as a result of t= he DSB miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.ITLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x14", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= iTLB (Instruction TLB) true miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L1I_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x12", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions who experienced = Instruction L1 Cache true miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.L2_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x13", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions who experienced = Instruction L2 Cache true miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x600106", + "PEBS": "1", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 1 cycle which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", + "MSRIndex": "0x3F7", + "MSRValue": "0x608006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 12= 8 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", + "MSRIndex": "0x3F7", + "MSRValue": "0x601006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 16 cycles. During th= is period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", + "MSRIndex": "0x3F7", + "MSRValue": "0x600206", + "PEBS": "1", + "PublicDescription": "Retired instructions that are fetched after = an interval where the front-end delivered no uops for a period of at least = 2 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", + "MSRIndex": "0x3F7", + "MSRValue": "0x610006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 25= 6 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", + "MSRIndex": "0x3F7", + "MSRValue": "0x100206", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after the front-end had at least 1 bubble-slot for a per= iod of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there = was no RAT stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", + "MSRIndex": "0x3F7", + "MSRValue": "0x602006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 32 cycles. During th= is period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", + "MSRIndex": "0x3F7", + "MSRValue": "0x600406", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 4 = cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", + "MSRIndex": "0x3F7", + "MSRValue": "0x620006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 51= 2 cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", + "MSRIndex": "0x3F7", + "MSRValue": "0x604006", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are fetched= after an interval where the front-end delivered no uops for a period of 64= cycles which was not interrupted by a back-end stall.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", + "MSRIndex": "0x3F7", + "MSRValue": "0x600806", + "PEBS": "1", + "PublicDescription": "Counts retired instructions that are deliver= ed to the back-end after a front-end stall of at least 8 cycles. During thi= s period the front-end delivered no uops.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "I-Cache miss too close to Code Prefetch Instr= uction", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.LATE_SWPF", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "PEBS": "1", + "PublicDescription": "Number of Instruction Cache demand miss in s= hadow of an on-going i-fetch cache-line triggered by PREFETCHIT0/1 instruct= ions", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Mispredicted Retired ANT branches", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.MISP_ANT", + "MSRIndex": "0x3F7", + "MSRValue": "0x9", + "PEBS": "1", + "PublicDescription": "ANT retired branches that got just mispredic= ted", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.MS_FLOWS", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.STLB_MISS", + "MSRIndex": "0x3F7", + "MSRValue": "0x15", + "PEBS": "1", + "PublicDescription": "Counts retired Instructions that experienced= STLB (2nd level TLB) true miss.", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc6", + "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "MSRIndex": "0x3F7", + "MSRValue": "0x17", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x3" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALLS", + "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The decode pipeline works at a 32= Byte granularity.", + "SampleAfterValue": "500009", + "UMask": "0x4" + }, + { + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "SampleAfterValue": "500009", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "ICACHE_TAG.STALLS", + "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", + "SampleAfterValue": "200003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_ANY", + "PublicDescription": "Counts the number of cycles uops were delive= red to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) p= ath.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x79", + "EventName": "IDQ.DSB_CYCLES_OK", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the D= SB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the I= DQ.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.DSB_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_ANY", + "PublicDescription": "Counts the number of cycles uops were delive= red to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipe= line) path. During these cycles uops are not being delivered from the Decod= e Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0x79", + "EventName": "IDQ.MITE_CYCLES_OK", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MITE_UOPS", + "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_CYCLES_ANY", + "PublicDescription": "Counts cycles during which uops are being de= livered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS= ) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x79", + "EventName": "IDQ.MS_SWITCHES", + "PublicDescription": "Number of switches from DSB (Decode Stream B= uffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Uops initiated by MITE or Decode Stream Buffe= r (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Seq= uencer (MS) is busy", + "Counter": "0,1,2,3", + "EventCode": "0x79", + "EventName": "IDQ.MS_UOPS", + "PublicDescription": "Counts the number of uops initiated by MITE = or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (ID= Q) while the Microcode Sequencer (MS) is busy. Counting includes uops that = may 'bypass' the IDQ.", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that when no operation was delivered to the back-end pipeline due = to instruction fetch limitations when the back-end could have accepted more= operations. Common examples include instruction cache misses or x86 instru= ction decode limitations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", - "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were no operation was delivered to the back-end pipeline due= to instruction fetch limitations when the back-end could have accepted mor= e operations. Common examples include instruction cache misses or x86 instr= uction decode limitations.\nThe count may be distributed among unhalted log= ical processors (hyper-threads) who share the same physical core, in proces= sors that support Intel Hyper-Threading Technology. Software can use this e= vent as the numerator for the Frontend Bound metric (or top-level category)= of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that when no operation was delivered to the back-end pipeline due= to instruction fetch limitations when the back-end could have accepted mor= e operations. Common examples include instruction cache misses or x86 instr= uction decode limitations. The count may be distributed among unhalted logi= cal processors (hyper-threads) who share the same physical core, in process= ors that support Intel Hyper-Threading Technology. Software can use this ev= ent as the numerator for the Frontend Bound metric (or top-level category) = of the Top-down Microarchitecture Analysis method.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CYCLES= _0_UOPS_DELIV.CORE]", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9c", + "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", + "Invert": "1", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle. [This event is alias to IDQ_UOPS_N= OT_DELIVERED.CYCLES_FE_WAS_OK]", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", + "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", + "PublicDescription": "Counts the number of cycles when no uops wer= e delivered by the Instruction Decode Queue (IDQ) to the back-end of the pi= peline when there was no back-end stalls. This event counts for one SMT thr= ead in a given cycle. [This event is alias to IDQ_BUBBLES.CYCLES_0_UOPS_DEL= IV.CORE]", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0x9c", + "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", + "Invert": "1", + "PublicDescription": "Counts the number of cycles when the optimal= number of uops were delivered by the Instruction Decode Queue (IDQ) to the= back-end of the pipeline when there was no back-end stalls. This event cou= nts for one SMT thread in a given cycle. [This event is alias to IDQ_BUBBLE= S.CYCLES_FE_WAS_OK]", "SampleAfterValue": "1000003", "UMask": "0x1" } diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/memory.json b/too= ls/perf/pmu-events/arch/x86/graniterapids/memory.json index 1c0e0e86e58e..38b74c6752c2 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/memory.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/memory.json @@ -1,6 +1,85 @@ [ + { + "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "6", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x6" + }, + { + "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", + "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", + "CounterMask": "2", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "3", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", + "PublicDescription": "Execution stalls while L2 cache miss demand = cacheable load request is outstanding (will not count for uncacheable deman= d requests e.g. bus lock).", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Execution stalls while L3 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "9", + "EventCode": "0x47", + "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", + "PublicDescription": "Execution stalls while L3 cache miss demand = cacheable load request is outstanding (will not count for uncacheable deman= d requests e.g. bus lock).", + "SampleAfterValue": "1000003", + "UMask": "0x9" + }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 1024 cycles. Reporte= d latency may be longer than just the memory latency.", + "SampleAfterValue": "53", + "UMask": "0x1" + }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -13,6 +92,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -23,8 +103,22 @@ "SampleAfterValue": "20011", "UMask": "0x1" }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 2048 cycles.", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", + "MSRIndex": "0x3F6", + "MSRValue": "0x800", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 2048 cycles. Reporte= d latency may be longer than just the memory latency.", + "SampleAfterValue": "23", + "UMask": "0x1" + }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -37,6 +131,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -49,6 +144,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -61,6 +157,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -73,6 +170,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -85,6 +183,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -97,6 +196,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -105,8 +205,19 @@ "SampleAfterValue": "1000003", "UMask": "0x2" }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3FBFC00004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -116,6 +227,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -124,51 +236,40 @@ "UMask": "0x1" }, { - "BriefDescription": "Number of times an RTM execution aborted.", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.ABORTED", - "PublicDescription": "Counts the number of times RTM abort was tri= ggered.", - "SampleAfterValue": "100003", - "UMask": "0x4" - }, - { - "BriefDescription": "Number of times an RTM execution successfully= committed", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.COMMIT", - "PublicDescription": "Counts the number of times RTM commit succee= ded.", - "SampleAfterValue": "100003", - "UMask": "0x2" - }, - { - "BriefDescription": "Number of times an RTM execution started.", - "EventCode": "0xc9", - "EventName": "RTM_RETIRED.START", - "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.L3_MISS", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FC04477", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_READ", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", + "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", - "UMask": "0x80" + "UMask": "0x10" }, { - "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", - "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", - "SampleAfterValue": "100003", - "UMask": "0x2" + "BriefDescription": "Cycles where data return is pending for a Dem= and Data Read request who miss L3 cache.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", + "PublicDescription": "Cycles with at least 1 Demand Data Read requ= ests who miss L3 cache in the superQ.", + "SampleAfterValue": "1000003", + "UMask": "0x10" }, { - "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", - "EventCode": "0x54", - "EventName": "TX_MEM.ABORT_CONFLICT", - "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", - "SampleAfterValue": "100003", - "UMask": "0x1" + "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", + "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known by the requesti= ng core to have missed the L3 cache.", + "SampleAfterValue": "2000003", + "UMask": "0x10" } ] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/other.json b/tool= s/perf/pmu-events/arch/x86/graniterapids/other.json index 5e799bae03ea..8b9b3c920934 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/other.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/other.json @@ -1,6 +1,53 @@ [ + { + "BriefDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.PAGE_FAULT", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the cycles where the AMX (Advance Matr= ix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb7", + "EventName": "EXE.AMX_BUSY", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM attached to this socket= , unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM= accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x104000004", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -9,21 +56,112 @@ "UMask": "0x1" }, { - "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S= NC Mode counts only those DRAM accesses that are controlled by the close SN= C Cluster.", + "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.DEMAND_DATA_RD.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C000001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", - "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", + "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x104000001", + "MSRValue": "0x73C000002", "SampleAfterValue": "100003", "UMask": "0x1" }, { - "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mo= de. In SNC Mode counts only those DRAM accesses that are controlled by the= close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", - "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", + "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", - "MSRValue": "0x3F3FFC0002", + "MSRValue": "0x104000002", "SampleAfterValue": "100003", "UMask": "0x1" + }, + { + "BriefDescription": "Counts writebacks of modified cachelines and = streaming stores that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10808", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x3F3FFC4477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.READS_TO_CORE.DRAM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x73C004477", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", + "EventCode": "0x2A,0x2B", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY", + "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", + "SampleAfterValue": "1000003", + "UMask": "0x7" + }, + { + "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_COUNT", + "Invert": "1", + "PublicDescription": "Counts end of periods where the Reservation = Station (RS) was empty. Could be useful to closely sample on front-end late= ncy issues (see the FRONTEND_RETIRED event of designated precise events)", + "SampleAfterValue": "100003", + "UMask": "0x7" + }, + { + "BriefDescription": "Cycles when RS was empty and a resource alloc= ation stall is asserted", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_RESOURCE", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles the uncore cannot take further request= s", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x2d", + "EventName": "XQ.FULL_CYCLES", + "PublicDescription": "number of cycles when the thread is active a= nd the uncore cannot take any further requests (for example prefetches, loa= ds or stores initiated by the Core that miss the L2 cache).", + "SampleAfterValue": "1000003", + "UMask": "0x1" } ] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json b/t= ools/perf/pmu-events/arch/x86/graniterapids/pipeline.json index 764c0435d1d2..0ef9daf64e2e 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/pipeline.json @@ -1,22 +1,347 @@ [ + { + "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.DIV_ACTIVE", + "PublicDescription": "Counts cycles when divide unit is busy execu= ting divide or square root operations. Accounts for integer and floating-po= int operations.", + "SampleAfterValue": "1000003", + "UMask": "0x9" + }, + { + "BriefDescription": "This event counts the cycles the integer divi= der is busy.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb0", + "EventName": "ARITH.IDIV_ACTIVE", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc1", + "EventName": "ASSISTS.ANY", + "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware. Examples include AD (page Access Dirt= y), FP and AVX related assists.", + "SampleAfterValue": "100003", + "UMask": "0x1b" + }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", "PublicDescription": "Counts all branch instructions retired.", "SampleAfterValue": "400009" }, + { + "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND", + "PEBS": "1", + "PublicDescription": "Counts conditional branch instructions retir= ed.", + "SampleAfterValue": "400009", + "UMask": "0x11" + }, + { + "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PublicDescription": "Counts not taken branch instructions retired= .", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.COND_TAKEN", + "PEBS": "1", + "PublicDescription": "Counts taken conditional branch instructions= retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.FAR_BRANCH", + "PEBS": "1", + "PublicDescription": "Counts far branch instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x40" + }, + { + "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.INDIRECT", + "PEBS": "1", + "PublicDescription": "Counts near indirect branch instructions ret= ired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_CALL", + "PEBS": "1", + "PublicDescription": "Counts both direct and indirect near call in= structions retired.", + "SampleAfterValue": "100007", + "UMask": "0x2" + }, + { + "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_RETURN", + "PEBS": "1", + "PublicDescription": "Counts return instructions retired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc4", + "EventName": "BR_INST_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Counts taken branch instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", "SampleAfterValue": "400009" }, + { + "BriefDescription": "All mispredicted branch instructions retired.= This precise event may be used to get the misprediction cost via the Retir= e_Latency field of PEBS. It fires on the instruction that immediately follo= ws the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x44" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND", + "PEBS": "1", + "PublicDescription": "Counts mispredicted conditional branch instr= uctions retired.", + "SampleAfterValue": "400009", + "UMask": "0x11" + }, + { + "BriefDescription": "Mispredicted conditional branch instructions = retired. This precise event may be used to get the misprediction cost via t= he Retire_Latency field of PEBS. It fires on the instruction that immediate= ly follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x51" + }, + { + "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN", + "PEBS": "1", + "PublicDescription": "Counts the number of conditional branch inst= ructions retired that were mispredicted and the branch direction was not ta= ken.", + "SampleAfterValue": "400009", + "UMask": "0x10" + }, + { + "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired. This precise event may be used to get the misprediction = cost via the Retire_Latency field of PEBS. It fires on the instruction that= immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x50" + }, + { + "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN", + "PEBS": "1", + "PublicDescription": "Counts taken conditional mispredicted branch= instructions retired.", + "SampleAfterValue": "400009", + "UMask": "0x1" + }, + { + "BriefDescription": "Mispredicted taken conditional branch instruc= tions retired. This precise event may be used to get the misprediction cost= via the Retire_Latency field of PEBS. It fires on the instruction that imm= ediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x41" + }, + { + "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT", + "PEBS": "1", + "PublicDescription": "Counts miss-predicted near indirect branch i= nstructions retired excluding returns. TSX abort is an indirect branch.", + "SampleAfterValue": "100003", + "UMask": "0x80" + }, + { + "BriefDescription": "Mispredicted indirect CALL retired.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", + "PEBS": "1", + "PublicDescription": "Counts retired mispredicted indirect (near t= aken) CALL instructions, including both register and memory indirect.", + "SampleAfterValue": "400009", + "UMask": "0x2" + }, + { + "BriefDescription": "Mispredicted indirect CALL retired. This prec= ise event may be used to get the misprediction cost via the Retire_Latency = field of PEBS. It fires on the instruction that immediately follows the mis= predicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x42" + }, + { + "BriefDescription": "Mispredicted near indirect branch instruction= s retired (excluding returns). This precise event may be used to get the mi= sprediction cost via the Retire_Latency field of PEBS. It fires on the inst= ruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.INDIRECT_COST", + "PEBS": "1", + "SampleAfterValue": "100003", + "UMask": "0xc0" + }, + { + "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", + "PEBS": "1", + "PublicDescription": "Counts number of near branch instructions re= tired that were mispredicted and taken.", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Mispredicted taken near branch instructions r= etired. This precise event may be used to get the misprediction cost via th= e Retire_Latency field of PEBS. It fires on the instruction that immediatel= y follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST", + "PEBS": "1", + "SampleAfterValue": "400009", + "UMask": "0x60" + }, + { + "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET", + "PEBS": "1", + "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts mispredicted return instructions re= tired.", + "SampleAfterValue": "100007", + "UMask": "0x8" + }, + { + "BriefDescription": "Mispredicted ret instructions retired. This p= recise event may be used to get the misprediction cost via the Retire_Laten= cy field of PEBS. It fires on the instruction that immediately follows the = mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc5", + "EventName": "BR_MISP_RETIRED.RET_COST", + "PEBS": "1", + "SampleAfterValue": "100007", + "UMask": "0x48" + }, + { + "BriefDescription": "Core clocks when the thread is in the C0.1 li= ght-weight slower wakeup time but more power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C01", + "PublicDescription": "Counts core clocks when the thread is in the= C0.1 light-weight slower wakeup time but more power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Core clocks when the thread is in the C0.2 li= ght-weight faster wakeup time but less power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C02", + "PublicDescription": "Counts core clocks when the thread is in the= C0.2 light-weight faster wakeup time but less power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Core clocks when the thread is in the C0.1 or= C0.2 or running a PAUSE in C0 ACPI state.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.C0_WAIT", + "PublicDescription": "Counts core clocks when the thread is in the= C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions)= or running the PAUSE instruction.", + "SampleAfterValue": "2000003", + "UMask": "0x70" + }, + { + "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", + "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", + "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", + "SampleAfterValue": "25003", + "UMask": "0x2" + }, + { + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.PAUSE", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xec", + "EventName": "CPU_CLK_UNHALTED.PAUSE_INST", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0x3c", + "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", + "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the eight programmable counte= rs available for other events. Note: On all current platforms this event st= ops counting during 'throttling (TM)' states duty off periods the processor= is 'halted'. The counter update is done at a lower clock rate then the co= re clock the overflow status bit for this counter may appear 'sticky'. Aft= er the counter has overflowed and software clears the overflow status bit a= nd resets the counter to less than MAX. The reset value to the counter is n= ot clocked immediately so the overflow status bit will flip 'high (1)' and = generate another PMI (if enabled) after which the reset value gets clocked = into the counter. Therefore, software will get the interrupt, read the over= flow status bit '1 for bit 34 while the counter value is less than MAX. Sof= tware should ignore this case.", "SampleAfterValue": "2000003", @@ -24,6 +349,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", @@ -32,6 +358,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -39,13 +366,150 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", + "CounterMask": "8", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "16", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "12", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", + "SampleAfterValue": "1000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", + "CounterMask": "5", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", + "SampleAfterValue": "1000003", + "UMask": "0x5" + }, + { + "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xa3", + "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles total of 2 or 3 uops are executed on a= ll ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, + { + "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", + "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", + "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", + "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "5", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", + "SampleAfterValue": "2000003", + "UMask": "0x21" + }, + { + "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", + "PublicDescription": "Counts cycles where the Store Buffer was ful= l and no loads caused an execution stall.", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", + "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", + "EventCode": "0x75", + "EventName": "INST_DECODED.DECODERS", + "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -54,30 +518,322 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", "SampleAfterValue": "2000003" }, + { + "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.MACRO_FUSED", + "PEBS": "1", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.NOP", + "PEBS": "1", + "PublicDescription": "Counts all retired NOP or ENDBR32/64 or PREF= ETCHIT0/1 instructions", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", + "Counter": "Fixed counter 0", + "EventName": "INST_RETIRED.PREC_DIST", + "PEBS": "1", + "PublicDescription": "A version of INST_RETIRED that allows for a = precise distribution of samples across instructions retired. It utilizes th= e Precise Distribution of Instructions Retired (PDIR++) feature to fix bias= in how retired instructions get sampled. Use on Fixed Counter 0.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Iterations of Repeat string retired instructi= ons.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc0", + "EventName": "INST_RETIRED.REP_ITERATION", + "PEBS": "1", + "PublicDescription": "Number of iterations of Repeat (REP) string = retired instructions such as MOVS, CMPS, and SCAS. Each has a byte, word, a= nd doubleword version and string instructions can be repeated using a repet= ition prefix, REP, that allows their architectural execution to be repeated= a number of times as specified by the RCX register. Note the number of ite= rations is implementation-dependent.", + "SampleAfterValue": "2000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xad", + "EventName": "INT_MISC.CLEARS_COUNT", + "PublicDescription": "Counts the number of speculative clears due = to any type of branch misprediction or machine clears", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", + "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", + "SampleAfterValue": "500009", + "UMask": "0x80" + }, + { + "BriefDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.MBA_STALLS", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.RECOVERY_CYCLES", + "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", + "SampleAfterValue": "500009", + "UMask": "0x1" + }, + { + "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", + "MSRIndex": "0x3F7", + "MSRValue": "0x7", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xad", + "EventName": "INT_MISC.UOP_DROPPING", + "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.128BIT", + "SampleAfterValue": "1000003", + "UMask": "0x13" + }, + { + "BriefDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.256BIT", + "SampleAfterValue": "1000003", + "UMask": "0xac" + }, + { + "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.ADD_128", + "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 128-bit vector instructions.", + "SampleAfterValue": "1000003", + "UMask": "0x3" + }, + { + "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.ADD_256", + "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 256-bit vector instructions.", + "SampleAfterValue": "1000003", + "UMask": "0xc" + }, + { + "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.MUL_256", + "SampleAfterValue": "1000003", + "UMask": "0x80" + }, + { + "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.SHUFFLES", + "SampleAfterValue": "1000003", + "UMask": "0x40" + }, + { + "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.VNNI_128", + "SampleAfterValue": "1000003", + "UMask": "0x10" + }, + { + "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe7", + "EventName": "INT_VEC_RETIRED.VNNI_256", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.ADDRESS_ALIAS", + "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "LD_BLOCKS.NO_SR", + "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", + "SampleAfterValue": "100003", + "UMask": "0x88" + }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", "SampleAfterValue": "100003", "UMask": "0x82" }, + { + "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_ACTIVE", + "PublicDescription": "Counts the cycles when at least one uop is d= elivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "6", + "EventCode": "0xa8", + "EventName": "LSD.CYCLES_OK", + "PublicDescription": "Counts the cycles when optimal number of uop= s is delivered by the LSD (Loop-stream detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa8", + "EventName": "LSD.UOPS", + "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.COUNT", + "PublicDescription": "Counts the number of machine clears (nukes) = of any type.", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.SMC", + "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "LFENCE instructions retired", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xe0", + "EventName": "MISC2_RETIRED.LFENCE", + "PublicDescription": "number of LFENCE retired instructions", + "SampleAfterValue": "400009", + "UMask": "0x20" + }, + { + "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa2", + "EventName": "RESOURCE_STALLS.SCOREBOARD", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were not consumed by the back-end pipeline due to lack of bac= k-end resources, as a result of memory subsystem delays, execution units li= mitations, or other conditions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", - "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were not consumed by the back-end pipeline due to lack of ba= ck-end resources, as a result of memory subsystem delays, execution units l= imitations, or other conditions.\nThe count is distributed among unhalted l= ogical processors (hyper-threads) who share the same physical core, in proc= essors that support Intel Hyper-Threading Technology. Software can use this= event as the numerator for the Backend Bound metric (or top-level category= ) of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were not consumed by the back-end pipeline due to lack of ba= ck-end resources, as a result of memory subsystem delays, execution units l= imitations, or other conditions. The count is distributed among unhalted lo= gical processors (hyper-threads) who share the same physical core, in proce= ssors that support Intel Hyper-Threading Technology. Software can use this = event as the numerator for the Backend Bound metric (or top-level category)= of the Top-down Microarchitecture Analysis method.", "SampleAfterValue": "10000003", "UMask": "0x2" }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation= s.", + "Counter": "0", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BAD_SPEC_SLOTS", + "PublicDescription": "Number of slots of TMA method that were wast= ed due to incorrect speculation. It covers all types of control-flow or dat= a-related mis-speculations.", + "SampleAfterValue": "10000003", + "UMask": "0x4" + }, + { + "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "Counter": "0", + "EventCode": "0xa4", + "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", + "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by (any type of) branch mispredictions. This event es= timates number of speculative operations that were issued but not retired a= s well as the out-of-order engine recovery past a branch misprediction.", + "SampleAfterValue": "10000003", + "UMask": "0x8" + }, + { + "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa4", + "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", + "SampleAfterValue": "10000003", + "UMask": "0x10" + }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -85,18 +841,267 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", "SampleAfterValue": "10000003", "UMask": "0x1" }, + { + "BriefDescription": "Number of non dec-by-all uops decoded by deco= der", + "Counter": "0,1,2,3", + "EventCode": "0x76", + "EventName": "UOPS_DECODED.DEC0_UOPS", + "PublicDescription": "This event counts the number of not dec-by-a= ll uops decoded by decoder 0.", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_0", + "PublicDescription": "Number of uops dispatch to execution port 0= .", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_1", + "PublicDescription": "Number of uops dispatch to execution port 1= .", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Uops executed on ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_2_3_10", + "PublicDescription": "Number of uops dispatch to execution ports 2= , 3 and 10", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Uops executed on ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_4_9", + "PublicDescription": "Number of uops dispatch to execution ports 4= and 9", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops executed on ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_5_11", + "PublicDescription": "Number of uops dispatch to execution ports 5= and 11", + "SampleAfterValue": "2000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_6", + "PublicDescription": "Number of uops dispatch to execution port 6= .", + "SampleAfterValue": "2000003", + "UMask": "0x40" + }, + { + "BriefDescription": "Uops executed on ports 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "UOPS_DISPATCHED.PORT_7_8", + "PublicDescription": "Number of uops dispatch to execution ports = 7 and 8.", + "SampleAfterValue": "2000003", + "UMask": "0x80" + }, + { + "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE", + "PublicDescription": "Counts the number of uops executed from any = thread.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", + "PublicDescription": "Counts cycles when at least 1 micro-op is ex= ecuted from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", + "PublicDescription": "Counts cycles when at least 2 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", + "PublicDescription": "Counts cycles when at least 3 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", + "PublicDescription": "Counts cycles when at least 4 micro-ops are = executed from any thread on physical core.", + "SampleAfterValue": "2000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_1", + "PublicDescription": "Cycles where at least 1 uop was executed per= -thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "2", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_2", + "PublicDescription": "Cycles where at least 2 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "3", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_3", + "PublicDescription": "Cycles where at least 3 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "4", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.CYCLES_GE_4", + "PublicDescription": "Cycles where at least 4 uops were executed p= er-thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.STALLS", + "Invert": "1", + "PublicDescription": "Counts cycles during which no uops were disp= atched from the Reservation Station (RS) per thread.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.THREAD", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb1", + "EventName": "UOPS_EXECUTED.X87", + "PublicDescription": "Counts the number of x87 uops executed.", + "SampleAfterValue": "2000003", + "UMask": "0x10" + }, + { + "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.ANY", + "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Cycles with retired uop(s).", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.CYCLES", + "PublicDescription": "Counts cycles where at least one uop has ret= ired.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Retired uops except the last uop of each inst= ruction.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.HEAVY", + "PublicDescription": "Counts the number of retired micro-operation= s (uops) except the last uop of each instruction. An instruction that is de= coded into less than two uops does not contribute to the count.", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, + { + "BriefDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.MS", + "MSRIndex": "0x3F7", + "MSRValue": "0x8", + "SampleAfterValue": "2000003", + "UMask": "0x4" + }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that are utilized by operations that eventually get retired (commi= tted) by the processor pipeline. Usually, this event positively correlates = with higher performance for example, as measured by the instructions-per-c= ycle metric.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", - "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that are utilized by operations that eventually get retired (comm= itted) by the processor pipeline. Usually, this event positively correlates= with higher performance for example, as measured by the instructions-per-= cycle metric.\nSoftware can use this event as the numerator for the Retirin= g metric (or top-level category) of the Top-down Microarchitecture Analysis= method.", + "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that are utilized by operations that eventually get retired (comm= itted) by the processor pipeline. Usually, this event positively correlates= with higher performance for example, as measured by the instructions-per-= cycle metric. Software can use this event as the numerator for the Retiring= metric (or top-level category) of the Top-down Microarchitecture Analysis = method.", "SampleAfterValue": "2000003", "UMask": "0x2" + }, + { + "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xc2", + "EventName": "UOPS_RETIRED.STALLS", + "Invert": "1", + "PublicDescription": "This event counts cycles without actually re= tired uops.", + "SampleAfterValue": "1000003", + "UMask": "0x2" } ] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json= b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json new file mode 100644 index 000000000000..e0a45d4ea848 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cache.json @@ -0,0 +1,3674 @@ +[ + { + "BriefDescription": "Clockticks for CMS units attached to CHA", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_CHACMS_CLOCKTICKS", + "PerPkg": "1", + "PortMask": "0x000", + "PublicDescription": "UNC_CHACMS_CLOCKTICKS", + "Unit": "CHACMS" + }, + { + "BriefDescription": "Number of CHA clock cycles while the event is= enabled", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_CHA_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks of the uncore caching and home ag= ent (CHA)", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts transactions that looked into the mult= i-socket cacheline Directory state, and therefore did not send a snoop beca= use the Directory indicated it was not needed.", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts transactions that looked into the mul= ti-socket cacheline Directory state, and sent one or more snoops, because t= he Directory indicated it was needed.", + "Counter": "0,1,2,3", + "EventCode": "0x53", + "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts only multi-socket cacheline Directory = state updates memory writes issued from the HA pipe. This does not include = memory write requests which are for I (Invalid) or E (Exclusive) cachelines= .", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.HA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts only multi-socket cacheline Directory = state updates due to memory writes issued from the TOR pipe which are the r= esult of remote transaction hitting the SF/LLC and returning data Core2Core= . This does not include memory write requests which are for I (Invalid) or = E (Exclusive) cachelines.", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR o= r IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in IRQ (= immediate cause for triggering).", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR (= immediate cause for triggering).", + "Counter": "0,1,2,3", + "EventCode": "0x59", + "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts when a normal (Non-Isochronous) full l= ine write is issued from the CHA to the any of the memory controller channe= ls.", + "Counter": "0,1,2,3", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line : Counts the total number of full line writes issued from the HA in= to the memory controller.", + "Counter": "0,1,2,3", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH : Counts the total number of full line writes issued from the HA = into the memory controller.", + "Counter": "0,1,2,3", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial : Counts the total number of full line writes issued from the HA into= the memory controller.", + "Counter": "0,1,2,3", + "EventCode": "0x5b", + "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: All Requests to Remotely Homed= Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All transactions from Remote= Agents", + "UMask": "0x17e0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: CRd Requests", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests", + "UMask": "0x1bd0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1bc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Reads", + "UMask": "0x1fc1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Demand Data Reads, Core and = LLC prefetches", + "UMask": "0x841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops which miss the Cache", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Data Read Misses", + "UMask": "0x1fc101", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: All Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed locally", + "UMask": "0xbdfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Code Read Requests and Code Re= ad Prefetches to Locally Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests", + "UMask": "0x19d0ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes to Locally Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x19c1ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Code Read Requests to Locally = Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests", + "UMask": "0x1850ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1841ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: RFO Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests", + "UMask": "0x1848ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: LLC Prefetch Requests to Local= ly Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x189dff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: All Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x199dff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Code Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests", + "UMask": "0x1910ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Read Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1981ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: RFO Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests", + "UMask": "0x1908ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests", + "UMask": "0x19c8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: All Requests to Remotely Homed= Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", + "UMask": "0x15dfff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Code Read/Prefetch Requests fr= om a Remote Socket", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : CRd Requests", + "UMask": "0x1a10ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Data Read/Prefetch Requests fr= om a Remote Socket", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", + "UMask": "0x1a01ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: RFO Requests/Prefetches from a= Remote Socket", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : RFO Requests", + "UMask": "0x1a08ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Snoop Requests from a Remote S= ocket", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Counts the number of times the LLC was acces= sed", + "UMask": "0x1c19ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: All RFO and RFO Prefetches", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : All RFOs - Demand and Prefet= ches", + "UMask": "0x1bc8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Locally HOMed RFOs - Demand = and Prefetches", + "UMask": "0x9c8ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Writes to Locally Homed Memory= (includes writebacks from L1/L2)", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Writes", + "UMask": "0x842ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Cache Lookups: Writes to Remotely Homed Memor= y (includes writebacks from L1/L2)", + "Counter": "0,1,2,3", + "EventCode": "0x34", + "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Cache Lookups : Remote Writes", + "UMask": "0x17c2ff", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : All Lines Victimized", + "UMask": "0xf", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : IA traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : IO traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - All Lines", + "UMask": "0x200f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in E State", + "UMask": "0x2002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in F State", + "UMask": "0x2008", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in M State", + "UMask": "0x2001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Local - Lines in S State", + "UMask": "0x2004", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - All Lines", + "UMask": "0x800f", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in E State= ", + "UMask": "0x8002", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in M State= ", + "UMask": "0x8001", + "Unit": "CHA" + }, + { + "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Remote - Lines in S State= ", + "UMask": "0x8004", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in E state", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in M state", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", + "EventCode": "0x37", + "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Lines Victimized : Lines in S State", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts when a RFO (the Read for Ownership iss= ued before a write) request hit a cacheline in the S (Shared) state.", + "Counter": "0,1,2,3", + "EventCode": "0x39", + "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "PerPkg": "1", + "PublicDescription": "Cbo Misc : RFO HitS", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local InvItoE : Count o= f OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be br= oadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB= snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadca= st. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Off : Count of OSB snoo= p broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. D= oes not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : Remote Rd : Count of OS= B snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadc= ast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.REMOTE_READ", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoo= ps to be broadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", + "EventCode": "0x55", + "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_SHARED", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.ALLOC_SHARED", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY", + "Experimental": "1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_SHARED", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.HIT_SHARED", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY", + "Experimental": "1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.MISS", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.MISS", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE", + "Experimental": "1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_SHARED", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.UPDATE_SHARED", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE", + "Experimental": "1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_SHARED", + "Counter": "0,1,2,3", + "EventCode": "0x69", + "EventName": "UNC_CHA_REMOTE_SF.VICTIM_SHARED", + "Experimental": "1", + "PerPkg": "1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE", + "PerPkg": "1", + "PublicDescription": "HA Read and Write Requests : InvalItoE", + "UMask": "0x30", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the total number of requests coming fr= om a remote socket for exclusive ownership of a cache line without receivin= g data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts read requests made into this CHA. Read= s include all read opcodes (including RFO: the Read for Ownership issued be= fore a write) .", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS", + "PerPkg": "1", + "PublicDescription": "HA Read and Write Requests : Reads", + "UMask": "0x3", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts read requests coming from a unit on th= is socket made into this CHA. Reads include all read opcodes (including RFO= : the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts read requests coming from a remote soc= ket made into the CHA. Reads include all read opcodes (including RFO: the R= ead for Ownership issued before a write).", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts write requests made into the CHA, incl= uding streaming, evictions, HitM (Reads from another core to a Modified cac= heline), etc.", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES", + "PerPkg": "1", + "PublicDescription": "HA Read and Write Requests : Writes", + "UMask": "0xc", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts write requests coming from a unit on = this socket made into this CHA, including streaming, evictions, HitM (Reads= from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "CHA" + }, + { + "BriefDescription": "Counts the total number of read requests made= into the Home Agent. Reads include all read opcodes (including RFO). Writ= es include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", + "EventCode": "0x50", + "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR Inserts", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "CLFlush transactions from a CXL device which = hit in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_CLFLUSH", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8c7fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "FsRdCur transactions from a CXL device which = hit in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCUR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8effd20", + "Unit": "CHA" + }, + { + "BriefDescription": "FsRdCurPtl transactions from a CXL device whi= ch hit in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCURPTL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c9effd20", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM transactions from a CXL device which hit= in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc47fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMWr transactions from a CXL device which h= it in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOMWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc4ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "MemPushWr transactions from a CXL device whic= h hit in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_MEMPUSHWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc6ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "WCiL transactions from a CXL device which hit= in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c86ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "WcilF transactions from a CXL device which hi= t in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCILF", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c867fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "WiL transactions from a CXL device which hit = in the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c87ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "CLFlush transactions from a CXL device which = miss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_CLFLUSH", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8c7fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "FsRdCur transactions from a CXL device which = miss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCUR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8effe20", + "Unit": "CHA" + }, + { + "BriefDescription": "FsRdCurPtl transactions from a CXL device whi= ch miss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCURPTL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c9effe20", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM transactions from a CXL device which mis= s the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc47fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMWr transactions from a CXL device which m= iss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOMWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc4ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "MemPushWr transactions from a CXL device whic= h miss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_MEMPUSHWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc6ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "WCiL transactions from a CXL device which mis= s the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c86ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "WcilF transactions from a CXL device which mi= ss the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCILF", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c867fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "WiL transactions from a CXL device which miss= the L3.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c87ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "All locally initiated requests from IA Cores", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "CLFlush events that are initiated from the Co= re", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRDs issued by iA Cores", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd PTEs issued by iA Cores due to a page wal= k", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due = to a page walk", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "All locally initiated requests from IA Cores = which hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Hit the LLC", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read from local IA that hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that H= it the LLC", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read prefetch from local IA that hit the= cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat hit the LLC", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c0018101", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read from local IA that hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that H= it the LLC", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd PTEs issued by iA Cores due to page walks= that hit the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due = to a page walk that hit the LLC", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read prefetch from local IA that hit the= cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= hat Hit the LLC", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM requests from local IA cores that hit th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that = Hit LLC", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch code read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= that hit the LLC", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch data read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores= that hit the LLC", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch read for ownership = from local IA that hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that hit the LLC", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership from local IA that hit the= cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that H= it the LLC", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership prefetch from local IA tha= t hit the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Hit the LLC", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM events that are initiated from the Core", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNear requests from local IA cores", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Co= res", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch code read from loca= l IA.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= ", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch data read from loca= l IA.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores= ", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "All locally initiated requests from IA Cores = which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Missed the LLC", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRds issued by iA Cores that M= issed the LLC", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "CRDs from local IA cores to locally homed mem= ory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Mi= ssed the LLC - HOMed locally", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "CRD Prefetches from local IA cores to locally= homed memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC - HOMed locally", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "CRD Prefetches from local IA cores to remotel= y homed memory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC - HOMed remotely", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "CRDs from local IA cores to remotely homed me= mory", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Mi= ssed the LLC - HOMed remotely", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c0018201", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that M= issed the LLC", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd PTEs issued by iA Cores due to a page wal= k that missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRdPte issued by iA Cores due = to a page walk that missed the LLC", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 memory expander c= ard.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "PerPkg": "1", + "PublicDescription": "DRds issued from an IA core which miss the L= 3 and target memory in a CXL type 2 memory expander card.", + "UMask": "0x10c8178201", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds issued by iA Cores targeting DDR Mem tha= t Missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing DDR Mem that Missed the LLC", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that M= issed the LLC - HOMed locally", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds from local IA cores to locally homed DDR= addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing DDR Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds from local IA cores to locally homed PMM= addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing PMM Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds issued by iA Cores targeting PMM Mem tha= t Missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing PMM Mem that Missed the LLC", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= hat Missed the LLC", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "L2 data prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8978201", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to DDR add= resses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores whi= ch miss the LLC and snoop filter with the opcode DRD_PREF, and target local= memory", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to locally= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to locally= homed PMM addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to PMM add= resses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "Inserts into the TOR from local IA cores whi= ch miss the LLC and snoop filter with the opcode DRD_PREF, and target remot= e memory", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to remotel= y homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "DRd Prefetches from local IA cores to remotel= y homed PMM addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "Data read from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores that M= issed the LLC - HOMed remotely", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds from local IA cores to remotely homed DD= R addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing DDR Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "DRds from local IA cores to remotely homed PM= M addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : DRds issued by iA Cores target= ing PMM Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM requests from local IA cores that miss t= he cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that = Missed LLC", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch code read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= that missed the LLC", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch data read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores= that missed the LLC", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "LLC data prefetches issued from an IA core wh= ich miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10ccd78201", + "Unit": "CHA" + }, + { + "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores = that missed the LLC", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "L2 RFO prefetches issued from an IA core whic= h miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8878201", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to locally= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC - HOMed locally", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to locally= homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from local IA cores to locally = homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC - HOMed locally", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from local IA cores to locally = homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to remotel= y homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC - HOMed remotely", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to remotel= y homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from local IA cores to remotely= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC - HOMed remotely", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from local IA cores to remotely= homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remotely", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "RFOs issued from an IA core which miss the L3= and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8078201", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC - HOMed locally", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Missed the LLC", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "LLC RFO prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10ccc78201", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Missed the LLC - HOMed locally", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores t= hat Missed the LLC - HOMed remotely", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores that M= issed the LLC - HOMed remotely", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "UCRDF requests from local IA cores that miss = the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that= Missed LLC", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from a local IA core that miss = the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that = Missed the LLC", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA core that miss t= he cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that = Missed the LLC", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to DDR hom= ed addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA cores to PMM hom= ed addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from local IA cores to DDR home= d addresses which miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from a local IA core to PMM hom= ed addresses that miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "WIL requests from local IA cores that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that M= issed LLC", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by iA Cores", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "SpecItoM events that are initiated from the C= ore", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC", + "UMask": "0xcc3fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified = Write Backs)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC", + "UMask": "0xcc37ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write= Backs)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC", + "UMask": "0xcc2fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbMtoI requests from local IA cores", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WbMtoIs issued by iA Cores", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC", + "UMask": "0xcc67ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCIL requests from a local IA core", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "WCILF requests from local IA core", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR inserts from local IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "CLFlush requests from IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices= ", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR inserts from local IO devices which h= it the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat hit the LLC", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMs from local IO devices which hit the cac= he", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t Hit the LLC", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that hit the LLC", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCURs issued by IO devices which hit the = LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that hit the LLC", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "RFOs from local IO devices which hit the cach= e", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= hit the LLC", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR ItoM inserts from local IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on the local socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that address memory on the local sock= et", + "UMask": "0xcd42ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that address memory on a remote socke= t", + "UMask": "0xcd437f04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on the local socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoM, indicating a write reque= st, from IO Devices that address memory on the local socket", + "UMask": "0xcc42ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on a remote socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoM, indicating a write reque= st, from IO Devices that address memory on a remote socket", + "UMask": "0xcc437f04", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR inserts from local IO devices which m= iss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR ItoM inserts from local IO devices wh= ich miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCURs issued by IO devices which miss the= LLC", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that missed the LLC", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "All TOR RFO inserts from local IO devices whi= ch miss the cache", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= missed the LLC", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCURs issued by IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= ", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on the local socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that addresses memory on the local socket", + "UMask": "0xc8f2ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that addresses memory on a remote socket", + "UMask": "0xc8f37f04", + "Unit": "CHA" + }, + { + "BriefDescription": "RFOs from local IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : RFOs issued by IO Devices", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "WBMtoI requests from IO devices", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", + "PerPkg": "1", + "PublicDescription": "TOR allocation occurred as a result of SF/LL= C evictions (came from the ISMQ)", + "UMask": "0xc001ff02", + "Unit": "CHA" + }, + { + "BriefDescription": "All locally initiated requests", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA and IO", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "All from Local iA", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local iA", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "All from Local IO", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All from Local IO", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "All remote requests (e.g. snoops, writebacks)= that came from remote sockets", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All Remote Requests", + "UMask": "0xc001ffc8", + "Unit": "CHA" + }, + { + "BriefDescription": "All snoops to this LLC that came from remote = sockets", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : All Snoops from Remote", + "UMask": "0xc001ff08", + "Unit": "CHA" + }, + { + "BriefDescription": "Occupancy for all TOR entries", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All", + "UMask": "0xc001ffff", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CLFlush transactions from a= CXL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_CLFLUSH", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8c7fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for FsRdCur transactions from a= CXL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCUR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8effd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions fro= m a CXL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCURPTL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c9effd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM transactions from a CX= L device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc47fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMWr transactions from a = CXL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOMWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc4ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for MemPushWr transactions from= a CXL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_MEMPUSHWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc6ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCiL transactions from a CX= L device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c86ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WcilF transactions from a C= XL device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCILF", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c867fd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WiL transactions from a CXL= device which hit in the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c87ffd20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CLFlush transactions from a= CXL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_CLFLUSH", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8c7fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for FsRdCur transactions from a= CXL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCUR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c8effe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions fro= m a CXL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCURPTL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c9effe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM transactions from a CX= L device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc47fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMWr transactions from a = CXL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOMWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc4ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for MemPushWr transactions from= a CXL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_MEMPUSHWR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78cc6ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCiL transactions from a CX= L device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c86ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WcilF transactions from a C= XL device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCILF", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c867fe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WiL transactions from a CXL= device which miss the L3.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WIL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x78c87ffe20", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores", + "UMask": "0xc001ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CLFlush events that are ini= tiated from the Core", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores= ", + "UMask": "0xc8c7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRDs issued by iA Cores", + "UMask": "0xc80fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", + "UMask": "0xc88fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores", + "UMask": "0xc817ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores= due to a page walk", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk", + "UMask": "0xc837ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= ", + "UMask": "0xc897ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Hit the LLC", + "UMask": "0xc001fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read from local IA tha= t hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Hit the LLC", + "UMask": "0xc80ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that hit the LLC", + "UMask": "0xc88ffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c0018101", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read from local IA tha= t hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that= Hit the LLC", + "UMask": "0xc817fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores= due to page walks that hit the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that hit the LLC", + "UMask": "0xc837fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read prefetch from loc= al IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= that Hit the LLC", + "UMask": "0xc897fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Hit LLC", + "UMask": "0xcc47fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es that hit the LLC", + "UMask": "0xcccffd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es that hit the LLC", + "UMask": "0xccd7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s that hit the LLC", + "UMask": "0xccc7fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Hit the LLC", + "UMask": "0xc807fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Hit the LLC", + "UMask": "0xc887fd01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM events that are initia= ted from the Core", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "UMask": "0xcc47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from= local IA cores", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA = Cores", + "UMask": "0xcd47ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es", + "UMask": "0xcccfff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es", + "UMask": "0xccd7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s", + "UMask": "0xccc7ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Missed the LLC", + "UMask": "0xc001fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Missed the LLC", + "UMask": "0xc80ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to= locally homed memory", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed locally", + "UMask": "0xc80efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC", + "UMask": "0xc88ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CRD Prefetches from local I= A cores to locally homed memory", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed locally", + "UMask": "0xc88efe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CRD Prefetches from local I= A cores to remotely homed memory", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely", + "UMask": "0xc88f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CRDs from local IA cores to= remotely homed memory", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed remotely", + "UMask": "0xc80f7e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c0018201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that= Missed the LLC", + "UMask": "0xc817fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd PTEs issued by iA Cores= due to a page walk that missed the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that missed the LLC", + "UMask": "0xc837fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= memory expander card.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8178201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting DDR Mem that Missed the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting DDR Mem that Missed the LLC", + "UMask": "0xc8178601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that= Missed the LLC - HOMed locally", + "UMask": "0xc816fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds from local IA cores to= locally homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting DDR Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8168601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds from local IA cores to= locally homed PMM addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting PMM Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8168a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting PMM Mem that Missed the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting PMM Mem that Missed the LLC", + "UMask": "0xc8178a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= that Missed the LLC", + "UMask": "0xc897fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for L2 data prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8978201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC", + "UMask": "0xc8978601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", + "UMask": "0xc896fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to locally homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8968601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to locally homed PMM addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed locally", + "UMask": "0xc8968a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to PMM addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC", + "UMask": "0xc8978a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read prefetch from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", + "UMask": "0xc8977e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to remotely homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8970601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRd Prefetches from local I= A cores to remotely homed PMM addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8970a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Data read from local IA tha= t miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that= Missed the LLC - HOMed remotely", + "UMask": "0xc8177e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds from local IA cores to= remotely homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting DDR Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8170601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for DRds from local IA cores to= remotely homed PMM addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting PMM Mem that Missed the LLC - HOMed remotely", + "UMask": "0xc8170a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Missed LLC", + "UMask": "0xcc47fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es that missed the LLC", + "UMask": "0xcccffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es that missed the LLC", + "UMask": "0xccd7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for LLC data prefetches issued = from an IA core which miss the L3 and target memory in a CXL type 2 acceler= ator.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10ccd78201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s that missed the LLC", + "UMask": "0xccc7fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued fr= om an IA core which miss the L3 and target memory in a CXL type 2 accelerat= or.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8878201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to locally homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed locally", + "UMask": "0xc8668601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to locally homed PMM addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed locally", + "UMask": "0xc8668a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to locally homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally", + "UMask": "0xc86e8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to locally homed PMM addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally", + "UMask": "0xc86e8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to remotely homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed remotely", + "UMask": "0xc8670601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to remotely homed PMM addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed remotely", + "UMask": "0xc8670a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to remotely homed DDR addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely", + "UMask": "0xc86f0601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to remotely homed PMM addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely", + "UMask": "0xc86f0a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC", + "UMask": "0xc807fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for RFOs issued from an IA core= which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10c8078201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC - HOMed locally", + "UMask": "0xc806fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC", + "UMask": "0xc887fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "PerPkg": "1", + "UMask": "0x10ccc78201", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC - HOMed locally", + "UMask": "0xc886fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely", + "UMask": "0xc8877e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC - HOMed remotely", + "UMask": "0xc8077e01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for UCRDF requests from local I= A cores that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC", + "UMask": "0xc877de01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC", + "UMask": "0xc86ffe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC", + "UMask": "0xc867fe01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to DDR homed addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC", + "UMask": "0xc8678601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to PMM homed addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC", + "UMask": "0xc8678a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to DDR homed addresses which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC", + "UMask": "0xc86f8601", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core to PMM homed addresses that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC", + "UMask": "0xc86f8a01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WIL requests from local IA = cores that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC", + "UMask": "0xc87fde01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores", + "UMask": "0xc807ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= ", + "UMask": "0xc887ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for SpecItoM events that are in= itiated from the Core", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores= ", + "UMask": "0xcc57ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WbMtoI requests from local = IA cores", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "UMask": "0xcc27ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "UMask": "0xc86fff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "UMask": "0xc867ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= ", + "UMask": "0xc001ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for CLFlush requests from IO de= vices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es", + "UMask": "0xc8c3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that hit the LLC", + "UMask": "0xc001fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMs from local IO devices= which hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat Hit the LLC", + "UMask": "0xcc43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that hit the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that hit the LLC", + "UMask": "0xcd43fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which hit the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that hit the LLC", + "UMask": "0xc8f3fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for RFOs from local IO devices = which hit the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC", + "UMask": "0xc803fd04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "UMask": "0xcc43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices", + "UMask": "0xcd43ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All requests from IO Devices= that missed the LLC", + "UMask": "0xc001fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC", + "UMask": "0xcc43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that missed the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC", + "UMask": "0xcd43fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions = from an IO device on the local socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC", + "UMask": "0xcd42fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions = from an IO device on a remote socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC", + "UMask": "0xcd437e04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM transactions from an I= O device on the local socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC", + "UMask": "0xcc42fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for ItoM transactions from an I= O device on a remote socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC", + "UMask": "0xcc437e04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which miss the LLC", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC", + "UMask": "0xc8f3fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from = an IO device on the local socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC", + "UMask": "0xc8f2fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from = an IO device on a remote socket that miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC", + "UMask": "0xc8f37e04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All TOR RFO inserts from lo= cal IO devices which miss the cache", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC", + "UMask": "0xc803fe04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es", + "UMask": "0xc8f3ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for RFOs from local IO devices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices", + "UMask": "0xc803ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for WBMtoI requests from IO dev= ices", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= ", + "UMask": "0xcc23ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All locally initiated reque= sts", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA and IO", + "UMask": "0xc000ff05", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All from Local iA", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local iA", + "UMask": "0xc000ff01", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All from Local IO", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All from Local IO", + "UMask": "0xc000ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All remote requests (e.g. s= noops, writebacks) that came from remote sockets", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All Remote Requests", + "UMask": "0xc001ffc8", + "Unit": "CHA" + }, + { + "BriefDescription": "TOR Occupancy for All snoops to this LLC that= came from remote sockets", + "Counter": "0", + "EventCode": "0x36", + "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "TOR Occupancy : All Snoops from Remote", + "UMask": "0xc001ff08", + "Unit": "CHA" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cxl.json b= /tools/perf/pmu-events/arch/x86/graniterapids/uncore-cxl.json new file mode 100644 index 000000000000..383a5ba5a697 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-cxl.json @@ -0,0 +1,31 @@ +[ + { + "BriefDescription": "B2CXL Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_B2CXL_CLOCKTICKS", + "PerPkg": "1", + "PortMask": "0x000", + "Unit": "B2CXL" + }, + { + "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "4,5,6,7", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLDP" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconne= ct.json b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.= json new file mode 100644 index 000000000000..856ee985ecd4 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json @@ -0,0 +1,1849 @@ +[ + { + "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_B2CMI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of time D2C was not honoure= d by egress due to directory state constraints", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_B2CMI_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of times B2CMI egress did D= 2C (direct to core)", + "Counter": "0,1,2,3", + "EventCode": "0x16", + "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of times D2C wasn't honoure= d even though the incoming request had d2c set for non cisgress txn", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of d2k wasn't done due to c= redit constraints", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Direct to UPI Transactions - Ignored due to l= ack of credits : All : Counts the number of d2k wasn't done due to credit c= onstraints", + "Counter": "0,1,2,3", + "EventCode": "0x1B", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of time D2K was not honoure= d by egress due to directory state constraints", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U : Counts the number of time D2K was not honoured by egress due = to directory state constraints", + "Counter": "0,1,2,3", + "EventCode": "0x1A", + "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of times egress did D2K (Di= rect to KTI)", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of times D2K wasn't honoure= d even though the incoming request had d2k set for non cisgress txn", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit Clean", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit Dirty (modified)", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S", + "PerPkg": "1", + "PublicDescription": "Counts the number of 1lm or 2lm hit read da= ta returns to egress with directory S to non persistent memory", + "UMask": "0x4", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss Clean", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x38", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss Dirty (modified)", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x7", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any A2I Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I", + "PerPkg": "1", + "UMask": "0x320", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any A2S Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S", + "PerPkg": "1", + "UMask": "0x340", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts cisgress directory updates", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY", + "PerPkg": "1", + "UMask": "0x301", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts any 1lm or 2lm hit data return that wo= uld result in directory update to non persistent memory (DRAM)", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_ANY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in near memory to the A stat= e", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x114", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in near memory to the I stat= e", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x128", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in near memory to the S stat= e", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x142", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any I2A Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A", + "PerPkg": "1", + "UMask": "0x304", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any I2S Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S", + "PerPkg": "1", + "UMask": "0x302", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in far memory to the A state= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x214", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in far memory to the I state= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x228", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update in far memory to the S state= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x242", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any S2A Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x310", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Any S2I Transition", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x308", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update to the A state", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2A", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x314", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update to the I state", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2I", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x328", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Directory update to the S state", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2S", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x342", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts any read", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_B2CMI_IMC_READS.ALL", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_B2CMI_IMC_READS.NORMAL", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Count reads to NM region", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_CACHE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x110", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts reads to 1lm non persistent memory reg= ions", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "B2CMI" + }, + { + "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.ALL", + "PerPkg": "1", + "UMask": "0x110", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.FULL", + "PerPkg": "1", + "UMask": "0x101", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.NI", + "Experimental": "1", + "PerPkg": "1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.NI_MISS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", + "PerPkg": "1", + "UMask": "0x102", + "Unit": "B2CMI" + }, + { + "BriefDescription": "DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_CACHE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x140", + "Unit": "B2CMI" + }, + { + "BriefDescription": "DDR - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x25", + "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x120", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "Counter": "0,1,2,3", + "EventCode": "0x56", + "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", + "PerPkg": "1", + "PublicDescription": "Prefetch CAM Inserts : XPT - All Channels", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x54", + "EventName": "UNC_B2CMI_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm reads and WRNI which were a hi= t", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_B2CMI_TAG_HIT.ALL", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm reads which were a hit clean", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_B2CMI_TAG_HIT.RD_CLEAN", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm reads which were a hit dirty", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_B2CMI_TAG_HIT.RD_DIRTY", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm WRNI which were a hit clean", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_B2CMI_TAG_HIT.WR_CLEAN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm WRNI which were a hit dirty", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_B2CMI_TAG_HIT.WR_DIRTY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.CLEAN", + "PerPkg": "1", + "UMask": "0x5", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.DIRTY", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm second way read miss for a Rd", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.RD_2WAY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm reads which were a miss and th= e cache line is unmodified", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.RD_CLEAN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm reads which were a miss and th= e cache line is modified", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.RD_DIRTY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.WR_2WAY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm WRNI which were a miss and the= cache line is unmodified", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.WR_CLEAN", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Counts the 2lm WRNI which were a miss and the= cache line is modified", + "Counter": "0,1,2,3", + "EventCode": "0x4B", + "EventName": "UNC_B2CMI_TAG_MISS.WR_DIRTY", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", + "PerPkg": "1", + "UMask": "0x104", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x33", + "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_B2CMI_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "B2CMI" + }, + { + "BriefDescription": "UNC_B2HOT_CLOCKTICKS", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_B2HOT_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Clockticks for the B2HOT unit", + "UMask": "0x1", + "Unit": "B2HOT" + }, + { + "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_B2UPI_CLOCKTICKS", + "PerPkg": "1", + "Unit": "B2UPI" + }, + { + "BriefDescription": "Total Write Cache Occupancy : Mem", + "Counter": "0,1,2,3", + "EventCode": "0x0F", + "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "IRP" + }, + { + "BriefDescription": "IRP Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_I_CLOCKTICKS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue", + "Counter": "0,1,2,3", + "EventCode": "0x18", + "EventName": "UNC_I_FAF_INSERTS", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "FAF occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x19", + "EventName": "UNC_I_FAF_OCCUPANCY", + "Experimental": "1", + "PerPkg": "1", + "Unit": "IRP" + }, + { + "BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pu= lled away ownership before a write was committed", + "Counter": "0,1,2,3", + "EventCode": "0x1F", + "EventName": "UNC_I_MISC1.LOST_FWD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IRP" + }, + { + "BriefDescription": "Inbound write (fast path) requests to coheren= t memory, received by the IRP resulting in write ownership requests issued = by IRP to the mesh.", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "UNC_I_TRANSACTIONS.WR_PREF", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "IRP" + }, + { + "BriefDescription": "MDF Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_MDF_CLOCKTICKS", + "PerPkg": "1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of packets bypassing the ingress queue= ", + "Counter": "0,1,2,3", + "EventCode": "0x14", + "EventName": "UNC_MDF_RxR_BYPASS.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (AD_BNC)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (AD)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (AK)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (BL_BNC)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (BL_CRD)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of allocations into the Ingress used = to queue up requests from the mesh (IV)", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "UNC_MDF_RxR_INSERTS.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Occupancy counts for the Ingress buffer", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "UNC_MDF_RxR_OCCUPANCY.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for AD_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for AD_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for AK", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for BL_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for BL_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress bypasses for for IV", + "Counter": "0,1,2,3", + "EventCode": "0x1E", + "EventName": "UNC_MDF_TxR_BYPASS.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for AD_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for AD_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for AK", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for BL_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for BL_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of egress inserts for for IV", + "Counter": "0,1,2,3", + "EventCode": "0x1C", + "EventName": "UNC_MDF_TxR_INSERTS.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for AD_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.AD_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for AD_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.AD_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for AK", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.AK", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for BL_BNC", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.BL_BNC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for BL_CRD", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.BL_CRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "MDF" + }, + { + "BriefDescription": "Egress occupancy for for IV", + "Counter": "0,1,2,3", + "EventCode": "0x1D", + "EventName": "UNC_MDF_TxR_OCCUPANCY.IV", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "MDF" + }, + { + "BriefDescription": "Number of UPI LL clock cycles while the event= is enabled", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_UPI_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "Number of kfclks", + "Unit": "UPI" + }, + { + "BriefDescription": "Cycles in L1 : Number of UPI qfclk cycles spe= nt in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use= edge detect to count the number of instances when the UPI link entered L1.= Link power states are per link and per direction, so for example the Tx d= irection could be in one state while Rx was in another. Because L1 totally = shuts down the link, it takes a good amount of time to exit this mode.", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "UNC_UPI_L1_POWER_CYCLES", + "Experimental": "1", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= ", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= , Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Write= back", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Receive path of a UPI Port : Write= back, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Data : Shows legal= flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "Valid Flits Received : Null FLITs received f= rom any slot", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Data : Shows legal fli= t time (hides impact of L0p and L0c). : Count Data Flits (which consume all= slots), but how much to count is based on Slot0-2 mask, so count can be 0-= 3 depending on which slots are enabled for counting..", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Idle : Shows legal fli= t time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCRD Not Empty : Show= s legal flit time (hides impact of L0p and L0c). : Enables counting of LLCR= D (with non-zero payload). This only applies to slot 2 since LLCRD is only = allowed in slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : LLCTRL : Shows legal f= lit time (hides impact of L0p and L0c). : Equivalent to an idle packet. En= ables counting of slot 0 LLCTRL messages.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : All Non Data : Shows l= egal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", + "PerPkg": "1", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Emp= ty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all = zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual= slot. This can apply to slot 0,1, or 2.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.NULL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Protocol Header : Show= s legal flit time (hides impact of L0p and L0c). : Enables count of protoco= l headers in slot 0,1,2 (depending on slot uMask bits)", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 0 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 1 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Received : Slot 2 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", + "EventCode": "0x30", + "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xe", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10e", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10f", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x108", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Conflict", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1aa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Invalid", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x12a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xc", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10c", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xa", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10a", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x9", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x109", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xd", + "Unit": "UPI" + }, + { + "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback, Match Opcode", + "Counter": "0,1,2,3", + "EventCode": "0x04", + "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10d", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Data : Counts number o= f data flits across this UPI link.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", + "PerPkg": "1", + "UMask": "0xf", + "Unit": "UPI" + }, + { + "BriefDescription": "All Null Flits", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Idle", + "UMask": "0x27", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Data : Shows legal flit ti= me (hides impact of L0p and L0c). : Count Data Flits (which consume all slo= ts), but how much to count is based on Slot0-2 mask, so count can be 0-3 de= pending on which slots are enabled for counting..", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x8", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit ti= me (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "PerPkg": "1", + "UMask": "0x47", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCRD Not Empty : Shows le= gal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (w= ith non-zero payload). This only applies to slot 2 since LLCRD is only allo= wed in slot 2", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : LLCTRL : Shows legal flit = time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enable= s counting of slot 0 LLCTRL messages.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal= flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", + "PerPkg": "1", + "PublicDescription": "Valid Flits Sent : Null FLITs transmitted to= any slot", + "UMask": "0x97", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty := Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zero= s is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slo= t. This can apply to slot 0,1, or 2.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.NULL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Protocol Header : Shows le= gal flit time (hides impact of L0p and L0c). : Enables count of protocol he= aders in slot 0,1,2 (depending on slot uMask bits)", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 0 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x1", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 1 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x2", + "Unit": "UPI" + }, + { + "BriefDescription": "Valid Flits Sent : Slot 2 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x4", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Allocations : Number of alloca= tions into the UPI Tx Flit Buffer. Generally, when data is transmitted acr= oss UPI, it will bypass the TxQ and pass directly to the link. However, th= e TxQ will be used with L0p and when LLR occurs, increasing latency to tran= sfer out to the link. This event can be used in conjunction with the Flit = Buffer Occupancy event in order to calculate the average flit buffer lifeti= me.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", + "PerPkg": "1", + "Unit": "UPI" + }, + { + "BriefDescription": "Tx Flit Buffer Occupancy : Accumulates the nu= mber of flits in the TxQ. Generally, when data is transmitted across UPI, = it will bypass the TxQ and pass directly to the link. However, the TxQ wil= l be used with L0p and when LLR occurs, increasing latency to transfer out = to the link. This can be used with the cycles not empty event to track aver= age occupancy, or the allocations event to track average lifetime in the Tx= Q.", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", + "PerPkg": "1", + "Unit": "UPI" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-io.json b/= tools/perf/pmu-events/arch/x86/graniterapids/uncore-io.json new file mode 100644 index 000000000000..cffb9d94b53d --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-io.json @@ -0,0 +1,1901 @@ +[ + { + "BriefDescription": "IIO Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_IIO_CLOCKTICKS", + "PerPkg": "1", + "PortMask": "0x000", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", + "EventCode": "0xC2", + "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff0ff", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001001", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002002", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008008", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010010", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020020", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040040", + "Unit": "IIO" + }, + { + "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", + "EventCode": "0xD5", + "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080080", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", + "EventCode": "0xC0", + "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "Counts once for every 4 bytes read from this = card to memory. This event does include reads to IO.", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Counts once for every 4 bytes written from th= is card to memory. This event does include writes to IO.", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x02", + "UMask": "0x7002001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x04", + "UMask": "0x7004001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x08", + "UMask": "0x7008001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x10", + "UMask": "0x7010001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x20", + "UMask": "0x7020001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x40", + "UMask": "0x7040001", + "Unit": "IIO" + }, + { + "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x80", + "UMask": "0x7080001", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040008", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080008", + "Unit": "IIO" + }, + { + "BriefDescription": "Counts once for every 4 bytes written from th= is card to a peer device's IO space.", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.ALL_PARTS", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040002", + "Unit": "IIO" + }, + { + "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x83", + "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080002", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB lookups all", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Context cache hits", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Context cache lookups", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB lookups first", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "IOMMU memory access (both low and high priori= ty)", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0xc0", + "Unit": "IIO" + }, + { + "BriefDescription": "IOMMU high priority memory access", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_HIGH", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "IOMMU low priority memory access", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_LOW", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page= ", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache Hit to a 256T pa= ge", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache Hit to a 2M page= ", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_2M_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache Hit to a 512G pa= ge", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache fill", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_FILLS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "Second Level Page Walk Cache lookup", + "Counter": "0,1,2,3", + "EventCode": "0x41", + "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_LOOKUPS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x1", + "Unit": "IIO" + }, + { + "BriefDescription": "Cycles PWT full", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.CYC_PWT_FULL", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x2", + "Unit": "IIO" + }, + { + "BriefDescription": "Interrupt Entry cache hit", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x80", + "Unit": "IIO" + }, + { + "BriefDescription": "Interrupt Entry cache lookup", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x40", + "Unit": "IIO" + }, + { + "BriefDescription": "Context Cache invalidation events", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_CTXT_CACHE", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x8", + "Unit": "IIO" + }, + { + "BriefDescription": "Interrupt Entry Cache invalidation events", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_INT_CACHE", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x20", + "Unit": "IIO" + }, + { + "BriefDescription": "IOTLB invalidation events", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_IOTLB", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x4", + "Unit": "IIO" + }, + { + "BriefDescription": "PASID Cache invalidation events", + "Counter": "0,1,2,3", + "EventCode": "0x43", + "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PASID_CACHE", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "UMask": "0x10", + "Unit": "IIO" + }, + { + "BriefDescription": "Occupancy of outbound request queue : To devi= ce : Counts number of outbound requests/completions IIO is currently proces= sing", + "Counter": "2,3", + "EventCode": "0xc5", + "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Passing data to be written", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f020", + "Unit": "IIO" + }, + { + "BriefDescription": "Issuing final read or write of line", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f008", + "Unit": "IIO" + }, + { + "BriefDescription": "Processing response from IOMMU", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f002", + "Unit": "IIO" + }, + { + "BriefDescription": "Issuing to IOMMU", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f001", + "Unit": "IIO" + }, + { + "BriefDescription": "Request Ownership", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f004", + "Unit": "IIO" + }, + { + "BriefDescription": "Writing line", + "Counter": "0,1,2,3", + "EventCode": "0x88", + "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x700f010", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff080", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff040", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff020", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff010", + "Unit": "IIO" + }, + { + "BriefDescription": "-", + "Counter": "0,1,2,3", + "EventCode": "0x8e", + "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy", + "Counter": "0,1,2,3", + "EventCode": "0x42", + "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", + "PerPkg": "1", + "PortMask": "0x000", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "2,3", + "EventCode": "0xC1", + "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x0FF", + "UMask": "0x70ff002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080004", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080001", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080008", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x001", + "UMask": "0x7001002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x002", + "UMask": "0x7002002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x004", + "UMask": "0x7004002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x008", + "UMask": "0x7008002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x010", + "UMask": "0x7010002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x020", + "UMask": "0x7020002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x040", + "UMask": "0x7040002", + "Unit": "IIO" + }, + { + "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", + "EventCode": "0x84", + "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", + "FCMask": "0x07", + "PerPkg": "1", + "PortMask": "0x080", + "UMask": "0x7080002", + "Unit": "IIO" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.jso= n b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json new file mode 100644 index 000000000000..08e410b9b0a2 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json @@ -0,0 +1,449 @@ +[ + { + "BriefDescription": "DRAM Activate Count : Counts the number of DR= AM Activate commands sent on this channel. Activate commands are issued to= open up a page on the DRAM devices so that it can be read or written to wi= th a CAS. One can calculate the number of Page Misses by subtracting the n= umber of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_M_ACT_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xf7", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Activate Count : Read transaction on Pag= e Empty or Page Miss : Counts the number of DRAM Activate commands sent on = this channel. Activate commands are issued to open up a page on the DRAM d= evices so that it can be read or written to with a CAS. One can calculate = the number of Page Misses by subtracting the number of Page Miss precharges= from the number of Activates.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_M_ACT_COUNT.RD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf1", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Activate Count : Underfill Read transact= ion on Page Empty or Page Miss : Counts the number of DRAM Activate command= s sent on this channel. Activate commands are issued to open up a page on = the DRAM devices so that it can be read or written to with a CAS. One can = calculate the number of Page Misses by subtracting the number of Page Miss = precharges from the number of Activates.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_M_ACT_COUNT.UFILL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf4", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Activate Count : Write transaction on Pa= ge Empty or Page Miss : Counts the number of DRAM Activate commands sent on= this channel. Activate commands are issued to open up a page on the DRAM = devices so that it can be read or written to with a CAS. One can calculate= the number of Page Misses by subtracting the number of Page Miss precharge= s from the number of Activates.", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_M_ACT_COUNT.WR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf2", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0, all CAS operation= s", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD", + "PerPkg": "1", + "UMask": "0xcf", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0 regular writes", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xd0", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 0 auto-precharge wri= tes", + "Counter": "0,1,2,3", + "EventCode": "0x05", + "EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xe0", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1, all CAS operation= s", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD", + "PerPkg": "1", + "UMask": "0xcf", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", + "PerPkg": "1", + "UMask": "0xc1", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", + "PerPkg": "1", + "UMask": "0xc4", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR", + "PerPkg": "1", + "UMask": "0xf0", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1 regular writes", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xd0", + "Unit": "IMC" + }, + { + "BriefDescription": "CAS count for SubChannel 1 auto-precharge wri= tes", + "Counter": "0,1,2,3", + "EventCode": "0x06", + "EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xe0", + "Unit": "IMC" + }, + { + "BriefDescription": "Number of DRAM DCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_M_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "DRAM Clockticks", + "UMask": "0x1", + "Unit": "IMC" + }, + { + "BriefDescription": "Number of DRAM HCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_M_HCLOCKTICKS", + "Experimental": "1", + "PerPkg": "1", + "PublicDescription": "DRAM Clockticks", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.ALL", + "PerPkg": "1", + "UMask": "0xff", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Precharge due to (= ?) : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.PGT", + "PerPkg": "1", + "UMask": "0xf8", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.RD", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf1", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.UFILL", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf4", + "Unit": "IMC" + }, + { + "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", + "EventCode": "0x03", + "EventName": "UNC_M_PRE_COUNT.WR", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xf2", + "Unit": "IMC" + }, + { + "BriefDescription": "Read buffer inserts on subchannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS.SCH0", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IMC" + }, + { + "BriefDescription": "Read buffer inserts on subchannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x17", + "EventName": "UNC_M_RDB_INSERTS.SCH1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IMC" + }, + { + "BriefDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x1a", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x1b", + "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IMC" + }, + { + "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x10", + "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IMC" + }, + { + "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x80", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x81", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x82", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x83", + "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x50", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0xa0", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", + "PerPkg": "1", + "UMask": "0x40", + "Unit": "IMC" + }, + { + "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x22", + "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", + "PerPkg": "1", + "UMask": "0x80", + "Unit": "IMC" + }, + { + "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x84", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x85", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 0", + "Counter": "0,1,2,3", + "EventCode": "0x86", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", + "PerPkg": "1", + "Unit": "IMC" + }, + { + "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 1", + "Counter": "0,1,2,3", + "EventCode": "0x87", + "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", + "PerPkg": "1", + "Unit": "IMC" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-power.json= b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-power.json new file mode 100644 index 000000000000..02e59f64a544 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-power.json @@ -0,0 +1,11 @@ +[ + { + "BriefDescription": "PCU Clockticks", + "Counter": "0,1,2,3", + "EventCode": "0x01", + "EventName": "UNC_P_CLOCKTICKS", + "PerPkg": "1", + "PublicDescription": "PCU Clockticks: The PCU runs off a fixed 1 = GHz clock. This event counts the number of pclk cycles measured while the = counter was enabled. The pclk, like the Memory Controller's dclk, counts a= t a constant rate making it a good measure of actual wall time.", + "Unit": "PCU" + } +] diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json index 8784c97b7534..609a9549cbf3 100644 --- a/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/graniterapids/virtual-memory.json @@ -1,26 +1,185 @@ [ + { + "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.STLB_HIT", + "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a demand load.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0xe" }, + { + "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x12", + "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", + "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.STLB_HIT", + "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a store.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", "SampleAfterValue": "100003", "UMask": "0xe" }, + { + "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", + "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", + "SampleAfterValue": "100003", + "UMask": "0x8" + }, + { + "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x13", + "EventName": "DTLB_STORE_MISSES.WALK_PENDING", + "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, + { + "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.STLB_HIT", + "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", + "SampleAfterValue": "100003", + "UMask": "0x20" + }, + { + "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_ACTIVE", + "PublicDescription": "Counts cycles when at least one PMH (Page Mi= ss Handler) is busy with a page walk for a code (instruction fetch) request= .", + "SampleAfterValue": "100003", + "UMask": "0x10" + }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", "SampleAfterValue": "100003", "UMask": "0xe" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", + "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, + { + "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", + "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, + { + "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x11", + "EventName": "ITLB_MISSES.WALK_PENDING", + "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", + "SampleAfterValue": "100003", + "UMask": "0x10" } ] diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 53c16bb56fdf..2fc3cc4d7f5a 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -11,7 +11,7 @@ GenuineIntel-6-CF,v1.09,emeraldrapids,core GenuineIntel-6-5[CF],v13,goldmont,core GenuineIntel-6-7A,v1.01,goldmontplus,core GenuineIntel-6-B6,v1.03,grandridge,core -GenuineIntel-6-A[DE],v1.01,graniterapids,core +GenuineIntel-6-A[DE],v1.02,graniterapids,core GenuineIntel-6-(3C|45|46),v35,haswell,core GenuineIntel-6-3F,v28,haswellx,core GenuineIntel-6-7[DE],v1.21,icelake,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07EF61B5813 for ; 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Thu, 20 Jun 2024 11:19:46 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:28 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-15-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 14/37] perf vendor events: Add haswell counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/haswell/cache.json | 94 +++++++++++++ .../pmu-events/arch/x86/haswell/counter.json | 22 +++ .../arch/x86/haswell/floating-point.json | 10 ++ .../pmu-events/arch/x86/haswell/frontend.json | 29 ++++ .../arch/x86/haswell/hsw-metrics.json | 66 +++++---- .../pmu-events/arch/x86/haswell/memory.json | 60 ++++++++ .../arch/x86/haswell/metricgroups.json | 11 ++ .../pmu-events/arch/x86/haswell/other.json | 4 + .../pmu-events/arch/x86/haswell/pipeline.json | 130 ++++++++++++++++++ .../arch/x86/haswell/uncore-cache.json | 33 +++++ .../arch/x86/haswell/uncore-interconnect.json | 6 + .../arch/x86/haswell/uncore-other.json | 1 + .../arch/x86/haswell/virtual-memory.json | 49 +++++++ 13 files changed, 485 insertions(+), 30 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/haswell/counter.json diff --git a/tools/perf/pmu-events/arch/x86/haswell/cache.json b/tools/perf= /pmu-events/arch/x86/haswell/cache.json index 0831f14b3cc6..29b408d036c2 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -34,6 +38,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", "SampleAfterValue": "2000003", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "Not rejected writebacks that hit L2 cache.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "L2 cache lines in E state filling L2.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "L2 cache lines in I state filling L2.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "L2 cache lines in S state filling L2.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts all L2 code requests.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts all L2 store RFO requests.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", @@ -190,6 +213,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", @@ -198,6 +222,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", @@ -206,6 +231,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", @@ -215,6 +241,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", @@ -224,6 +251,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "Transactions accessing L2 pipe.", @@ -256,6 +287,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "L2 cache accesses when fetching instructions= .", @@ -264,6 +296,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "Demand data read requests that access L2 cac= he.", @@ -272,6 +305,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "L1D writebacks that access L2 cache.", @@ -280,6 +314,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "L2 fill requests that access L2 cache.", @@ -288,6 +323,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "L2 writebacks that access L2 cache.", @@ -296,6 +332,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.RFO", "PublicDescription": "RFO requests that access L2 cache.", @@ -304,6 +341,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", @@ -312,6 +350,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", @@ -320,6 +359,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", @@ -328,6 +368,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -338,6 +379,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -348,6 +390,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -358,6 +401,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -368,6 +412,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM30", "EventCode": "0xD3", @@ -379,6 +424,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -389,6 +435,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -399,6 +446,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -410,6 +458,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD1", @@ -420,6 +469,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -431,6 +481,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -442,6 +493,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -453,6 +505,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -464,6 +517,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -475,6 +529,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD0", @@ -485,6 +540,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -495,6 +551,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -515,6 +573,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -525,6 +584,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", @@ -533,6 +593,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Demand code read requests sent to uncore.", @@ -541,6 +602,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", @@ -550,6 +612,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", @@ -558,6 +621,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -565,6 +629,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -574,6 +639,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -583,6 +649,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -592,6 +659,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -601,6 +669,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -610,6 +679,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -619,6 +689,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -628,6 +699,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -637,6 +709,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -644,6 +717,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -653,6 +727,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -662,6 +737,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -671,6 +747,7 @@ }, { "BriefDescription": "hit in the L3 and the snoop to one of the sib= ling cores hits the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -680,6 +757,7 @@ }, { "BriefDescription": "hit in the L3 and the snoops to sibling cores= hit in either E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -689,6 +767,7 @@ }, { "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -698,6 +777,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -707,6 +787,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -716,6 +797,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -725,6 +807,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +817,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -743,6 +827,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -752,6 +837,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -761,6 +847,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -770,6 +857,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -779,6 +867,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -788,6 +877,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -797,6 +887,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -806,6 +897,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -815,6 +907,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +917,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/haswell/counter.json b/tools/pe= rf/pmu-events/arch/x86/haswell/counter.json new file mode 100644 index 000000000000..1be6522e2bbc --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswell/counter.json @@ -0,0 +1,22 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "cbox_0", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json b/t= ools/perf/pmu-events/arch/x86/haswell/floating-point.json index 8fcc10f74ad9..a0b917306887 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswell/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "AVX_INSTS.ALL", "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "Number of SIMD FP assists due to input value= s.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "Number of SIMD FP assists due to output valu= es.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "Number of X87 FP assists due to input values= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "Number of X87 FP assists due to output value= s.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "Errata": "HSD56, HSM57", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "Errata": "HSD56, HSM57", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", diff --git a/tools/perf/pmu-events/arch/x86/haswell/frontend.json b/tools/p= erf/pmu-events/arch/x86/haswell/frontend.json index 73d6d681dfa7..a9f81fd17925 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswell/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFDATA_STALL", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFETCH_STALL", "SampleAfterValue": "2000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", @@ -45,6 +51,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0x79", "EventName": "IDQ.EMPTY", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -156,6 +175,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", @@ -189,6 +212,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", @@ -198,6 +222,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD135", "EventCode": "0x9C", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", "EventCode": "0x9C", @@ -218,6 +244,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD135", "EventCode": "0x9C", @@ -227,6 +254,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD135", "EventCode": "0x9C", @@ -236,6 +264,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", "EventCode": "0x9C", diff --git a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json b/tool= s/perf/pmu-events/arch/x86/haswell/hsw-metrics.json index 5631018ed388..b693c0b0cafe 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswell/hsw-metrics.json @@ -90,7 +90,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -100,7 +100,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -121,7 +121,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -151,7 +151,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 = + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_= UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS= _L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LO= AD_UOPS_RETIRED.L3_MISS))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS *= (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_L= OAD_UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_= UOPS_L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + ME= M_LOAD_UOPS_RETIRED.L3_MISS)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -172,7 +172,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + = MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UO= PS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L= 3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD= _UOPS_RETIRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -181,7 +181,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "10 * ARITH.DIVIDER_UOPS / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -218,7 +218,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -227,7 +227,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES= .WALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -236,7 +236,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_= CORE / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -246,7 +246,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.REQUEST_FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -275,7 +275,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -295,7 +295,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -388,12 +388,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -414,7 +414,7 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -426,7 +426,7 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -438,7 +438,13 @@ "MetricName": "tma_info_memory_l2mpki" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -503,13 +509,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -590,7 +596,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -599,7 +605,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -617,7 +623,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY= .STALLS_L2_PENDING) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -637,7 +643,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_= UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRE= D.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RET= IRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_RET= IRED.L3_MISS))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -686,7 +692,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -696,7 +702,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -705,7 +711,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -861,7 +867,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -869,7 +875,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -898,7 +904,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -926,7 +932,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", diff --git a/tools/perf/pmu-events/arch/x86/haswell/memory.json b/tools/per= f/pmu-events/arch/x86/haswell/memory.json index 6ba0ea6e3fa6..edb1b5b9f553 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", + "Counter": "0,1,2,3", "Errata": "HSD65", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", @@ -68,6 +77,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -104,6 +116,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -128,6 +142,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -140,6 +155,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -152,6 +168,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -164,6 +181,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", @@ -172,6 +190,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", @@ -180,6 +199,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -189,6 +209,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -198,6 +219,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -207,6 +229,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -216,6 +239,7 @@ }, { "BriefDescription": "miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -225,6 +249,7 @@ }, { "BriefDescription": "miss the L3 and the data is returned from loc= al dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -234,6 +259,7 @@ }, { "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -243,6 +269,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -252,6 +279,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -261,6 +289,7 @@ }, { "BriefDescription": "Counts all demand code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -270,6 +299,7 @@ }, { "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -279,6 +309,7 @@ }, { "BriefDescription": "Counts demand data reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -288,6 +319,7 @@ }, { "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -297,6 +329,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -306,6 +339,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -315,6 +349,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -324,6 +359,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -333,6 +369,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -342,6 +379,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_CODE_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -351,6 +389,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -360,6 +399,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -369,6 +409,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "2", @@ -377,6 +418,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -385,6 +427,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", @@ -392,6 +435,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", @@ -399,6 +443,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", + "Counter": "0,1,2,3", "Errata": "HSD65", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", @@ -407,6 +452,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed.", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "SampleAfterValue": "2000003", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "SampleAfterValue": "2000003", @@ -429,6 +477,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -436,6 +485,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "SampleAfterValue": "2000003", @@ -443,6 +493,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "SampleAfterValue": "2000003", @@ -450,6 +501,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "SampleAfterValue": "2000003", @@ -457,6 +509,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -464,6 +517,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "SampleAfterValue": "2000003", @@ -471,6 +525,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "SampleAfterValue": "2000003", @@ -478,6 +533,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "SampleAfterValue": "2000003", @@ -485,6 +541,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "SampleAfterValue": "2000003", @@ -492,6 +549,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "SampleAfterValue": "2000003", @@ -499,6 +557,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "SampleAfterValue": "2000003", @@ -506,6 +565,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/haswell/metricgroups.json b/too= ls/perf/pmu-events/arch/x86/haswell/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/haswell/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/haswell/other.json b/tools/perf= /pmu-events/arch/x86/haswell/other.json index 2395ebf112db..7d8769ef6d04 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", diff --git a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json b/tools/p= erf/pmu-events/arch/x86/haswell/pipeline.json index 540f4372623c..c00301fdb3d7 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswell/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -58,6 +66,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -65,6 +74,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", @@ -72,6 +82,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -86,6 +98,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls.= ", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -93,6 +106,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -100,6 +114,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Branch instructions at retirement.", @@ -107,6 +122,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -115,6 +131,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -124,6 +141,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Number of far branches retired.", @@ -132,6 +150,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -140,6 +159,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -148,6 +168,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -157,6 +178,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -166,6 +188,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", @@ -174,6 +197,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -182,6 +206,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -189,6 +214,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -196,6 +222,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -204,6 +231,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -211,6 +239,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -218,6 +247,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -225,6 +255,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -232,6 +263,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", @@ -239,6 +271,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Mispredicted branch instructions at retireme= nt.", @@ -246,6 +279,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -255,6 +289,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -263,6 +298,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -272,6 +308,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -279,6 +316,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", @@ -288,6 +326,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", @@ -296,6 +335,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -303,6 +343,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", "SampleAfterValue": "2000003", @@ -310,6 +351,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", @@ -319,6 +361,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", @@ -327,6 +370,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", "SampleAfterValue": "2000003", @@ -335,12 +379,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", @@ -349,12 +395,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -364,6 +412,7 @@ }, { "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD78, HSM63, HSM80", "EventCode": "0xa3", @@ -374,6 +423,7 @@ }, { "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -383,6 +433,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -392,6 +443,7 @@ }, { "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -401,6 +453,7 @@ }, { "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", "CounterMask": "5", "Errata": "HSM63, HSM80", "EventCode": "0xa3", @@ -411,6 +464,7 @@ }, { "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -420,6 +474,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "PublicDescription": "Stall cycles due to IQ is full.", @@ -428,6 +483,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", @@ -436,6 +492,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "Errata": "HSD140, HSD143", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", @@ -444,6 +501,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "HSD11, HSD140", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -452,6 +510,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "HSD140", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -462,6 +521,7 @@ }, { "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts FP operations retired. For X87 FP o= perations that have no exceptions counting also includes flows that have se= veral X87, or flows that use X87 uops in the exception handling.", @@ -470,6 +530,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -480,6 +541,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -489,6 +551,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -497,6 +560,7 @@ }, { "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", @@ -505,6 +569,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", @@ -513,6 +578,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", @@ -521,6 +587,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", @@ -529,6 +596,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -537,6 +605,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -545,6 +614,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered by the LSD.", @@ -553,6 +623,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -562,6 +633,7 @@ }, { "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "2000003", @@ -569,6 +641,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "SampleAfterValue": "100003", @@ -576,6 +649,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", @@ -584,6 +658,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", @@ -592,6 +667,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", @@ -600,6 +676,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "PublicDescription": "Number of microcode assists invoked by HW up= on uop writeback.", @@ -608,6 +685,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", @@ -617,6 +695,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -624,6 +703,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -631,6 +711,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts cycles during which no ins= tructions were allocated because no Store Buffers (SB) were available.", @@ -639,6 +720,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Count cases of saving new LBR records by har= dware.", @@ -647,6 +729,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", @@ -655,6 +738,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -665,6 +749,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", @@ -672,6 +757,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", @@ -679,6 +765,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", @@ -686,6 +773,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", @@ -693,6 +781,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", @@ -700,6 +789,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", @@ -707,6 +797,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "SampleAfterValue": "2000003", @@ -714,6 +805,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "SampleAfterValue": "2000003", @@ -721,6 +813,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "Errata": "HSD30, HSM31", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", @@ -730,6 +823,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -739,6 +833,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -748,6 +843,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -757,6 +853,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -766,6 +863,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "Errata": "HSD30, HSM31", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -775,6 +873,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -785,6 +884,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -795,6 +895,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -805,6 +906,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -814,6 +916,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -824,6 +927,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0", "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", @@ -833,6 +937,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -840,6 +945,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1", "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", @@ -849,6 +955,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -856,6 +963,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2", "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", @@ -865,6 +973,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -872,6 +981,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3", "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", @@ -881,6 +991,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -888,6 +999,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4", "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", @@ -897,6 +1009,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -904,6 +1017,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5", "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", @@ -913,6 +1027,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -920,6 +1035,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6", "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", @@ -929,6 +1045,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -936,6 +1053,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7", "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", @@ -945,6 +1063,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "SampleAfterValue": "2000003", @@ -952,6 +1071,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", @@ -961,6 +1081,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -970,6 +1091,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", @@ -978,6 +1100,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", @@ -986,6 +1109,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", @@ -994,6 +1118,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -1003,6 +1128,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1013,6 +1139,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -1022,6 +1149,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1031,6 +1159,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1040,6 +1169,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/haswell/uncore-cache.json index be9a3ed1a940..fb116637e83e 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -129,6 +145,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", @@ -137,6 +154,7 @@ }, { "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", @@ -153,6 +172,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", @@ -193,10 +217,19 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", "Unit": "CBOX" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "Unit": "cbox_0" } ] diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.jso= n b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json index 8da28239ebf9..557b278e631d 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Each cycle count number of valid entries in C= oherency Tracker queue from allocation till deallocation. Aperture requests= (snoops) appear as NC decoded internally and become coherent (snoop L3, ac= cess memory)", + "Counter": "0", "EventCode": "0x83", "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.All", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Each cycle counts number of all Core outgoing= valid entries. Such entry is defined as valid from its allocation till fir= st of IDI0 or DRS0 messages is sent out. Accounts for Coherent and non-cohe= rent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0", "CounterMask": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Total number of Core outgoing entries allocat= ed. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/haswell/uncore-other.json index 2af92e43b28a..1ac5b5ef8094 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/haswell/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/haswell/virtual-memory.json index 87a4ec1ee7d7..7cf00ae0e993 100644 --- a/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswell/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Number of cache load STLB hits. No page walk= .", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in any TLB of any page = size due to demand load misses.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", @@ -88,6 +99,7 @@ }, { "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks due to store miss in an= y TLB levels of any page size (4K/2M/4M/1G).", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", @@ -143,6 +161,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", @@ -151,6 +170,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", @@ -159,6 +179,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in ITLB that causes a page walk of an= y page size.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "ITLB misses that hit STLB. No page walk.", @@ -190,6 +214,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "PublicDescription": "ITLB misses that hit STLB (2M).", @@ -198,6 +223,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "PublicDescription": "ITLB misses that hit STLB (4K).", @@ -206,6 +232,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB of any page siz= e.", @@ -214,6 +241,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -221,6 +249,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", @@ -229,6 +258,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", @@ -245,6 +276,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "PublicDescription": "Number of DTLB page walker loads that hit in= the L1+FB.", @@ -253,6 +285,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "PublicDescription": "Number of DTLB page walker loads that hit in= the L2.", @@ -261,6 +294,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -270,6 +304,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -279,6 +314,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", @@ -286,6 +322,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", @@ -293,6 +330,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", @@ -300,6 +338,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", @@ -307,6 +346,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", @@ -314,6 +354,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", @@ -321,6 +362,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", @@ -328,6 +370,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", @@ -335,6 +378,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", @@ -343,6 +387,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", @@ -351,6 +396,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -360,6 +406,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", @@ -369,6 +416,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", @@ -377,6 +425,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com 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11:19:49 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:29 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-16-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 15/37] perf vendor events: Update haswellx metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/haswellx/cache.json | 97 ++++ .../pmu-events/arch/x86/haswellx/counter.json | 57 +++ .../arch/x86/haswellx/floating-point.json | 10 + .../arch/x86/haswellx/frontend.json | 29 ++ .../arch/x86/haswellx/hsx-metrics.json | 114 ++--- .../pmu-events/arch/x86/haswellx/memory.json | 67 +++ .../arch/x86/haswellx/metricgroups.json | 11 + .../pmu-events/arch/x86/haswellx/other.json | 4 + .../arch/x86/haswellx/pipeline.json | 130 +++++ .../arch/x86/haswellx/uncore-cache.json | 398 ++++++++++++++++ .../x86/haswellx/uncore-interconnect.json | 448 ++++++++++++++++++ .../arch/x86/haswellx/uncore-io.json | 59 +++ .../arch/x86/haswellx/uncore-memory.json | 325 +++++++++++++ .../arch/x86/haswellx/uncore-power.json | 62 +++ .../arch/x86/haswellx/virtual-memory.json | 49 ++ 15 files changed, 1785 insertions(+), 75 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/haswellx/counter.json diff --git a/tools/perf/pmu-events/arch/x86/haswellx/cache.json b/tools/per= f/pmu-events/arch/x86/haswellx/cache.json index a6c81010b394..42f24cdbe6ae 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts when new data lines are br= ought into the L1 Data cache, which cause other lines to be evicted from th= e cache.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -34,6 +38,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch. HWP are e.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", "SampleAfterValue": "2000003", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Not rejected writebacks that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_DEMAND_RQSTS.WB_HIT", "PublicDescription": "Not rejected writebacks that hit L2 cache.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "L2 cache lines in E state filling L2.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "L2 cache lines in I state filling L2.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "L2 cache lines in S state filling L2.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts all L2 code requests.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts all L2 store RFO requests.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", @@ -190,6 +213,7 @@ }, { "BriefDescription": "L2 prefetch requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_HIT", "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", @@ -198,6 +222,7 @@ }, { "BriefDescription": "L2 prefetch requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.L2_PF_MISS", "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", @@ -206,6 +231,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", @@ -215,6 +241,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", @@ -224,6 +251,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the number of store RFO requests that= hit the L2 cache.", @@ -232,6 +260,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", @@ -240,6 +269,7 @@ }, { "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, incl= uding rejects.", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "Transactions accessing L2 pipe.", @@ -256,6 +287,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "L2 cache accesses when fetching instructions= .", @@ -264,6 +296,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "Demand data read requests that access L2 cac= he.", @@ -272,6 +305,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "L1D writebacks that access L2 cache.", @@ -280,6 +314,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "L2 fill requests that access L2 cache.", @@ -288,6 +323,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "L2 writebacks that access L2 cache.", @@ -296,6 +332,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.RFO", "PublicDescription": "RFO requests that access L2 cache.", @@ -304,6 +341,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", @@ -312,6 +350,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", @@ -320,6 +359,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", @@ -328,6 +368,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -338,6 +379,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -348,6 +390,7 @@ }, { "BriefDescription": "Retired load uops which data sources were L3 = hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -358,6 +401,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD2", @@ -368,6 +412,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM30", "EventCode": "0xD3", @@ -379,6 +424,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: remot= e DRAM either Snoop not needed or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD3", @@ -389,6 +435,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: forwa= rded from remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD3", @@ -399,6 +446,7 @@ }, { "BriefDescription": "Retired load uop whose Data Source was: Remot= e cache HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD3", @@ -409,6 +457,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -419,6 +468,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -429,6 +479,7 @@ }, { "BriefDescription": "Retired load uops misses in L1 cache as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSM30", "EventCode": "0xD1", @@ -440,6 +491,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD1", @@ -450,6 +502,7 @@ }, { "BriefDescription": "Miss in mid-level (L2) cache. Excludes Unknow= n data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD1", @@ -461,6 +514,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in L3 without snoops required.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -472,6 +526,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", "EventCode": "0xD1", @@ -483,6 +538,7 @@ }, { "BriefDescription": "Retired load uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -494,6 +550,7 @@ }, { "BriefDescription": "Retired store uops.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD76, HSD29, HSM30", "EventCode": "0xD0", @@ -515,6 +573,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -525,6 +584,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -535,6 +595,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -545,6 +606,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "Errata": "HSD29, HSM30", "EventCode": "0xD0", @@ -555,6 +617,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", @@ -563,6 +626,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Demand code read requests sent to uncore.", @@ -571,6 +635,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "Errata": "HSD78, HSM80", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", @@ -580,6 +645,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", @@ -588,6 +654,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -595,6 +662,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -604,6 +672,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -613,6 +682,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -622,6 +692,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", @@ -631,6 +702,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", @@ -640,6 +712,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", @@ -649,6 +722,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "Errata": "HSD78, HSD62, HSD61, HSM63, HSM80", "EventCode": "0x60", @@ -658,6 +732,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "Errata": "HSD62, HSD61, HSM63", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", @@ -667,6 +742,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100003", @@ -674,6 +750,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -683,6 +760,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoop to one of the sibling cores hits the line in M state= and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -692,6 +770,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads hit i= n the L3 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -701,6 +780,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -710,6 +790,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) hit in the L3 and the snoops to sibling cores hit in either E/S state= and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -719,6 +800,7 @@ }, { "BriefDescription": "Counts all requests hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -728,6 +810,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -737,6 +820,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs hit in the = L3 and the snoops to sibling cores hit in either E/S state and the line is = not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -746,6 +830,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoop to one of the sibling cores hits the line in M state and the li= ne is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -755,6 +840,7 @@ }, { "BriefDescription": "Counts all demand code reads hit in the L3 an= d the snoops to sibling cores hit in either E/S state and the line is not f= orwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +850,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoop to one of the sibling cores hits the line in M state and the line i= s forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -773,6 +860,7 @@ }, { "BriefDescription": "Counts demand data reads hit in the L3 and th= e snoops to sibling cores hit in either E/S state and the line is not forwa= rded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -782,6 +870,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoop to one of the sibling cores hits the line in M state an= d the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -791,6 +880,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) hit in t= he L3 and the snoops to sibling cores hit in either E/S state and the line = is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -800,6 +890,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -809,6 +900,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -818,6 +910,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -827,6 +920,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -836,6 +930,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -845,6 +940,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs hit in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -854,6 +950,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/counter.json b/tools/p= erf/pmu-events/arch/x86/haswellx/counter.json new file mode 100644 index 000000000000..84c01d8023f1 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/haswellx/counter.json @@ -0,0 +1,57 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "HA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R3QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "SBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json b/= tools/perf/pmu-events/arch/x86/haswellx/floating-point.json index 8fcc10f74ad9..a0b917306887 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Approximate counts of AVX & AVX2 256-bit inst= ructions, including non-arithmetic instructions, loads, and stores. May co= unt non-AVX instructions that employ 256-bit operations, including (but not= necessarily limited to) rep string instructions that use 256-bit loads and= stores for optimized performance, XSAVE* and XRSTOR*, and operations that = transition the x87 FPU data registers between x87 and MMX.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "AVX_INSTS.ALL", "PublicDescription": "Note that a whole rep string only counts AVX= _INST.ALL once.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "Number of SIMD FP assists due to input value= s.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "Number of SIMD FP assists due to output valu= es.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "Number of X87 FP assists due to input values= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "Number of X87 FP assists due to output value= s.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were eliminated.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "PublicDescription": "Number of SIMD move elimination candidate uo= ps that were not eliminated.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "Errata": "HSD56, HSM57", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "Errata": "HSD56, HSM57", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json b/tools/= perf/pmu-events/arch/x86/haswellx/frontend.json index 73d6d681dfa7..a9f81fd17925 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/frontend.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "SampleAfterValue": "2000003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFDATA_STALL", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFETCH_STALL", "SampleAfterValue": "2000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Misses. Includes Uncacheable accesses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts Instruction Cache (ICACHE)= misses.", @@ -45,6 +51,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -63,6 +71,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0x79", "EventName": "IDQ.EMPTY", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -156,6 +175,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "This event counts uops delivered by the Fron= t-end with the assistance of the microcode sequencer. Microcode assists ar= e used for complex instructions or scenarios that can't be handled by the s= tandard decoder. Using other instructions, if possible, will usually impro= ve performance.", @@ -189,6 +212,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", @@ -198,6 +222,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD135", "EventCode": "0x9C", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", "EventCode": "0x9C", @@ -218,6 +244,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD135", "EventCode": "0x9C", @@ -227,6 +254,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD135", "EventCode": "0x9C", @@ -236,6 +264,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD135", "EventCode": "0x9C", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json b/too= ls/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json index 83d50d80a148..8f2ba3391e35 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/hsx-metrics.json @@ -68,7 +68,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -292,7 +292,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -302,7 +302,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -323,7 +323,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -353,7 +353,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM * (1 = + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_= UOPS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS= _L3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LO= AD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_D= RAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RET= IRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS * (1 + ME= M_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS= _RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_= HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_U= OPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM = + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED= .REMOTE_FWD)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -374,7 +374,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT * (1 + = MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UO= PS_RETIRED.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L= 3_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD= _UOPS_L3_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRA= M + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIR= ED.REMOTE_FWD))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -383,7 +383,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "10 * ARITH.DIVIDER_UOPS / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -420,7 +420,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(8 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -429,7 +429,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(8 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES= .WALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -438,7 +438,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_= HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info= _thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -448,7 +448,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.REQUEST_FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -477,7 +477,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -497,7 +497,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFDATA_STALL / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -590,12 +590,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -616,23 +616,11 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, - { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.= ANY", @@ -640,17 +628,11 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, { "BriefDescription": "L2 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.= ANY", @@ -658,16 +640,16 @@ "MetricName": "tma_info_memory_l2mpki" }, { - "BriefDescription": "", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + "MetricName": "tma_info_memory_l3_cache_fill_bw" }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", @@ -681,29 +663,17 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_data_l2_mlp" }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "tma_info_memory_load_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" + "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, { "BriefDescription": "Average Parallel L2 cache miss demand Loads", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" + "MetricName": "tma_info_memory_latency_load_l2_mlp" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -720,12 +690,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, { "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", "MetricExpr": "(ITLB_MISSES.WALK_DURATION + DTLB_LOAD_MISSES.WALK_= DURATION + DTLB_STORE_MISSES.WALK_DURATION) / tma_info_core_core_clks", @@ -747,13 +711,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -854,7 +818,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -863,7 +827,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(14 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -881,7 +845,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY= .STALLS_L2_PENDING) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -901,7 +865,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.L3_HIT * (1 + MEM_LOAD_= UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIRE= D.L3_HIT + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_L3_HIT_RET= IRED.XSNP_HITM + MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOPS_L3_= MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM + MEM_L= OAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE= _FWD))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -959,7 +923,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -969,7 +933,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -978,7 +942,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -1134,7 +1098,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1161,7 +1125,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1190,7 +1154,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -1218,7 +1182,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/memory.json b/tools/pe= rf/pmu-events/arch/x86/haswellx/memory.json index 2d212cf59e92..be0108558103 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC1", "SampleAfterValue": "2000003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to uncommon conditions.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type.", + "Counter": "0,1,2,3", "Errata": "HSD65", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC4", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to none of the previous 4 categories (e.g. interrupts)", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an HLE execution aborted due= to none of the previous 4 categories (e.g. interrupts).", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed.", + "Counter": "0,1,2,3", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "SampleAfterValue": "2000003", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing machine clears detected. Memory ordering machine clears can result from= memory address aliasing or snoops from another hardware thread or core to = data inflight in the pipeline. Machine clears can have a significant perfo= rmance impact if they are happening frequently.", @@ -68,6 +77,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 128.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 16.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 256.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -104,6 +116,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 32.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 4.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -128,6 +142,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 512.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -140,6 +155,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 64.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -152,6 +168,7 @@ }, { "BriefDescription": "Randomly selected loads with latency value be= ing above 8.", + "Counter": "3", "Data_LA": "1", "Errata": "HSD76, HSD25, HSM26", "EventCode": "0xcd", @@ -164,6 +181,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", @@ -172,6 +190,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "Speculative cache-line split store-address u= ops dispatched to L1D.", @@ -180,6 +199,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -189,6 +209,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -198,6 +219,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -207,6 +229,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -216,6 +239,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -225,6 +249,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -234,6 +259,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads miss = the L3 and clean or shared data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", "MSRIndex": "0x1a6,0x1a7", @@ -243,6 +269,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -252,6 +279,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -261,6 +289,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the data is returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -270,6 +299,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -279,6 +309,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) miss the L3 and clean or shared data is transferred from remote cache= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", @@ -288,6 +319,7 @@ }, { "BriefDescription": "Counts all requests miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -297,6 +329,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss in the= L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -306,6 +339,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs miss the L3= and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -315,6 +349,7 @@ }, { "BriefDescription": "Counts all demand code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -324,6 +359,7 @@ }, { "BriefDescription": "Counts all demand code reads miss the L3 and = the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -333,6 +369,7 @@ }, { "BriefDescription": "Counts demand data reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -342,6 +379,7 @@ }, { "BriefDescription": "Counts demand data reads miss the L3 and the = data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -351,6 +389,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss in = the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -360,6 +399,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the data is returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -369,6 +409,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) miss the= L3 and the modified data is transferred from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -378,6 +419,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -387,6 +429,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -396,6 +439,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -405,6 +449,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -414,6 +459,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -423,6 +469,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs miss in the L3", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -432,6 +479,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -440,6 +488,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC1", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -448,6 +497,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC2", "SampleAfterValue": "2000003", @@ -455,6 +505,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions.", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC3", "SampleAfterValue": "2000003", @@ -462,6 +513,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type.", + "Counter": "0,1,2,3", "Errata": "HSD65", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC4", @@ -470,6 +522,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MISC5", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -478,6 +531,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed.", + "Counter": "0,1,2,3", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "SampleAfterValue": "2000003", @@ -485,6 +539,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "SampleAfterValue": "2000003", @@ -492,6 +547,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -499,6 +555,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "SampleAfterValue": "2000003", @@ -506,6 +563,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "SampleAfterValue": "2000003", @@ -513,6 +571,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "SampleAfterValue": "2000003", @@ -520,6 +579,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "SampleAfterValue": "2000003", @@ -527,6 +587,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "SampleAfterValue": "2000003", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "SampleAfterValue": "2000003", @@ -541,6 +603,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "SampleAfterValue": "2000003", @@ -548,6 +611,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "SampleAfterValue": "2000003", @@ -555,6 +619,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "SampleAfterValue": "2000003", @@ -562,6 +627,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "SampleAfterValue": "2000003", @@ -569,6 +635,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/metricgroups.json b/to= ols/perf/pmu-events/arch/x86/haswellx/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/other.json b/tools/per= f/pmu-events/arch/x86/haswellx/other.json index 2395ebf112db..7d8769ef6d04 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/other.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json b/tools/= perf/pmu-events/arch/x86/haswellx/pipeline.json index 540f4372623c..c00301fdb3d7 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Any uop executed by the Divider. (This includ= es all divide uops, sqrt, ...)", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_UOPS", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -58,6 +66,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -65,6 +74,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", @@ -72,6 +82,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -86,6 +98,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls.= ", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -93,6 +106,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -100,6 +114,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Branch instructions at retirement.", @@ -107,6 +122,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -115,6 +131,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -124,6 +141,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Number of far branches retired.", @@ -132,6 +150,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -140,6 +159,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -148,6 +168,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -157,6 +178,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -166,6 +188,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", @@ -174,6 +197,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -182,6 +206,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -189,6 +214,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -196,6 +222,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -204,6 +231,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -211,6 +239,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -218,6 +247,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -225,6 +255,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -232,6 +263,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", @@ -239,6 +271,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Mispredicted branch instructions at retireme= nt.", @@ -246,6 +279,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -255,6 +289,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -263,6 +298,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -272,6 +308,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -279,6 +316,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", @@ -288,6 +326,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", @@ -296,6 +335,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "100003", @@ -303,6 +343,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate.", "SampleAfterValue": "2000003", @@ -310,6 +351,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", @@ -319,6 +361,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "PublicDescription": "Reference cycles when the at least one threa= d on the physical core is unhalted (counts at 100 MHz rate).", @@ -327,6 +370,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of thread cycle= s while the thread is not in a halt state. The thread enters the halt state= when it is running the HLT instruction. The core frequency may change from= time to time due to power or thermal throttling.", "SampleAfterValue": "2000003", @@ -335,12 +379,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", @@ -349,12 +395,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -364,6 +412,7 @@ }, { "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD78, HSM63, HSM80", "EventCode": "0xa3", @@ -374,6 +423,7 @@ }, { "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -383,6 +433,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -392,6 +443,7 @@ }, { "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -401,6 +453,7 @@ }, { "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", "CounterMask": "5", "Errata": "HSM63, HSM80", "EventCode": "0xa3", @@ -411,6 +464,7 @@ }, { "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -420,6 +474,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "PublicDescription": "Stall cycles due to IQ is full.", @@ -428,6 +483,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "This event counts cycles where the decoder i= s stalled on an instruction with a length changing prefix (LCP).", @@ -436,6 +492,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "Errata": "HSD140, HSD143", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers. INST_RETIRED.ANY is counted by a designated fixed counter, leav= ing the programmable counters available for other events. Faulting executio= ns of GETSEC/VM entry/VM Exit/MWait will not count as retired instructions.= ", @@ -444,6 +501,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "HSD11, HSD140", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -452,6 +510,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "HSD140", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -462,6 +521,7 @@ }, { "BriefDescription": "FP operations retired. X87 FP operations that= have no exceptions: Counts also flows that have several X87 or flows that = use X87 uops in the exception handling.", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PublicDescription": "This is a non-precise version (that is, does= not use PEBS) of the event that counts FP operations retired. For X87 FP o= perations that have no exceptions counting also includes flows that have se= veral X87, or flows that use X87 uops in the exception handling.", @@ -470,6 +530,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -480,6 +541,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -489,6 +551,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -497,6 +560,7 @@ }, { "BriefDescription": "loads blocked by overlapping with store buffe= r that cannot be forwarded", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. The penalty for blocked store forwarding is t= hat the load must wait for the store to write its value to the cache before= it can be issued.", @@ -505,6 +569,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline which can have a performance impact.", @@ -513,6 +578,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", @@ -521,6 +587,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", @@ -529,6 +596,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -537,6 +605,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -545,6 +614,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered by the LSD.", @@ -553,6 +623,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -562,6 +633,7 @@ }, { "BriefDescription": "Cycles there was a Nuke. Account for both thr= ead-specific and All Thread Nukes.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "2000003", @@ -569,6 +641,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "SampleAfterValue": "100003", @@ -576,6 +649,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", @@ -584,6 +658,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "PublicDescription": "Number of integer move elimination candidate= uops that were eliminated.", @@ -592,6 +667,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "PublicDescription": "Number of integer move elimination candidate= uops that were not eliminated.", @@ -600,6 +676,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "PublicDescription": "Number of microcode assists invoked by HW up= on uop writeback.", @@ -608,6 +685,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "Errata": "HSD135", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", @@ -617,6 +695,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -624,6 +703,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -631,6 +711,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "This event counts cycles during which no ins= tructions were allocated because no Store Buffers (SB) were available.", @@ -639,6 +720,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Count cases of saving new LBR records by har= dware.", @@ -647,6 +729,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "This event counts cycles when the Reservatio= n Station ( RS ) is empty for the thread. The RS is a structure that buffer= s allocated micro-ops from the Front-end. If there are many cycles when the= RS is empty, it may represent an underflow of instructions delivered from = the Front-end.", @@ -655,6 +738,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -665,6 +749,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", @@ -672,6 +757,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", @@ -679,6 +765,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", @@ -686,6 +773,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", @@ -693,6 +781,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", @@ -700,6 +789,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", @@ -707,6 +797,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "SampleAfterValue": "2000003", @@ -714,6 +805,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "SampleAfterValue": "2000003", @@ -721,6 +813,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "Errata": "HSD30, HSM31", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", @@ -730,6 +823,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -739,6 +833,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -748,6 +843,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -757,6 +853,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD30, HSM31", "EventCode": "0xb1", @@ -766,6 +863,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "Errata": "HSD30, HSM31", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -775,6 +873,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -785,6 +884,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -795,6 +895,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -805,6 +906,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -814,6 +916,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "Errata": "HSD144, HSD30, HSM31", "EventCode": "0xB1", @@ -824,6 +927,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0", "PublicDescription": "Cycles which a uop is dispatched on port 0 i= n this thread.", @@ -833,6 +937,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -840,6 +945,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1", "PublicDescription": "Cycles which a uop is dispatched on port 1 i= n this thread.", @@ -849,6 +955,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -856,6 +963,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2", "PublicDescription": "Cycles which a uop is dispatched on port 2 i= n this thread.", @@ -865,6 +973,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -872,6 +981,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3", "PublicDescription": "Cycles which a uop is dispatched on port 3 i= n this thread.", @@ -881,6 +991,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -888,6 +999,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4", "PublicDescription": "Cycles which a uop is dispatched on port 4 i= n this thread.", @@ -897,6 +1009,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -904,6 +1017,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5", "PublicDescription": "Cycles which a uop is dispatched on port 5 i= n this thread.", @@ -913,6 +1027,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -920,6 +1035,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6", "PublicDescription": "Cycles which a uop is dispatched on port 6 i= n this thread.", @@ -929,6 +1045,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are executed in por= t 6.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_6_CORE", "SampleAfterValue": "2000003", @@ -936,6 +1053,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7", "PublicDescription": "Cycles which a uop is dispatched on port 7 i= n this thread.", @@ -945,6 +1063,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 7.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_EXECUTED_PORT.PORT_7_CORE", "SampleAfterValue": "2000003", @@ -952,6 +1071,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of uops issued = by the Front-end of the pipeline to the Back-end. This event is counted at = the allocation stage and will count both retired and non-retired uops.", @@ -961,6 +1081,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -970,6 +1091,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated. S= uch uops considered perf sensitive; added by GSR u-arch.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops allocated. Such u= ops add delay.", @@ -978,6 +1100,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", @@ -986,6 +1109,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (for example, 2 sources + immediate) regardless of= whether it is a result of LEA instruction or not.", @@ -994,6 +1118,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -1003,6 +1128,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -1013,6 +1139,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -1022,6 +1149,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1031,6 +1159,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1040,6 +1169,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/haswellx/uncore-cache.json index 9227cc226002..3c23bafcba28 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "LLC prefetch misses for code reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x191", @@ -12,6 +13,7 @@ }, { "BriefDescription": "LLC prefetch misses for data reads. Derived f= rom unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.DATA_LLC_PREFETCH", "Filter": "filter_opc=3D0x192", @@ -23,6 +25,7 @@ }, { "BriefDescription": "LLC misses - demand and prefetch data reads -= excludes LLC prefetches. Derived from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.DATA_READ", "Filter": "filter_opc=3D0x182", @@ -34,6 +37,7 @@ }, { "BriefDescription": "MMIO reads. Derived from unc_c_tor_inserts.mi= ss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_READ", "Filter": "filter_opc=3D0x187,filter_nc=3D1", @@ -45,6 +49,7 @@ }, { "BriefDescription": "MMIO writes. Derived from unc_c_tor_inserts.m= iss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "filter_opc=3D0x18f,filter_nc=3D1", @@ -56,6 +61,7 @@ }, { "BriefDescription": "PCIe write misses (full cache line). Derived = from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_NON_SNOOP_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", @@ -67,6 +73,7 @@ }, { "BriefDescription": "LLC misses for PCIe read current. Derived fro= m unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_READ", "Filter": "filter_opc=3D0x19e", @@ -78,6 +85,7 @@ }, { "BriefDescription": "ItoM write misses (as part of fast string mem= cpy stores) + PCIe full line writes. Derived from unc_c_tor_inserts.miss_op= code", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8", @@ -89,6 +97,7 @@ }, { "BriefDescription": "LLC prefetch misses for RFO. Derived from unc= _c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.RFO_LLC_PREFETCH", "Filter": "filter_opc=3D0x190", @@ -100,6 +109,7 @@ }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_c_tor_inserts.miss_opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "filter_opc=3D0x187", @@ -111,6 +121,7 @@ }, { "BriefDescription": "L2 demand and L2 prefetch code references to = LLC. Derived from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.CODE_LLC_PREFETCH", "Filter": "filter_opc=3D0x181", @@ -122,6 +133,7 @@ }, { "BriefDescription": "PCIe writes (partial cache line). Derived fro= m unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_NS_PARTIAL_WRITE", "Filter": "filter_opc=3D0x180,filter_tid=3D0x3e", @@ -132,6 +144,7 @@ }, { "BriefDescription": "PCIe read current. Derived from unc_c_tor_ins= erts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_READ", "Filter": "filter_opc=3D0x19e", @@ -143,6 +156,7 @@ }, { "BriefDescription": "PCIe write references (full cache line). Deri= ved from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.PCIE_WRITE", "Filter": "filter_opc=3D0x1c8,filter_tid=3D0x3e", @@ -154,6 +168,7 @@ }, { "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "filter_opc=3D0x18c", @@ -165,6 +180,7 @@ }, { "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_c_tor_inserts.opcode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "filter_opc=3D0x18d", @@ -176,6 +192,7 @@ }, { "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_C_BOUNCE_CONTROL", "PerPkg": "1", @@ -183,12 +200,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", @@ -197,6 +216,7 @@ }, { "BriefDescription": "FaST wire asserted", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_C_FAST_ASSERTED", "PerPkg": "1", @@ -205,6 +225,7 @@ }, { "BriefDescription": "All LLC Misses (code+ data rd + data wr - inc= luding demand and prefetch)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", "Filter": "filter_state=3D0x1", @@ -216,6 +237,7 @@ }, { "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -225,6 +247,7 @@ }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", "PerPkg": "1", @@ -234,6 +257,7 @@ }, { "BriefDescription": "Cache Lookups; Any Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.READ", "PerPkg": "1", @@ -243,6 +267,7 @@ }, { "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -252,6 +277,7 @@ }, { "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", @@ -261,6 +287,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.F_STATE", "PerPkg": "1", @@ -279,6 +307,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.I_STATE", "PerPkg": "1", @@ -288,6 +317,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", @@ -297,6 +327,7 @@ }, { "BriefDescription": "M line evictions from LLC (writebacks to memo= ry)", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", @@ -307,6 +338,7 @@ }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", "PerPkg": "1", @@ -316,6 +348,7 @@ }, { "BriefDescription": "Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", @@ -325,6 +358,7 @@ }, { "BriefDescription": "Cbo Misc; DRd hitting non-M with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_MISS", "PerPkg": "1", @@ -334,6 +368,7 @@ }, { "BriefDescription": "Cbo Misc; Clean Victim with raw CV=3D0", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.CVZERO_PREFETCH_VICTIM", "PerPkg": "1", @@ -343,6 +378,7 @@ }, { "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", @@ -352,6 +388,7 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -361,6 +398,7 @@ }, { "BriefDescription": "Cbo Misc", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", @@ -370,6 +408,7 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", @@ -379,6 +418,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 0", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", @@ -388,6 +428,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 1", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", @@ -397,6 +438,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 2", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE2", "PerPkg": "1", @@ -406,6 +448,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.AGE3", "PerPkg": "1", @@ -415,6 +458,7 @@ }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.LRU_DECREMENT", "PerPkg": "1", @@ -424,6 +468,7 @@ }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", "PerPkg": "1", @@ -433,6 +478,7 @@ }, { "BriefDescription": "AD Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.ALL", "PerPkg": "1", @@ -442,6 +488,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN", "PerPkg": "1", @@ -451,6 +498,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -460,6 +508,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -469,6 +518,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP", "PerPkg": "1", @@ -478,6 +528,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -487,6 +538,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -496,6 +548,7 @@ }, { "BriefDescription": "AK Ring In Use; All", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.ALL", "PerPkg": "1", @@ -505,6 +558,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN", "PerPkg": "1", @@ -514,6 +568,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -523,6 +578,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -532,6 +588,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP", "PerPkg": "1", @@ -541,6 +598,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -550,6 +608,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -559,6 +618,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.ALL", "PerPkg": "1", @@ -568,6 +628,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN", "PerPkg": "1", @@ -577,6 +638,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -586,6 +648,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -595,6 +658,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP", "PerPkg": "1", @@ -604,6 +668,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -613,6 +678,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -622,6 +688,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AD", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD", "PerPkg": "1", @@ -630,6 +697,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; AK", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", @@ -638,6 +706,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; BL", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", @@ -646,6 +715,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", @@ -654,6 +724,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.ANY", "PerPkg": "1", @@ -663,6 +734,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DN", "PerPkg": "1", @@ -672,6 +744,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.DOWN", "PerPkg": "1", @@ -681,6 +754,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_C_RING_IV_USED.UP", "PerPkg": "1", @@ -690,6 +764,7 @@ }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.AD", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD", "PerPkg": "1", @@ -698,6 +773,7 @@ }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.AK", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK", "PerPkg": "1", @@ -706,6 +782,7 @@ }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.BL", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL", "PerPkg": "1", @@ -714,6 +791,7 @@ }, { "BriefDescription": "UNC_C_RING_SINK_STARVED.IV", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", @@ -722,6 +800,7 @@ }, { "BriefDescription": "Number of cycles the Cbo is actively throttli= ng traffic onto the Ring in order to limit bounce traffic.", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", @@ -729,6 +808,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "PerPkg": "1", @@ -738,6 +818,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", @@ -747,6 +828,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", "PerPkg": "1", @@ -756,6 +838,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", "PerPkg": "1", @@ -765,6 +848,7 @@ }, { "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IPQ", "PerPkg": "1", @@ -774,6 +858,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ", "PerPkg": "1", @@ -783,6 +868,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", "PerPkg": "1", @@ -792,6 +878,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ", "PerPkg": "1", @@ -801,6 +888,7 @@ }, { "BriefDescription": "Ingress Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.PRQ_REJ", "PerPkg": "1", @@ -810,6 +898,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IPQ", "PerPkg": "1", @@ -819,6 +908,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IRQ", "PerPkg": "1", @@ -828,6 +918,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", @@ -837,6 +928,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.PRQ", "PerPkg": "1", @@ -846,6 +938,7 @@ }, { "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -855,6 +948,7 @@ }, { "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", "PerPkg": "1", @@ -864,6 +958,7 @@ }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", "PerPkg": "1", @@ -873,6 +968,7 @@ }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -882,6 +978,7 @@ }, { "BriefDescription": "Probe Queue Retries; No AD Sbo Credits", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -891,6 +988,7 @@ }, { "BriefDescription": "Probe Queue Retries; Target Node Filter", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_C_RxR_IPQ_RETRY2.TARGET", "PerPkg": "1", @@ -900,6 +998,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -909,6 +1008,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", @@ -918,6 +1018,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", @@ -927,6 +1028,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -936,6 +1038,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.NID", "PerPkg": "1", @@ -945,6 +1048,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -954,6 +1058,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", @@ -963,6 +1068,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No AD Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -972,6 +1078,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No BL Sbo Cred= its", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -981,6 +1088,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Target Node Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_C_RxR_IRQ_RETRY2.TARGET", "PerPkg": "1", @@ -990,6 +1098,7 @@ }, { "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", "PerPkg": "1", @@ -999,6 +1108,7 @@ }, { "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", "PerPkg": "1", @@ -1008,6 +1118,7 @@ }, { "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -1017,6 +1128,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.NID", "PerPkg": "1", @@ -1026,6 +1138,7 @@ }, { "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -1035,6 +1148,7 @@ }, { "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", "PerPkg": "1", @@ -1044,6 +1158,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", "PerPkg": "1", @@ -1053,6 +1168,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No AD Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.AD_SBO", "PerPkg": "1", @@ -1062,6 +1178,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; No BL Sbo Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.BL_SBO", "PerPkg": "1", @@ -1071,6 +1188,7 @@ }, { "BriefDescription": "ISMQ Request Queue Rejects; Target Node Filte= r", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_C_RxR_ISMQ_RETRY2.TARGET", "PerPkg": "1", @@ -1080,6 +1198,7 @@ }, { "BriefDescription": "Ingress Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -1089,6 +1208,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -1098,6 +1218,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", "PerPkg": "1", @@ -1107,6 +1228,7 @@ }, { "BriefDescription": "Ingress Occupancy; PRQ Rejects", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.PRQ_REJ", "PerPkg": "1", @@ -1116,6 +1238,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -1125,6 +1248,7 @@ }, { "BriefDescription": "SBo Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_C_SBO_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -1134,6 +1258,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -1143,6 +1268,7 @@ }, { "BriefDescription": "SBo Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x3E", "EventName": "UNC_C_SBO_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -1152,6 +1278,7 @@ }, { "BriefDescription": "TOR Inserts; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", @@ -1161,6 +1288,7 @@ }, { "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", @@ -1170,6 +1298,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", @@ -1179,6 +1308,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", @@ -1188,6 +1318,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", @@ -1197,6 +1328,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1206,6 +1338,7 @@ }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", @@ -1215,6 +1348,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", @@ -1224,6 +1358,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1233,6 +1368,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", @@ -1242,6 +1378,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", @@ -1251,6 +1388,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", @@ -1260,6 +1398,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", @@ -1269,6 +1408,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", @@ -1278,6 +1418,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", @@ -1287,6 +1428,7 @@ }, { "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", @@ -1296,6 +1438,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", @@ -1305,6 +1448,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", @@ -1314,6 +1458,7 @@ }, { "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", @@ -1323,6 +1468,7 @@ }, { "BriefDescription": "TOR Occupancy; Any", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.ALL", "PerPkg": "1", @@ -1332,6 +1478,7 @@ }, { "BriefDescription": "TOR Occupancy; Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", "PerPkg": "1", @@ -1341,6 +1488,7 @@ }, { "BriefDescription": "Occupancy counter for LLC data reads (demand = and L2 prefetch). Derived from unc_c_tor_occupancy.miss_opcode", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LLC_DATA_READ", "Filter": "filter_opc=3D0x182", @@ -1351,6 +1499,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -1360,6 +1509,7 @@ }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", @@ -1369,6 +1519,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", "PerPkg": "1", @@ -1378,6 +1529,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", "PerPkg": "1", @@ -1387,6 +1539,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1396,6 +1549,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", "PerPkg": "1", @@ -1405,6 +1559,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", "PerPkg": "1", @@ -1414,6 +1569,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1423,6 +1579,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", "PerPkg": "1", @@ -1432,6 +1589,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", "PerPkg": "1", @@ -1441,6 +1599,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", "PerPkg": "1", @@ -1450,6 +1609,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", "PerPkg": "1", @@ -1459,6 +1619,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", "PerPkg": "1", @@ -1468,6 +1629,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", "PerPkg": "1", @@ -1477,6 +1639,7 @@ }, { "BriefDescription": "TOR Occupancy; Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", @@ -1486,6 +1649,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -1495,6 +1659,7 @@ }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", @@ -1504,6 +1669,7 @@ }, { "BriefDescription": "TOR Occupancy; Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.WB", "PerPkg": "1", @@ -1513,6 +1679,7 @@ }, { "BriefDescription": "Onto AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", @@ -1521,6 +1688,7 @@ }, { "BriefDescription": "Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", @@ -1529,6 +1697,7 @@ }, { "BriefDescription": "Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", @@ -1537,6 +1706,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", "PerPkg": "1", @@ -1546,6 +1716,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CORE", "PerPkg": "1", @@ -1555,6 +1726,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", "PerPkg": "1", @@ -1564,6 +1736,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CORE", "PerPkg": "1", @@ -1573,6 +1746,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", "PerPkg": "1", @@ -1582,6 +1756,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", @@ -1591,6 +1766,7 @@ }, { "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", "PerPkg": "1", @@ -1600,6 +1776,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AD_CORE", "PerPkg": "1", @@ -1609,6 +1786,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AK_BOTH", "PerPkg": "1", @@ -1618,6 +1796,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.BL_BOTH", "PerPkg": "1", @@ -1627,6 +1806,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.IV", "PerPkg": "1", @@ -1636,6 +1816,7 @@ }, { "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE", "PerPkg": "1", @@ -1644,6 +1825,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", "PerPkg": "1", @@ -1653,6 +1835,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", "PerPkg": "1", @@ -1662,6 +1845,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", "PerPkg": "1", @@ -1671,6 +1855,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", "PerPkg": "1", @@ -1680,6 +1865,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "PerPkg": "1", @@ -1689,6 +1875,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "PerPkg": "1", @@ -1698,6 +1885,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_H_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", @@ -1705,6 +1893,7 @@ }, { "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_H_DIRECT2CORE_COUNT", "PerPkg": "1", @@ -1713,6 +1902,7 @@ }, { "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", "PerPkg": "1", @@ -1721,6 +1911,7 @@ }, { "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1729,6 +1920,7 @@ }, { "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", @@ -1737,6 +1929,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", "PerPkg": "1", @@ -1746,6 +1939,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", "PerPkg": "1", @@ -1755,6 +1949,7 @@ }, { "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1764,6 +1959,7 @@ }, { "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", "PerPkg": "1", @@ -1773,6 +1969,7 @@ }, { "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.SET", "PerPkg": "1", @@ -1782,6 +1979,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is A= ckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ACKCNFLTWBI", "PerPkg": "1", @@ -1790,6 +1988,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; All Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALL", "PerPkg": "1", @@ -1798,6 +1997,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.ALLOCS", "PerPkg": "1", @@ -1806,6 +2006,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Allocat= ions", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.EVICTS", "PerPkg": "1", @@ -1814,6 +2015,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; HOM Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.HOM", "PerPkg": "1", @@ -1822,6 +2024,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Invalid= ations", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.INVALS", "PerPkg": "1", @@ -1830,6 +2033,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= dCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.READ_OR_INVITOE", "PerPkg": "1", @@ -1838,6 +2042,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSP", "PerPkg": "1", @@ -1846,6 +2051,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1854,6 +2060,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= spIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1862,6 +2069,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is R= sSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.RSPFWDS", "PerPkg": "1", @@ -1870,6 +2078,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOE_OR_S", "PerPkg": "1", @@ -1878,6 +2087,7 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_H_HITME_HIT.WBMTOI", "PerPkg": "1", @@ -1886,6 +2096,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ACKCNFLTWBI", "PerPkg": "1", @@ -1894,6 +2105,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.ALL", "PerPkg": "1", @@ -1902,6 +2114,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.HOM", "PerPkg": "1", @@ -1910,6 +2123,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE= ", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.READ_OR_INVITOE", "PerPkg": "1", @@ -1918,6 +2132,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSP", "PerPkg": "1", @@ -1926,6 +2141,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_LOCAL", "PerPkg": "1", @@ -1934,6 +2150,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDI_REMOTE", "PerPkg": "1", @@ -1942,6 +2159,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.RSPFWDS", "PerPkg": "1", @@ -1950,6 +2168,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOE_OR_S", "PerPkg": "1", @@ -1958,6 +2177,7 @@ }, { "BriefDescription": "Accumulates Number of PV bits set on HitMe Ca= che Hits; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_H_HITME_HIT_PV_BITS_SET.WBMTOI", "PerPkg": "1", @@ -1966,6 +2186,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is AckCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ACKCNFLTWBI", "PerPkg": "1", @@ -1974,6 +2195,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALL", "PerPkg": "1", @@ -1982,6 +2204,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Allocations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.ALLOCS", "PerPkg": "1", @@ -1990,6 +2213,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; HOM Requests", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.HOM", "PerPkg": "1", @@ -1998,6 +2222,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; Invalidations", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.INVALS", "PerPkg": "1", @@ -2006,6 +2231,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdInvOwn, RdCur or InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.READ_OR_INVITOE", "PerPkg": "1", @@ -2014,6 +2240,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspI, RspIWb, RspS, RspSWb, RspCnflt or RspCnfltWbI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSP", "PerPkg": "1", @@ -2022,6 +2249,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_LOCAL", "PerPkg": "1", @@ -2030,6 +2258,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDI_REMOTE", "PerPkg": "1", @@ -2038,6 +2267,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RsSFwd or RspSFwdWb", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.RSPFWDS", "PerPkg": "1", @@ -2046,6 +2276,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOE_OR_S", "PerPkg": "1", @@ -2054,6 +2285,7 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_H_HITME_LOOKUP.WBMTOI", "PerPkg": "1", @@ -2062,6 +2294,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", "PerPkg": "1", @@ -2071,6 +2304,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", "PerPkg": "1", @@ -2080,6 +2314,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI2", "PerPkg": "1", @@ -2089,6 +2324,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", "PerPkg": "1", @@ -2098,6 +2334,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", "PerPkg": "1", @@ -2107,6 +2344,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI2", "PerPkg": "1", @@ -2116,6 +2354,7 @@ }, { "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_H_IMC_READS.NORMAL", "PerPkg": "1", @@ -2125,6 +2364,7 @@ }, { "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", @@ -2132,6 +2372,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.ALL", "PerPkg": "1", @@ -2141,6 +2382,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL", "PerPkg": "1", @@ -2150,6 +2392,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", @@ -2159,6 +2402,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -2168,6 +2412,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", @@ -2177,6 +2422,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.HUB", "PerPkg": "1", @@ -2185,6 +2431,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_H_IOT_BACKPRESSURE.SAT", "PerPkg": "1", @@ -2193,6 +2440,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS0", "PerPkg": "1", @@ -2202,6 +2450,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x64", "EventName": "UNC_H_IOT_CTS_EAST_LO.CTS1", "PerPkg": "1", @@ -2211,6 +2460,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS2", "PerPkg": "1", @@ -2220,6 +2470,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0x65", "EventName": "UNC_H_IOT_CTS_HI.CTS3", "PerPkg": "1", @@ -2229,6 +2480,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS0", "PerPkg": "1", @@ -2238,6 +2490,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_H_IOT_CTS_WEST_LO.CTS1", "PerPkg": "1", @@ -2247,6 +2500,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Cancelled", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.CANCELLED", "PerPkg": "1", @@ -2256,6 +2510,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.INVITOE_LOCAL", "PerPkg": "1", @@ -2265,6 +2520,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL", "PerPkg": "1", @@ -2274,6 +2530,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Reads Local - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL_USEFUL", "PerPkg": "1", @@ -2283,6 +2540,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE", "PerPkg": "1", @@ -2292,6 +2550,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote - Useful", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE_USEFUL", "PerPkg": "1", @@ -2301,6 +2560,7 @@ }, { "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.ALL", "PerPkg": "1", @@ -2310,6 +2570,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", "PerPkg": "1", @@ -2319,6 +2580,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", "PerPkg": "1", @@ -2328,6 +2590,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", "PerPkg": "1", @@ -2337,6 +2600,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", "PerPkg": "1", @@ -2346,6 +2610,7 @@ }, { "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -2355,6 +2620,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -2364,6 +2630,7 @@ }, { "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", @@ -2373,6 +2640,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -2382,6 +2650,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -2391,6 +2660,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", @@ -2400,6 +2670,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -2409,6 +2680,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -2418,6 +2690,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW", "PerPkg": "1", @@ -2427,6 +2700,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -2436,6 +2710,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -2445,6 +2720,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW", "PerPkg": "1", @@ -2454,6 +2730,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -2463,6 +2740,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -2472,6 +2750,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW", "PerPkg": "1", @@ -2481,6 +2760,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -2490,6 +2770,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -2499,6 +2780,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW", "PerPkg": "1", @@ -2508,6 +2790,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -2517,6 +2800,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -2526,6 +2810,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW", "PerPkg": "1", @@ -2535,6 +2820,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -2544,6 +2830,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -2553,6 +2840,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW", "PerPkg": "1", @@ -2562,6 +2850,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -2571,6 +2860,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -2580,6 +2870,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -2589,6 +2880,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -2598,6 +2890,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -2607,6 +2900,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -2616,6 +2910,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -2625,6 +2920,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -2634,6 +2930,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -2643,6 +2940,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", @@ -2652,6 +2950,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2661,6 +2960,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_H_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2670,6 +2970,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2679,6 +2980,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_H_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2688,6 +2990,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2697,6 +3000,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_H_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2706,6 +3010,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2715,6 +3020,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_H_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2724,6 +3030,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Local Requests= ", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.LOCAL", "PerPkg": "1", @@ -2733,6 +3040,7 @@ }, { "BriefDescription": "Data beat the Snoop Responses; Remote Request= s", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_H_SNOOPS_RSP_AFTER_DATA.REMOTE", "PerPkg": "1", @@ -2742,6 +3050,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.ALL", "PerPkg": "1", @@ -2751,6 +3060,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Local Request= s", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -2760,6 +3070,7 @@ }, { "BriefDescription": "Cycles with Snoops Outstanding; Remote Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_H_SNOOP_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -2769,6 +3080,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Local= Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -2778,6 +3090,7 @@ }, { "BriefDescription": "Tracker Snoops Outstanding Accumulator; Remot= e Requests", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_H_SNOOP_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -2787,6 +3100,7 @@ }, { "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", @@ -2796,6 +3110,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -2805,6 +3120,7 @@ }, { "BriefDescription": "M line forwarded from remote cache with no wr= iteback to memory", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -2815,6 +3131,7 @@ }, { "BriefDescription": "Shared line response from remote cache", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPS", "PerPkg": "1", @@ -2825,6 +3142,7 @@ }, { "BriefDescription": "Shared line forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -2835,6 +3153,7 @@ }, { "BriefDescription": "M line forwarded from remote cache along with= writeback to memory", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -2845,6 +3164,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", "PerPkg": "1", @@ -2854,6 +3174,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", "PerPkg": "1", @@ -2863,6 +3184,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", "PerPkg": "1", @@ -2872,6 +3194,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", "PerPkg": "1", @@ -2881,6 +3204,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", "PerPkg": "1", @@ -2890,6 +3214,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", "PerPkg": "1", @@ -2899,6 +3224,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", @@ -2908,6 +3234,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", "PerPkg": "1", @@ -2917,6 +3244,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", "PerPkg": "1", @@ -2926,6 +3254,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -2935,6 +3264,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -2944,6 +3274,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -2953,6 +3284,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_H_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -2962,6 +3294,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", "PerPkg": "1", @@ -2971,6 +3304,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", "PerPkg": "1", @@ -2980,6 +3314,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", "PerPkg": "1", @@ -2989,6 +3324,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", "PerPkg": "1", @@ -2998,6 +3334,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", "PerPkg": "1", @@ -3007,6 +3344,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", "PerPkg": "1", @@ -3016,6 +3354,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", "PerPkg": "1", @@ -3025,6 +3364,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", "PerPkg": "1", @@ -3034,6 +3374,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", "PerPkg": "1", @@ -3043,6 +3384,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", "PerPkg": "1", @@ -3052,6 +3394,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", "PerPkg": "1", @@ -3061,6 +3404,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", "PerPkg": "1", @@ -3070,6 +3414,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles Completely Used", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3079,6 +3424,7 @@ }, { "BriefDescription": "Tracker Cycles Full; Cycles GP Completely Use= d", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_H_TRACKER_CYCLES_FULL.GP", "PerPkg": "1", @@ -3088,6 +3434,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.ALL", "PerPkg": "1", @@ -3097,6 +3444,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -3106,6 +3454,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty; Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -3115,6 +3464,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local InvItoE = Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_LOCAL", "PerPkg": "1", @@ -3124,6 +3474,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote InvItoE= Requests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.INVITOE_REMOTE", "PerPkg": "1", @@ -3133,6 +3484,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Read Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -3142,6 +3494,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Read Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -3151,6 +3504,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Local Write Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -3160,6 +3514,7 @@ }, { "BriefDescription": "Tracker Occupancy Accumulator; Remote Write R= equests", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_H_TRACKER_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -3169,6 +3524,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Local Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -3178,6 +3534,7 @@ }, { "BriefDescription": "Data Pending Occupancy Accumulator; Remote Re= quests", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_H_TRACKER_PENDING_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -3187,6 +3544,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_H_TxR_AD.HOM", "PerPkg": "1", @@ -3196,6 +3554,7 @@ }, { "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3205,6 +3564,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3214,6 +3574,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3223,6 +3584,7 @@ }, { "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", "PerPkg": "1", @@ -3232,6 +3594,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3241,6 +3604,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3250,6 +3614,7 @@ }, { "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.ALL", "PerPkg": "1", @@ -3259,6 +3624,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", "PerPkg": "1", @@ -3268,6 +3634,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", "PerPkg": "1", @@ -3277,6 +3644,7 @@ }, { "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3286,6 +3654,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3295,6 +3664,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3304,6 +3674,7 @@ }, { "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", "PerPkg": "1", @@ -3313,6 +3684,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3322,6 +3694,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3331,6 +3704,7 @@ }, { "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.ALL", "PerPkg": "1", @@ -3340,6 +3714,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", "PerPkg": "1", @@ -3349,6 +3724,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", "PerPkg": "1", @@ -3358,6 +3734,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CACHE", "PerPkg": "1", @@ -3367,6 +3744,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CORE", "PerPkg": "1", @@ -3376,6 +3754,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_QPI", "PerPkg": "1", @@ -3385,6 +3764,7 @@ }, { "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", "PerPkg": "1", @@ -3394,6 +3774,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -3403,6 +3784,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -3412,6 +3794,7 @@ }, { "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", "PerPkg": "1", @@ -3421,6 +3804,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -3430,6 +3814,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -3439,6 +3824,7 @@ }, { "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.ALL", "PerPkg": "1", @@ -3448,6 +3834,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", "PerPkg": "1", @@ -3457,6 +3844,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", "PerPkg": "1", @@ -3466,6 +3854,7 @@ }, { "BriefDescription": "Injection Starvation; For AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.AK", "PerPkg": "1", @@ -3475,6 +3864,7 @@ }, { "BriefDescription": "Injection Starvation; For BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_H_TxR_STARVED.BL", "PerPkg": "1", @@ -3484,6 +3874,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -3493,6 +3884,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -3502,6 +3894,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -3511,6 +3904,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -3520,6 +3914,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -3529,6 +3924,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -3538,6 +3934,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -3547,6 +3944,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.js= on b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json index bef1f5ef6f31..121de411d312 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of non data (control) flits transmitte= d . Derived from unc_q_txl_flits_g0.non_data", + "Counter": "0,1,2,3", "EventName": "QPI_CTL_BANDWIDTH_TX", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of data flits transmitted . Derived fr= om unc_q_txl_flits_g0.data", + "Counter": "0,1,2,3", "EventName": "QPI_DATA_BANDWIDTH_TX", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Number of clocks in the IRP.", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", "PerPkg": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.CRD", "PerPkg": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.DRD", "PerPkg": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", "PerPkg": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", "PerPkg": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Coherent Ops; PCIItoM", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Coherent Ops; RFO", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", "PerPkg": "1", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", "PerPkg": "1", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", "PerPkg": "1", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REJ", "PerPkg": "1", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_REQ", "PerPkg": "1", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.FAST_XFER", "PerPkg": "1", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_ACK_HINT", "PerPkg": "1", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Misc Events - Set 0; Prefetch TimeOut", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_MISC0.PF_TIMEOUT", "PerPkg": "1", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Data Throttled", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.DATA_THROTTLE", "PerPkg": "1", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Misc Events - Set 1", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", "PerPkg": "1", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", "PerPkg": "1", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_E", "PerPkg": "1", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_I", "PerPkg": "1", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_M", "PerPkg": "1", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_MISC1.SLOW_S", "PerPkg": "1", @@ -260,6 +289,7 @@ }, { "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", @@ -268,6 +298,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -276,6 +307,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", @@ -284,6 +316,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_DRS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -292,6 +325,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -300,6 +334,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", @@ -308,6 +343,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCB_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -316,6 +352,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_CYCLES_FULL", + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -324,6 +361,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", @@ -332,6 +370,7 @@ }, { "BriefDescription": "UNC_I_RxR_BL_NCS_OCCUPANCY", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", "PerPkg": "1", @@ -349,6 +389,7 @@ }, { "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_I", "PerPkg": "1", @@ -358,6 +399,7 @@ }, { "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.HIT_M", "PerPkg": "1", @@ -367,6 +409,7 @@ }, { "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.MISS", "PerPkg": "1", @@ -376,6 +419,7 @@ }, { "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", "PerPkg": "1", @@ -385,6 +429,7 @@ }, { "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", "PerPkg": "1", @@ -394,6 +439,7 @@ }, { "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_SNOOP_RESP.SNPINV", "PerPkg": "1", @@ -403,6 +449,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", "PerPkg": "1", @@ -412,6 +459,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.OTHER", "PerPkg": "1", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.RD_PREF", "PerPkg": "1", @@ -430,6 +479,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", @@ -439,6 +489,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -448,6 +499,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Write Prefetches", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -457,6 +509,7 @@ }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -465,6 +518,7 @@ }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -473,6 +527,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", "PerPkg": "1", @@ -481,6 +536,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", "PerPkg": "1", @@ -489,6 +545,7 @@ }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", @@ -497,6 +554,7 @@ }, { "BriefDescription": "Number of qfclks", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", @@ -505,6 +563,7 @@ }, { "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", @@ -513,6 +572,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", @@ -522,6 +582,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", "PerPkg": "1", @@ -531,6 +592,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", @@ -540,6 +602,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss, Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", "PerPkg": "1", @@ -549,6 +612,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", "PerPkg": "1", @@ -558,6 +622,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT I= nvalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", "PerPkg": "1", @@ -567,6 +632,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss and Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", "PerPkg": "1", @@ -576,6 +642,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", "PerPkg": "1", @@ -585,6 +652,7 @@ }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", @@ -593,6 +661,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -601,6 +670,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", @@ -609,6 +679,7 @@ }, { "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", @@ -617,6 +688,7 @@ }, { "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", "PerPkg": "1", @@ -626,6 +698,7 @@ }, { "BriefDescription": "CRC Errors Detected; Normal Operations", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", "PerPkg": "1", @@ -635,6 +708,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", "PerPkg": "1", @@ -644,6 +718,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", "PerPkg": "1", @@ -653,6 +728,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", "PerPkg": "1", @@ -662,6 +738,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", "PerPkg": "1", @@ -671,6 +748,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", "PerPkg": "1", @@ -680,6 +758,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", "PerPkg": "1", @@ -689,6 +768,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", "PerPkg": "1", @@ -698,6 +778,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", "PerPkg": "1", @@ -707,6 +788,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", "PerPkg": "1", @@ -716,6 +798,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", "PerPkg": "1", @@ -725,6 +808,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", "PerPkg": "1", @@ -734,6 +818,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", "PerPkg": "1", @@ -743,6 +828,7 @@ }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", @@ -751,6 +837,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", @@ -759,6 +846,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", "PerPkg": "1", @@ -768,6 +856,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", "PerPkg": "1", @@ -777,6 +866,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", "PerPkg": "1", @@ -786,6 +876,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", "PerPkg": "1", @@ -795,6 +886,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", "PerPkg": "1", @@ -804,6 +896,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", "PerPkg": "1", @@ -813,6 +906,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", "PerPkg": "1", @@ -822,6 +916,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", "PerPkg": "1", @@ -831,6 +926,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", "PerPkg": "1", @@ -840,6 +936,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", "PerPkg": "1", @@ -849,6 +946,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", "PerPkg": "1", @@ -858,6 +956,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", "PerPkg": "1", @@ -867,6 +966,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", @@ -876,6 +976,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", @@ -885,6 +986,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", @@ -894,6 +996,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", @@ -903,6 +1006,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", @@ -912,6 +1016,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", @@ -921,6 +1026,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", @@ -930,6 +1036,7 @@ }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", @@ -939,6 +1046,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", @@ -948,6 +1056,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -957,6 +1066,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -966,6 +1076,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", @@ -975,6 +1086,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -984,6 +1096,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -993,6 +1106,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", @@ -1001,6 +1115,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", "PerPkg": "1", @@ -1010,6 +1125,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", "PerPkg": "1", @@ -1019,6 +1135,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", "PerPkg": "1", @@ -1028,6 +1145,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", "PerPkg": "1", @@ -1037,6 +1155,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", "PerPkg": "1", @@ -1046,6 +1165,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", "PerPkg": "1", @@ -1055,6 +1175,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", "PerPkg": "1", @@ -1064,6 +1185,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", "PerPkg": "1", @@ -1073,6 +1195,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", "PerPkg": "1", @@ -1082,6 +1205,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", "PerPkg": "1", @@ -1091,6 +1215,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", "PerPkg": "1", @@ -1100,6 +1225,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", "PerPkg": "1", @@ -1109,6 +1235,7 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", @@ -1117,6 +1244,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", "PerPkg": "1", @@ -1126,6 +1254,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", "PerPkg": "1", @@ -1135,6 +1264,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", "PerPkg": "1", @@ -1144,6 +1274,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", "PerPkg": "1", @@ -1153,6 +1284,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", "PerPkg": "1", @@ -1162,6 +1294,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", "PerPkg": "1", @@ -1171,6 +1304,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", "PerPkg": "1", @@ -1180,6 +1314,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", "PerPkg": "1", @@ -1189,6 +1324,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", "PerPkg": "1", @@ -1198,6 +1334,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", "PerPkg": "1", @@ -1207,6 +1344,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", "PerPkg": "1", @@ -1216,6 +1354,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", "PerPkg": "1", @@ -1225,6 +1364,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", "PerPkg": "1", @@ -1234,6 +1374,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", "PerPkg": "1", @@ -1243,6 +1384,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", "PerPkg": "1", @@ -1252,6 +1394,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", "PerPkg": "1", @@ -1261,6 +1404,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", "PerPkg": "1", @@ -1270,6 +1414,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", "PerPkg": "1", @@ -1279,6 +1424,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", "PerPkg": "1", @@ -1288,6 +1434,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.GV", "PerPkg": "1", @@ -1297,6 +1444,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", "PerPkg": "1", @@ -1306,6 +1454,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", "PerPkg": "1", @@ -1315,6 +1464,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", "PerPkg": "1", @@ -1324,6 +1474,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", "PerPkg": "1", @@ -1333,6 +1484,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", "PerPkg": "1", @@ -1342,6 +1494,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", "PerPkg": "1", @@ -1351,6 +1504,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -1359,6 +1513,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", @@ -1367,6 +1522,7 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", @@ -1375,6 +1531,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", "PerPkg": "1", @@ -1384,6 +1541,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", "PerPkg": "1", @@ -1393,6 +1551,7 @@ }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", @@ -1401,6 +1560,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", @@ -1409,6 +1569,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", @@ -1417,6 +1578,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency.", @@ -1425,6 +1587,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of data flits transmitted over QPI on the DR= S (Data Response) channel. DRS flits are used to transmit data with cohere= ncy. This does not count data flits transmitted over the NCB channel which= transmits non-coherent data. This includes only the data flits (not the h= eader).", @@ -1433,6 +1596,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of protocol flits transmitted over QPI on th= e DRS (Data Response) channel. DRS flits are used to transmit data with co= herency. This does not count data flits transmitted over the NCB channel w= hich transmits non-coherent data. This includes only the header flits (not= the data). This includes extended headers.", @@ -1441,6 +1605,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of flits transmitted over QPI on the home channel.= ", @@ -1449,6 +1614,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of non-request flits transmitted over QPI on the h= ome channel. These are most commonly snoop responses, and this event can b= e used as a proxy for that.", @@ -1457,6 +1623,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of data request transmitted over QPI on the home c= hannel. This basically counts the number of remote memory requests transmi= tted over QPI. In conjunction with the local read count in the Home Agent,= one can calculate the number of LLC Misses.", @@ -1465,6 +1632,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of snoop request flits transmitted over QPI. Thes= e requests are contained in the snoop channel. This does not include snoop= responses, which are transmitted on the home channel.", @@ -1473,6 +1641,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", @@ -1482,6 +1651,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -1491,6 +1661,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -1500,6 +1671,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", @@ -1509,6 +1681,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -1518,6 +1691,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -1527,6 +1701,7 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", @@ -1535,6 +1710,7 @@ }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", @@ -1543,6 +1719,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1552,6 +1729,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1561,6 +1739,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1570,6 +1749,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1579,6 +1759,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1588,6 +1769,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1597,6 +1779,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1606,6 +1789,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1615,6 +1799,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1624,6 +1809,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1633,6 +1819,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1642,6 +1829,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1651,6 +1839,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", "PerPkg": "1", @@ -1659,6 +1848,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", "PerPkg": "1", @@ -1667,6 +1857,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1676,6 +1867,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1685,6 +1877,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shar= ed VN", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", "PerPkg": "1", @@ -1694,6 +1887,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1703,6 +1897,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1712,6 +1907,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for S= hared VN", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", "PerPkg": "1", @@ -1721,6 +1917,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1730,6 +1927,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1739,6 +1937,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1748,6 +1947,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1757,6 +1957,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1766,6 +1967,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1775,6 +1977,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1784,6 +1987,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1793,6 +1997,7 @@ }, { "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", @@ -1801,6 +2006,7 @@ }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", @@ -1809,6 +2015,7 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_R3_CLOCKTICKS", "PerPkg": "1", @@ -1817,6 +2024,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", "PerPkg": "1", @@ -1826,6 +2034,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", "PerPkg": "1", @@ -1835,6 +2044,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", "PerPkg": "1", @@ -1844,6 +2054,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", "PerPkg": "1", @@ -1853,6 +2064,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14_16", "PerPkg": "1", @@ -1862,6 +2074,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", "PerPkg": "1", @@ -1871,6 +2084,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", "PerPkg": "1", @@ -1880,6 +2094,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO_15_17", "PerPkg": "1", @@ -1889,6 +2104,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", "PerPkg": "1", @@ -1898,6 +2114,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", "PerPkg": "1", @@ -1907,6 +2124,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", "PerPkg": "1", @@ -1916,6 +2134,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", "PerPkg": "1", @@ -1925,6 +2144,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", "PerPkg": "1", @@ -1934,6 +2154,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", "PerPkg": "1", @@ -1943,6 +2164,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", "PerPkg": "1", @@ -1952,6 +2174,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", "PerPkg": "1", @@ -1961,6 +2184,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", "PerPkg": "1", @@ -1970,6 +2194,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", "PerPkg": "1", @@ -1979,6 +2204,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", "PerPkg": "1", @@ -1988,6 +2214,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", "PerPkg": "1", @@ -1997,6 +2224,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.HUB", "PerPkg": "1", @@ -2005,6 +2233,7 @@ }, { "BriefDescription": "IOT Backpressure", + "Counter": "0,1,2", "EventCode": "0xB", "EventName": "UNC_R3_IOT_BACKPRESSURE.SAT", "PerPkg": "1", @@ -2013,6 +2242,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0xD", "EventName": "UNC_R3_IOT_CTS_HI.CTS2", "PerPkg": "1", @@ -2022,6 +2252,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Hi", + "Counter": "0,1,2", "EventCode": "0xD", "EventName": "UNC_R3_IOT_CTS_HI.CTS3", "PerPkg": "1", @@ -2031,6 +2262,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0xC", "EventName": "UNC_R3_IOT_CTS_LO.CTS0", "PerPkg": "1", @@ -2040,6 +2272,7 @@ }, { "BriefDescription": "IOT Common Trigger Sequencer - Lo", + "Counter": "0,1,2", "EventCode": "0xC", "EventName": "UNC_R3_IOT_CTS_LO.CTS1", "PerPkg": "1", @@ -2049,6 +2282,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2058,6 +2292,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2067,6 +2302,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2076,6 +2312,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2085,6 +2322,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2094,6 +2332,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2103,6 +2342,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2112,6 +2352,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2121,6 +2362,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2130,6 +2372,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2139,6 +2382,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2148,6 +2392,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2157,6 +2402,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2166,6 +2412,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2175,6 +2422,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2184,6 +2432,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2193,6 +2442,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2202,6 +2452,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2211,6 +2462,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2220,6 +2472,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2229,6 +2482,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2238,6 +2492,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2F", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2247,6 +2502,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW", "PerPkg": "1", @@ -2256,6 +2512,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -2265,6 +2522,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -2274,6 +2532,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW", "PerPkg": "1", @@ -2283,6 +2542,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -2292,6 +2552,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -2301,6 +2562,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW", "PerPkg": "1", @@ -2310,6 +2572,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -2319,6 +2582,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -2328,6 +2592,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW", "PerPkg": "1", @@ -2337,6 +2602,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -2346,6 +2612,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -2355,6 +2622,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW", "PerPkg": "1", @@ -2364,6 +2632,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -2373,6 +2642,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -2382,6 +2652,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW", "PerPkg": "1", @@ -2391,6 +2662,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -2400,6 +2672,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -2409,6 +2682,7 @@ }, { "BriefDescription": "R3 IV Ring in Use; Any", + "Counter": "0,1,2", "EventCode": "0xA", "EventName": "UNC_R3_RING_IV_USED.ANY", "PerPkg": "1", @@ -2418,6 +2692,7 @@ }, { "BriefDescription": "R3 IV Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0xA", "EventName": "UNC_R3_RING_IV_USED.CW", "PerPkg": "1", @@ -2427,6 +2702,7 @@ }, { "BriefDescription": "Ring Stop Starved; AK", + "Counter": "0,1,2", "EventCode": "0xE", "EventName": "UNC_R3_RING_SINK_STARVED.AK", "PerPkg": "1", @@ -2436,6 +2712,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", "PerPkg": "1", @@ -2445,6 +2722,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", "PerPkg": "1", @@ -2454,6 +2732,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", "PerPkg": "1", @@ -2463,6 +2742,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; DRS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.DRS", "PerPkg": "1", @@ -2472,6 +2752,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.HOM", "PerPkg": "1", @@ -2481,6 +2762,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCB", "PerPkg": "1", @@ -2490,6 +2772,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NCS", "PerPkg": "1", @@ -2499,6 +2782,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.NDR", "PerPkg": "1", @@ -2508,6 +2792,7 @@ }, { "BriefDescription": "VN1 Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_R3_RxR_CYCLES_NE_VN1.SNP", "PerPkg": "1", @@ -2517,6 +2802,7 @@ }, { "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.DRS", "PerPkg": "1", @@ -2526,6 +2812,7 @@ }, { "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.HOM", "PerPkg": "1", @@ -2535,6 +2822,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCB", "PerPkg": "1", @@ -2544,6 +2832,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCS", "PerPkg": "1", @@ -2553,6 +2842,7 @@ }, { "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NDR", "PerPkg": "1", @@ -2562,6 +2852,7 @@ }, { "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.SNP", "PerPkg": "1", @@ -2571,6 +2862,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.DRS", "PerPkg": "1", @@ -2580,6 +2872,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.HOM", "PerPkg": "1", @@ -2589,6 +2882,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NCB", "PerPkg": "1", @@ -2598,6 +2892,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NCS", "PerPkg": "1", @@ -2607,6 +2902,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.NDR", "PerPkg": "1", @@ -2616,6 +2912,7 @@ }, { "BriefDescription": "VN1 Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_R3_RxR_INSERTS_VN1.SNP", "PerPkg": "1", @@ -2625,6 +2922,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.DRS", "PerPkg": "1", @@ -2634,6 +2932,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; HOM", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.HOM", "PerPkg": "1", @@ -2643,6 +2942,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCB", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCB", "PerPkg": "1", @@ -2652,6 +2952,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NCS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NCS", "PerPkg": "1", @@ -2661,6 +2962,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; NDR", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.NDR", "PerPkg": "1", @@ -2670,6 +2972,7 @@ }, { "BriefDescription": "VN1 Ingress Occupancy Accumulator; SNP", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY_VN1.SNP", "PerPkg": "1", @@ -2679,6 +2982,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2688,6 +2992,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2697,6 +3002,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2706,6 +3012,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R3_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2715,6 +3022,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -2724,6 +3032,7 @@ }, { "BriefDescription": "SBo1 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_SBO1_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -2733,6 +3042,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2B", "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -2742,6 +3052,7 @@ }, { "BriefDescription": "SBo1 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2B", "EventName": "UNC_R3_SBO1_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -2751,6 +3062,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -2760,6 +3072,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -2769,6 +3082,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -2778,6 +3092,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R3_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -2787,6 +3102,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_AD", "PerPkg": "1", @@ -2796,6 +3112,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_AK", "PerPkg": "1", @@ -2805,6 +3122,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.DN_BL", "PerPkg": "1", @@ -2814,6 +3132,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_AD", "PerPkg": "1", @@ -2823,6 +3142,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_AK", "PerPkg": "1", @@ -2832,6 +3152,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK.UP_BL", "PerPkg": "1", @@ -2841,6 +3162,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2850,6 +3172,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2859,6 +3182,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -2868,6 +3192,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -2877,6 +3202,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -2886,6 +3212,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -2895,6 +3222,7 @@ }, { "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", @@ -2904,6 +3232,7 @@ }, { "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", @@ -2913,6 +3242,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", @@ -2922,6 +3252,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", "PerPkg": "1", @@ -2931,6 +3262,7 @@ }, { "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", "PerPkg": "1", @@ -2940,6 +3272,7 @@ }, { "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", "PerPkg": "1", @@ -2949,6 +3282,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2958,6 +3292,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2967,6 +3302,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -2976,6 +3312,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -2985,6 +3322,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -2994,6 +3332,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -3003,6 +3342,7 @@ }, { "BriefDescription": "VN1 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", "PerPkg": "1", @@ -3012,6 +3352,7 @@ }, { "BriefDescription": "VN1 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", "PerPkg": "1", @@ -3021,6 +3362,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", "PerPkg": "1", @@ -3030,6 +3372,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", "PerPkg": "1", @@ -3039,6 +3382,7 @@ }, { "BriefDescription": "VN1 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", "PerPkg": "1", @@ -3048,6 +3392,7 @@ }, { "BriefDescription": "VN1 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", "PerPkg": "1", @@ -3057,6 +3402,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -3066,6 +3412,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -3075,6 +3422,7 @@ }, { "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -3084,6 +3432,7 @@ }, { "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -3093,6 +3442,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -3102,6 +3452,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -3111,6 +3462,7 @@ }, { "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -3120,6 +3472,7 @@ }, { "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -3129,6 +3482,7 @@ }, { "BriefDescription": "Bounce Control", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_S_BOUNCE_CONTROL", "PerPkg": "1", @@ -3136,12 +3490,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_S_CLOCKTICKS", "PerPkg": "1", "Unit": "SBOX" }, { "BriefDescription": "FaST wire asserted", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_S_FAST_ASSERTED", "PerPkg": "1", @@ -3150,6 +3506,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN", "PerPkg": "1", @@ -3159,6 +3516,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -3168,6 +3526,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -3177,6 +3536,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP", "PerPkg": "1", @@ -3186,6 +3546,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -3195,6 +3556,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_S_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -3204,6 +3566,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN", "PerPkg": "1", @@ -3213,6 +3576,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -3222,6 +3586,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -3231,6 +3596,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP", "PerPkg": "1", @@ -3240,6 +3606,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -3249,6 +3616,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_S_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -3258,6 +3626,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN", "PerPkg": "1", @@ -3267,6 +3636,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Event", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -3276,6 +3646,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -3285,6 +3656,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP", "PerPkg": "1", @@ -3294,6 +3666,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -3303,6 +3676,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_S_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -3312,6 +3686,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AD_CACHE", "PerPkg": "1", @@ -3320,6 +3695,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.AK_CORE", "PerPkg": "1", @@ -3328,6 +3704,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.BL_CORE", "PerPkg": "1", @@ -3336,6 +3713,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_S_RING_BOUNCES.IV_CORE", "PerPkg": "1", @@ -3344,6 +3722,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_S_RING_IV_USED.DN", "PerPkg": "1", @@ -3353,6 +3732,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_S_RING_IV_USED.UP", "PerPkg": "1", @@ -3362,6 +3742,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.AD_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", @@ -3370,6 +3751,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.AK_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", @@ -3378,6 +3760,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.BL_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", @@ -3386,6 +3769,7 @@ }, { "BriefDescription": "UNC_S_RING_SINK_STARVED.IV_CORE", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_S_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", @@ -3394,6 +3778,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.AD_BNC", "PerPkg": "1", @@ -3403,6 +3788,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.AD_CRD", "PerPkg": "1", @@ -3412,6 +3798,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.BL_BNC", "PerPkg": "1", @@ -3421,6 +3808,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_S_RxR_BUSY_STARVED.BL_CRD", "PerPkg": "1", @@ -3430,6 +3818,7 @@ }, { "BriefDescription": "Bypass; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AD_BNC", "PerPkg": "1", @@ -3439,6 +3828,7 @@ }, { "BriefDescription": "Bypass; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AD_CRD", "PerPkg": "1", @@ -3448,6 +3838,7 @@ }, { "BriefDescription": "Bypass; AK", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.AK", "PerPkg": "1", @@ -3457,6 +3848,7 @@ }, { "BriefDescription": "Bypass; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.BL_BNC", "PerPkg": "1", @@ -3466,6 +3858,7 @@ }, { "BriefDescription": "Bypass; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.BL_CRD", "PerPkg": "1", @@ -3475,6 +3868,7 @@ }, { "BriefDescription": "Bypass; IV", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_S_RxR_BYPASS.IV", "PerPkg": "1", @@ -3484,6 +3878,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AD_BNC", "PerPkg": "1", @@ -3493,6 +3888,7 @@ }, { "BriefDescription": "Injection Starvation; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AD_CRD", "PerPkg": "1", @@ -3502,6 +3898,7 @@ }, { "BriefDescription": "Injection Starvation; AK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.AK", "PerPkg": "1", @@ -3511,6 +3908,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.BL_BNC", "PerPkg": "1", @@ -3520,6 +3918,7 @@ }, { "BriefDescription": "Injection Starvation; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.BL_CRD", "PerPkg": "1", @@ -3529,6 +3928,7 @@ }, { "BriefDescription": "Injection Starvation; IVF Credit", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.IFV", "PerPkg": "1", @@ -3538,6 +3938,7 @@ }, { "BriefDescription": "Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_S_RxR_CRD_STARVED.IV", "PerPkg": "1", @@ -3547,6 +3948,7 @@ }, { "BriefDescription": "Ingress Allocations; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AD_BNC", "PerPkg": "1", @@ -3556,6 +3958,7 @@ }, { "BriefDescription": "Ingress Allocations; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AD_CRD", "PerPkg": "1", @@ -3565,6 +3968,7 @@ }, { "BriefDescription": "Ingress Allocations; AK", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.AK", "PerPkg": "1", @@ -3574,6 +3978,7 @@ }, { "BriefDescription": "Ingress Allocations; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.BL_BNC", "PerPkg": "1", @@ -3583,6 +3988,7 @@ }, { "BriefDescription": "Ingress Allocations; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.BL_CRD", "PerPkg": "1", @@ -3592,6 +3998,7 @@ }, { "BriefDescription": "Ingress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_S_RxR_INSERTS.IV", "PerPkg": "1", @@ -3601,6 +4008,7 @@ }, { "BriefDescription": "Ingress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AD_BNC", "PerPkg": "1", @@ -3610,6 +4018,7 @@ }, { "BriefDescription": "Ingress Occupancy; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AD_CRD", "PerPkg": "1", @@ -3619,6 +4028,7 @@ }, { "BriefDescription": "Ingress Occupancy; AK", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.AK", "PerPkg": "1", @@ -3628,6 +4038,7 @@ }, { "BriefDescription": "Ingress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.BL_BNC", "PerPkg": "1", @@ -3637,6 +4048,7 @@ }, { "BriefDescription": "Ingress Occupancy; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.BL_CRD", "PerPkg": "1", @@ -3646,6 +4058,7 @@ }, { "BriefDescription": "Ingress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_S_RxR_OCCUPANCY.IV", "PerPkg": "1", @@ -3655,6 +4068,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.AD", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.AD", "PerPkg": "1", @@ -3663,6 +4077,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.AK", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.AK", "PerPkg": "1", @@ -3671,6 +4086,7 @@ }, { "BriefDescription": "UNC_S_TxR_ADS_USED.BL", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_S_TxR_ADS_USED.BL", "PerPkg": "1", @@ -3679,6 +4095,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AD_BNC", "PerPkg": "1", @@ -3688,6 +4105,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AD_CRD", "PerPkg": "1", @@ -3697,6 +4115,7 @@ }, { "BriefDescription": "Egress Allocations; AK", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.AK", "PerPkg": "1", @@ -3706,6 +4125,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.BL_BNC", "PerPkg": "1", @@ -3715,6 +4135,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.BL_CRD", "PerPkg": "1", @@ -3724,6 +4145,7 @@ }, { "BriefDescription": "Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_S_TxR_INSERTS.IV", "PerPkg": "1", @@ -3733,6 +4155,7 @@ }, { "BriefDescription": "Egress Occupancy; AD - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AD_BNC", "PerPkg": "1", @@ -3742,6 +4165,7 @@ }, { "BriefDescription": "Egress Occupancy; AD - Credits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AD_CRD", "PerPkg": "1", @@ -3751,6 +4175,7 @@ }, { "BriefDescription": "Egress Occupancy; AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.AK", "PerPkg": "1", @@ -3760,6 +4185,7 @@ }, { "BriefDescription": "Egress Occupancy; BL - Bounces", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.BL_BNC", "PerPkg": "1", @@ -3769,6 +4195,7 @@ }, { "BriefDescription": "Egress Occupancy; BL - Credits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.BL_CRD", "PerPkg": "1", @@ -3778,6 +4205,7 @@ }, { "BriefDescription": "Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_S_TxR_OCCUPANCY.IV", "PerPkg": "1", @@ -3787,6 +4215,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.AD", "PerPkg": "1", @@ -3796,6 +4225,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.AK", "PerPkg": "1", @@ -3805,6 +4235,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.BL", "PerPkg": "1", @@ -3814,6 +4245,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_S_TxR_STARVED.IV", "PerPkg": "1", @@ -3823,12 +4255,14 @@ }, { "BriefDescription": "UNC_U_CLOCKTICKS", + "Counter": "0,1", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", "Unit": "UBOX" }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", @@ -3838,6 +4272,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", @@ -3847,6 +4282,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", @@ -3856,6 +4292,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", @@ -3865,6 +4302,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", @@ -3874,6 +4312,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", @@ -3883,6 +4322,7 @@ }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", @@ -3891,6 +4331,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", @@ -3900,6 +4341,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", @@ -3909,6 +4351,7 @@ }, { "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", @@ -3918,6 +4361,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", @@ -3927,6 +4371,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", @@ -3936,6 +4381,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", @@ -3945,6 +4391,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", @@ -3954,6 +4401,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json b/tools= /perf/pmu-events/arch/x86/haswellx/uncore-io.json index bd64a8a1625f..84d1d601ea95 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_R2_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI0", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.ISOCH_QPI1", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI0", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI0", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "UNC_R2_IIO_CREDIT.PRQ_QPI1", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_R2_IIO_CREDIT.PRQ_QPI1", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -50,6 +56,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -59,6 +66,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -68,6 +76,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -77,6 +86,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -86,6 +96,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -95,6 +106,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW", "PerPkg": "1", @@ -104,6 +116,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -113,6 +126,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -122,6 +136,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW", "PerPkg": "1", @@ -131,6 +146,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -140,6 +156,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -149,6 +166,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Dn", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.DN", "PerPkg": "1", @@ -158,6 +176,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Up", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_R2_RING_AK_BOUNCES.UP", "PerPkg": "1", @@ -167,6 +186,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW", "PerPkg": "1", @@ -176,6 +196,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -185,6 +206,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -194,6 +216,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW", "PerPkg": "1", @@ -203,6 +226,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -212,6 +236,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -221,6 +246,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW", "PerPkg": "1", @@ -230,6 +256,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -239,6 +266,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -248,6 +276,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW", "PerPkg": "1", @@ -257,6 +286,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -266,6 +296,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -275,6 +306,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.ANY", "PerPkg": "1", @@ -284,6 +316,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CCW", "PerPkg": "1", @@ -293,6 +326,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.CW", "PerPkg": "1", @@ -302,6 +336,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -311,6 +346,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -320,6 +356,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCB", "PerPkg": "1", @@ -329,6 +366,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCS", "PerPkg": "1", @@ -338,6 +376,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -347,6 +386,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For AD Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -356,6 +396,7 @@ }, { "BriefDescription": "SBo0 Credits Acquired; For BL Ring", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_SBO0_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -365,6 +406,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For AD Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.AD", "PerPkg": "1", @@ -374,6 +416,7 @@ }, { "BriefDescription": "SBo0 Credits Occupancy; For BL Ring", + "Counter": "0", "EventCode": "0x2A", "EventName": "UNC_R2_SBO0_CREDIT_OCCUPANCY.BL", "PerPkg": "1", @@ -383,6 +426,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_AD", "PerPkg": "1", @@ -392,6 +436,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo0, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO0_BL", "PerPkg": "1", @@ -401,6 +446,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, AD Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_AD", "PerPkg": "1", @@ -410,6 +456,7 @@ }, { "BriefDescription": "Stall on No Sbo Credits; For SBo1, BL Ring", + "Counter": "0,1", "EventCode": "0x2C", "EventName": "UNC_R2_STALL_NO_SBO_CREDIT.SBO1_BL", "PerPkg": "1", @@ -419,6 +466,7 @@ }, { "BriefDescription": "Egress Cycles Full; AD", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", "PerPkg": "1", @@ -428,6 +476,7 @@ }, { "BriefDescription": "Egress Cycles Full; AK", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", "PerPkg": "1", @@ -437,6 +486,7 @@ }, { "BriefDescription": "Egress Cycles Full; BL", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", "PerPkg": "1", @@ -446,6 +496,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AD", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AD", "PerPkg": "1", @@ -455,6 +506,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AK", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AK", "PerPkg": "1", @@ -464,6 +516,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; BL", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.BL", "PerPkg": "1", @@ -473,6 +526,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AD", "PerPkg": "1", @@ -482,6 +536,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_AK", "PerPkg": "1", @@ -491,6 +546,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.DN_BL", "PerPkg": "1", @@ -500,6 +556,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AD", "PerPkg": "1", @@ -509,6 +566,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_AK", "PerPkg": "1", @@ -518,6 +576,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.UP_BL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json index c005f5115722..9ef5eeba3ef4 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,6 +23,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", @@ -30,6 +33,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", @@ -39,6 +43,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -48,6 +53,7 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", @@ -56,6 +62,7 @@ }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", @@ -72,6 +80,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -81,6 +90,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -90,6 +100,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -99,6 +110,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -151,18 +168,21 @@ }, { "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_DCLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -180,6 +201,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -189,6 +211,7 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", @@ -197,6 +220,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", @@ -206,6 +230,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", @@ -224,6 +250,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", @@ -233,6 +260,7 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", @@ -241,6 +269,7 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "PerPkg": "1", @@ -249,6 +278,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", @@ -258,6 +288,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", @@ -267,6 +298,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", @@ -276,6 +308,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", @@ -285,6 +318,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", @@ -294,6 +328,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", @@ -303,6 +338,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", @@ -312,6 +348,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", @@ -321,6 +358,7 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", @@ -329,6 +367,7 @@ }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -336,6 +375,7 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "PerPkg": "1", @@ -344,6 +384,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", @@ -353,6 +394,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", @@ -362,6 +404,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", @@ -371,6 +414,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", @@ -380,6 +424,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", @@ -389,6 +434,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", @@ -398,6 +444,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", @@ -407,6 +454,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", @@ -416,6 +464,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", @@ -425,6 +474,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", @@ -434,6 +484,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", "PerPkg": "1", @@ -443,6 +494,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", @@ -452,6 +504,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -461,6 +514,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -470,6 +524,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -479,6 +534,7 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", @@ -487,6 +543,7 @@ }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", @@ -495,6 +552,7 @@ }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", @@ -503,6 +561,7 @@ }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", @@ -511,6 +570,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -520,6 +580,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", @@ -528,6 +589,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", @@ -537,6 +599,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", "PerPkg": "1", @@ -546,6 +609,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", "PerPkg": "1", @@ -555,6 +619,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", "PerPkg": "1", @@ -564,6 +629,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", "PerPkg": "1", @@ -573,6 +639,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", "PerPkg": "1", @@ -582,6 +649,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", "PerPkg": "1", @@ -591,6 +659,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", @@ -600,6 +669,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", @@ -609,6 +679,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", @@ -618,6 +689,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", @@ -627,6 +699,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", @@ -636,6 +709,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", @@ -645,6 +719,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", "PerPkg": "1", @@ -654,6 +729,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", "PerPkg": "1", @@ -663,6 +739,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -672,6 +749,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -681,6 +759,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -690,6 +769,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -699,6 +779,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -708,6 +789,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", @@ -716,6 +798,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", @@ -725,6 +808,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", "PerPkg": "1", @@ -734,6 +818,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", "PerPkg": "1", @@ -743,6 +828,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", "PerPkg": "1", @@ -752,6 +838,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", "PerPkg": "1", @@ -761,6 +848,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", "PerPkg": "1", @@ -770,6 +858,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", "PerPkg": "1", @@ -779,6 +868,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", @@ -788,6 +878,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", @@ -797,6 +888,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", @@ -806,6 +898,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", @@ -815,6 +908,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", @@ -824,6 +918,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", @@ -833,6 +928,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", "PerPkg": "1", @@ -842,6 +938,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", "PerPkg": "1", @@ -851,6 +948,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -860,6 +958,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -869,6 +968,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -878,6 +978,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -887,6 +988,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", @@ -895,6 +997,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -904,6 +1007,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", @@ -912,6 +1016,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", @@ -921,6 +1026,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", "PerPkg": "1", @@ -930,6 +1036,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", "PerPkg": "1", @@ -939,6 +1046,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", "PerPkg": "1", @@ -948,6 +1056,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", "PerPkg": "1", @@ -957,6 +1066,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", "PerPkg": "1", @@ -966,6 +1076,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", "PerPkg": "1", @@ -975,6 +1086,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", @@ -984,6 +1096,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", @@ -993,6 +1106,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", @@ -1002,6 +1116,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", @@ -1011,6 +1126,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", @@ -1020,6 +1136,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", @@ -1029,6 +1146,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", "PerPkg": "1", @@ -1038,6 +1156,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", "PerPkg": "1", @@ -1047,6 +1166,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -1056,6 +1176,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -1065,6 +1186,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -1074,6 +1196,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -1083,6 +1206,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -1092,6 +1216,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", @@ -1100,6 +1225,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", @@ -1109,6 +1235,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", "PerPkg": "1", @@ -1118,6 +1245,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", "PerPkg": "1", @@ -1127,6 +1255,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", "PerPkg": "1", @@ -1136,6 +1265,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", "PerPkg": "1", @@ -1145,6 +1275,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", "PerPkg": "1", @@ -1154,6 +1285,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", "PerPkg": "1", @@ -1163,6 +1295,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", @@ -1172,6 +1305,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", @@ -1181,6 +1315,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", @@ -1190,6 +1325,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", @@ -1199,6 +1335,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", @@ -1208,6 +1345,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", @@ -1217,6 +1355,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", "PerPkg": "1", @@ -1226,6 +1365,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", "PerPkg": "1", @@ -1235,6 +1375,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -1244,6 +1385,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -1253,6 +1395,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -1262,6 +1405,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -1271,6 +1415,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -1280,6 +1425,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", @@ -1288,6 +1434,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", @@ -1297,6 +1444,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", "PerPkg": "1", @@ -1306,6 +1454,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", "PerPkg": "1", @@ -1315,6 +1464,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", "PerPkg": "1", @@ -1324,6 +1474,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", "PerPkg": "1", @@ -1333,6 +1484,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", "PerPkg": "1", @@ -1342,6 +1494,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", "PerPkg": "1", @@ -1351,6 +1504,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", @@ -1360,6 +1514,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", @@ -1369,6 +1524,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", @@ -1378,6 +1534,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", @@ -1387,6 +1544,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", @@ -1396,6 +1554,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", @@ -1405,6 +1564,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", "PerPkg": "1", @@ -1414,6 +1574,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", "PerPkg": "1", @@ -1423,6 +1584,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -1432,6 +1594,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -1441,6 +1604,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -1450,6 +1614,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -1459,6 +1624,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -1468,6 +1634,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", @@ -1476,6 +1643,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", @@ -1485,6 +1653,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", "PerPkg": "1", @@ -1494,6 +1663,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", "PerPkg": "1", @@ -1503,6 +1673,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", "PerPkg": "1", @@ -1512,6 +1683,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", "PerPkg": "1", @@ -1521,6 +1693,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", "PerPkg": "1", @@ -1530,6 +1703,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", "PerPkg": "1", @@ -1539,6 +1713,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", @@ -1548,6 +1723,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", @@ -1557,6 +1733,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", @@ -1566,6 +1743,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", @@ -1575,6 +1753,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", @@ -1584,6 +1763,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", @@ -1593,6 +1773,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", "PerPkg": "1", @@ -1602,6 +1783,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", "PerPkg": "1", @@ -1611,6 +1793,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -1620,6 +1803,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -1629,6 +1813,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -1638,6 +1823,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", "PerPkg": "1", @@ -1647,6 +1833,7 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", @@ -1655,6 +1842,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -1663,6 +1851,7 @@ }, { "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", @@ -1670,6 +1859,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", @@ -1678,6 +1868,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", @@ -1686,6 +1877,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", @@ -1694,6 +1886,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", @@ -1702,6 +1895,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", @@ -1710,6 +1904,7 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", @@ -1718,6 +1913,7 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", @@ -1726,6 +1922,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", @@ -1734,6 +1931,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", @@ -1742,6 +1940,7 @@ }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", @@ -1749,6 +1948,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", "PerPkg": "1", @@ -1758,6 +1958,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", @@ -1766,6 +1967,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", @@ -1775,6 +1977,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", "PerPkg": "1", @@ -1784,6 +1987,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", "PerPkg": "1", @@ -1793,6 +1997,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", "PerPkg": "1", @@ -1802,6 +2007,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", "PerPkg": "1", @@ -1811,6 +2017,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", "PerPkg": "1", @@ -1820,6 +2027,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", "PerPkg": "1", @@ -1829,6 +2037,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", @@ -1838,6 +2047,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", @@ -1847,6 +2057,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", @@ -1856,6 +2067,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", @@ -1865,6 +2077,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", @@ -1874,6 +2087,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", @@ -1883,6 +2097,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", "PerPkg": "1", @@ -1892,6 +2107,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", "PerPkg": "1", @@ -1901,6 +2117,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", "PerPkg": "1", @@ -1910,6 +2127,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", "PerPkg": "1", @@ -1919,6 +2137,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", "PerPkg": "1", @@ -1928,6 +2147,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", "PerPkg": "1", @@ -1937,6 +2157,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", "PerPkg": "1", @@ -1946,6 +2167,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", @@ -1954,6 +2176,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", @@ -1963,6 +2186,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", "PerPkg": "1", @@ -1972,6 +2196,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", "PerPkg": "1", @@ -1981,6 +2206,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", "PerPkg": "1", @@ -1990,6 +2216,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", "PerPkg": "1", @@ -1999,6 +2226,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", "PerPkg": "1", @@ -2008,6 +2236,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", "PerPkg": "1", @@ -2017,6 +2246,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", @@ -2026,6 +2256,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", @@ -2035,6 +2266,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", @@ -2044,6 +2276,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", @@ -2053,6 +2286,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", @@ -2062,6 +2296,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", @@ -2071,6 +2306,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", "PerPkg": "1", @@ -2080,6 +2316,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", "PerPkg": "1", @@ -2089,6 +2326,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", "PerPkg": "1", @@ -2098,6 +2336,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", "PerPkg": "1", @@ -2107,6 +2346,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", "PerPkg": "1", @@ -2116,6 +2356,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", "PerPkg": "1", @@ -2125,6 +2366,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", "PerPkg": "1", @@ -2134,6 +2376,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", @@ -2142,6 +2385,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", @@ -2151,6 +2395,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", "PerPkg": "1", @@ -2160,6 +2405,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", "PerPkg": "1", @@ -2169,6 +2415,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", "PerPkg": "1", @@ -2178,6 +2425,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", "PerPkg": "1", @@ -2187,6 +2435,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", "PerPkg": "1", @@ -2196,6 +2445,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", "PerPkg": "1", @@ -2205,6 +2455,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", @@ -2214,6 +2465,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", @@ -2223,6 +2475,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", @@ -2232,6 +2485,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", @@ -2241,6 +2495,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", @@ -2250,6 +2505,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", @@ -2259,6 +2515,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", "PerPkg": "1", @@ -2268,6 +2525,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", "PerPkg": "1", @@ -2277,6 +2535,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", "PerPkg": "1", @@ -2286,6 +2545,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", "PerPkg": "1", @@ -2295,6 +2555,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", "PerPkg": "1", @@ -2304,6 +2565,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", "PerPkg": "1", @@ -2313,6 +2575,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", "PerPkg": "1", @@ -2322,6 +2585,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", @@ -2330,6 +2594,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", @@ -2339,6 +2604,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", "PerPkg": "1", @@ -2348,6 +2614,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", "PerPkg": "1", @@ -2357,6 +2624,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", "PerPkg": "1", @@ -2366,6 +2634,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", "PerPkg": "1", @@ -2375,6 +2644,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", "PerPkg": "1", @@ -2384,6 +2654,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", "PerPkg": "1", @@ -2393,6 +2664,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", @@ -2402,6 +2674,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", @@ -2411,6 +2684,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", @@ -2420,6 +2694,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", @@ -2429,6 +2704,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", @@ -2438,6 +2714,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", @@ -2447,6 +2724,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", "PerPkg": "1", @@ -2456,6 +2734,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", "PerPkg": "1", @@ -2465,6 +2744,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", "PerPkg": "1", @@ -2474,6 +2754,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", "PerPkg": "1", @@ -2483,6 +2764,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", "PerPkg": "1", @@ -2492,6 +2774,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", "PerPkg": "1", @@ -2501,6 +2784,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", "PerPkg": "1", @@ -2510,6 +2794,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", @@ -2518,6 +2803,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", @@ -2527,6 +2813,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", "PerPkg": "1", @@ -2536,6 +2823,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", "PerPkg": "1", @@ -2545,6 +2833,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", "PerPkg": "1", @@ -2554,6 +2843,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", "PerPkg": "1", @@ -2563,6 +2853,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", "PerPkg": "1", @@ -2572,6 +2863,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", "PerPkg": "1", @@ -2581,6 +2873,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", @@ -2590,6 +2883,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", @@ -2599,6 +2893,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", @@ -2608,6 +2903,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", @@ -2617,6 +2913,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", @@ -2626,6 +2923,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", @@ -2635,6 +2933,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", "PerPkg": "1", @@ -2644,6 +2943,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", "PerPkg": "1", @@ -2653,6 +2953,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", "PerPkg": "1", @@ -2662,6 +2963,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", "PerPkg": "1", @@ -2671,6 +2973,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", "PerPkg": "1", @@ -2680,6 +2983,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", "PerPkg": "1", @@ -2689,6 +2993,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", "PerPkg": "1", @@ -2698,6 +3003,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", @@ -2706,6 +3012,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", @@ -2715,6 +3022,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", "PerPkg": "1", @@ -2724,6 +3032,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", "PerPkg": "1", @@ -2733,6 +3042,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", "PerPkg": "1", @@ -2742,6 +3052,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", "PerPkg": "1", @@ -2751,6 +3062,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", "PerPkg": "1", @@ -2760,6 +3072,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", "PerPkg": "1", @@ -2769,6 +3082,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", @@ -2778,6 +3092,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", @@ -2787,6 +3102,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", @@ -2796,6 +3112,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", @@ -2805,6 +3122,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", @@ -2814,6 +3132,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", @@ -2823,6 +3142,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", "PerPkg": "1", @@ -2832,6 +3152,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", "PerPkg": "1", @@ -2841,6 +3162,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", "PerPkg": "1", @@ -2850,6 +3172,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", "PerPkg": "1", @@ -2859,6 +3182,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", "PerPkg": "1", @@ -2868,6 +3192,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/haswellx/uncore-power.json index c391325ee36b..252415937680 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 800 MHz clock. Thi= s event counts the number of pclk cycles measured while the counter was ena= bled. The pclk, like the Memory Controller's dclk, counts at a constant ra= te making it a good measure of actual wall time.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", "PerPkg": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_P_CORE15_TRANSITION_CYCLES", "PerPkg": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_P_CORE16_TRANSITION_CYCLES", "PerPkg": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_P_CORE17_TRANSITION_CYCLES", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", "PerPkg": "1", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", "PerPkg": "1", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x68", "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", "PerPkg": "1", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", "PerPkg": "1", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS_CORE0", "PerPkg": "1", @@ -160,6 +180,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_P_DEMOTIONS_CORE1", "PerPkg": "1", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_P_DEMOTIONS_CORE10", "PerPkg": "1", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3B", "EventName": "UNC_P_DEMOTIONS_CORE11", "PerPkg": "1", @@ -184,6 +207,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "UNC_P_DEMOTIONS_CORE12", "PerPkg": "1", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_P_DEMOTIONS_CORE13", "PerPkg": "1", @@ -200,6 +225,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_P_DEMOTIONS_CORE14", "PerPkg": "1", @@ -208,6 +234,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_P_DEMOTIONS_CORE15", "PerPkg": "1", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_P_DEMOTIONS_CORE16", "PerPkg": "1", @@ -224,6 +252,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_P_DEMOTIONS_CORE17", "PerPkg": "1", @@ -232,6 +261,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", @@ -240,6 +270,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_P_DEMOTIONS_CORE3", "PerPkg": "1", @@ -248,6 +279,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_P_DEMOTIONS_CORE4", "PerPkg": "1", @@ -256,6 +288,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_P_DEMOTIONS_CORE5", "PerPkg": "1", @@ -264,6 +297,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_P_DEMOTIONS_CORE6", "PerPkg": "1", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_P_DEMOTIONS_CORE7", "PerPkg": "1", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_P_DEMOTIONS_CORE8", "PerPkg": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_P_DEMOTIONS_CORE9", "PerPkg": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_P_FREQ_BAND0_CYCLES", "PerPkg": "1", @@ -304,6 +342,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_P_FREQ_BAND1_CYCLES", "PerPkg": "1", @@ -312,6 +351,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_P_FREQ_BAND2_CYCLES", "PerPkg": "1", @@ -320,6 +360,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_P_FREQ_BAND3_CYCLES", "PerPkg": "1", @@ -328,6 +369,7 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", @@ -336,6 +378,7 @@ }, { "BriefDescription": "OS Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", "PerPkg": "1", @@ -344,6 +387,7 @@ }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", @@ -352,6 +396,7 @@ }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", @@ -360,6 +405,7 @@ }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", @@ -368,6 +414,7 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", @@ -376,6 +423,7 @@ }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", "PerPkg": "1", @@ -384,6 +432,7 @@ }, { "BriefDescription": "Package C State Residency - C1E", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES", "PerPkg": "1", @@ -392,6 +441,7 @@ }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", "PerPkg": "1", @@ -400,6 +450,7 @@ }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", "PerPkg": "1", @@ -408,6 +459,7 @@ }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", "PerPkg": "1", @@ -416,6 +468,7 @@ }, { "BriefDescription": "Package C7 State Residency", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES", "PerPkg": "1", @@ -424,6 +477,7 @@ }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "Filter": "occ_sel=3D1", @@ -433,6 +487,7 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "Filter": "occ_sel=3D2", @@ -442,6 +497,7 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "Filter": "occ_sel=3D3", @@ -451,6 +507,7 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", @@ -459,6 +516,7 @@ }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", @@ -467,6 +525,7 @@ }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", @@ -475,6 +534,7 @@ }, { "BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE", "PerPkg": "1", @@ -483,6 +543,7 @@ }, { "BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_P_UFS_TRANSITIONS_RING_GV", "PerPkg": "1", @@ -491,6 +552,7 @@ }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json index 87a4ec1ee7d7..7cf00ae0e993 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "DTLB demand load misses with low part of line= ar-to-physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB demand load misses with low part of lin= ear-to-physical address translation missed.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Number of cache load STLB hits. No page walk= .", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts load operations from a 2M = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the S= TLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts load operations from a 4K = page that miss the first DTLB level but hit the second and do not cause pag= e walks.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in any TLB of any page = size due to demand load misses.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to demand load miss= es that caused 2M/4M page walks in any TLB levels.", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to demand load miss= es that caused 4K page walks in any TLB levels.", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", @@ -88,6 +99,7 @@ }, { "BriefDescription": "DTLB store misses with low part of linear-to-= physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB store misses with low part of linear-to= -physical address translation missed.", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts store operations from a 2M= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the = STLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts store operations from a 4K= page that miss the first DTLB level but hit the second and do not cause pa= ge walks.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks due to store miss in an= y TLB levels of any page size (4K/2M/4M/1G).", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 2M/4M page structure.", @@ -143,6 +161,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to store misses in = one or more TLB levels of 4K page structure.", @@ -151,6 +170,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB store misses.", @@ -159,6 +179,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in ITLB that causes a page walk of an= y page size.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "ITLB misses that hit STLB. No page walk.", @@ -190,6 +214,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the S= TLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "PublicDescription": "ITLB misses that hit STLB (2M).", @@ -198,6 +223,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the S= TLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "PublicDescription": "ITLB misses that hit STLB (4K).", @@ -206,6 +232,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB of any page siz= e.", @@ -214,6 +241,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page wa= lk that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -221,6 +249,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to misses in ITLB 2= M/4M page entries.", @@ -229,6 +258,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to misses in ITLB 4= K page entries.", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by ITLB misses.", @@ -245,6 +276,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "PublicDescription": "Number of DTLB page walker loads that hit in= the L1+FB.", @@ -253,6 +285,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "PublicDescription": "Number of DTLB page walker loads that hit in= the L2.", @@ -261,6 +294,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + X= SNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -270,6 +304,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -279,6 +314,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", @@ -286,6 +322,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", @@ -293,6 +330,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", @@ -300,6 +338,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the DTLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", @@ -307,6 +346,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", @@ -314,6 +354,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", @@ -321,6 +362,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", @@ -328,6 +370,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walk= s from the ITLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", @@ -335,6 +378,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "PublicDescription": "Number of ITLB page walker loads that hit in= the L1+FB.", @@ -343,6 +387,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "PublicDescription": "Number of ITLB page walker loads that hit in= the L2.", @@ -351,6 +396,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + X= SNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -360,6 +406,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", @@ -369,6 +416,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", @@ -377,6 +425,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pl1-f201.google.com (mail-pl1-f201.google.com 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11:19:51 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:30 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-17-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 16/37] perf vendor events: Add/update icelake events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.21 to v1.22. Add TMA metrics v4.8. Bring in the event updates v1.22: https://github.com/intel/perfmon/commit/e5640646e96d59e3c1c1e0d0100a475220f= f1dfe The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Adds the event SW_PREFETCH_ACCESS.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/icelake/cache.json | 109 +++++++ .../pmu-events/arch/x86/icelake/counter.json | 17 + .../arch/x86/icelake/floating-point.json | 13 + .../pmu-events/arch/x86/icelake/frontend.json | 41 ++- .../arch/x86/icelake/icl-metrics.json | 308 +++++++++++++----- .../pmu-events/arch/x86/icelake/memory.json | 44 +++ .../arch/x86/icelake/metricgroups.json | 13 + .../pmu-events/arch/x86/icelake/other.json | 27 ++ .../pmu-events/arch/x86/icelake/pipeline.json | 94 ++++++ .../arch/x86/icelake/uncore-interconnect.json | 34 +- .../arch/x86/icelake/uncore-other.json | 1 + .../arch/x86/icelake/virtual-memory.json | 20 ++ tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 13 files changed, 635 insertions(+), 88 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/icelake/counter.json diff --git a/tools/perf/pmu-events/arch/x86/icelake/cache.json b/tools/perf= /pmu-events/arch/x86/icelake/cache.json index d26c4efe35f0..3508340acd0e 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -52,6 +58,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", @@ -68,6 +76,7 @@ }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", "EventCode": "0xf2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", @@ -84,6 +94,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -100,6 +112,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -108,6 +121,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts demand requests to L2 cache.", @@ -116,6 +130,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -124,6 +139,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", @@ -164,6 +184,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", @@ -172,6 +193,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -180,6 +202,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -188,6 +211,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -196,6 +220,7 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", @@ -204,6 +229,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -212,6 +238,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -220,6 +247,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -230,6 +258,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -240,6 +269,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -250,6 +280,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -260,6 +291,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -280,6 +313,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -290,6 +324,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -300,6 +335,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -310,6 +346,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -320,6 +357,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -330,6 +368,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or Bus Lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -350,6 +390,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -360,6 +401,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -370,6 +412,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -380,6 +423,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -390,6 +434,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -400,6 +445,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -410,6 +456,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -420,6 +467,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -429,6 +477,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another cores caches, data forwarding is required as the data is modified= .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -438,6 +487,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -447,6 +497,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -456,6 +507,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was n= ot needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -465,6 +517,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -474,6 +527,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -483,6 +537,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -492,6 +547,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another core, data forwarding is not requir= ed.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -501,6 +557,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -510,6 +567,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -519,6 +577,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -528,6 +587,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -537,6 +597,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another cores caches, data forward= ing is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -546,6 +607,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another core, data forwarding is n= ot required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -555,6 +617,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent but no other cores had the data.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -564,6 +627,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -573,6 +637,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -582,6 +647,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -591,6 +657,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -600,6 +667,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -609,6 +677,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent or n= ot.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -618,6 +687,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -627,6 +697,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -636,6 +707,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent but = no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -645,6 +717,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was not neede= d to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -654,6 +727,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -663,6 +737,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -672,6 +747,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another cores= caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -681,6 +757,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another core,= data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -690,6 +767,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent but no othe= r cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -699,6 +777,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was not needed to sa= tisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -708,6 +787,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -717,6 +797,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit a cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -726,6 +807,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in= another core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -735,6 +817,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -744,6 +827,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was no= t needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -753,6 +837,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -762,6 +847,7 @@ }, { "BriefDescription": "Counts streaming stores that hit a cacheline = in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -771,6 +857,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -779,6 +866,7 @@ }, { "BriefDescription": "Counts memory transactions sent to the uncore= .", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", @@ -787,6 +875,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -795,6 +884,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -803,6 +893,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests pending. Data read requests include cachea= ble demand reads and L2 prefetches, but do not include RFOs, code reads or = prefetches to the L3. Reads due to page walks resulting from any request t= ype will also be counted. Requests are considered outstanding from the tim= e they miss the core's L2 cache until the transaction completion message is= sent to the requestor.", @@ -811,6 +902,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding data read= request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -820,6 +912,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding Demand RF= O request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -829,6 +922,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -837,6 +931,7 @@ }, { "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", @@ -845,6 +940,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -853,14 +949,24 @@ }, { "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SQ_FULL", "PublicDescription": "Counts the cycles for which the thread is ac= tive and the queue waiting for responses from the uncore cannot take any mo= re entries.", "SampleAfterValue": "100003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -869,6 +975,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -877,6 +984,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -885,6 +993,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/icelake/counter.json b/tools/pe= rf/pmu-events/arch/x86/icelake/counter.json new file mode 100644 index 000000000000..5a350072522a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelake/counter.json @@ -0,0 +1,17 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "CLOCK", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/icelake/floating-point.json index 85c26c889088..61ddce0c8db6 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP= and FM(N)ADD/SUB instructions count twice as they perform multiple calcula= tions per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/icelake/frontend.json b/tools/p= erf/pmu-events/arch/x86/icelake/frontend.json index 2b539a08d2bf..e7c7d4d4152d 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xab", @@ -27,6 +30,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,6 +75,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -90,6 +99,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -101,6 +111,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -123,6 +135,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -134,6 +147,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -145,6 +159,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -156,6 +171,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -167,6 +183,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -189,6 +207,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -200,6 +219,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -211,6 +231,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -222,6 +243,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", @@ -230,6 +252,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", @@ -238,6 +261,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", @@ -246,6 +270,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.ST= ALLS]", @@ -254,6 +279,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", @@ -262,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IF= TAG_STALL]", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -279,15 +307,17 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the D= SB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the I= DQ.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -296,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -305,6 +336,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -314,6 +346,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -322,6 +355,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -331,6 +365,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -341,6 +376,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -349,6 +385,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", @@ -357,6 +394,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -366,6 +404,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json b/tool= s/perf/pmu-events/arch/x86/icelake/icl-metrics.json index f67cc73779f8..9085ea60f516 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelake/icl-metrics.json @@ -104,7 +104,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -114,7 +114,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MIS= C.CLEARS_COUNT / tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -135,7 +135,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions.", "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES= / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_branch_instructions", "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_oper= ations > 0.6", "ScaleUnit": "100%" @@ -143,7 +143,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -181,7 +181,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(29 * tma_info_system_core_frequency * MEM_LOAD_L3_= HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3= _HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -201,7 +201,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "23.5 * tma_info_system_core_frequency * MEM_LOAD_L3= _HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_= MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -219,7 +219,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -250,13 +250,13 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -265,7 +265,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -274,7 +274,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "32.5 * tma_info_system_core_frequency * OCR.DEMAND_= RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -283,7 +283,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -296,7 +296,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -338,7 +338,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -347,7 +347,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0xfc@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -385,7 +385,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -405,7 +405,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -460,6 +460,27 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "tma_info_botlnk_l0_core_bound_likely", + "MetricGroup": "Cor;Metric;SMT", + "MetricName": "tma_info_botlnk_core_bound_likely", + "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + t= ma_lcp + tma_dsb_switches) + tma_fetch_bandwidth * tma_mite / (tma_mite + t= ma_dsb + tma_lsd))", + "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", + "MetricName": "tma_info_botlnk_dsb_misses", + "MetricThreshold": "tma_info_botlnk_dsb_misses > 10" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma= _icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + = tma_lcp + tma_dsb_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", + "MetricName": "tma_info_botlnk_ic_misses", + "MetricThreshold": "tma_info_botlnk_ic_misses > 5" + }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricConstraint": "NO_GROUP_EVENTS", @@ -468,6 +489,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd = + tma_mite)))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -475,7 +504,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -486,40 +515,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound= / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store= _bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_= full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -527,23 +550,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -551,8 +574,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store /= (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency= + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_spl= it_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma= _dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)= ) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_store= s + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -560,7 +583,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (t= ma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_d= ata_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores = + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_mach= ine_clears * (1 - tma_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -569,18 +592,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -638,7 +668,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -655,7 +685,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 5 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -721,7 +751,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -816,12 +846,24 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 11", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "tma_info_memory_mix_bus_lock_pki", + "MetricGroup": "Mem;Metric", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", + "MetricGroup": "Fed;MemoryTLB;Metric", + "MetricName": "tma_info_memory_code_stlb_mpki" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -847,6 +889,12 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "tma_info_memory_latency_data_l2_mlp", + "MetricGroup": "Memory_BW;Metric;Offcore", + "MetricName": "tma_info_memory_data_l2_mlp" + }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -854,11 +902,17 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "tma_info_memory_l1d_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -872,11 +926,17 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l2_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", @@ -902,17 +962,35 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_access_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -927,7 +1005,7 @@ }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", + "MetricExpr": "tma_info_memory_load_l2_miss_latency", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, @@ -943,12 +1021,36 @@ "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l3_miss_latency" }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Load= s", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Clocks_Latency;Memory_Lat;Offcore", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@O= FFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=3D0x1@", + "MetricGroup": "Memory_BW;Metric;Offcore", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Load= s", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,u= mask\\=3D0x0@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Clocks_Latency;Memory_Lat;Offcore", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS += MEM_LOAD_RETIRED.FB_HIT)", "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", + "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", + "MetricGroup": "Mem;MemoryTLB;Metric", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, { "BriefDescription": "\"Bus lock\" per kilo instruction", "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", @@ -957,7 +1059,7 @@ }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricExpr": "tma_info_memory_uc_load_pki", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -968,6 +1070,19 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", + "MetricGroup": "Core_Metric;Mem;MemoryTLB", + "MetricName": "tma_info_memory_page_walks_utilization", + "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", + "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", + "MetricGroup": "Mem;MemoryTLB;Metric", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -994,11 +1109,35 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "", + "BriefDescription": "Un-cacheable retired load per kilo instructio= n", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;Metric", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from LSD per c= ycle", + "MetricExpr": "LSD.UOPS / LSD.CYCLES_ACTIVE", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_lsd" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", @@ -1021,13 +1160,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1151,7 +1290,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1160,7 +1299,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1175,11 +1314,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS)= * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_= info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1198,7 +1346,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "9 * tma_info_system_core_frequency * (MEM_LOAD_RETI= RED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) = / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1210,7 +1358,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1255,7 +1403,7 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { @@ -1270,7 +1418,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1280,7 +1428,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1289,7 +1437,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1326,7 +1474,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1370,7 +1518,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1389,7 +1537,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1397,7 +1545,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1449,7 +1597,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + = tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_AC= TIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks= ", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ / t= ma_info_thread_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1477,7 +1625,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -1487,7 +1635,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -1497,7 +1645,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -1534,7 +1682,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1562,7 +1710,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1605,7 +1753,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/icelake/memory.json b/tools/per= f/pmu-events/arch/x86/icelake/memory.json index f84763220549..f73035f44330 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PublicDescription": "Counts the number of times HLE abort was tri= ggered.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an HLE execution = aborted due to unfriendly events (such as interrupts).", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an HLE execution = aborted due to various memory events (e.g., read/write capacity and conflic= ts).", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an HLE execution = aborted due to HLE-unfriendly instructions and certain unfriendly events (s= uch as AD assists etc.).", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Counts the number of times HLE commit succee= ded.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Counts the number of times we entered an HLE= region. Does not count nested transactions.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -121,6 +134,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -133,6 +147,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -145,6 +160,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -157,6 +173,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -169,6 +186,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +196,7 @@ }, { "BriefDescription": "Counts demand data reads that was not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +206,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that was no= t supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +216,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that was not supplied by the L3 cache.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +226,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +236,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +246,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +256,7 @@ }, { "BriefDescription": "Counts streaming stores that was not supplied= by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +266,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -248,6 +274,7 @@ }, { "BriefDescription": "Cycles where at least one demand data read re= quest known to have missed the L3 cache is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -257,6 +284,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -266,6 +294,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -274,6 +303,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -282,6 +312,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -290,6 +321,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -298,6 +330,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -306,6 +339,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -314,6 +348,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", @@ -322,6 +357,7 @@ }, { "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", @@ -330,6 +366,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -338,6 +375,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -346,6 +384,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", @@ -354,6 +393,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to release/commit but data and address mismatch.", @@ -362,6 +402,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to commit but Lock Buffer not empty.", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to attempting an unsupported alignment from Lock Buffer.", @@ -378,6 +420,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to a non-release/commit store to lock.", @@ -386,6 +429,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Counts the number of times we could not allo= cate Lock Buffer.", diff --git a/tools/perf/pmu-events/arch/x86/icelake/metricgroups.json b/too= ls/perf/pmu-events/arch/x86/icelake/metricgroups.json index 5452a1448ded..3a88260194d1 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/icelake/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/icelake/other.json b/tools/perf= /pmu-events/arch/x86/icelake/other.json index 4fdc87339555..a96b2a989d3f 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -70,6 +78,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -79,6 +88,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -88,6 +98,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -124,6 +138,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -133,6 +148,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -160,6 +178,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +198,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +208,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +218,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +228,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +238,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +248,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +258,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json b/tools/p= erf/pmu-events/arch/x86/icelake/pipeline.json index c7313fd4fdf4..4fdf07c7beb7 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -160,6 +178,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -185,6 +206,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", "SampleAfterValue": "2000003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", @@ -208,6 +232,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -254,6 +284,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -262,6 +293,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "20", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -278,6 +311,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -286,6 +320,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -302,6 +338,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -310,6 +347,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -319,6 +357,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -327,6 +366,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -335,6 +375,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -343,6 +384,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -351,6 +393,7 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -359,6 +402,7 @@ }, { "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", @@ -367,6 +411,7 @@ }, { "BriefDescription": "Cycles without actually retired instructions.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc0", "EventName": "INST_RETIRED.STALL_CYCLES", @@ -377,6 +422,7 @@ }, { "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", @@ -386,6 +432,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -396,6 +443,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -404,6 +452,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -412,6 +461,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -420,6 +470,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -428,6 +479,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -436,6 +488,7 @@ }, { "BriefDescription": "False dependencies due to partial compare on = address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", @@ -444,6 +497,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -452,6 +506,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -461,6 +516,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -470,6 +526,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -478,6 +535,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -488,6 +546,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -496,6 +555,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR to be enabled properly.", @@ -504,6 +564,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.PAUSE_INST", "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", @@ -512,6 +573,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -520,6 +582,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -527,6 +590,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5e", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -535,6 +599,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -546,6 +611,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", @@ -554,6 +620,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -561,6 +628,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -569,6 +637,7 @@ }, { "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UOPS_DECODED.DEC0", "PublicDescription": "Uops exclusively fetched by decoder 0", @@ -577,6 +646,7 @@ }, { "BriefDescription": "Number of uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -585,6 +655,7 @@ }, { "BriefDescription": "Number of uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -593,6 +664,7 @@ }, { "BriefDescription": "Number of uops executed on port 2 and 3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_2_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", @@ -601,6 +673,7 @@ }, { "BriefDescription": "Number of uops executed on port 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", @@ -609,6 +682,7 @@ }, { "BriefDescription": "Number of uops executed on port 5", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -617,6 +691,7 @@ }, { "BriefDescription": "Number of uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -625,6 +700,7 @@ }, { "BriefDescription": "Number of uops executed on port 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", @@ -633,6 +709,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -641,6 +718,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -650,6 +728,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -659,6 +738,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -668,6 +748,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -677,6 +758,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -686,6 +768,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -695,6 +778,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -704,6 +788,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -713,6 +798,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -723,6 +809,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -730,6 +817,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -738,6 +826,7 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -746,6 +835,7 @@ }, { "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -756,6 +846,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to 'Mixing Intel AVX and Intel = SSE Code' section of the Optimization Guide.", @@ -764,6 +855,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -772,6 +864,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -782,6 +875,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "10", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.jso= n b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json index 8027590f1776..909a73d7f2d3 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, etc.", + "Counter": "1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -8,55 +9,73 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core. This event is not su= pported on ICL products but is supported on RKL products.", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_IFA_OCCUPANCY.ALL", + "Counter": "0", + "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core. T= his event is not supported on ICL products but is supported on RKL products= .", + "BriefDescription": "This event is deprecated.", + "Counter": "0", + "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches. This event is not supported on I= CL products but is supported on RKL products.", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_TRK_OCCUPANCY.RD", + "Counter": "0", + "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches", + "Counter": "1", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. T= his event is not supported on ICL products but is supported on RKL products= .", + "BriefDescription": "This event is deprecated.", + "Counter": "0", + "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches. This event is not supported on I= CL products but is supported on RKL products.", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Counter": "0", + "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Total number of all outgoing entries allocate= d. Accounts for Coherent and non-coherent traffic.", + "Counter": "1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -64,9 +83,12 @@ "Unit": "ARB" }, { - "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches. This event is not supported on ICL products but is= supported on RKL products.", + "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Counter": "0,1", + "Deprecated": "1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" diff --git a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/icelake/uncore-other.json index c6596ba09195..cc8110ac020c 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/icelake/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "UNC_CLOCK.SOCKET", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/icelake/virtual-memory.json index b28f62ce1f39..3ff51040f84f 100644 --- a/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -116,6 +130,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 2fc3cc4d7f5a..bb16463d9701 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -14,7 +14,7 @@ GenuineIntel-6-B6,v1.03,grandridge,core GenuineIntel-6-A[DE],v1.02,graniterapids,core GenuineIntel-6-(3C|45|46),v35,haswell,core GenuineIntel-6-3F,v28,haswellx,core -GenuineIntel-6-7[DE],v1.21,icelake,core +GenuineIntel-6-7[DE],v1.22,icelake,core GenuineIntel-6-6[AC],v1.24,icelakex,core GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v24,ivytown,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86DD1B5833 for ; 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Thu, 20 Jun 2024 11:19:53 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:31 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-18-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 17/37] perf vendor events: Add/update icelakex events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.24 to v1.26. Add TMA metrics v4.8. Bring in the event updates v1.26: https://github.com/intel/perfmon/commit/c607c739e05f2569f95998cc98e1283f042= b4fd1 v1.25: https://github.com/intel/perfmon/commit/42d996769069921ec06f6fbb600b0c663b9= ec5a9 The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Adds the event SW_PREFETCH_ACCESS.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/icelakex/cache.json | 106 + .../pmu-events/arch/x86/icelakex/counter.json | 57 + .../arch/x86/icelakex/floating-point.json | 13 + .../arch/x86/icelakex/frontend.json | 38 + .../arch/x86/icelakex/icx-metrics.json | 340 +- .../pmu-events/arch/x86/icelakex/memory.json | 45 + .../arch/x86/icelakex/metricgroups.json | 13 + .../pmu-events/arch/x86/icelakex/other.json | 52 + .../arch/x86/icelakex/pipeline.json | 92 + .../arch/x86/icelakex/uncore-cache.json | 2149 ++++++++++- .../x86/icelakex/uncore-interconnect.json | 3344 +++++++++++++++++ .../arch/x86/icelakex/uncore-io.json | 1829 +++++++++ .../arch/x86/icelakex/uncore-memory.json | 338 ++ .../arch/x86/icelakex/uncore-power.json | 51 + .../arch/x86/icelakex/virtual-memory.json | 22 + tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- 16 files changed, 8269 insertions(+), 222 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/icelakex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/icelakex/cache.json b/tools/per= f/pmu-events/arch/x86/icelakex/cache.json index 3bdc56a75097..0cbb9d6a3ec1 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -52,6 +58,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Cache lines that are evicted by L2 cache when= triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by the L2 cache due to L2 cache fills. Evicted lines are delivered to the = L3, which may or may not cache them, according to system load and prioritie= s.", @@ -68,6 +76,7 @@ }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -76,6 +85,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -100,6 +112,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -108,6 +121,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -116,6 +130,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -140,6 +157,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -180,6 +202,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -188,6 +211,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -196,6 +220,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -206,6 +231,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -216,6 +242,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -226,6 +253,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -236,6 +264,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -256,6 +286,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -266,6 +297,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -276,6 +308,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -286,6 +319,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", + "Counter": "0,1,2,3", "Data_LA": "1", "Deprecated": "1", "EventCode": "0xd2", @@ -296,6 +330,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", + "Counter": "0,1,2,3", "Data_LA": "1", "Deprecated": "1", "EventCode": "0xd2", @@ -306,6 +341,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -316,6 +352,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -326,6 +363,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -336,6 +374,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -346,6 +385,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -355,6 +395,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -365,6 +406,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was remote HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -375,6 +417,7 @@ }, { "BriefDescription": "Retired load instructions with remote Intel(R= ) Optane(TM) DC persistent memory as the data source where the data request= missed all caches.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", @@ -385,6 +428,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or Bus Lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -395,6 +439,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -405,6 +450,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -425,6 +472,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -435,6 +483,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -445,6 +494,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -455,6 +505,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -465,6 +516,7 @@ }, { "BriefDescription": "Retired load instructions with local Intel(R)= Optane(TM) DC persistent memory as the data source where the data request = missed all caches.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", @@ -475,6 +527,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit in the L3 or were snooped from another co= re's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -484,6 +537,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that resulted in a snoop hit a modified line in an= other core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -493,6 +547,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a modified line in a distant L3 Cache or = were snooped from a distant core's L1/L2 caches on this socket when the sys= tem is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -502,6 +557,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that either hit a non-modified line in a distant L= 3 Cache or were snooped from a distant core's L1/L2 caches on this socket w= hen the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -511,6 +567,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 o= r were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -520,6 +577,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit a modified line in another core's caches which forwarded the data.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -529,6 +587,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -538,6 +597,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another core's caches which forwarded the unmodified data to th= e requesting core.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -547,6 +607,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit a modified line in another c= ore's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -556,6 +617,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit in another core's caches whi= ch forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -565,6 +627,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a modified = line in a distant L3 Cache or were snooped from a distant core's L1/L2 cach= es on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +637,7 @@ }, { "BriefDescription": "Counts demand data reads that either hit a no= n-modified line in a distant L3 Cache or were snooped from a distant core's= L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) m= ode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -583,6 +647,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit in= the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -592,6 +657,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that result= ed in a snoop hit a modified line in another core's caches which forwarded = the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -601,6 +667,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = modified line in a distant L3 Cache or were snooped from a distant core's L= 1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mod= e.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -610,6 +677,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that either= hit a non-modified line in a distant L3 Cache or were snooped from a dista= nt core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA c= luster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -619,6 +687,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit in the L3 or were snooped fro= m another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -628,6 +697,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit in the L3 or were snooped from another core's caches on the same sock= et.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -637,6 +707,7 @@ }, { "BriefDescription": "Counts hardware and software prefetches to al= l cache levels that hit in the L3 or were snooped from another core's cache= s on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PREFETCHES.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -646,6 +717,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit in the L3 or were snooped from another core's caches on the sa= me socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -655,6 +727,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit a modified line in another core's caches w= hich forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -664,6 +737,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop that hit in another core, which did not forwar= d the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -673,6 +747,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit in another core's caches which forwarded t= he unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -682,6 +757,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop was sent= and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -691,6 +767,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit a mo= dified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -700,6 +777,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit in a= nother core's caches which forwarded the unmodified data to the requesting = core.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -709,6 +787,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit a modified line in a distant L3 Cache or were snooped from a d= istant core's L1/L2 caches on this socket when the system is in SNC (sub-NU= MA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -718,6 +797,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that either hit a non-modified line in a distant L3 Cache or were snoop= ed from a distant core's L1/L2 caches on this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -727,6 +807,7 @@ }, { "BriefDescription": "Counts streaming stores that hit in the L3 or= were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -736,6 +817,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -744,6 +826,7 @@ }, { "BriefDescription": "Counts memory transactions sent to the uncore= .", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", @@ -752,6 +835,7 @@ }, { "BriefDescription": "Counts cacheable and non-cacheable code reads= to the core.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= reads to the core.", @@ -760,6 +844,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -768,6 +853,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -776,6 +862,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests pending. Data read requests include cachea= ble demand reads and L2 prefetches, but do not include RFOs, code reads or = prefetches to the L3. Reads due to page walks resulting from any request t= ype will also be counted. Requests are considered outstanding from the tim= e they miss the core's L2 cache until the transaction completion message is= sent to the requestor.", @@ -784,6 +871,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding data read= request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -793,6 +881,7 @@ }, { "BriefDescription": "Cycles with outstanding code read requests pe= nding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -802,6 +891,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding Demand RF= O request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -811,6 +901,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding code read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding code read requests pending. Code Read requests include both c= acheable and non-cacheable Code Reads. Requests are considered outstandin= g from the time they miss the core's L2 cache until the transaction complet= ion message is sent to the requestor.", @@ -819,6 +910,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -827,6 +919,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -835,14 +928,24 @@ }, { "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SQ_FULL", "PublicDescription": "Counts the cycles for which the thread is ac= tive and the queue waiting for responses from the uncore cannot take any mo= re entries.", "SampleAfterValue": "100003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -851,6 +954,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -859,6 +963,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -867,6 +972,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/counter.json b/tools/p= erf/pmu-events/arch/x86/icelakex/counter.json new file mode 100644 index 000000000000..63657e0a51a3 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/icelakex/counter.json @@ -0,0 +1,57 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M3UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": 1, + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/icelakex/floating-point.json index 85c26c889088..61ddce0c8db6 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP= and FM(N)ADD/SUB instructions count twice as they perform multiple calcula= tions per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json b/tools/= perf/pmu-events/arch/x86/icelakex/frontend.json index 66669d062e68..d79ddc15b220 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xab", @@ -27,6 +30,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,6 +75,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -90,6 +99,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -101,6 +111,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -123,6 +135,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -134,6 +147,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -145,6 +159,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -156,6 +171,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -167,6 +183,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -189,6 +207,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -200,6 +219,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -211,6 +231,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -222,6 +243,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", @@ -230,6 +252,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", @@ -238,6 +261,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", @@ -246,6 +270,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.ST= ALLS]", @@ -254,6 +279,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", @@ -262,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IF= TAG_STALL]", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -279,6 +307,7 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -288,6 +317,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -296,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -305,6 +336,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -314,6 +346,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -322,6 +355,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -332,6 +366,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -340,6 +375,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", @@ -348,6 +384,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -357,6 +394,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json b/too= ls/perf/pmu-events/arch/x86/icelakex/icx-metrics.json index 769ba12bef87..db5510ba9099 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/icx-metrics.json @@ -47,7 +47,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -72,12 +72,36 @@ "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", "ScaleUnit": "1per_instr" }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the local CPU socket.= ", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / = duration_time", + "MetricName": "io_bandwidth_read_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from a remote CPU socket.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 /= duration_time", + "MetricName": "io_bandwidth_read_remote", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_HIT_ITOM + UNC_CHA_TOR_INSE= RTS.IO_MISS_ITOM + UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR + UNC_CHA_TOR_I= NSERTS.IO_MISS_ITOMCACHENEAR) * 64 / 1e6 / duration_time", "MetricName": "io_bandwidth_write", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the local CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_IN= SERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to a remote CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_I= NSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_remote", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions", "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", @@ -308,7 +332,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -318,7 +342,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MIS= C.CLEARS_COUNT / tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -339,7 +363,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions.", "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES= / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_branch_instructions", "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_oper= ations > 0.6", "ScaleUnit": "100%" @@ -347,7 +371,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -385,7 +409,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3= _HIT_RETIRED.XSNP_HITM * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD)= )) + 43.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_M= ISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_i= nfo_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -405,7 +429,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43.5 * tma_info_system_core_frequency * (MEM_LOAD_L= 3_HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.D= EMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT /= MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -423,7 +447,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -454,13 +478,13 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -469,7 +493,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -478,7 +502,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "48 * tma_info_system_core_frequency * OCR.DEMAND_RF= O.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -487,7 +511,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -500,7 +524,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -542,7 +566,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -551,7 +575,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0xfc@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -589,7 +613,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -609,7 +633,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -664,24 +688,6 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\= \-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-b= ound) + 5 * INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY = + EXE_ACTIVITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIV= ITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-b= ad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_POR= TS_UTIL) + EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown= \\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-= bound) + 5 * INT_MISC.CLEARS_COUNT / slots)) / (((cpu@EXE_ACTIVITY.3_PORTS_= UTIL\\,umask\\=3D0x80@ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-boun= d + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 *= INT_MISC.CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIV= ITY.BOUND_ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS= _UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec += topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + = EXE_ACTIVITY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bou= nd + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 = * INT_MISC.CLEARS_COUNT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHAL= TED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) = / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS= _UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec += topdown\\-retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) /= CPU_CLK_UNHALTED.THREAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TO= TAL - CYCLE_ACTIVITY.STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdo= wn\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-re= tiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHAL= TED.THREAD) if max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.= CLEARS_COUNT / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_= ON_STORES) / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + to= pdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\= -retiring + topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVI= TY.BOUND_ON_STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdo= wn\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC= .CLEARS_COUNT / slots)) < (((cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80= @ + max(0, topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-s= pec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COUN= T / slots - (CYCLE_ACTIVITY.STALLS_MEM_ANY + EXE_ACTIVITY.BOUND_ON_STORES) = / (CYCLE_ACTIVITY.STALLS_TOTAL + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-ret= iring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring += topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) + EXE_ACTIVITY.BOUND_ON= _STORES) * (topdown\\-be\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-= spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MISC.CLEARS_COU= NT / slots)) * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.THREAD * (CYCLE_A= CTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU_CLK_UNHALTED.TH= READ * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-ret= iring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring += topdown\\-be\\-bound) * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THR= EAD if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.= STALLS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + topdown\\-retiring / (topd= own\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be= \\-bound) * EXE_ACTIVITY.2_PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) i= f tma_info_system_smt_2t_utilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "tma_info_botlnk_core_bound_likely" - }, - { - "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_= UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (DSB2MITE_SWITCHES.PENAL= TY_CYCLES / CPU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALT= ED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_R= ESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHAL= TED.THREAD) + min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECOD= E.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CL= K_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound + = topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MIS= C.UOP_DROPPING / slots - (5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CO= RE - INT_MISC.UOP_DROPPING) / slots) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYC= LES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.TH= READ) / 2) / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTE= D.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLE= S_ANY - IDQ.DSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else = CPU_CLK_UNHALTED.THREAD) / 2)))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "tma_info_botlnk_dsb_misses" - }, - { - "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", - "MetricExpr": "100 * (100 * ((5 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_= UOPS_DELIV.CORE - INT_MISC.UOP_DROPPING) / slots * (ICACHE_DATA.STALLS / CP= U_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + IC= ACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES = / CPU_CLK_UNHALTED.THREAD + 10 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) + = min(3 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_CL= K_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.THR= EAD)))", - "MetricGroup": "Fed;FetchLat;IcMiss", - "MetricName": "tma_info_botlnk_ic_misses" - }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricConstraint": "NO_GROUP_EVENTS", @@ -690,6 +696,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -697,7 +711,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -708,40 +722,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency = + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latenc= y + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tm= a_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_s= tore_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -749,23 +757,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -773,8 +781,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= 4k_aliasing + tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_lo= ads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_s= tore_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_= split_stores + tma_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= 4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_l= atency + tma_split_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_st= ore_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma= _false_sharing + tma_split_stores + tma_store_latency + tma_streaming_store= s)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -782,7 +790,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) *= tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + t= ma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound = + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sha= ring) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bou= nd + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / = (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency = + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tm= a_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -791,18 +799,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -860,7 +875,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -877,7 +892,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 5 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -937,7 +952,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -1032,24 +1047,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 11", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" - }, - { - "BriefDescription": "\"Bus lock\" per kilo instruction", - "MetricExpr": "tma_info_memory_mix_bus_lock_pki", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_bus_lock_pki" - }, - { - "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", - "MetricGroup": "Fed;MemoryTLB", - "MetricName": "tma_info_memory_code_stlb_mpki" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -1087,12 +1090,6 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, - { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -1100,17 +1097,11 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -1124,29 +1115,11 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, - { - "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" - }, - { - "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_silent_pki" - }, { "BriefDescription": "L2 cache hits per kilo instruction for all de= mand loads (including speculative)", "MetricExpr": "1e3 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.AN= Y", @@ -1172,29 +1145,23 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duratio= n_time * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -1209,7 +1176,7 @@ }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, @@ -1219,29 +1186,11 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_load_l2_mlp" }, - { - "BriefDescription": "Average Latency for L3 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l3_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l3_miss_latency" - }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@O= FFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=3D0x1@", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L3 cache miss demand Load= s", "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,u= mask\\=3D0x10@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l3_miss_latency" + "MetricName": "tma_info_memory_latency_load_l3_miss_latency" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -1249,12 +1198,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, - { - "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_load_stlb_mpki" - }, { "BriefDescription": "\"Bus lock\" per kilo instruction", "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", @@ -1263,7 +1206,7 @@ }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "tma_info_memory_uc_load_pki", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -1274,18 +1217,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING) / (2 * (CPU_CLK_UNHALTED.DISTRIBUT= ED if #SMT_on else CPU_CLK_UNHALTED.THREAD))", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, - { - "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_store_stlb_mpki" - }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -1312,17 +1243,23 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_uc_load_pki" - }, - { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", @@ -1345,13 +1282,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1535,7 +1472,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1544,7 +1481,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1559,11 +1496,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS)= * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_= info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1582,7 +1528,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "19 * tma_info_system_core_frequency * (MEM_LOAD_RET= IRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2))= / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1594,7 +1540,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1638,7 +1584,7 @@ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", "MetricName": "tma_local_mem", "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 &= (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)= ))", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM_PS", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM", "ScaleUnit": "100%" }, { @@ -1648,13 +1594,13 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1664,7 +1610,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1673,7 +1619,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1710,7 +1656,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1754,7 +1700,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1773,7 +1719,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1781,7 +1727,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1842,7 +1788,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + = tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_AC= TIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks= ", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ / t= ma_info_thread_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1870,7 +1816,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -1898,7 +1844,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -1908,7 +1854,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -1945,7 +1891,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1973,7 +1919,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -2016,7 +1962,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/icelakex/memory.json index 875b584b8443..32a3dedb82fb 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -53,6 +58,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -65,6 +71,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -77,6 +84,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -89,6 +97,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -101,6 +110,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -113,6 +123,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -122,6 +133,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -131,6 +143,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -140,6 +153,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches and the cacheline is homed lo= cally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -149,6 +163,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -158,6 +173,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches and were supplied by= the local socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -167,6 +183,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were not supplied by the local so= cket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -176,6 +193,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were not supplied by the local so= cket's L1, L2, or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -185,6 +203,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -194,6 +213,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -203,6 +223,7 @@ }, { "BriefDescription": "Counts full cacheline writes (ItoM) that were= not supplied by the local socket's L1, L2, or L3 caches and the cacheline = is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ITOM.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -212,6 +233,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that were not supplied by the local socket's L1, L2= , or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that were not supplied by the local socket's L1, L2= , or L3 caches and the cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -230,6 +253,7 @@ }, { "BriefDescription": "Counts hardware and software prefetches to al= l cache levels that were not supplied by the local socket's L1, L2, or L3 c= aches and the cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.PREFETCHES.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -239,6 +263,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -248,6 +273,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by the local socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -257,6 +283,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that missed the L3 Cache and were supplied by the local socket (DRAM or= PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PM= M or DRAM accesses that are controlled by the close or distant SNC Cluster.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", "MSRIndex": "0x1a6,0x1a7", @@ -266,6 +293,7 @@ }, { "BriefDescription": "Counts streaming stores that missed the local= socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -275,6 +303,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the local socket's L1, L2, or L3 caches and the cacheline is homed loc= ally.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -284,6 +313,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -291,6 +321,7 @@ }, { "BriefDescription": "Cycles where at least one demand data read re= quest known to have missed the L3 cache is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -300,6 +331,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", @@ -308,6 +340,7 @@ }, { "BriefDescription": "Cycles where the core is waiting on at least = 6 outstanding demand data read requests known to have missed the L3 cache.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -317,6 +350,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -326,6 +360,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -334,6 +369,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -342,6 +378,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -350,6 +387,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -358,6 +396,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -366,6 +405,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -374,6 +414,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", @@ -382,6 +423,7 @@ }, { "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", @@ -390,6 +432,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -398,6 +441,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -406,6 +450,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json b/to= ols/perf/pmu-events/arch/x86/icelakex/metricgroups.json index 904d299c95a3..cccfcab3425e 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/other.json b/tools/per= f/pmu-events/arch/x86/icelakex/other.json index 11810daaf150..05b348d9c838 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/other.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Hit snoop reply with data, line invalidated.", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.I_FWD_FE", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's cache, after the dat= a is forwarded back to the requestor and indicating the data was found unmo= dified in the (FE) Forward or Exclusive State in this cores caches cache. = A single snoop response from the core counts on all hyperthreads of the cor= e.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "HitM snoop reply with data, line invalidated.= ", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.I_FWD_M", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated: removed from this core's caches, after the da= ta is forwarded back to the requestor, and indicating the data was found mo= dified(M) in this cores caches cache (aka HitM response). A single snoop r= esponse from the core counts on all hyperthreads of the core.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Hit snoop reply without sending the data, lin= e invalidated.", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.I_HIT_FSE", "PublicDescription": "Counts responses to snoops indicating the li= ne will now be (I)nvalidated in this core's caches without being forwarded = back to the requestor. The line was in Forward, Shared or Exclusive (FSE) s= tate in this cores caches. A single snoop response from the core counts on= all hyperthreads of the core.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Line not found snoop reply", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.MISS", "PublicDescription": "Counts responses to snoops indicating that t= he data was not found (IHitI) in this core's caches. A single snoop respons= e from the core counts on all hyperthreads of the Core.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Hit snoop reply with data, line kept in Share= d state.", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.S_FWD_FE", "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (FS) Forward or Shared state. A single snoop response from the core count= s on all hyperthreads of the core.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "HitM snoop reply with data, line kept in Shar= ed state", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.S_FWD_M", "PublicDescription": "Counts responses to snoops indicating the li= ne may be kept on this core in the (S)hared state, after the data is forwar= ded back to the requestor, initially the data was found in the cache in the= (M)odified state. A single snoop response from the core counts on all hyp= erthreads of the core.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Hit snoop reply without sending the data, lin= e kept in Shared state.", + "Counter": "0,1,2,3", "EventCode": "0xef", "EventName": "CORE_SNOOP_RESPONSE.S_HIT_FSE", "PublicDescription": "Counts responses to snoops indicating the li= ne was kept on this core in the (S)hared state, and that the data was found= unmodified but not forwarded back to the requestor, initially the data was= found in the cache in the (FSE) Forward, Shared state or Exclusive state. = A single snoop response from the core counts on all hyperthreads of the co= re.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -90,6 +101,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM attached to this socket= , unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM= accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -108,6 +121,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM on a distant memory con= troller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -117,6 +131,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S= NC Mode counts only those DRAM accesses that are controlled by the close SN= C Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -144,6 +161,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In SN= C Mode counts only those PMM accesses that are controlled by the close SNC = Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -153,6 +171,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.PMM", "MSRIndex": "0x1a6,0x1a7", @@ -162,6 +181,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -180,6 +201,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM on a distant memory controller of this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -189,6 +211,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM on a distant memory controller of this socket when the system is in S= NC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.SNC_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -198,6 +221,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -207,6 +231,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -216,6 +241,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mo= de. In SNC Mode counts only those DRAM accesses that are controlled by the= close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -225,6 +251,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM attached to this socket, unless in Sub NUMA Cluster(SNC) Mod= e. In SNC Mode counts only those PMM accesses that are controlled by the c= lose SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -234,6 +261,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.PMM", "MSRIndex": "0x1a6,0x1a7", @@ -243,6 +271,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.REMOTE_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -252,6 +281,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM on a distant memory controller of this socket when the syst= em is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -261,6 +291,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by PMM on a distant memory controller of this socket when the syste= m is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.SNC_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -270,6 +301,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -279,6 +311,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that were supplied by DRAM attached to= this socket, unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts onl= y those DRAM accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -288,6 +321,7 @@ }, { "BriefDescription": "Counts hardware prefetch (which bring data to= L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -297,6 +331,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -306,6 +341,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline was homed in a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -315,6 +351,7 @@ }, { "BriefDescription": "Counts full cacheline writes (ItoM) that were= not supplied by the local socket's L1, L2, or L3 caches and the cacheline = was homed in a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.ITOM.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -324,6 +361,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -333,6 +371,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -342,6 +381,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -351,6 +391,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA = Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are co= ntrolled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -360,6 +401,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to this socket, unless in Sub NUMA C= luster(SNC) Mode. In SNC Mode counts only those PMM accesses that are cont= rolled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -369,6 +411,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, whether or not in S= ub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are contr= olled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -378,6 +421,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to this socket, whether or not in Su= b NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are control= led by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -387,6 +431,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -396,6 +441,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -405,6 +451,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", "MSRIndex": "0x1a6,0x1a7", @@ -414,6 +461,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -423,6 +471,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM on a distant memory controller of this socke= t when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -432,6 +481,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM on a distant memory controller of this socket= when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.READS_TO_CORE.SNC_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -441,6 +491,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -450,6 +501,7 @@ }, { "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hard= ware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted = in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.WRITE_ESTIMATE.MEMORY", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/icelakex/pipeline.json index 45ee6bceba7f..74285b6c81e7 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -160,6 +178,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -185,6 +206,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", "SampleAfterValue": "2000003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", @@ -208,6 +232,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -254,6 +284,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -262,6 +293,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "20", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -278,6 +311,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -286,6 +320,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -302,6 +338,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -310,6 +347,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -319,6 +357,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -327,6 +366,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -335,6 +375,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -343,6 +384,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -351,6 +393,7 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -359,6 +402,7 @@ }, { "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", @@ -367,6 +411,7 @@ }, { "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", @@ -376,6 +421,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -386,6 +432,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -394,6 +441,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -402,6 +450,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -410,6 +459,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -418,6 +468,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -426,6 +477,7 @@ }, { "BriefDescription": "False dependencies due to partial compare on = address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", @@ -434,6 +486,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -442,6 +495,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -451,6 +505,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -460,6 +515,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -468,6 +524,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -478,6 +535,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -486,6 +544,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR to be enabled properly.", @@ -494,6 +553,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.PAUSE_INST", "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", @@ -502,6 +562,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -510,6 +571,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -517,6 +579,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5e", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -525,6 +588,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -536,6 +600,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", @@ -544,6 +609,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -551,6 +617,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -559,6 +626,7 @@ }, { "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UOPS_DECODED.DEC0", "PublicDescription": "Uops exclusively fetched by decoder 0", @@ -567,6 +635,7 @@ }, { "BriefDescription": "Number of uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -575,6 +644,7 @@ }, { "BriefDescription": "Number of uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -583,6 +653,7 @@ }, { "BriefDescription": "Number of uops executed on port 2 and 3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_2_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", @@ -591,6 +662,7 @@ }, { "BriefDescription": "Number of uops executed on port 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", @@ -599,6 +671,7 @@ }, { "BriefDescription": "Number of uops executed on port 5", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -607,6 +680,7 @@ }, { "BriefDescription": "Number of uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -615,6 +689,7 @@ }, { "BriefDescription": "Number of uops executed on port 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", @@ -623,6 +698,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -632,6 +708,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -641,6 +718,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -650,6 +728,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -659,6 +738,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -668,6 +748,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -677,6 +758,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -686,6 +768,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -695,6 +778,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -705,6 +789,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -712,6 +797,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -720,6 +806,7 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -728,6 +815,7 @@ }, { "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -738,6 +826,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to 'Mixing Intel AVX and Intel = SSE Code' section of the Optimization Guide.", @@ -746,6 +835,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -754,6 +844,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -764,6 +855,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "10", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/icelakex/uncore-cache.json index a950ba3ddcb4..8c73708befef 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-cache.json @@ -1,80 +1,98 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x65", "EventName": "UNC_CHA_2LM_NM_INVITOX.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x65", "EventName": "UNC_CHA_2LM_NM_INVITOX.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x65", "EventName": "UNC_CHA_2LM_NM_INVITOX.SETCONFLICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x64", "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.LLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x64", "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.SF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x64", "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS.TOR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x70", "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x70", "EventName": "UNC_CHA_2LM_NM_SETCONFLICTS2.MEMWRNI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -82,8 +100,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -91,8 +111,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -100,8 +122,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -109,8 +133,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -118,8 +144,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -127,8 +155,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -136,8 +166,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -145,8 +177,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -154,8 +188,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -163,8 +199,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -172,8 +210,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -181,8 +221,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -190,8 +232,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -199,8 +243,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -208,8 +254,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -217,8 +265,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -226,8 +276,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -235,8 +287,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -244,8 +298,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -253,8 +309,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -262,8 +320,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -271,8 +331,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -280,8 +342,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -289,8 +353,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -298,8 +364,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -307,8 +375,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -316,8 +386,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -325,8 +397,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -334,8 +408,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -343,8 +419,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -352,8 +430,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -361,8 +441,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -370,8 +452,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -379,8 +463,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -388,8 +474,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -397,8 +485,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -406,8 +496,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -415,8 +507,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -424,8 +518,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -433,8 +529,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -442,8 +540,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -451,8 +551,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -460,8 +562,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -469,8 +573,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -478,8 +584,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -487,8 +595,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -496,8 +606,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -505,8 +617,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -514,8 +628,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -523,8 +639,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -532,8 +650,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -541,8 +661,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -550,8 +672,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -559,8 +683,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -568,8 +694,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -577,8 +705,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -586,8 +716,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -595,8 +727,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -604,8 +738,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -613,8 +749,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -622,8 +760,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -631,8 +771,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -640,8 +782,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -649,8 +793,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -658,8 +804,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -667,8 +815,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -676,8 +826,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -685,8 +837,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -694,8 +848,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -703,8 +859,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -712,8 +870,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -721,8 +881,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -730,8 +892,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -739,8 +903,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -748,8 +914,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -757,8 +925,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -766,8 +936,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -775,8 +947,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -784,8 +958,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -793,8 +969,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -802,8 +980,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -811,8 +991,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -820,8 +1002,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -829,8 +1013,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -838,8 +1024,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -847,8 +1035,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -856,8 +1046,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -865,8 +1057,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", "UMask": "0x2", @@ -874,8 +1068,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", "UMask": "0x4", @@ -883,8 +1079,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", "UMask": "0x1", @@ -892,12 +1090,14 @@ }, { "BriefDescription": "Clockticks of the uncore caching and home age= nt (CHA)", + "Counter": "0,1,2,3", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", @@ -905,8 +1105,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0xf2", @@ -914,8 +1116,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", "UMask": "0xf1", @@ -923,8 +1127,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", @@ -932,8 +1138,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", "UMask": "0x41", @@ -941,8 +1149,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", @@ -950,8 +1160,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", "UMask": "0x81", @@ -959,8 +1171,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x22", @@ -968,8 +1182,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x21", @@ -977,8 +1193,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Tar= gets from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Ta= rgets from Remote : Counts the number of transactions that trigger a config= urable number of cross snoops. Cores are snooped if the transaction looks = up the cache and determines that it is necessary based on the operation typ= e and what CoreValid bits are set. For example, if 2 CV bits are set on a = data read, the cores must have the data in S state so it is not necessary t= o snoop them. However, if only 1 CV bit is set the core my have modified t= he data. If the transaction was an RFO, it would need to invalidate the li= nes. This event can be filtered based on who triggered the initial snoop(s= ).", "UMask": "0x12", @@ -986,8 +1204,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Snoop Targe= t from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Snoop Targ= et from Remote : Counts the number of transactions that trigger a configura= ble number of cross snoops. Cores are snooped if the transaction looks up = the cache and determines that it is necessary based on the operation type a= nd what CoreValid bits are set. For example, if 2 CV bits are set on a dat= a read, the cores must have the data in S state so it is not necessary to s= noop them. However, if only 1 CV bit is set the core my have modified the = data. If the transaction was an RFO, it would need to invalidate the lines= . This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x11", @@ -995,104 +1215,130 @@ }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counter 0 Occupancy : Since occupancy counts= can only be captured in the Cbo's 0 counter, this event allows a user to c= apture occupancy related information by filtering the Cb0 occupancy count c= aptured in Counter 0. The filtering available is found in the control reg= ister - threshold, invert and edge detect. E.g. setting threshold to 1 ca= n effectively monitor how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Multi-socket cacheline directory state lookup= s : Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi-socket cacheline directory state looku= ps : Snoop Not Needed : Counts the number of transactions that looked up th= e directory. Can be filtered by requests that had to snoop and those that = did not have to. : Filters for transactions that did not have to send any s= noops because the directory was clean.", "UMask": "0x2", @@ -1100,8 +1346,10 @@ }, { "BriefDescription": "Multi-socket cacheline directory state lookup= s : Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi-socket cacheline directory state looku= ps : Snoop Needed : Counts the number of transactions that looked up the di= rectory. Can be filtered by requests that had to snoop and those that did = not have to. : Filters for transactions that had to send one or more snoops= because the directory was not clean.", "UMask": "0x1", @@ -1109,6 +1357,7 @@ }, { "BriefDescription": "Multi-socket cacheline directory state update= s; memory write due to directory update from the home agent (HA) pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", @@ -1118,6 +1367,7 @@ }, { "BriefDescription": "Multi-socket cacheline directory state update= s; memory write due to directory update from (table of requests) TOR pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", @@ -1127,8 +1377,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1136,8 +1388,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1145,8 +1399,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1154,8 +1410,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1163,8 +1421,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1172,8 +1432,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : If the CHA TOR has too many PMM transactions, this signal will th= rottle outgoing MS2IDI traffic", "UMask": "0x10", @@ -1181,8 +1443,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.PMM_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If another CHA TOR has too many PMM transactions, this signal wi= ll throttle outgoing MS2IDI traffic", "UMask": "0x20", @@ -1190,8 +1454,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1199,8 +1465,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1208,8 +1476,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1217,8 +1487,10 @@ }, { "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts read requests from a remote socket wh= ich hit in the HitME cache (used to cache the multi-socket Directory state)= to a line in the E(Exclusive) state. This includes the following read opc= odes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", "UMask": "0x1", @@ -1226,8 +1498,10 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote= socket ownership read requests that hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of Hits in HitMe Cache : Remot= e socket ownership read requests that hit in S state. : Shared hit and op i= s RdInvOwn, RdInv, Inv*", "UMask": "0x4", @@ -1235,16 +1509,20 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote= socket WBMtoE requests", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : Remote= socket writeback to I or S requests", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of Hits in HitMe Cache : Remot= e socket writeback to I or S requests : op is WbMtoI, WbPushMtoI, WbFlush, = or WbMtoS", "UMask": "0x10", @@ -1252,8 +1530,10 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : Remote socket read requests", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of times HitMe Cache is access= ed : Remote socket read requests : op is RdCode, RdData, RdDataMigratory, R= dCur, RdInvOwn, RdInv, Inv*", "UMask": "0x1", @@ -1261,8 +1541,10 @@ }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : Remote socket write (i.e. writeback) requests", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of times HitMe Cache is access= ed : Remote socket write (i.e. writeback) requests : op is WbMtoE, WbMtoI, = WbPushMtoI, WbFlush, or WbMtoS", "UMask": "0x2", @@ -1270,8 +1552,10 @@ }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : Remo= te socket RdInvOwn requests that are not to shared line", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of Misses in HitMe Cache : Rem= ote socket RdInvOwn requests that are not to shared line : No SF/LLC HitS/F= and op is RdInvOwn", "UMask": "0x40", @@ -1279,8 +1563,10 @@ }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : Remo= te socket read or invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of Misses in HitMe Cache : Rem= ote socket read or invalidate requests : op is RdCode, RdData, RdDataMigrat= ory, RdCur, RdInv, Inv*", "UMask": "0x80", @@ -1288,8 +1574,10 @@ }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : Remo= te socket RdInvOwn requests to shared line", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts Number of Misses in HitMe Cache : Rem= ote socket RdInvOwn requests to shared line : SF/LLC HitS/F and op is RdInv= Own", "UMask": "0x20", @@ -1297,16 +1585,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Deallocate HitME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI= * for a local request, but converted HitME$ to SF entry", "UMask": "0x1", @@ -1314,16 +1606,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ = on RspFwdI* or local HitM/E received for a remote request", "UMask": "0x2", @@ -1331,16 +1627,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1348,8 +1648,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1357,8 +1659,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1366,8 +1670,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1375,8 +1681,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1384,8 +1692,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1393,8 +1703,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1402,8 +1714,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1411,8 +1725,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1420,8 +1736,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1429,8 +1747,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1438,8 +1758,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1447,8 +1769,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1456,8 +1780,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1465,8 +1791,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1474,8 +1802,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1483,8 +1813,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1492,8 +1824,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1501,6 +1835,7 @@ }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -1510,8 +1845,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", "UMask": "0x2", @@ -1519,6 +1856,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -1528,8 +1866,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", "UMask": "0x4", @@ -1537,8 +1877,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", "UMask": "0x2", @@ -1546,8 +1888,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", "UMask": "0x8", @@ -1555,8 +1899,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1fffff", @@ -1564,8 +1910,10 @@ }, { "BriefDescription": "Cache Lookups : All transactions from Remote = Agents", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All transactions from Remote= Agents : Counts the number of times the LLC was accessed - this includes c= ode, data, prefetches and hints coming from L2. This has numerous filters = available. Note the non-standard filtering equation. This event will coun= t requests that lookup the cache multiple times with multiple increments. = One must ALWAYS select a state or states (in the umask field) to match. Ot= herwise, the event will count nothing.", "UMask": "0x1e20ff", @@ -1573,34 +1921,42 @@ }, { "BriefDescription": "Cache Lookups : All Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Any local or remote transaction to the LLC, includi= ng prefetch.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bd0ff", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x19d0ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Code Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bd0ff", @@ -1608,16 +1964,20 @@ }, { "BriefDescription": "Cache Lookups : CRd Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote CRd transactions to the LLC. This = includes CRd prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : CRd Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x19d0ff", @@ -1625,8 +1985,10 @@ }, { "BriefDescription": "Cache Lookups : Code Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bd001", @@ -1634,8 +1996,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1a10ff", @@ -1643,32 +2007,39 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1a10ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Local request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Any local transaction to the LLC, including prefe= tches from the Core", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -1678,25 +2049,31 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1fc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Data Read Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Request Filter : C= ounts the number of times the LLC was accessed - this includes code, data, = prefetches and hints coming from L2. This has numerous filters available. = Note the non-standard filtering equation. This event will count requests = that lookup the cache multiple times with multiple increments. One must AL= WAYS select a state or states (in the umask field) to match. Otherwise, th= e event will count nothing. : Read transactions.", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x19c1ff", @@ -1704,8 +2081,10 @@ }, { "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bc101", @@ -1713,8 +2092,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uests that come from a Remote socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1a01ff", @@ -1722,17 +2103,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x841ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Exclusive State", "UMask": "0x20", @@ -1740,8 +2125,10 @@ }, { "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Forward State", "UMask": "0x80", @@ -1749,8 +2136,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a44ff", @@ -1758,8 +2147,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests = that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1844ff", @@ -1767,8 +2158,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate requests = that come from a Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a04ff", @@ -1776,16 +2169,20 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush or Invalidate Filter := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Miss", "UMask": "0x1", @@ -1793,8 +2190,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requ= ests to the LLC that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x189dff", @@ -1802,42 +2201,52 @@ }, { "BriefDescription": "Cache Lookups : Local LLC prefetch requests (= from LLC) Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local LLC prefetch requests = (from LLC) Filter : Counts the number of times the LLC was accessed - this = includes code, data, prefetches and hints coming from L2. This has numerou= s filters available. Note the non-standard filtering equation. This event= will count requests that lookup the cache multiple times with multiple inc= rements. One must ALWAYS select a state or states (in the umask field) to = match. Otherwise, the event will count nothing. : Any local LLC prefetch t= o the LLC", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LLC_PF_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x189dff", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LOC_HOM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xbdfff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed locally Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally F= ilter : Counts the number of times the LLC was accessed - this includes cod= e, data, prefetches and hints coming from L2. This has numerous filters av= ailable. Note the non-standard filtering equation. This event will count = requests that lookup the cache multiple times with multiple increments. On= e must ALWAYS select a state or states (in the umask field) to match. Othe= rwise, the event will count nothing. : Transaction whose address resides in= the local MC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed locally", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS set umask bit 0 and select a state or states to match. Otherwise, t= he event will count nothing. : Transaction whose address resides in the loc= al MC.", "UMask": "0xbdfff", @@ -1845,8 +2254,10 @@ }, { "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Modified State", "UMask": "0x40", @@ -1854,8 +2265,10 @@ }, { "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1fe001", @@ -1863,24 +2276,30 @@ }, { "BriefDescription": "Cache Lookups : Write Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Writeback transactions to the LLC This includes = all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Remote non-snoop request Filt= er", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote non-snoop request Fil= ter : Counts the number of times the LLC was accessed - this includes code,= data, prefetches and hints coming from L2. This has numerous filters avai= lable. Note the non-standard filtering equation. This event will count re= quests that lookup the cache multiple times with multiple increments. One = must ALWAYS select a state or states (in the umask field) to match. Otherw= ise, the event will count nothing. : Non-snoop transactions to the LLC from= remote agent", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS select a state= or states (in the umask field) to match. Otherwise, the event will count = nothing.", "UMask": "0x1bd9ff", @@ -1888,8 +2307,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Locally HOMed : Counts the number of times the LLC was accessed - this= includes code, data, prefetches and hints coming from L2. This has numero= us filters available. Note the non-standard filtering equation. This even= t will count requests that lookup the cache multiple times with multiple in= crements. One must ALWAYS select a state or states (in the umask field) to= match. Otherwise, the event will count nothing.", "UMask": "0x9d9ff", @@ -1897,8 +2318,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Remotely HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0x11d9ff", @@ -1906,8 +2329,10 @@ }, { "BriefDescription": "Cache Lookups : Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Read Misses : Counts the num= ber of times the LLC was accessed - this includes code, data, prefetches an= d hints coming from L2. This has numerous filters available. Note the non= -standard filtering equation. This event will count requests that lookup t= he cache multiple times with multiple increments. One must ALWAYS select a= state or states (in the umask field) to match. Otherwise, the event will = count nothing.", "UMask": "0x1bd901", @@ -1915,8 +2340,10 @@ }, { "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS select a state or states (in the umask field) to match. Otherwise, t= he event will count nothing.", "UMask": "0xbd901", @@ -1924,8 +2351,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "UMask": "0x13d901", @@ -1933,8 +2362,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely requested Read or Sn= oop Misses that are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM= ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely requested Read or S= noop Misses that are Remotely HOMed : Counts the number of times the LLC wa= s accessed - this includes code, data, prefetches and hints coming from L2.= This has numerous filters available. Note the non-standard filtering equ= ation. This event will count requests that lookup the cache multiple times= with multiple increments. One must ALWAYS select a state or states (in th= e umask field) to match. Otherwise, the event will count nothing.", "UMask": "0x161901", @@ -1942,8 +2373,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely Requested Reads that= are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely Requested Reads tha= t are Locally HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0xa19ff", @@ -1951,8 +2384,10 @@ }, { "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filt= er", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Fil= ter : Counts the number of times the LLC was accessed - this includes code,= data, prefetches and hints coming from L2. This has numerous filters avai= lable. Note the non-standard filtering equation. This event will count re= quests that lookup the cache multiple times with multiple increments. One = must ALWAYS select a state or states (in the umask field) to match. Otherw= ise, the event will count nothing.", "UMask": "0x1bd90e", @@ -1960,33 +2395,41 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REM_HOM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15dfff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed remotely F= ilter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = Filter : Counts the number of times the LLC was accessed - this includes co= de, data, prefetches and hints coming from L2. This has numerous filters a= vailable. Note the non-standard filtering equation. This event will count= requests that lookup the cache multiple times with multiple increments. O= ne must ALWAYS select a state or states (in the umask field) to match. Oth= erwise, the event will count nothing. : Transaction whose address resides i= n a remote MC", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Remote snoop request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote snoop request Filter = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS select a state or states (in the umask field) to match. Otherwise,= the event will count nothing. : Snoop transactions to the LLC from remote = agent", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Request= s from a Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1c19ff", @@ -1994,8 +2437,10 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed remotely", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "UMask": "0x15dfff", @@ -2003,8 +2448,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1bc8ff", @@ -2012,16 +2459,20 @@ }, { "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote RFO transactions to the LLC. This = includes RFO prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : RFO Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x19c8ff", @@ -2029,8 +2480,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bc801", @@ -2038,17 +2491,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x888ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : RFO Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1a08ff", @@ -2056,8 +2513,10 @@ }, { "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Shared State", "UMask": "0x10", @@ -2065,8 +2524,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Exclusive State", "UMask": "0x4", @@ -2074,8 +2535,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit HitMe State", "UMask": "0x8", @@ -2083,8 +2546,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Shared State", "UMask": "0x2", @@ -2092,8 +2557,10 @@ }, { "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "UMask": "0x1a42ff", @@ -2101,24 +2568,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x842ff", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x17c2ff", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : All Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.ALL", "PerPkg": "1", @@ -2128,8 +2600,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x2", @@ -2137,8 +2611,10 @@ }, { "BriefDescription": "Lines Victimized : Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - All Lines : Count= s the number of lines that were victimized on a fill. This can be filtered= by the state that the line was in.", "UMask": "0x200f", @@ -2146,8 +2622,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in E State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2002", @@ -2155,8 +2633,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in M State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2001", @@ -2164,16 +2644,20 @@ }, { "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : Local - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in S State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2004", @@ -2181,8 +2665,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x1", @@ -2190,8 +2676,10 @@ }, { "BriefDescription": "Lines Victimized : Remote - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - All Lines : Coun= ts the number of lines that were victimized on a fill. This can be filtere= d by the state that the line was in.", "UMask": "0x800f", @@ -2199,8 +2687,10 @@ }, { "BriefDescription": "Lines Victimized : Remote - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in E State= : Counts the number of lines that were victimized on a fill. This can be = filtered by the state that the line was in.", "UMask": "0x8002", @@ -2208,8 +2698,10 @@ }, { "BriefDescription": "Lines Victimized : Remote - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in M State= : Counts the number of lines that were victimized on a fill. This can be = filtered by the state that the line was in.", "UMask": "0x8001", @@ -2217,16 +2709,20 @@ }, { "BriefDescription": "Lines Victimized : Remote Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote Only : Counts the = number of lines that were victimized on a fill. This can be filtered by th= e state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : Remote - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in S State= : Counts the number of lines that were victimized on a fill. This can be = filtered by the state that the line was in.", "UMask": "0x8004", @@ -2234,8 +2730,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x4", @@ -2243,8 +2741,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", "UMask": "0x20", @@ -2252,8 +2752,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", "UMask": "0x10", @@ -2261,8 +2763,10 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x8", @@ -2270,8 +2774,10 @@ }, { "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", "UMask": "0x1", @@ -2279,8 +2785,10 @@ }, { "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", @@ -2288,24 +2796,30 @@ }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count = of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be b= roadcast. Does not count all the snoops generated by OSB.", "UMask": "0x1", @@ -2313,8 +2827,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OS= B snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadc= ast. Does not count all the snoops generated by OSB.", "UMask": "0x2", @@ -2322,8 +2838,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Off", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB sno= op broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. = Does not count all the snoops generated by OSB.", "UMask": "0x20", @@ -2331,8 +2849,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of O= SB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broad= cast. Does not count all the snoops generated by OSB.", "UMask": "0x4", @@ -2340,8 +2860,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Co= unt of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to = be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x8", @@ -2349,8 +2871,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadca= st : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB sno= ops to be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x10", @@ -2358,48 +2882,60 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x4", @@ -2407,8 +2943,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x10", @@ -2416,8 +2954,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x2", @@ -2425,8 +2965,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x8", @@ -2434,32 +2976,40 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IRQ_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x20", @@ -2467,80 +3017,100 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TORMATCH_MULTI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PMM_MEMMODE_TOR_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PRQ_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x40", @@ -2548,8 +3118,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x80", @@ -2557,8 +3129,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x1", @@ -2566,128 +3140,130 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PMM Memory Mode related events : Counts the n= umber of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Memory Mode related events : Counts the = number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to ano= ther read to the same near memory set in the LLC.", "UMask": "0x2", @@ -2695,8 +3271,10 @@ }, { "BriefDescription": "PMM Memory Mode related events : Counts the n= umber of times CHA saw NM Set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Memory Mode related events : Counts the = number of times CHA saw NM Set conflict in SF/LLC : NM evictions due to ano= ther read to the same near memory set in the SF.", "UMask": "0x1", @@ -2704,8 +3282,10 @@ }, { "BriefDescription": "PMM Memory Mode related events : Counts the n= umber of times CHA saw NM Set conflict in TOR", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Memory Mode related events : Counts the = number of times CHA saw NM Set conflict in TOR : No Reject in the CHA due t= o a pending read to the same near memory set in the TOR.", "UMask": "0x4", @@ -2713,88 +3293,110 @@ }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": count # of FAST TOR Request inserted to ha= _tor_req_fifo", "UMask": "0x2", @@ -2802,8 +3404,10 @@ }, { "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": count # of SLOW TOR Request inserted to ha= _pmm_tor_req_fifo", "UMask": "0x1", @@ -2811,8 +3415,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", "UMask": "0x1", @@ -2820,8 +3426,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", "UMask": "0x2", @@ -2829,40 +3437,50 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", "UMask": "0x4", @@ -2870,8 +3488,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", "UMask": "0x8", @@ -2879,8 +3499,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", @@ -2888,8 +3510,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", @@ -2897,8 +3521,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 6 only.", "UMask": "0x40", @@ -2906,8 +3532,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 7 only.", "UMask": "0x80", @@ -2915,24 +3543,30 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and remote INVI= TOE requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", "UMask": "0x30", @@ -2940,6 +3574,7 @@ }, { "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and are sent to= the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -2949,6 +3584,7 @@ }, { "BriefDescription": "Remote INVITOE requests (exclusive ownership = of a cache line without receiving data) sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -2958,6 +3594,7 @@ }, { "BriefDescription": "Local read requests that miss the SF/LLC and = remote read requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -2967,6 +3604,7 @@ }, { "BriefDescription": "Local read requests that miss the SF/LLC and = are sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -2976,6 +3614,7 @@ }, { "BriefDescription": "Remote read requests sent to the CHA's home a= gent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -2985,6 +3624,7 @@ }, { "BriefDescription": "Local write requests that miss the SF/LLC and= remote write requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -2994,6 +3634,7 @@ }, { "BriefDescription": "Local write requests that miss the SF/LLC and= are sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -3003,6 +3644,7 @@ }, { "BriefDescription": "Remote write requests sent to the CHA's home = agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -3012,8 +3654,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -3021,8 +3665,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -3030,8 +3676,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -3039,8 +3687,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -3048,8 +3698,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -3057,8 +3709,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -3066,8 +3720,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -3075,8 +3731,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -3084,8 +3742,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -3093,95 +3753,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_CHA_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", @@ -3189,8 +3873,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", @@ -3198,8 +3884,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", "UMask": "0x2", @@ -3207,8 +3895,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", @@ -3216,8 +3906,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", @@ -3225,8 +3917,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x40", @@ -3234,8 +3928,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x80", @@ -3243,8 +3939,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3252,8 +3950,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3261,8 +3961,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -3270,8 +3972,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3279,8 +3983,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3288,8 +3994,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3297,8 +4005,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3306,8 +4016,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -3315,16 +4027,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IPQ0 Reject counter was true", "UMask": "0x1", @@ -3332,16 +4048,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3349,16 +4069,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -3366,8 +4090,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3375,16 +4101,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3392,8 +4122,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3401,8 +4133,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -3410,8 +4144,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3419,8 +4155,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3428,8 +4166,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3437,8 +4177,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3446,8 +4188,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -3455,16 +4199,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", "UMask": "0x1", @@ -3472,16 +4220,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3489,24 +4241,30 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3514,16 +4272,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3531,8 +4293,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3540,8 +4304,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -3549,8 +4315,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3558,8 +4326,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3567,8 +4337,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3576,8 +4348,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3585,8 +4359,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -3594,8 +4370,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3603,8 +4381,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3612,8 +4392,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -3621,8 +4403,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3630,8 +4414,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3639,8 +4425,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3648,8 +4436,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3657,8 +4447,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -3666,8 +4458,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -3675,8 +4469,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -3684,8 +4480,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -3693,8 +4491,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -3702,8 +4502,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", @@ -3711,8 +4513,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", @@ -3720,8 +4524,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x40", @@ -3729,8 +4535,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x80", @@ -3738,8 +4546,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", "UMask": "0x1", @@ -3747,8 +4557,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", "UMask": "0x2", @@ -3756,8 +4568,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", "UMask": "0x40", @@ -3765,8 +4579,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3774,8 +4590,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3783,8 +4601,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", "UMask": "0x4", @@ -3792,8 +4612,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", "UMask": "0x8", @@ -3801,8 +4623,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", "UMask": "0x80", @@ -3810,8 +4634,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", "UMask": "0x40", @@ -3819,8 +4645,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", "UMask": "0x1", @@ -3828,8 +4656,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", "UMask": "0x2", @@ -3837,8 +4667,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", "UMask": "0x20", @@ -3846,8 +4678,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", "UMask": "0x4", @@ -3855,8 +4689,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", "UMask": "0x80", @@ -3864,8 +4700,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", "UMask": "0x8", @@ -3873,8 +4711,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", "UMask": "0x10", @@ -3882,8 +4722,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3891,8 +4733,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3900,8 +4744,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -3909,8 +4755,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3918,8 +4766,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3927,8 +4777,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3936,8 +4788,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3945,8 +4799,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -3954,16 +4810,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", "UMask": "0x1", @@ -3971,16 +4831,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3988,16 +4852,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -4005,8 +4873,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -4014,16 +4884,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -4031,8 +4905,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -4040,8 +4916,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", @@ -4049,8 +4927,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -4058,8 +4938,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -4067,8 +4949,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -4076,8 +4960,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -4085,8 +4971,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", "UMask": "0x80", @@ -4094,8 +4982,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x40", @@ -4103,8 +4993,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -4112,8 +5004,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x2", @@ -4121,8 +5015,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -4130,8 +5026,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x4", @@ -4139,8 +5037,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -4148,8 +5048,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -4157,8 +5059,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x10", @@ -4166,8 +5070,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -4175,8 +5081,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -4184,8 +5092,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -4193,8 +5103,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -4202,8 +5114,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -4211,8 +5125,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -4220,8 +5136,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the RRQ (Remote Response Queue) had = to retry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -4229,8 +5147,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -4238,8 +5158,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the RRQ (Remote Response Queue) had t= o retry.", "UMask": "0x40", @@ -4247,8 +5169,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the RRQ (Remote Response Queue) had to retry= . : Any condition listed in the RRQ0 Reject counter was true", "UMask": "0x1", @@ -4256,8 +5180,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -4265,8 +5191,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -4274,8 +5202,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the RRQ (Remote Response Queue) had to= retry.", "UMask": "0x4", @@ -4283,8 +5213,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -4292,8 +5224,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the RRQ (Remote Response Queue) had to = retry. : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -4301,8 +5235,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the RRQ (Remote Response Queue) had to ret= ry.", "UMask": "0x10", @@ -4310,8 +5246,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -4319,8 +5257,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -4328,8 +5268,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -4337,8 +5279,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -4346,8 +5290,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -4355,8 +5301,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -4364,8 +5312,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the WBQ (Writeback Queue) had to ret= ry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -4373,8 +5323,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -4382,8 +5334,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the WBQ (Writeback Queue) had to retr= y.", "UMask": "0x40", @@ -4391,8 +5345,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the WBQ (Writeback Queue) had to retry. : An= y condition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -4400,8 +5356,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -4409,8 +5367,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -4418,8 +5378,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the WBQ (Writeback Queue) had to retry= .", "UMask": "0x4", @@ -4427,8 +5389,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -4436,8 +5400,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the WBQ (Writeback Queue) had to retry.= : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -4445,8 +5411,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -4454,8 +5422,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4463,8 +5433,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -4472,8 +5444,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -4481,8 +5455,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4490,8 +5466,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -4499,8 +5477,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -4508,8 +5488,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4517,8 +5499,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -4526,8 +5510,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -4535,8 +5521,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -4544,8 +5532,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -4553,8 +5543,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4562,8 +5554,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -4571,8 +5565,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -4580,8 +5576,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -4589,8 +5587,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4598,8 +5598,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -4607,8 +5609,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -4616,8 +5620,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -4625,8 +5631,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4634,8 +5642,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -4643,8 +5653,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -4652,8 +5664,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -4661,8 +5675,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -4670,16 +5686,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "CHA" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4687,8 +5707,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -4696,8 +5718,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -4705,8 +5729,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -4714,8 +5740,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -4723,8 +5751,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4732,8 +5762,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -4741,8 +5773,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -4750,8 +5784,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -4759,8 +5795,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4768,8 +5806,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -4777,8 +5817,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -4786,8 +5828,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -4795,8 +5839,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -4804,8 +5850,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4813,8 +5861,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -4822,8 +5872,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -4831,8 +5883,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -4840,6 +5894,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", @@ -4849,6 +5904,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", @@ -4858,6 +5914,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", @@ -4867,8 +5924,10 @@ }, { "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", "UMask": "0x1", @@ -4876,8 +5935,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Local Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f broadcast snoops issued by the HA responding to local requests", "UMask": "0x10", @@ -4885,8 +5946,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Re= quests : Counts the number of snoops issued by the HA. : Counts the number = of broadcast snoops issued by the HA responding to remote requests", "UMask": "0x20", @@ -4894,8 +5957,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA responding to local requests", "UMask": "0x40", @@ -4903,8 +5968,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Remote Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Remote Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f directed snoops issued by the HA responding to remote requests", "UMask": "0x80", @@ -4912,8 +5979,10 @@ }, { "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Snoops sent for Local Requests= : Counts the number of snoops issued by the HA. : Counts the number of bro= adcast or directed snoops issued by the HA responding to local requests", "UMask": "0x4", @@ -4921,8 +5990,10 @@ }, { "BriefDescription": "Snoops Sent : Snoops sent for Remote Requests= ", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Snoops sent for Remote Request= s : Counts the number of snoops issued by the HA. : Counts the number of br= oadcast or directed snoops issued by the HA responding to remote requests", "UMask": "0x8", @@ -4930,8 +6001,10 @@ }, { "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for snoops responses of RspC= onflict. This is returned when a snoop finds an existing outstanding trans= action in a remote caching agent when it CAMs that caching agent. This tri= ggers conflict resolution hardware. This covers both RspCnflct and RspCnfl= ctWbI.", "UMask": "0x40", @@ -4939,8 +6012,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RspFwd : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspFwd t= o a CA request. This snoop response is only possible for RdCur when a snoo= p HITM/E in a remote caching agent and it directly forwards data to a reque= stor without changing the requestor's cache line state.", "UMask": "0x80", @@ -4948,8 +6023,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for a snoop response of Rsp*= Fwd*WB. This snoop response is only used in 4s systems. It is used when a= snoop HITM's in a remote caching agent and it directly forwards data to a = requestor, and simultaneously returns data to the home to be written back t= o memory.", "UMask": "0x20", @@ -4957,8 +6034,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspI Snoop Response was received which indicates the remote cache does n= ot have the data, or when the remote cache silently evicts data (such as wh= en an RFO: the Read for Ownership issued before a write hits non-modified d= ata).", "UMask": "0x1", @@ -4966,8 +6045,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspIFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data and the requesting agent is able to acquire the dat= a in E (Exclusive) or M (modified) states. This is commonly returned with = RFO (the Read for Ownership issued before a write) transactions. The snoop= could have either been to a cacheline in the M,E,F (Modified, Exclusive or= Forward) states.", "UMask": "0x4", @@ -4975,8 +6056,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspS Snoop Response was received which indicates when a remote cache has= data but is not forwarding it. It is a way to let the requesting socket k= now that it cannot allocate the data in E state. No data is sent with S Rs= pS.", "UMask": "0x2", @@ -4984,8 +6067,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspSFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data but held on to its current copy. This is common fo= r data and code reads that hit in a remote socket in E (Exclusive) or F (Fo= rward) state.", "UMask": "0x8", @@ -4993,8 +6078,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspIWB o= r RspSWB. This is returned when a non-RFO request hits in M state. Data a= nd Code Reads can return either RspIWB or RspSWB depending on how the syste= m has been configured. InvItoE transactions will also return RspIWB becaus= e they must acquire ownership.", "UMask": "0x10", @@ -5002,8 +6089,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", "UMask": "0x40", @@ -5011,8 +6100,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", "UMask": "0x80", @@ -5020,8 +6111,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", "UMask": "0x20", @@ -5029,8 +6122,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", "UMask": "0x1", @@ -5038,8 +6133,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -5047,8 +6144,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", "UMask": "0x2", @@ -5056,8 +6155,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its currently copy. This is c= ommon for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", @@ -5065,8 +6166,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", "UMask": "0x10", @@ -5074,56 +6177,70 @@ }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5131,8 +6248,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5140,8 +6259,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5149,8 +6270,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -5158,8 +6281,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -5167,8 +6292,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -5176,8 +6303,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -5185,8 +6314,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -5194,8 +6325,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5203,8 +6336,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5212,8 +6347,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5221,8 +6358,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -5230,8 +6369,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -5239,8 +6380,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -5248,8 +6391,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -5257,8 +6402,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -5266,8 +6413,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5275,8 +6424,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5284,8 +6435,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5293,8 +6446,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -5302,8 +6457,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -5311,8 +6468,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -5320,8 +6479,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -5329,8 +6490,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -5338,8 +6501,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5347,8 +6512,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5356,8 +6523,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5365,8 +6534,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -5374,8 +6545,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -5383,8 +6556,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -5392,8 +6567,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -5401,8 +6578,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -5410,8 +6589,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5419,8 +6600,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5428,8 +6611,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5437,8 +6622,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5446,8 +6633,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5455,8 +6644,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5464,8 +6655,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5473,8 +6666,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5482,8 +6677,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5491,8 +6688,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -5500,8 +6699,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -5509,8 +6710,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -5518,8 +6721,10 @@ }, { "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0xc001ffff", @@ -5527,24 +6732,30 @@ }, { "BriefDescription": "TOR Inserts : DDR4 Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DDR4 Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts. : TOR allocation occurred as a result of SF/LLC e= victions (came from the ISMQ)", "UMask": "0x2", @@ -5552,14 +6763,17 @@ }, { "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All requests from iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -5569,6 +6783,7 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -5578,8 +6793,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -5587,6 +6804,7 @@ }, { "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -5596,8 +6814,10 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", "UMask": "0xc88fff01", @@ -5605,8 +6825,10 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRds issued by iA Cores : Coun= ts the number of entries successfully inserted into the TOR that match qual= ifications specified by the subevent. Does not include addressless reques= ts such as locks and interrupts.", "UMask": "0xc817ff01", @@ -5614,8 +6836,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -5623,8 +6847,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores : = Counts the number of entries successfully inserted into the TOR that match = qualifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "UMask": "0xc827ff01", @@ -5632,8 +6858,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es : Counts the number of entries successfully inserted into the TOR that m= atch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", "UMask": "0xc8a7ff01", @@ -5641,6 +6869,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", "PerPkg": "1", @@ -5650,6 +6879,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -5659,6 +6889,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -5668,6 +6899,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -5677,6 +6909,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", "PerPkg": "1", @@ -5686,8 +6919,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837fd01", @@ -5695,8 +6930,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opts issued by iA Cores th= at hit the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xc827fd01", @@ -5704,8 +6941,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that hit the LLC : Counts the number of entries successfully inserted in= to the TOR that match qualifications specified by the subevent. Does not = include addressless requests such as locks and interrupts.", "UMask": "0xc8a7fd01", @@ -5713,6 +6952,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores th= at Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", "PerPkg": "1", @@ -5722,8 +6962,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that H= it LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that = Hit LLC : Counts the number of entries successfully inserted into the TOR t= hat match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -5731,8 +6973,10 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores = that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= that hit the LLC : Counts the number of entries successfully inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", "UMask": "0xcccffd01", @@ -5740,17 +6984,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xcccffd01", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores = that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : LLCPrefData issued by iA Cores= that hit the LLC : Counts the number of entries successfully inserted into= the TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", "UMask": "0xccd7fd01", @@ -5758,15 +7006,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xccd7fd01", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -5776,6 +7027,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -5785,6 +7037,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -5794,8 +7047,10 @@ }, { "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores th= at hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_SPECITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores t= hat missed the LLC : Counts the number of entries successfully inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xcc57fd01", @@ -5803,8 +7058,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xcc47ff01", @@ -5812,8 +7069,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cor= es", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : ItoMCacheNears issued by iA Co= res : Counts the number of entries successfully inserted into the TOR that = match qualifications specified by the subevent. Does not include addressl= ess requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -5821,8 +7080,10 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xcccfff01", @@ -5830,6 +7091,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", "PerPkg": "1", @@ -5839,6 +7101,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", "PerPkg": "1", @@ -5848,6 +7111,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -5857,6 +7121,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -5866,8 +7131,10 @@ }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Mi= ssed the LLC - HOMed locally : Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80efe01", @@ -5875,6 +7142,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -5884,8 +7152,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC - HOMed locally : Counts the number of entries successfu= lly inserted into the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88efe01", @@ -5893,8 +7163,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CRd_Prefs issued by iA Cores t= hat Missed the LLC - HOMed remotely : Counts the number of entries successf= ully inserted into the TOR that match qualifications specified by the subev= ent. Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88f7e01", @@ -5902,8 +7174,10 @@ }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CRd issued by iA Cores that Mi= ssed the LLC - HOMed remotely : Counts the number of entries successfully i= nserted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80f7e01", @@ -5911,6 +7185,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", "PerPkg": "1", @@ -5920,8 +7195,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc837fe01", @@ -5929,6 +7206,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -5938,6 +7216,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -5947,6 +7226,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", @@ -5956,6 +7236,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", "PerPkg": "1", @@ -5965,8 +7246,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opt issued by iA Cores tha= t missed the LLC : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc827fe01", @@ -5974,8 +7257,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Cor= es that missed the LLC : Counts the number of entries successfully inserted= into the TOR that match qualifications specified by the subevent. Does n= ot include addressless requests such as locks and interrupts.", "UMask": "0xc8a7fe01", @@ -5983,6 +7268,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -5992,6 +7278,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", "PerPkg": "1", @@ -6001,8 +7288,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc8978601", @@ -6010,6 +7299,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", "PerPkg": "1", @@ -6019,8 +7309,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC - HOMed locally : Counts the number of= entries successfully inserted into the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc8968601", @@ -6028,8 +7320,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC - HOMed locally : Counts the number of= entries successfully inserted into the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc8968a01", @@ -6037,8 +7331,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc8978a01", @@ -6046,6 +7342,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", "PerPkg": "1", @@ -6055,8 +7352,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting DDR Mem that Missed the LLC - HOMed remotely : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc8970601", @@ -6064,8 +7363,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd_Prefs issued by iA Cores t= argeting PMM Mem that Missed the LLC - HOMed remotely : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc8970a01", @@ -6073,6 +7374,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -6082,6 +7384,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", @@ -6091,6 +7394,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", "PerPkg": "1", @@ -6100,6 +7404,7 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", @@ -6109,8 +7414,10 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8678601", @@ -6118,17 +7425,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_DRAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8678601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_= DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8668601", @@ -6136,17 +7447,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_= DRAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8668601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_LOCAL_= PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8668a01", @@ -6154,8 +7469,10 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8678a01", @@ -6163,8 +7480,10 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE= _DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8670601", @@ -6172,17 +7491,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE= _DRAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8670601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR_REMOTE= _PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc8670a01", @@ -6190,8 +7513,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that M= issed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : ItoMs issued by iA Cores that = Missed LLC : Counts the number of entries successfully inserted into the TO= R that match qualifications specified by the subevent. Does not include a= ddressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -6199,8 +7524,10 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefCode issued by iA Cores = that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : LLCPrefCode issued by iA Cores= that missed the LLC : Counts the number of entries successfully inserted i= nto the TOR that match qualifications specified by the subevent. Does not= include addressless requests such as locks and interrupts.", "UMask": "0xcccffe01", @@ -6208,6 +7535,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefData issued by iA Cores = that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -6217,6 +7545,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -6226,8 +7555,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC - HOMed locally : Counts the number of entrie= s successfully inserted into the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and in= terrupts.", "UMask": "0xc8668601", @@ -6235,8 +7566,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally : Counts the number of entrie= s successfully inserted into the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and in= terrupts.", "UMask": "0xc8668a01", @@ -6244,8 +7577,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC - HOMed locally : Counts the number of entries= successfully inserted into the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc86e8601", @@ -6253,8 +7588,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally : Counts the number of entries= successfully inserted into the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc86e8a01", @@ -6262,6 +7599,7 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", "PerPkg": "1", @@ -6271,8 +7609,10 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DDR= ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86f8601", @@ -6280,17 +7620,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_DRA= M", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc86f8601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOC= AL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86e8601", @@ -6298,17 +7642,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOC= AL_DRAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc86e8601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_LOC= AL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86e8a01", @@ -6316,8 +7664,10 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_PMM= ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86f8a01", @@ -6325,8 +7675,10 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REM= OTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86f0601", @@ -6334,17 +7686,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REM= OTE_DRAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc86f0601", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR_REM= OTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read from local IA that mi= sses in the snoop filter", "UMask": "0xc86f0a01", @@ -6352,8 +7708,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC - HOMed remotely : Counts the number of entri= es successfully inserted into the TOR that match qualifications specified b= y the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc8670601", @@ -6361,8 +7719,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely : Counts the number of entri= es successfully inserted into the TOR that match qualifications specified b= y the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc8670a01", @@ -6370,8 +7730,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC - HOMed remotely : Counts the number of entrie= s successfully inserted into the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and in= terrupts.", "UMask": "0xc86f0601", @@ -6379,8 +7741,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remotely : Counts the number of entrie= s successfully inserted into the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and in= terrupts.", "UMask": "0xc86f0a01", @@ -6388,6 +7752,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -6397,6 +7762,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -6406,6 +7772,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -6415,6 +7782,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -6424,6 +7792,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -6433,6 +7802,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -6442,8 +7812,10 @@ }, { "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores th= at missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_SPECITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SpecItoMs issued by iA Cores t= hat missed the LLC : Counts the number of entries successfully inserted int= o the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xcc57fe01", @@ -6451,8 +7823,10 @@ }, { "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : UCRdFs issued by iA Cores that= Missed LLC : Counts the number of entries successfully inserted into the T= OR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -6460,8 +7834,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores that = Missed the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -6469,8 +7845,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores that = Missed the LLC : Counts the number of entries successfully inserted into th= e TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -6478,8 +7856,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting DDR that missed the LLC : Counts the number of entries successfully i= nserted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678601", @@ -6487,8 +7867,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC : Counts the number of entries successfully i= nserted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678a01", @@ -6496,8 +7878,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting DDR that missed the LLC : Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8601", @@ -6505,8 +7889,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC : Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8a01", @@ -6514,8 +7900,10 @@ }, { "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WiLs issued by iA Cores that M= issed LLC : Counts the number of entries successfully inserted into the TOR= that match qualifications specified by the subevent. Does not include ad= dressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -6523,6 +7911,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -6532,6 +7921,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -6541,6 +7931,7 @@ }, { "BriefDescription": "TOR Inserts : SpecItoMs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", "PerPkg": "1", @@ -6550,8 +7941,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc3fff01", @@ -6559,8 +7952,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc37ff01", @@ -6568,8 +7963,10 @@ }, { "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc2fff01", @@ -6577,8 +7974,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -6586,8 +7985,10 @@ }, { "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc67ff01", @@ -6595,8 +7996,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc86fff01", @@ -6604,8 +8007,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc867ff01", @@ -6613,6 +8018,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", @@ -6622,8 +8028,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -6631,6 +8039,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -6640,6 +8049,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -6649,6 +8059,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -6658,6 +8069,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -6667,8 +8079,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= hit the LLC : Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -6676,6 +8090,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -6685,6 +8100,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -6694,6 +8110,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices to locally HOMed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", "PerPkg": "1", @@ -6703,6 +8120,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices to remotely HOMed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", "PerPkg": "1", @@ -6712,6 +8130,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to l= ocally HOMed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", "PerPkg": "1", @@ -6721,6 +8140,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices to r= emotely HOMed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", "PerPkg": "1", @@ -6730,6 +8150,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -6739,6 +8160,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -6748,6 +8170,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -6757,6 +8180,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -6766,8 +8190,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= missed the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -6775,6 +8201,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -6784,6 +8211,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", "PerPkg": "1", @@ -6793,6 +8221,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", "PerPkg": "1", @@ -6802,8 +8231,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Co= unts the number of entries successfully inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -6811,8 +8242,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -6820,8 +8253,10 @@ }, { "BriefDescription": "TOR Inserts : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IPQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0x8", @@ -6829,8 +8264,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts. : From an iA Core", "UMask": "0x1", @@ -6838,8 +8275,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "UMask": "0x10", @@ -6847,24 +8286,30 @@ }, { "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts. : All locally initiated requests", "UMask": "0xc000ff05", @@ -6872,8 +8317,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally initiated requests from iA Cores", "UMask": "0xc000ff01", @@ -6881,8 +8328,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally generated IO traffic", "UMask": "0xc000ff04", @@ -6890,72 +8339,90 @@ }, { "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent. Do= es not include addressless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests such = as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PMM Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PMM Access : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event. Does not include addressless requests such as locks and interrupts= .", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. Does not include addressless requests such as lo= cks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -6963,8 +8430,10 @@ }, { "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent. Does not include addressless requests such a= s locks and interrupts.", "UMask": "0x20", @@ -6972,16 +8441,20 @@ }, { "BriefDescription": "TOR Inserts : Just Remote Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Remote Targets : Counts t= he number of entries successfully inserted into the TOR that match qualific= ations specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RRQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0x40", @@ -6989,8 +8462,10 @@ }, { "BriefDescription": "TOR Inserts : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WBQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0x80", @@ -6998,16 +8473,20 @@ }, { "BriefDescription": "TOR Occupancy : DDR4 Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts. : TOR allocation occurred as a = result of SF/LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -7015,14 +8494,17 @@ }, { "BriefDescription": "TOR Occupancy : Just Hits", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -7032,8 +8514,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc8c7ff01", @@ -7041,8 +8525,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -7050,6 +8536,7 @@ }, { "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -7059,8 +8546,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88fff01", @@ -7068,6 +8557,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", "PerPkg": "1", @@ -7077,8 +8567,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -7086,8 +8578,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = : For each cycle, this event accumulates the number of valid entries in the= TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", "UMask": "0xc827ff01", @@ -7095,8 +8589,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores : For each cycle, this event accumulates the number of valid entries i= n the TOR that match qualifications specified by the subevent. Does not= include addressless requests such as locks and interrupts.", "UMask": "0xc8a7ff01", @@ -7104,8 +8600,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc897ff01", @@ -7113,6 +8611,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -7122,8 +8621,10 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80ffd01", @@ -7131,8 +8632,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88ffd01", @@ -7140,8 +8643,10 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRds issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc817fd01", @@ -7149,8 +8654,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that hit the LLC : For each cycle, this event accumulates = the number of valid entries in the TOR that match qualifications specified = by the subevent. Does not include addressless requests such as locks an= d interrupts.", "UMask": "0xc837fd01", @@ -7158,8 +8665,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = that hit the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc827fd01", @@ -7167,8 +8676,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that hit the LLC : For each cycle, this event accumulates the number o= f valid entries in the TOR that match qualifications specified by the subev= ent. Does not include addressless requests such as locks and interrupts= .", "UMask": "0xc8a7fd01", @@ -7176,8 +8687,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = that Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= that Hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc897fd01", @@ -7185,8 +8698,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Hit LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Hit LLC : For each cycle, this event accumulates the number of valid entr= ies in the TOR that match qualifications specified by the subevent. Doe= s not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -7194,8 +8709,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Core= s that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts.", "UMask": "0xcccffd01", @@ -7203,8 +8720,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Core= s that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts.", "UMask": "0xccd7fd01", @@ -7212,8 +8731,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s that hit the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xccc7fd01", @@ -7221,8 +8742,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc807fd01", @@ -7230,8 +8753,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc887fd01", @@ -7239,8 +8764,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc47ff01", @@ -7248,8 +8775,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA C= ores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA = Cores : For each cycle, this event accumulates the number of valid entries = in the TOR that match qualifications specified by the subevent. Does no= t include addressless requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -7257,8 +8786,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xcccfff01", @@ -7266,8 +8797,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xccd7ff01", @@ -7275,8 +8808,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s : For each cycle, this event accumulates the number of valid entries in t= he TOR that match qualifications specified by the subevent. Does not in= clude addressless requests such as locks and interrupts.", "UMask": "0xccc7ff01", @@ -7284,6 +8819,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -7293,6 +8829,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -7302,8 +8839,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed locally : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc80efe01", @@ -7311,8 +8850,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc88ffe01", @@ -7320,8 +8861,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed locally : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc88efe01", @@ -7329,8 +8872,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely : For each cycle, this event accumula= tes the number of valid entries in the TOR that match qualifications specif= ied by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc88f7e01", @@ -7338,8 +8883,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed remotely : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc80f7e01", @@ -7347,6 +8894,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "PerPkg": "1", @@ -7356,8 +8904,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that missed the LLC : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc837fe01", @@ -7365,6 +8915,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -7374,6 +8925,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -7383,8 +8935,10 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting DDR Mem that Missed the LLC - HOMed locally : For each cycle, this ev= ent accumulates the number of valid entries in the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests = such as locks and interrupts.", "UMask": "0xc8168601", @@ -7392,8 +8946,10 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting PMM Mem that Missed the LLC - HOMed locally : For each cycle, this ev= ent accumulates the number of valid entries in the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests = such as locks and interrupts.", "UMask": "0xc8168a01", @@ -7401,8 +8957,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc827fe01", @@ -7410,8 +8968,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC : For each cycle, this event accumulates the numbe= r of valid entries in the TOR that match qualifications specified by the su= bevent. Does not include addressless requests such as locks and interru= pts.", "UMask": "0xc8a7fe01", @@ -7419,6 +8979,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -7428,8 +8989,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc897fe01", @@ -7437,8 +9000,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978601", @@ -7446,8 +9011,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc896fe01", @@ -7455,8 +9022,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968601", @@ -7464,8 +9033,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968a01", @@ -7473,8 +9044,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978a01", @@ -7482,8 +9055,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc8977e01", @@ -7491,8 +9066,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970601", @@ -7500,8 +9077,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970a01", @@ -7509,6 +9088,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -7518,8 +9098,10 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. Does not include addressless requests= such as locks and interrupts.", "UMask": "0xc8170601", @@ -7527,8 +9109,10 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRds issued by iA Cores targ= eting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. Does not include addressless requests= such as locks and interrupts.", "UMask": "0xc8170a01", @@ -7536,8 +9120,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc867fe01", @@ -7545,8 +9131,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8678601", @@ -7554,8 +9142,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCA= L_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8668601", @@ -7563,8 +9153,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_LOCA= L_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8668a01", @@ -7572,8 +9164,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8678a01", @@ -7581,8 +9175,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMO= TE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8670601", @@ -7590,8 +9186,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR_REMO= TE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc8670a01", @@ -7599,8 +9197,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Missed LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -7608,8 +9208,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefCode issued by iA Core= s that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefCode issued by iA Cor= es that missed the LLC : For each cycle, this event accumulates the number = of valid entries in the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupt= s.", "UMask": "0xcccffe01", @@ -7617,8 +9219,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefData issued by iA Core= s that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefData issued by iA Cor= es that missed the LLC : For each cycle, this event accumulates the number = of valid entries in the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupt= s.", "UMask": "0xccd7fe01", @@ -7626,8 +9230,10 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : LLCPrefRFO issued by iA Core= s that missed the LLC : For each cycle, this event accumulates the number o= f valid entries in the TOR that match qualifications specified by the subev= ent. Does not include addressless requests such as locks and interrupts= .", "UMask": "0xccc7fe01", @@ -7635,8 +9241,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668601", @@ -7644,8 +9252,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668a01", @@ -7653,8 +9263,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8601", @@ -7662,8 +9274,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8a01", @@ -7671,8 +9285,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86ffe01", @@ -7680,8 +9296,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_D= DR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86f8601", @@ -7689,8 +9307,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_L= OCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86e8601", @@ -7698,8 +9318,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_L= OCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86e8a01", @@ -7707,8 +9329,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_P= MM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86f8a01", @@ -7716,8 +9340,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_R= EMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86f0601", @@ -7725,8 +9351,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR_R= EMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86f0a01", @@ -7734,8 +9362,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670601", @@ -7743,8 +9373,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670a01", @@ -7752,8 +9384,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0601", @@ -7761,8 +9395,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0a01", @@ -7770,6 +9406,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -7779,8 +9416,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC - HOMed locally : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc806fe01", @@ -7788,8 +9427,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc887fe01", @@ -7797,8 +9438,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC - HOMed locally : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc886fe01", @@ -7806,8 +9449,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely : For each cycle, this event accumula= tes the number of valid entries in the TOR that match qualifications specif= ied by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc8877e01", @@ -7815,8 +9460,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Missed the LLC - HOMed remotely : For each cycle, this event accumulates t= he number of valid entries in the TOR that match qualifications specified b= y the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0xc8077e01", @@ -7824,8 +9471,10 @@ }, { "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores = that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_SPECITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores= that missed the LLC: For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc57fe01", @@ -7833,8 +9482,10 @@ }, { "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -7842,8 +9493,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -7851,8 +9504,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -7860,8 +9515,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678601", @@ -7869,8 +9526,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678a01", @@ -7878,8 +9537,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8601", @@ -7887,8 +9548,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8a01", @@ -7896,8 +9559,10 @@ }, { "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -7905,6 +9570,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -7914,8 +9580,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc887ff01", @@ -7923,8 +9591,10 @@ }, { "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SpecItoMs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc57ff01", @@ -7932,8 +9602,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -7941,8 +9613,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -7950,8 +9624,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -7959,6 +9635,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", @@ -7968,8 +9645,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -7977,6 +9656,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", @@ -7986,8 +9666,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fd04", @@ -7995,8 +9677,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that hit the LLC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "UMask": "0xcd43fd04", @@ -8004,8 +9688,10 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8f3fd04", @@ -8013,8 +9699,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -8022,8 +9710,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc43ff04", @@ -8031,8 +9721,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "UMask": "0xcd43ff04", @@ -8040,6 +9732,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", @@ -8049,8 +9742,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fe04", @@ -8058,8 +9753,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xcd43fe04", @@ -8067,6 +9764,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -8076,8 +9774,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -8085,6 +9785,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -8094,8 +9795,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -8103,8 +9806,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -8112,8 +9817,10 @@ }, { "BriefDescription": "TOR Occupancy : IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. Does not include addressless requests= such as locks and interrupts.", "UMask": "0x8", @@ -8121,8 +9828,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts. : From an iA Core", "UMask": "0x1", @@ -8130,8 +9839,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0x10", @@ -8139,24 +9850,30 @@ }, { "BriefDescription": "TOR Occupancy : Just ISOC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Local Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. Does not include addre= ssless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts. : All locally initiated= requests", "UMask": "0xc000ff05", @@ -8164,8 +9881,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally initiated reques= ts from iA Cores", "UMask": "0xc000ff01", @@ -8173,8 +9892,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally generated IO tra= ffic", "UMask": "0xc000ff04", @@ -8182,72 +9903,90 @@ }, { "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Misses", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMCFG Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NonCoherent", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NotNearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. Does not include addressl= ess requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PMM Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PMM Access : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -8255,8 +9994,10 @@ }, { "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", "UMask": "0x20", @@ -8264,16 +10005,20 @@ }, { "BriefDescription": "TOR Occupancy : Just Remote Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Remote Targets : For ea= ch cycle, this event accumulates the number of valid entries in the TOR tha= t match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8281,8 +10026,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -8290,8 +10037,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -8299,8 +10048,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8308,8 +10059,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -8317,8 +10070,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -8326,8 +10081,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8335,8 +10092,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -8344,8 +10103,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -8353,8 +10114,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -8362,8 +10125,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -8371,8 +10136,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8380,8 +10147,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -8389,8 +10158,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -8398,8 +10169,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -8407,8 +10180,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8416,8 +10191,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -8425,8 +10202,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -8434,8 +10213,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -8443,8 +10224,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -8452,8 +10235,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8461,8 +10246,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -8470,8 +10257,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -8479,8 +10268,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -8488,8 +10279,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8497,8 +10290,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -8506,8 +10301,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8515,8 +10312,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -8524,8 +10323,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -8533,8 +10334,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8542,8 +10345,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -8551,8 +10356,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8560,8 +10367,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -8569,8 +10378,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8578,8 +10389,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -8587,8 +10400,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -8596,8 +10411,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -8605,8 +10422,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -8614,8 +10433,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8623,8 +10444,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -8632,8 +10455,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -8641,8 +10466,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -8650,8 +10477,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -8659,8 +10488,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -8668,8 +10499,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -8677,8 +10510,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -8686,8 +10521,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -8695,8 +10532,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -8704,8 +10543,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -8713,8 +10554,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -8722,8 +10565,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -8731,8 +10576,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8740,8 +10587,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -8749,8 +10598,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -8758,8 +10609,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8767,8 +10620,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -8776,8 +10631,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8785,8 +10642,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -8794,8 +10653,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -8803,8 +10664,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8812,8 +10675,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -8821,8 +10686,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -8830,8 +10697,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -8839,8 +10708,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -8848,8 +10719,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -8857,8 +10730,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -8866,8 +10741,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -8875,8 +10752,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -8884,8 +10763,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -8893,8 +10774,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -8902,8 +10785,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -8911,8 +10796,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -8920,8 +10807,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -8929,8 +10818,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -8938,8 +10829,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -8947,8 +10840,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -8956,8 +10851,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -8965,8 +10862,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -8974,8 +10873,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -8983,8 +10884,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -8992,8 +10895,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9001,8 +10906,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -9010,8 +10917,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9019,8 +10928,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -9028,8 +10939,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -9037,8 +10950,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -9046,8 +10961,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -9055,8 +10972,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9064,8 +10983,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9073,8 +10994,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -9082,8 +11005,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -9091,8 +11016,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9100,8 +11027,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -9109,8 +11038,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -9118,8 +11049,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -9127,8 +11060,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9136,8 +11071,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -9145,8 +11082,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9154,8 +11093,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9163,8 +11104,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -9172,8 +11115,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -9181,8 +11126,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -9190,8 +11137,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -9199,8 +11148,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -9208,8 +11159,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -9217,8 +11170,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9226,8 +11181,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -9235,8 +11192,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -9244,8 +11203,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -9253,8 +11214,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -9262,8 +11225,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -9271,8 +11236,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -9280,8 +11247,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -9289,8 +11258,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -9298,8 +11269,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -9307,8 +11280,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -9316,8 +11291,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9325,8 +11302,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -9334,8 +11313,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -9343,8 +11324,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -9352,8 +11335,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -9361,8 +11346,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -9370,8 +11357,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -9379,8 +11368,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -9388,8 +11379,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -9397,8 +11390,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -9406,8 +11401,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -9415,8 +11412,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -9424,8 +11423,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -9433,8 +11434,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -9442,8 +11445,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -9451,8 +11456,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -9460,8 +11467,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -9469,8 +11478,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -9478,8 +11489,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -9487,8 +11500,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9496,8 +11511,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9505,8 +11522,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9514,8 +11533,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9523,8 +11544,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9532,8 +11555,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9541,8 +11566,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9550,8 +11577,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9559,8 +11588,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9568,8 +11599,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9577,8 +11610,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9586,8 +11621,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9595,8 +11632,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9604,8 +11643,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9613,8 +11654,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -9622,8 +11665,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -9631,8 +11676,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -9640,8 +11687,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -9649,8 +11698,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9658,8 +11709,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9667,8 +11720,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9676,8 +11731,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9685,8 +11742,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", "UMask": "0x1", @@ -9694,8 +11753,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", "UMask": "0x2", @@ -9703,8 +11764,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", "UMask": "0x1", @@ -9712,8 +11775,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", "UMask": "0x2", @@ -9721,40 +11786,50 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", "UMask": "0x4", @@ -9762,8 +11837,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", "UMask": "0x8", @@ -9771,8 +11848,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", "UMask": "0x10", @@ -9780,8 +11859,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", "UMask": "0x20", @@ -9789,8 +11870,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 6 only.", "UMask": "0x40", @@ -9798,8 +11881,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 7 only.", "UMask": "0x80", @@ -9807,24 +11892,30 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x8", @@ -9832,8 +11923,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x4", @@ -9841,8 +11934,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x80", @@ -9850,8 +11945,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x40", @@ -9859,8 +11956,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", "UMask": "0x1", @@ -9868,8 +11967,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", "UMask": "0x10", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.js= on b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json index 6997e6f7d366..97bec6cfc79c 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total Write Cache Occupancy : Any Source", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Any Source : A= ccumulates the number of reads and writes that are outstanding in the uncor= e in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRI= TE_OCCUPANCY events. : Tracks all requests from any source port.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "Total Write Cache Occupancy : Snoops", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Snoops : Accum= ulates the number of reads and writes that are outstanding in the uncore in= each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_O= CCUPANCY events.", "UMask": "0x2", @@ -19,6 +23,7 @@ }, { "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", "EventCode": "0x0f", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", @@ -28,6 +33,7 @@ }, { "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "Counter": "0,1", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -35,8 +41,10 @@ }, { "BriefDescription": "Coherent Ops : CLFlush", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Coherent Ops : CLFlush : Counts the number o= f coherency related operations serviced by the IRP", "UMask": "0x80", @@ -44,6 +52,7 @@ }, { "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -53,8 +62,10 @@ }, { "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RFO request issued by the IRP unit to the me= sh with the intention of writing a partial cacheline to coherent memory. R= FO is a Read For Ownership command that requests ownership of the cacheline= and moves data from the mesh to IRP cache.", "UMask": "0x8", @@ -62,6 +73,7 @@ }, { "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -71,6 +83,7 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", @@ -78,6 +91,7 @@ }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -86,6 +100,7 @@ }, { "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -94,6 +109,7 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", @@ -101,14 +117,17 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.EVICTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", @@ -117,78 +136,97 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -198,8 +236,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", @@ -207,8 +247,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", "UMask": "0x40", @@ -216,8 +258,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", "UMask": "0x4", @@ -225,8 +269,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", @@ -234,8 +280,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", @@ -243,8 +291,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", @@ -252,88 +302,110 @@ }, { "BriefDescription": "P2P Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_P2P_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Requests : P2P requests from the ITC", "Unit": "IRP" }, { "BriefDescription": "P2P Occupancy", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_P2P_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P completions", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local and target = matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Message", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P reads", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : Match if remote only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if remote and target= matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Writes", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -341,8 +413,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -350,8 +424,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -359,6 +435,7 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", @@ -368,8 +445,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -377,64 +456,80 @@ }, { "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound Transaction Count : Atomic", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Atomic : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks the number of atomic transactions", "UMask": "0x10", @@ -442,8 +537,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Other", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Other : Counts t= he number of Inbound transactions from the IRP to the Uncore. This can be = filtered based on request type in addition to the source queue. Note the s= pecial filtering equation. We do OR-reduction on the request type. If the= SOURCE bit is set, then we also do AND qualification based on the source p= ortID. : Tracks the number of 'other' kinds of transactions.", "UMask": "0x20", @@ -451,8 +548,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Writes", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WRITES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Writes : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks only write requests. Each write request should have a pre= fetch, so there is no need to explicitly track these requests. For writes = that are tickled and have to retry, the counter will be incremented for eac= h retry.", "UMask": "0x2", @@ -460,6 +559,7 @@ }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -469,134 +569,170 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0x0B", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x05", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x08", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x06", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x09", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x07", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x04", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x0A", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count= as 2", "Unit": "IRP" }, { "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1B", "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0D", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0E", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0x0C", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Request Queue Occupancy : Accumulat= es the number of outstanding outbound requests from the IRP to the switch (= towards the devices). This can be used in conjunction with the allocations= event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -604,8 +740,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -613,8 +751,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -622,8 +762,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -631,8 +773,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -640,8 +784,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -649,8 +795,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -658,8 +806,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -667,8 +817,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -676,8 +828,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -685,8 +839,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -694,8 +850,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -703,8 +861,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -712,8 +872,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -721,8 +883,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -730,8 +894,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -739,8 +905,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -748,8 +916,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -757,8 +927,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -766,8 +938,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -775,8 +949,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -784,8 +960,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -793,8 +971,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -802,8 +982,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -811,8 +993,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -820,8 +1004,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -829,8 +1015,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -838,8 +1026,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -847,8 +1037,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -856,8 +1048,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -865,8 +1059,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -874,8 +1070,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -883,8 +1081,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -892,8 +1092,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -901,8 +1103,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -910,8 +1114,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -919,8 +1125,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -928,8 +1136,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -937,8 +1147,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -946,8 +1158,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -955,8 +1169,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -964,8 +1180,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -973,8 +1191,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -982,8 +1202,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -991,8 +1213,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1000,8 +1224,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1009,8 +1235,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1018,8 +1246,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1027,8 +1257,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1036,8 +1268,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1045,8 +1279,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1054,8 +1290,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1063,8 +1301,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1072,8 +1312,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1081,8 +1323,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1090,8 +1334,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1099,8 +1345,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1108,8 +1356,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1117,8 +1367,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1126,8 +1378,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1135,8 +1389,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1144,8 +1400,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1153,8 +1411,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1162,8 +1422,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1171,8 +1433,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1180,8 +1444,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1189,8 +1455,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1198,8 +1466,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1207,8 +1477,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1216,8 +1488,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1225,8 +1499,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1234,8 +1510,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1243,8 +1521,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1252,8 +1532,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1261,8 +1543,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1270,8 +1554,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1279,8 +1565,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1288,8 +1576,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1297,8 +1587,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1306,8 +1598,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1315,8 +1609,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1324,8 +1620,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1333,8 +1631,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1342,8 +1642,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1351,8 +1653,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1360,8 +1664,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1369,8 +1675,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1378,8 +1686,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1387,44 +1697,54 @@ }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", @@ -1432,113 +1752,142 @@ }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles when Direct2UPI was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Clockticks of the mesh to PCI (M2P)", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Lookups : Fo= und in any state", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -1547,6 +1896,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Lookups : Fo= und in A state", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -1555,6 +1905,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Lookups : Fo= und in I state", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -1563,6 +1914,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Lookups : Fo= und in S state", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -1571,70 +1923,87 @@ }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Updates : Fr= om/to any state. Note: event counts are incorrect in 2LM mode.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1643,8 +2012,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1652,8 +2023,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1661,8 +2034,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1670,8 +2045,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1679,8 +2056,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1688,8 +2067,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : If the CHA TOR has too many PMM transactions, this signal will th= rottle outgoing MS2IDI traffic", "UMask": "0x10", @@ -1697,8 +2078,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.PMM_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If another CHA TOR has too many PMM transactions, this signal wi= ll throttle outgoing MS2IDI traffic", "UMask": "0x20", @@ -1706,8 +2089,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1715,22 +2100,28 @@ }, { "BriefDescription": "UNC_M2M_DISTRESS_PMM", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "UNC_M2M_DISTRESS_PMM", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "UNC_M2M_DISTRESS_PMM_MEMMODE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1738,8 +2129,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1747,8 +2140,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1756,8 +2151,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1765,8 +2162,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1774,8 +2173,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1783,8 +2184,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1792,8 +2195,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1801,8 +2206,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1810,8 +2217,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1819,8 +2228,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1828,8 +2239,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1837,8 +2250,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1846,8 +2261,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1855,8 +2272,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1864,8 +2283,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1873,8 +2294,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1882,8 +2305,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1891,8 +2316,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1900,8 +2327,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1909,64 +2338,80 @@ }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x704", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cach= e - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch0 : Counts= all PMM dimm read requests(full line) sent from M2M to iMC", "UMask": "0x120", @@ -1974,56 +2419,70 @@ }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x201", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cach= e - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x210", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x208", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : PMM - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2M Reads Issued to iMC : PMM - Ch1 : Counts= all PMM dimm read requests(full line) sent from M2M to iMC", "UMask": "0x220", @@ -2031,54 +2490,67 @@ }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch2", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH2_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x440", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Chan= nels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x740", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x702", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - A= ll Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x701", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR, acting as Cach= e - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x710", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : DDR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x708", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : PMM - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.TO_PMM", "PerPkg": "1", @@ -2087,93 +2559,117 @@ }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - All C= hannels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c10", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x410", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x401", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x404", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch= 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x402", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x408", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cac= he - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x440", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x420", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch0 : Count= s all PMM dimm writes requests(full line and partial) sent from M2M to iMC", "UMask": "0x480", @@ -2181,85 +2677,107 @@ }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x810", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x801", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Ch= 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x802", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cac= he - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x840", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x820", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : PMM - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2M Writes Issued to iMC : PMM - Ch1 : Count= s all PMM dimm writes requests(full line and partial) sent from M2M to iMC", "UMask": "0x880", @@ -2267,75 +2785,94 @@ }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Cha= nnels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c01", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c04", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive - Al= l Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c02", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Al= l Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c08", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR, acting as Cac= he - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c40", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : DDR - All Channels= ", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c20", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : PMM - All Channels= ", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", "PerPkg": "1", @@ -2344,281 +2881,353 @@ }, { "BriefDescription": "Write Tracker Inserts", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : MC Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : Mesh Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH2_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH2_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2a", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 0", "UMask": "0x1", @@ -2626,8 +3235,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI- Ch 1", "UMask": "0x4", @@ -2635,8 +3246,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 2", "UMask": "0x10", @@ -2644,8 +3257,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- All Channels", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - All Channels", "UMask": "0x15", @@ -2653,8 +3268,10 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 0", "UMask": "0x1", @@ -2662,8 +3279,10 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 1", "UMask": "0x4", @@ -2671,460 +3290,578 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.UPI_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.UPI_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.UPI_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch2 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH2.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH2_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2a", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": ": All Channels", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": ": Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCE= PT", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -3132,8 +3869,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -3141,8 +3880,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -3150,8 +3891,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -3159,8 +3902,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -3168,8 +3913,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -3177,8 +3924,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -3186,8 +3935,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -3195,8 +3946,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -3204,237 +3957,299 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2M_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 2", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel= 0", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel= 1", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC RPQ Cycles w/Credits - PMM : Channel= 2", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "UNC_M2M_RPQ_NO_REG_CRD_PMM.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2M_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M2M_RxC_BL_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3442,8 +4257,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -3451,8 +4268,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -3460,8 +4279,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3469,8 +4290,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -3478,8 +4301,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -3487,8 +4312,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3496,8 +4323,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -3505,8 +4334,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -3514,8 +4345,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -3523,8 +4356,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -3532,8 +4367,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3541,8 +4378,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -3550,8 +4389,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -3559,8 +4400,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -3568,8 +4411,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3577,8 +4422,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -3586,8 +4433,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -3595,8 +4444,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -3604,8 +4455,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3613,8 +4466,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -3622,8 +4477,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -3631,8 +4488,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -3640,8 +4499,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -3649,16 +4510,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3666,8 +4531,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -3675,8 +4542,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -3684,8 +4553,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -3693,8 +4564,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -3702,8 +4575,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3711,8 +4586,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -3720,8 +4597,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -3729,8 +4608,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -3738,8 +4619,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3747,8 +4630,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -3756,8 +4641,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -3765,8 +4652,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -3774,8 +4663,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -3783,8 +4674,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3792,8 +4685,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -3801,8 +4696,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -3810,8 +4707,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -3819,64 +4718,82 @@ }, { "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2M_SCOREBOARD_AD_RETRY_REJECTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Retry - Mem Mirroring Mode", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Retry - Mem Mirroring Mode", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_M2M_SCOREBOARD_BL_RETRY_REJECTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Scoreboard Accepts", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_M2M_SCOREBOARD_RD_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Scoreboard Rejects", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M2M_SCOREBOARD_RD_REJECTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Scoreboard Accepts", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_M2M_SCOREBOARD_WR_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Scoreboard Rejects", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2M_SCOREBOARD_WR_REJECTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3884,8 +4801,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3893,8 +4812,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3902,8 +4823,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3911,8 +4834,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3920,8 +4845,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3929,8 +4856,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3938,8 +4867,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3947,8 +4878,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3956,8 +4889,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3965,8 +4900,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3974,8 +4911,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3983,8 +4922,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3992,8 +4933,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -4001,8 +4944,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -4010,8 +4955,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4019,8 +4966,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4028,8 +4977,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4037,8 +4988,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4046,8 +4999,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -4055,8 +5010,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -4064,8 +5021,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -4073,8 +5032,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -4082,8 +5043,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4091,8 +5054,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4100,8 +5065,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4109,8 +5076,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4118,8 +5087,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -4127,8 +5098,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -4136,8 +5109,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -4145,8 +5120,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -4154,8 +5131,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4163,8 +5142,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4172,8 +5153,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4181,8 +5164,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4190,8 +5175,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4199,8 +5186,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4208,8 +5197,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4217,8 +5208,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4226,8 +5219,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4235,8 +5230,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4244,8 +5241,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4253,8 +5252,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4262,8 +5263,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4271,6 +5274,7 @@ }, { "BriefDescription": "Tag Hit : Clean NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", "PerPkg": "1", @@ -4280,6 +5284,7 @@ }, { "BriefDescription": "Tag Hit : Dirty NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", "PerPkg": "1", @@ -4289,8 +5294,10 @@ }, { "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit : Clean NearMem Underfill Hit : Tag = Hit indicates when a request sent to the iMC hit in Near Memory. : Counts c= lean underfill hits due to a partial write", "UMask": "0x4", @@ -4298,8 +5305,10 @@ }, { "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit : Dirty NearMem Underfill Hit : Tag = Hit indicates when a request sent to the iMC hit in Near Memory. : Counts d= irty underfill read hits due to a partial write", "UMask": "0x8", @@ -4307,620 +5316,778 @@ }, { "BriefDescription": "Tag Miss", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_TAG_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", "EventCode": "0x0d", "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x0c", "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x0b", "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_M2M_TxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : CRD Transa= ctions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : NDR Transa= ctions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.NDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AKC Credits", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Cache", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Core", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to QPI", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4928,8 +6095,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -4937,8 +6106,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -4946,8 +6117,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4955,8 +6128,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -4964,8 +6139,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -4973,8 +6150,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4982,8 +6161,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -4991,8 +6172,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -5000,8 +6183,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -5009,8 +6194,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -5018,8 +6205,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5027,8 +6216,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -5036,8 +6227,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -5045,8 +6238,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -5054,8 +6249,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5063,8 +6260,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -5072,8 +6271,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -5081,8 +6282,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -5090,8 +6293,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -5099,8 +6304,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5108,8 +6315,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -5117,8 +6326,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -5126,8 +6337,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -5135,8 +6348,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5144,8 +6359,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -5153,8 +6370,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -5162,8 +6381,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -5171,8 +6392,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -5180,8 +6403,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5189,8 +6414,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -5198,8 +6425,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -5207,8 +6436,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -5216,8 +6447,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5225,8 +6458,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -5234,8 +6469,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -5243,8 +6480,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -5252,8 +6491,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -5261,8 +6502,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5270,8 +6513,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -5279,8 +6524,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -5288,8 +6535,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -5297,8 +6546,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -5306,8 +6557,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -5315,8 +6568,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -5324,8 +6579,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -5333,8 +6590,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -5342,8 +6601,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -5351,8 +6612,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -5360,8 +6623,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -5369,8 +6634,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -5378,8 +6645,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5387,8 +6656,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -5396,8 +6667,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -5405,8 +6678,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -5414,8 +6689,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -5423,8 +6700,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5432,8 +6711,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -5441,8 +6722,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -5450,8 +6733,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -5459,8 +6744,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -5468,8 +6755,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -5477,8 +6766,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -5486,8 +6777,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -5495,8 +6788,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -5504,8 +6799,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -5513,8 +6810,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -5522,8 +6821,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -5531,8 +6832,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -5540,8 +6843,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -5549,8 +6854,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -5558,8 +6865,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -5567,8 +6876,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -5576,8 +6887,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -5585,8 +6898,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -5594,8 +6909,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -5603,8 +6920,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -5612,8 +6931,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -5621,8 +6942,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -5630,8 +6953,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -5639,8 +6964,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5648,8 +6975,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -5657,8 +6986,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5666,8 +6997,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5675,8 +7008,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -5684,8 +7019,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -5693,8 +7030,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -5702,8 +7041,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5711,8 +7052,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5720,8 +7063,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -5729,8 +7074,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -5738,8 +7085,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5747,8 +7096,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5756,8 +7107,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -5765,8 +7118,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -5774,8 +7129,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5783,8 +7140,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -5792,8 +7151,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5801,8 +7162,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5810,8 +7173,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -5819,8 +7184,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -5828,8 +7195,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5837,8 +7206,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -5846,8 +7217,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -5855,8 +7228,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -5864,8 +7239,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5873,8 +7250,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -5882,8 +7261,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5891,8 +7272,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -5900,8 +7283,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5909,8 +7294,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -5918,8 +7305,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -5927,8 +7316,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -5936,8 +7327,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -5945,8 +7338,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5954,8 +7349,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5963,8 +7360,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5972,8 +7371,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -5981,8 +7382,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -5990,8 +7393,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5999,8 +7404,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -6008,8 +7415,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -6017,8 +7426,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -6026,8 +7437,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6035,8 +7448,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -6044,8 +7459,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -6053,8 +7470,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -6062,8 +7481,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -6071,8 +7492,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -6080,8 +7503,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -6089,8 +7514,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -6098,8 +7525,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -6107,8 +7536,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -6116,8 +7547,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -6125,8 +7558,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -6134,8 +7569,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6143,8 +7580,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6152,8 +7591,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6161,8 +7602,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6170,8 +7613,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6179,8 +7624,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6188,8 +7635,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6197,8 +7646,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6206,8 +7657,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6215,8 +7668,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6224,8 +7679,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6233,8 +7690,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6242,8 +7701,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6251,8 +7712,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6260,8 +7723,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -6269,8 +7734,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -6278,8 +7745,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -6287,8 +7756,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -6296,8 +7767,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6305,8 +7778,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6314,8 +7789,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6323,8 +7800,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6332,352 +7811,440 @@ }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel= 0", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel= 1", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - PMM : Channel= 2", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M2M_WPQ_NO_REG_CRD_PMM.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 2", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -6685,8 +8252,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -6694,8 +8263,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -6703,8 +8274,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -6712,8 +8285,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -6721,8 +8296,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -6730,8 +8307,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -6739,8 +8318,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -6748,8 +8329,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -6757,8 +8340,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -6766,8 +8351,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -6775,8 +8362,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -6784,8 +8373,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -6793,8 +8384,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -6802,8 +8395,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -6811,8 +8406,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -6820,8 +8417,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -6829,8 +8428,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -6838,8 +8439,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -6847,8 +8450,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -6856,8 +8461,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -6865,8 +8472,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -6874,8 +8483,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -6883,8 +8494,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -6892,8 +8505,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -6901,8 +8516,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -6910,8 +8527,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -6919,8 +8538,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -6928,8 +8549,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -6937,8 +8560,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -6946,8 +8571,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -6955,8 +8582,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -6964,8 +8593,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -6973,8 +8604,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -6982,8 +8615,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -6991,8 +8626,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -7000,8 +8637,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -7009,8 +8648,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -7018,8 +8659,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -7027,8 +8670,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -7036,8 +8681,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -7045,8 +8692,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -7054,8 +8703,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -7063,8 +8714,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -7072,8 +8725,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -7081,8 +8736,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -7090,8 +8747,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -7099,8 +8758,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -7108,8 +8769,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -7117,8 +8780,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -7126,8 +8791,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -7135,8 +8802,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -7144,8 +8813,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -7153,8 +8824,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -7162,8 +8835,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -7171,8 +8846,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -7180,8 +8857,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -7189,8 +8868,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -7198,8 +8879,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -7207,8 +8890,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -7216,8 +8901,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -7225,8 +8912,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -7234,8 +8923,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -7243,8 +8934,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -7252,8 +8945,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -7261,8 +8956,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -7270,8 +8967,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -7279,8 +8978,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -7288,8 +8989,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -7297,8 +9000,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -7306,8 +9011,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -7315,8 +9022,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -7324,8 +9033,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -7333,8 +9044,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -7342,8 +9055,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -7351,8 +9066,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -7360,8 +9077,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M3UPI_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -7369,8 +9088,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -7378,8 +9099,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -7387,8 +9110,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -7396,8 +9121,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -7405,8 +9132,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -7414,8 +9143,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -7423,8 +9154,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -7432,8 +9165,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -7441,8 +9176,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -7450,8 +9187,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -7459,8 +9198,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -7468,8 +9209,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Requests", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Requests : No credit= s available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x4", @@ -7477,8 +9220,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Snoops", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Snoops : No credits = available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x8", @@ -7486,8 +9231,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : VNA Messages : No cr= edits available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x1", @@ -7495,8 +9242,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Writebacks : No cred= its available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x2", @@ -7504,6 +9253,7 @@ }, { "BriefDescription": "Clockticks of the mesh to UPI (M3UPI)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M3UPI_CLOCKTICKS", "PerPkg": "1", @@ -7512,31 +9262,39 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "D2C Sent", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M3UPI_D2C_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2C Sent : Count cases BL sends direct to co= re", "Unit": "M3UPI" }, { "BriefDescription": "D2U Sent", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M3UPI_D2U_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U comman= d", "Unit": "M3UPI" }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -7544,8 +9302,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -7553,8 +9313,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -7562,8 +9324,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -7571,8 +9335,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -7580,8 +9346,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : If the CHA TOR has too many PMM transactions, this signal will th= rottle outgoing MS2IDI traffic", "UMask": "0x10", @@ -7589,8 +9357,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.PMM_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If another CHA TOR has too many PMM transactions, this signal wi= ll throttle outgoing MS2IDI traffic", "UMask": "0x20", @@ -7598,8 +9368,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M3UPI_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -7607,8 +9379,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -7616,8 +9390,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -7625,8 +9401,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -7634,8 +9412,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -7643,8 +9423,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -7652,8 +9434,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -7661,8 +9445,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -7670,8 +9456,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -7679,8 +9467,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -7688,8 +9478,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M3UPI_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -7697,8 +9489,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -7706,8 +9500,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -7715,8 +9511,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -7724,8 +9522,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -7733,8 +9533,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -7742,8 +9544,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -7751,8 +9555,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -7760,8 +9566,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -7769,8 +9577,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -7778,8 +9588,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -7787,8 +9599,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the= same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share th= e same ring destination. (1 VN0 credit only) : No vn0 and vna credits avail= able to send to M2", "UMask": "0x1", @@ -7796,8 +9610,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO2", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna = credits available to send to M2", "UMask": "0x2", @@ -7805,8 +9621,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO3", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna = credits available to send to M2", "UMask": "0x4", @@ -7814,8 +9632,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO4", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna = credits available to send to M2", "UMask": "0x8", @@ -7823,8 +9643,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x10", @@ -7832,8 +9654,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS= are in single mask. ORs them together", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : All IIO targets for NC= S are in single mask. ORs them together : No vn0 and vna credits available = to send to M2", "UMask": "0x40", @@ -7841,8 +9665,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS cr= edits : No vn0 and vna credits available to send to M2", "UMask": "0x80", @@ -7850,8 +9676,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x20", @@ -7859,24 +9687,30 @@ }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M3UPI_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x1", @@ -7884,8 +9718,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x2", @@ -7893,8 +9729,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x4", @@ -7902,8 +9740,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x10", @@ -7911,8 +9751,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x20", @@ -7920,8 +9762,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x8", @@ -7929,8 +9773,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -7938,8 +9784,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -7947,8 +9795,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -7956,8 +9806,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -7965,8 +9817,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -7974,8 +9828,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -7983,8 +9839,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -7992,8 +9850,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -8001,8 +9861,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -8010,95 +9872,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -8106,8 +9992,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -8115,8 +10003,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -8124,8 +10014,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -8133,8 +10025,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -8142,8 +10036,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -8151,8 +10047,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -8160,8 +10058,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -8169,8 +10069,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -8178,8 +10080,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -8187,8 +10091,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -8196,8 +10102,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -8205,8 +10113,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -8214,8 +10124,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -8223,8 +10135,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x10", @@ -8232,8 +10146,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x20", @@ -8241,8 +10157,10 @@ }, { "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 a= nd VN1 arbitration sub-pipelines both produced AD and BL winners (maximum p= ossible parallel winners)", "UMask": "0x80", @@ -8250,8 +10168,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN0 : Arbitration stage made no progress on pending ad vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x1", @@ -8259,8 +10179,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN1 : Arbitration stage made no progress on pending ad vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x2", @@ -8268,8 +10190,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN0 : Arbitration stage made no progress on pending bl vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x4", @@ -8277,8 +10201,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN1 : Arbitration stage made no progress on pending bl vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x8", @@ -8286,8 +10212,10 @@ }, { "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : = VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD= or BL on each side)", "UMask": "0x40", @@ -8295,8 +10223,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -8304,8 +10234,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -8313,8 +10245,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8322,8 +10256,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -8331,8 +10267,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8340,8 +10278,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -8349,8 +10289,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -8358,8 +10300,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -8367,8 +10311,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -8376,8 +10322,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8385,8 +10333,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -8394,8 +10344,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8403,8 +10355,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -8412,8 +10366,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -8421,8 +10377,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -8430,8 +10388,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -8439,8 +10399,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8448,8 +10410,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -8457,8 +10421,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8466,8 +10432,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -8475,8 +10443,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -8484,8 +10454,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -8493,8 +10465,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -8502,8 +10476,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8511,8 +10487,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -8520,8 +10498,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8529,8 +10509,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -8538,8 +10520,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -8547,8 +10531,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL A= rb", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL = Arb : Number of times message is bypassed around the Ingress Queue : AD is = taking bypass to slot 0 of independent flit while bl message is in arbitrat= ion", "UMask": "0x2", @@ -8556,8 +10542,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle= ", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idl= e : Number of times message is bypassed around the Ingress Queue : AD is ta= king bypass to slot 0 of independent flit while pipeline is idle", "UMask": "0x1", @@ -8565,8 +10553,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 1 while merging with bl message in same flit", "UMask": "0x4", @@ -8574,8 +10564,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 2 while merging with bl message in same flit", "UMask": "0x8", @@ -8583,8 +10575,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO= ", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIF= O : Indication that at least one packet (flit) is in the bgf (fifo only)", "UMask": "0x1", @@ -8592,8 +10586,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path= ", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any in BGF Pat= h : Indication that at least one packet (flit) is in the bgf path (i.e. pip= e to fifo)", "UMask": "0x2", @@ -8601,8 +10597,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 1", "UMask": "0x10", @@ -8610,8 +10608,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 2", "UMask": "0x20", @@ -8619,8 +10619,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb= : VN0 BL RSP message was blocked from arbitration request due to lack of D= 2K CMP credit", "UMask": "0x4", @@ -8628,8 +10630,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP mes= sage was blocked from arbitration request due to lack of D2K CMP credits", "UMask": "0x8", @@ -8637,8 +10641,10 @@ }, { "BriefDescription": "Credit Occupancy : Credits Consumed", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Credits Consumed : number= of remote vna credits consumed per cycle", "UMask": "0x80", @@ -8646,8 +10652,10 @@ }, { "BriefDescription": "Credit Occupancy : D2K Credits", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : D2K Credits : D2K complet= ion fifo credit occupancy (credits in use), accumulated across all cycles", "UMask": "0x10", @@ -8655,8 +10663,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", "UMask": "0x2", @@ -8664,8 +10674,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e= . pipe to fifo or fifo)", "UMask": "0x4", @@ -8673,8 +10685,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in completion fifo only", "UMask": "0x40", @@ -8682,8 +10696,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in marker table and in fifo", "UMask": "0x20", @@ -8691,8 +10707,10 @@ }, { "BriefDescription": "Credit Occupancy : Transmit Credits", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Transmit Credits : Link l= ayer transmit queue credit occupancy (credits in use), accumulated across a= ll cycles", "UMask": "0x8", @@ -8700,8 +10718,10 @@ }, { "BriefDescription": "Credit Occupancy : VNA In Use", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI V= NA credit occupancy (number of credits in use), accumulated across all cycl= es", "UMask": "0x1", @@ -8709,8 +10729,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : REQ on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Home (REQ) me= ssages on AD. REQ is generally used to send requests, request responses, a= nd snoop responses.", "UMask": "0x1", @@ -8718,8 +10740,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on AD. RSP packets are used to transmit a variety of protocol f= lits including grants and completions (CMP).", "UMask": "0x4", @@ -8727,8 +10751,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : SNP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Snoops (SNP) = messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8736,8 +10762,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCB on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Broadcast (NCB) messages on BL. NCB is generally used to transmit data wit= hout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -8745,8 +10773,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCS on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8754,8 +10784,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on BL. RSP packets are used to transmit a variety of protocol fl= its including grants and completions (CMP).", "UMask": "0x8", @@ -8763,8 +10795,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : WB on BL : Counts the number of cycles when the UPI Ingress is not em= pty. This tracks one of the three rings that are used by the UPI agent. T= his can be used in conjunction with the UPI Ingress Occupancy Accumulator e= vent in order to calculate average queue occupancy. Multiple ingress buffe= rs can be tracked at a given time using multiple counters. : Data Response = (WB) messages on BL. WB is generally used to transmit data with coherency.= For example, remote reads and writes, or cache to cache transfers will tr= ansmit their data using WB.", "UMask": "0x10", @@ -8772,8 +10806,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : REQ on AD : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Home (REQ) me= ssages on AD. REQ is generally used to send requests, request responses, a= nd snoop responses.", "UMask": "0x1", @@ -8781,8 +10817,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on AD : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on AD. RSP packets are used to transmit a variety of protocol f= lits including grants and completions (CMP).", "UMask": "0x4", @@ -8790,8 +10828,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : SNP on AD : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Snoops (SNP) = messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -8799,8 +10839,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : NCB on BL : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Broadcast (NCB) messages on BL. NCB is generally used to transmit data wit= hout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -8808,8 +10850,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCS on BL", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : NCS on BL : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Standard (NCS) messages on BL.", "UMask": "0x40", @@ -8817,8 +10861,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on BL : Counts the number of allocations into the UPI VN1 Ingres= s. This tracks one of the three rings that are used by the UPI agent. Thi= s can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulato= r event in order to calculate average queue latency. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on BL. RSP packets are used to transmit a variety of protocol fl= its including grants and completions (CMP).", "UMask": "0x8", @@ -8826,8 +10872,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Em= pty : WB on BL : Counts the number of allocations into the UPI VN1 Ingress= . This tracks one of the three rings that are used by the UPI agent. This= can be used in conjunction with the UPI VN1 Ingress Occupancy Accumulator= event in order to calculate average queue latency. Multiple ingress buffe= rs can be tracked at a given time using multiple counters. : Data Response = (WB) messages on BL. WB is generally used to transmit data with coherency.= For example, remote reads and writes, or cache to cache transfers will tr= ansmit their data using WB.", "UMask": "0x10", @@ -8835,8 +10883,10 @@ }, { "BriefDescription": "Data Flit Not Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : All : Data flit is read= y for transmission but could not be sent : data flit is ready for transmiss= ion but could not be sent for any reason, e.g. low credits, low tsv, stall = injection", "UMask": "0x1", @@ -8844,8 +10894,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x8", @@ -8853,8 +10905,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x10", @@ -8862,8 +10916,10 @@ }, { "BriefDescription": "Data Flit Not Sent : TSV High", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is= ready for transmission but could not be sent : data flit is ready for tran= smission but was not sent while tsv high", "UMask": "0x2", @@ -8871,8 +10927,10 @@ }, { "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : = Data flit is ready for transmission but could not be sent : data flit is re= ady for transmission but was not sent while cycle is valid for flit transmi= ssion", "UMask": "0x4", @@ -8880,8 +10938,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 0", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 0 : generating bl data flit sequence; waiting for data pump 0", "UMask": "0x1", @@ -8889,8 +10949,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at capacity (pending table plus completion fifo at limit)", "UMask": "0x10", @@ -8898,8 +10960,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is tracking at least one message", "UMask": "0x8", @@ -8907,8 +10971,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding completion fifo is full", "UMask": "0x40", @@ -8916,8 +10982,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at or near capacity, such that pump-0-only bl messages are g= etting stalled in slotting stage", "UMask": "0x20", @@ -8925,8 +10993,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : a bl mess= age finished but is in limbo and moved to pump-1-pending logic", "UMask": "0x4", @@ -8934,8 +11004,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 1", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 1 : generating bl data flit sequence; waiting for data pump 1", "UMask": "0x2", @@ -8943,8 +11015,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request naturally serviced during h= old-off period", "UMask": "0x4", @@ -8952,8 +11026,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request forcibly serviced during se= rvice window", "UMask": "0x8", @@ -8961,8 +11037,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request received from link layer wh= ile idle (with no slot 2 request active immediately prior)", "UMask": "0x1", @@ -8970,8 +11048,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request withdrawn during hold-off p= eriod or service window", "UMask": "0x2", @@ -8979,16 +11059,20 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : All", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit : Needs = Data Flit", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Needs= Data Flit : BL message requires data flit sequence", "UMask": "0x2", @@ -8996,8 +11080,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 0 : Waiting for header pump 0", "UMask": "0x4", @@ -9005,8 +11091,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 : Header pump 1 is not required for flit", "UMask": "0x10", @@ -9014,8 +11102,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Bubble", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit tra= nsmission delayed", "UMask": "0x20", @@ -9023,8 +11113,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Not Avail", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not a= vailable", "UMask": "0x40", @@ -9032,8 +11124,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 1 : Waiting for header pump 1", "UMask": "0x8", @@ -9041,8 +11135,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events re= lated to Header Flit Generation - Set 1 : Header flit slotting control stat= e machine is in any accumulate state; multi-message flit may be assembled o= ver multiple cycles", "UMask": "0x1", @@ -9050,8 +11146,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Eve= nts related to Header Flit Generation - Set 1 : header flit slotting contro= l state machine is in accum_ready state; flit is ready to send but transmis= sion is blocked; more messages may be slotted into flit", "UMask": "0x2", @@ -9059,8 +11157,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Ev= ents related to Header Flit Generation - Set 1 : Flit is being assembled ov= er multiple cycles, but no additional message is being slotted into flit in= current cycle; accumulate cycle is wasted", "UMask": "0x4", @@ -9068,8 +11168,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : = Events related to Header Flit Generation - Set 1 : Header flit slotting ent= ered run-ahead state; new header flit is started while transmission of prio= r, fully assembled flit is blocked", "UMask": "0x8", @@ -9077,8 +11179,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: message was slotted only after= run-ahead was over; run-ahead mode definitely wasted", "UMask": "0x80", @@ -9086,8 +11190,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : = Events related to Header Flit Generation - Set 1 : run-ahead mode: one mess= age slotted during run-ahead", "UMask": "0x10", @@ -9095,8 +11201,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: second message slotted immedia= tely after run-ahead; potential run-ahead success", "UMask": "0x20", @@ -9104,8 +11212,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: two (or three) message flit se= nt immediately after run-ahead; complete run-ahead success", "UMask": "0x40", @@ -9113,8 +11223,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events r= elated to Header Flit Generation - Set 2 : new header flit construction may= proceed in parallel with data flit sequence", "UMask": "0x4", @@ -9122,8 +11234,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished= : Events related to Header Flit Generation - Set 2 : header flit finished = assembly in parallel with data flit sequence", "UMask": "0x10", @@ -9131,8 +11245,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Eve= nts related to Header Flit Generation - Set 2 : message is slotted into hea= der flit in parallel with data flit sequence", "UMask": "0x8", @@ -9140,8 +11256,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : = Events related to Header Flit Generation - Set 2 : Rate-matching stall inje= cted", "UMask": "0x1", @@ -9149,8 +11267,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - N= o Message", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - = No Message : Events related to Header Flit Generation - Set 2 : Rate matchi= ng stall injected, but no additional message slotted during stall cycle", "UMask": "0x2", @@ -9158,8 +11278,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message : One message= in flit; VNA or non-VNA flit", "UMask": "0x1", @@ -9167,8 +11289,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message in non-VNA : = One message in flit; non-VNA flit", "UMask": "0x8", @@ -9176,8 +11300,10 @@ }, { "BriefDescription": "Sent Header Flit : Two Messages", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Two Messages : Two messag= es in flit; VNA flit", "UMask": "0x2", @@ -9185,8 +11311,10 @@ }, { "BriefDescription": "Sent Header Flit : Three Messages", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Three Messages : Three me= ssages in flit; VNA flit", "UMask": "0x4", @@ -9194,32 +11322,40 @@ }, { "BriefDescription": "Sent Header Flit : One Slot Taken", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : Two Slots Taken", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : All Slots Taken", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "Header Not Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : All : header flit is ready= for transmission but could not be sent : header flit is ready for transmis= sion but could not be sent for any reason, e.g. no credits, low tsv, stall = injection", "UMask": "0x1", @@ -9227,8 +11363,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits : header fl= it is ready for transmission but could not be sent : No BGF credits availab= le", "UMask": "0x8", @@ -9236,8 +11374,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits + No Extra M= essage Slotted", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No BGF credits available; no additional message slotted into flit", "UMask": "0x20", @@ -9245,8 +11385,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits : header fl= it is ready for transmission but could not be sent : No TxQ credits availab= le", "UMask": "0x10", @@ -9254,8 +11396,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra M= essage Slotted", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No TxQ credits available; no additional message slotted into flit", "UMask": "0x40", @@ -9263,8 +11407,10 @@ }, { "BriefDescription": "Header Not Sent : TSV High", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : TSV High : header flit is = ready for transmission but could not be sent : header flit is ready for tra= nsmission but was not sent while tsv high", "UMask": "0x2", @@ -9272,8 +11418,10 @@ }, { "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : Cycle valid for Flit : hea= der flit is ready for transmission but could not be sent : header flit is r= eady for transmission but was not sent while cycle is valid for flit transm= ission", "UMask": "0x4", @@ -9281,8 +11429,10 @@ }, { "BriefDescription": "Message Held : Can't Slot AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot AD : some AD messa= ge could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x10", @@ -9290,8 +11440,10 @@ }, { "BriefDescription": "Message Held : Can't Slot BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot BL : some BL messa= ge could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x20", @@ -9299,8 +11451,10 @@ }, { "BriefDescription": "Message Held : Parallel Attempt", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Attempt : ad and bl = messages attempted to slot into the same flit in parallel", "UMask": "0x4", @@ -9308,8 +11462,10 @@ }, { "BriefDescription": "Message Held : Parallel Success", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Success : ad and bl = messages were actually slotted into the same flit in parallel", "UMask": "0x8", @@ -9317,8 +11473,10 @@ }, { "BriefDescription": "Message Held : VN0", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN0 : vn0 message(s) that cou= ldn't be slotted into last vn0 flit are held in slotting stage while proces= sing vn1 flit", "UMask": "0x1", @@ -9326,8 +11484,10 @@ }, { "BriefDescription": "Message Held : VN1", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN1 : vn1 message(s) that cou= ldn't be slotted into last vn1 flit are held in slotting stage while proces= sing vn0 flit", "UMask": "0x2", @@ -9335,8 +11495,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ = on AD", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : REQ= on AD : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Home (REQ) messages on AD. REQ = is generally used to send requests, request responses, and snoop responses.= ", "UMask": "0x1", @@ -9344,8 +11506,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP = on AD", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP= on AD : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Response (RSP) messages on AD. = RSP packets are used to transmit a variety of protocol flits including gran= ts and completions (CMP).", "UMask": "0x4", @@ -9353,8 +11517,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP = on AD", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : SNP= on AD : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Snoops (SNP) messages on AD. SN= P is used for outgoing snoops.", "UMask": "0x2", @@ -9362,8 +11528,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB = on BL", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCB= on BL : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Non-Coherent Broadcast (NCB) mes= sages on BL. NCB is generally used to transmit data without coherency. Fo= r example, non-coherent read data returns.", "UMask": "0x20", @@ -9371,8 +11539,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS = on BL", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : NCS= on BL : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Non-Coherent Standard (NCS) mess= ages on BL.", "UMask": "0x40", @@ -9380,8 +11550,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP = on BL", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : RSP= on BL : Counts the number of allocations into the UPI Ingress. This track= s one of the three rings that are used by the UPI agent. This can be used = in conjunction with the UPI Ingress Occupancy Accumulator event in order to= calculate average queue latency. Multiple ingress buffers can be tracked = at a given time using multiple counters. : Response (RSP) messages on BL. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x8", @@ -9389,8 +11561,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB o= n BL", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Inserts : WB = on BL : Counts the number of allocations into the UPI Ingress. This tracks= one of the three rings that are used by the UPI agent. This can be used i= n conjunction with the UPI Ingress Occupancy Accumulator event in order to = calculate average queue latency. Multiple ingress buffers can be tracked a= t a given time using multiple counters. : Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -9398,8 +11572,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ = on AD", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : REQ= on AD : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Home (REQ) messages on= AD. REQ is generally used to send requests, request responses, and snoop = responses.", "UMask": "0x1", @@ -9407,8 +11583,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP = on AD", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP= on AD : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Response (RSP) message= s on AD. RSP packets are used to transmit a variety of protocol flits incl= uding grants and completions (CMP).", "UMask": "0x4", @@ -9416,8 +11594,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP = on AD", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : SNP= on AD : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Snoops (SNP) messages = on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9425,8 +11605,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB = on BL", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCB= on BL : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Non-Coherent Broadcast= (NCB) messages on BL. NCB is generally used to transmit data without cohe= rency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -9434,8 +11616,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS = on BL", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : NCS= on BL : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Non-Coherent Standard = (NCS) messages on BL.", "UMask": "0x40", @@ -9443,8 +11627,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP = on BL", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : RSP= on BL : Counts the number of allocations into the UPI VN1 Ingress. This = tracks one of the three rings that are used by the UPI agent. This can be = used in conjunction with the UPI VN1 Ingress Occupancy Accumulator event i= n order to calculate average queue latency. Multiple ingress buffers can b= e tracked at a given time using multiple counters. : Response (RSP) message= s on BL. RSP packets are used to transmit a variety of protocol flits inclu= ding grants and completions (CMP).", "UMask": "0x8", @@ -9452,8 +11638,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB o= n BL", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Inserts : WB = on BL : Counts the number of allocations into the UPI VN1 Ingress. This t= racks one of the three rings that are used by the UPI agent. This can be u= sed in conjunction with the UPI VN1 Ingress Occupancy Accumulator event in= order to calculate average queue latency. Multiple ingress buffers can be= tracked at a given time using multiple counters. : Data Response (WB) mess= ages on BL. WB is generally used to transmit data with coherency. For exa= mple, remote reads and writes, or cache to cache transfers will transmit th= eir data using WB.", "UMask": "0x10", @@ -9461,8 +11649,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RE= Q on AD", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : R= EQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Home (REQ) messages on AD. REQ is generally used to se= nd requests, request responses, and snoop responses.", "UMask": "0x1", @@ -9470,8 +11660,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RS= P on AD", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : R= SP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Response (RSP) messages on AD. RSP packets are used to= transmit a variety of protocol flits including grants and completions (CMP= ).", "UMask": "0x4", @@ -9479,8 +11671,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : SN= P on AD", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : S= NP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing = snoops.", "UMask": "0x2", @@ -9488,8 +11682,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NC= B on BL", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : N= CB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is ge= nerally used to transmit data without coherency. For example, non-coherent= read data returns.", "UMask": "0x20", @@ -9497,8 +11693,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : NC= S on BL", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : N= CS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -9506,8 +11704,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : RS= P on BL", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : R= SP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Response (RSP) messages on BL. RSP packets are used to = transmit a variety of protocol flits including grants and completions (CMP)= .", "UMask": "0x8", @@ -9515,8 +11715,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy : WB= on BL", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Occupancy : W= B on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in ea= ch cycle. This tracks one of the three ring Ingress buffers. This can be = used with the UPI VN1 Ingress Not Empty event to calculate average occupan= cy or the UPI VN1 Ingress Allocations event in order to calculate average = queuing latency. : Data Response (WB) messages on BL. WB is generally used= to transmit data with coherency. For example, remote reads and writes, or= cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9524,8 +11726,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RE= Q on AD", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : R= EQ on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Home (REQ) messages on AD. REQ is generally used to se= nd requests, request responses, and snoop responses.", "UMask": "0x1", @@ -9533,8 +11737,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RS= P on AD", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : R= SP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Response (RSP) messages on AD. RSP packets are used to= transmit a variety of protocol flits including grants and completions (CMP= ).", "UMask": "0x4", @@ -9542,8 +11748,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : SN= P on AD", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : S= NP on AD : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Snoops (SNP) messages on AD. SNP is used for outgoing = snoops.", "UMask": "0x2", @@ -9551,8 +11759,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NC= B on BL", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : N= CB on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Non-Coherent Broadcast (NCB) messages on BL. NCB is ge= nerally used to transmit data without coherency. For example, non-coherent= read data returns.", "UMask": "0x20", @@ -9560,8 +11770,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : NC= S on BL", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : N= CS on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -9569,8 +11781,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : RS= P on BL", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : R= SP on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in e= ach cycle. This tracks one of the three ring Ingress buffers. This can be= used with the UPI VN1 Ingress Not Empty event to calculate average occupa= ncy or the UPI VN1 Ingress Allocations event in order to calculate average= queuing latency. : Response (RSP) messages on BL. RSP packets are used to = transmit a variety of protocol flits including grants and completions (CMP)= .", "UMask": "0x8", @@ -9578,8 +11792,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy : WB= on BL", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Ingress (from CMS) Queue - Occupancy : W= B on BL : Accumulates the occupancy of a given UPI VN1 Ingress queue in ea= ch cycle. This tracks one of the three ring Ingress buffers. This can be = used with the UPI VN1 Ingress Not Empty event to calculate average occupan= cy or the UPI VN1 Ingress Allocations event in order to calculate average = queuing latency. : Data Response (WB) messages on BL. WB is generally used= to transmit data with coherency. For example, remote reads and writes, or= cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9587,8 +11803,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -9596,8 +11814,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9605,8 +11825,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -9614,8 +11836,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -9623,8 +11847,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -9632,8 +11858,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9641,8 +11869,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9650,8 +11880,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -9659,8 +11891,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9668,8 +11902,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -9677,8 +11913,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -9686,8 +11924,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -9695,8 +11935,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9704,8 +11946,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9713,8 +11957,10 @@ }, { "BriefDescription": "Remote VNA Credits : Any In Use", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Any In Use : At least o= ne remote vna credit is in use", "UMask": "0x20", @@ -9722,8 +11968,10 @@ }, { "BriefDescription": "Remote VNA Credits : Corrected", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Corrected : Number of r= emote vna credits corrected (local return) per cycle", "UMask": "0x1", @@ -9731,8 +11979,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna = credit level is less than 1 (i.e. no vna credits available)", "UMask": "0x2", @@ -9740,8 +11990,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 10", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna= credit level is less than 10; parallel vn0/vn1 arb not possible", "UMask": "0x10", @@ -9749,8 +12001,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna = credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", "UMask": "0x4", @@ -9758,8 +12012,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna = credit level is less than 5; parallel ad/bl arb on vna not possible", "UMask": "0x8", @@ -9767,8 +12023,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 5 an= d allocation to ad or bl messages was required", "UMask": "0x2", @@ -9776,8 +12034,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT1= 0", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 10 a= nd allocation to vn0 or vn1 was required", "UMask": "0x1", @@ -9785,8 +12045,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x10", @@ -9794,8 +12056,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x20", @@ -9803,8 +12067,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn0, not to vn1", "UMask": "0x4", @@ -9812,8 +12078,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x40", @@ -9821,8 +12089,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x80", @@ -9830,8 +12100,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn1, not to vn0", "UMask": "0x8", @@ -9839,8 +12111,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -9848,8 +12122,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -9857,8 +12133,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -9866,8 +12144,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -9875,8 +12155,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -9884,8 +12166,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -9893,8 +12177,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -9902,8 +12188,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -9911,8 +12199,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -9920,8 +12210,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -9929,8 +12221,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -9938,8 +12232,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -9947,8 +12243,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -9956,8 +12254,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -9965,8 +12265,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M3UPI_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -9974,8 +12276,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -9983,8 +12287,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -9992,8 +12298,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -10001,8 +12309,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -10010,8 +12320,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -10019,8 +12331,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -10028,8 +12342,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -10037,8 +12353,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -10046,8 +12364,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -10055,16 +12375,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M3UPI_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M3UPI" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -10072,8 +12396,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -10081,8 +12407,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -10090,8 +12418,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -10099,8 +12429,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -10108,8 +12440,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -10117,8 +12451,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -10126,8 +12462,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -10135,8 +12473,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M3UPI_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -10144,8 +12484,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -10153,8 +12495,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -10162,8 +12506,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -10171,8 +12517,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -10180,8 +12528,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -10189,8 +12539,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -10198,8 +12550,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -10207,8 +12561,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -10216,8 +12572,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -10225,8 +12583,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10234,8 +12594,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10243,8 +12605,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10252,8 +12616,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -10261,8 +12627,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -10270,8 +12638,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -10279,8 +12649,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -10288,8 +12660,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -10297,8 +12671,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10306,8 +12682,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10315,8 +12693,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10324,8 +12704,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -10333,8 +12715,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -10342,8 +12726,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -10351,8 +12737,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -10360,8 +12748,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -10369,8 +12759,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10378,8 +12770,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10387,8 +12781,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10396,8 +12792,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -10405,8 +12803,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -10414,8 +12814,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -10423,8 +12825,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -10432,8 +12836,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -10441,8 +12847,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10450,8 +12858,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10459,8 +12869,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10468,8 +12880,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -10477,8 +12891,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -10486,8 +12902,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -10495,8 +12913,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -10504,8 +12924,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -10513,8 +12935,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10522,8 +12946,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10531,8 +12957,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10540,8 +12968,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10549,8 +12979,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10558,8 +12990,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10567,8 +13001,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10576,8 +13012,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10585,8 +13023,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10594,8 +13034,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -10603,8 +13045,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -10612,8 +13056,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M3UPI_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -10621,8 +13067,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -10630,8 +13078,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -10639,8 +13089,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x2", @@ -10648,8 +13100,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x8", @@ -10657,8 +13111,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -10666,8 +13122,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -10675,8 +13133,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x20", @@ -10684,8 +13144,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x80", @@ -10693,8 +13155,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x1", @@ -10702,8 +13166,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x2", @@ -10711,8 +13177,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x4", @@ -10720,8 +13188,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x8", @@ -10729,8 +13199,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x1", @@ -10738,8 +13210,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x4", @@ -10747,8 +13221,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x2", @@ -10756,8 +13232,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x8", @@ -10765,8 +13243,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x10", @@ -10774,8 +13254,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x40", @@ -10783,8 +13265,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x20", @@ -10792,8 +13276,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x80", @@ -10801,8 +13287,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -10810,8 +13298,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -10819,8 +13309,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -10828,8 +13320,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -10837,8 +13331,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -10846,8 +13342,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -10855,8 +13353,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -10864,78 +13364,98 @@ }, { "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Occupancy", + "Counter": "0", "EventCode": "0x1E", "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -10943,8 +13463,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x8", @@ -10952,8 +13474,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -10961,8 +13485,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x2", @@ -10970,8 +13496,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -10979,8 +13507,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x80", @@ -10988,8 +13518,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -10997,8 +13529,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x20", @@ -11006,8 +13540,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x1", @@ -11015,8 +13551,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x4", @@ -11024,8 +13562,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x2", @@ -11033,8 +13573,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x8", @@ -11042,8 +13584,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x10", @@ -11051,8 +13595,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x40", @@ -11060,8 +13606,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x20", @@ -11069,8 +13617,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x80", @@ -11078,8 +13628,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -11087,8 +13639,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -11096,8 +13650,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -11105,8 +13661,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -11114,8 +13672,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -11123,8 +13683,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -11132,8 +13694,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x80", @@ -11141,8 +13705,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -11150,120 +13716,150 @@ }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1F", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11271,8 +13867,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -11280,8 +13878,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -11289,8 +13889,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11298,8 +13900,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -11307,8 +13911,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -11316,8 +13922,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11325,8 +13933,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -11334,8 +13944,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -11343,8 +13955,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -11352,8 +13966,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -11361,8 +13977,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11370,8 +13988,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -11379,8 +13999,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -11388,8 +14010,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -11397,8 +14021,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11406,8 +14032,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -11415,8 +14043,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -11424,8 +14054,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -11433,8 +14065,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -11442,8 +14076,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11451,8 +14087,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -11460,8 +14098,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -11469,8 +14109,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -11478,8 +14120,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11487,8 +14131,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -11496,8 +14142,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -11505,8 +14153,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -11514,8 +14164,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -11523,8 +14175,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11532,8 +14186,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -11541,8 +14197,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -11550,8 +14208,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -11559,8 +14219,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11568,8 +14230,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -11577,8 +14241,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -11586,8 +14252,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -11595,8 +14263,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -11604,8 +14274,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11613,8 +14285,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -11622,8 +14296,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -11631,8 +14307,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -11640,8 +14318,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -11649,8 +14329,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -11658,8 +14340,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -11667,8 +14351,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -11676,8 +14362,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -11685,8 +14373,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -11694,8 +14384,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -11703,8 +14395,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -11712,8 +14406,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -11721,8 +14417,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -11730,8 +14428,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -11739,8 +14439,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -11748,8 +14450,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -11757,8 +14461,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -11766,8 +14472,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -11775,8 +14483,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -11784,8 +14494,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -11793,8 +14505,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -11802,8 +14516,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -11811,8 +14527,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -11820,8 +14538,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -11829,8 +14549,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -11838,8 +14560,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -11847,8 +14571,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -11856,8 +14582,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -11865,8 +14593,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -11874,8 +14604,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -11883,8 +14615,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -11892,8 +14626,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -11901,8 +14637,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -11910,8 +14648,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -11919,8 +14659,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -11928,8 +14670,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -11937,8 +14681,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -11946,8 +14692,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -11955,8 +14703,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -11964,8 +14714,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -11973,8 +14725,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -11982,8 +14736,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -11991,8 +14747,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -12000,8 +14758,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -12009,8 +14769,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -12018,8 +14780,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -12027,8 +14791,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -12036,8 +14802,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -12045,8 +14813,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -12054,8 +14824,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -12063,8 +14835,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -12072,8 +14846,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -12081,8 +14857,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -12090,8 +14868,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -12099,8 +14879,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -12108,8 +14890,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -12117,8 +14901,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -12126,8 +14912,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -12135,8 +14923,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -12144,8 +14934,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -12153,8 +14945,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -12162,8 +14956,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -12171,8 +14967,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -12180,8 +14978,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -12189,8 +14989,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -12198,8 +15000,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -12207,8 +15011,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -12216,8 +15022,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -12225,8 +15033,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -12234,8 +15044,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -12243,8 +15055,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -12252,8 +15066,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -12261,8 +15077,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -12270,8 +15088,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -12279,8 +15099,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -12288,8 +15110,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -12297,8 +15121,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -12306,8 +15132,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -12315,8 +15143,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -12324,8 +15154,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -12333,8 +15165,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -12342,8 +15176,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -12351,8 +15187,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -12360,8 +15198,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -12369,8 +15209,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -12378,8 +15220,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -12387,8 +15231,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -12396,8 +15242,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -12405,8 +15253,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -12414,8 +15264,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -12423,8 +15275,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -12432,8 +15286,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -12441,8 +15297,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -12450,8 +15308,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -12459,8 +15319,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -12468,8 +15330,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -12477,8 +15341,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x2", @@ -12486,8 +15352,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x8", @@ -12495,8 +15363,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x4", @@ -12504,8 +15374,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x10", @@ -12513,8 +15385,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x40", @@ -12522,8 +15396,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x20", @@ -12531,8 +15407,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VNA", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits ava= ilable to send to UPIs on the AD Ring", "UMask": "0x1", @@ -12540,8 +15418,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x4", @@ -12549,8 +15429,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x2", @@ -12558,8 +15440,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x8", @@ -12567,8 +15451,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x20", @@ -12576,8 +15462,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x10", @@ -12585,8 +15473,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x40", @@ -12594,8 +15484,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VNA", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits ava= ilable to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", "UMask": "0x1", @@ -12603,16 +15495,20 @@ }, { "BriefDescription": "FlowQ Generated Prefetch", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "FlowQ Generated Prefetch : Count cases where= FlowQ causes spawn of Prefetch to iMC/SMI3 target", "Unit": "M3UPI" }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -12620,8 +15516,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -12629,8 +15527,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -12638,8 +15538,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -12647,8 +15549,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -12656,8 +15560,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -12665,8 +15571,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -12674,8 +15582,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M3UPI_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -12683,8 +15593,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -12692,8 +15604,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -12701,8 +15615,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -12710,8 +15626,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -12719,8 +15637,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -12728,8 +15648,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -12737,8 +15659,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -12746,8 +15670,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -12755,8 +15681,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -12764,8 +15692,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -12773,8 +15703,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -12782,8 +15714,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -12791,8 +15725,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -12800,8 +15736,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M3UPI_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -12809,8 +15747,10 @@ }, { "BriefDescription": "VN0 Credit Used : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : WB on BL : Number of times= a VN0 credit was used on the DRS message channel. In order for a request = to be transferred across UPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN0.= VNA is a shared pool used to achieve high performance. The VN0 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN0 if= they fail. This counts the number of times a VN0 credit was used. Note t= hat a single VN0 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN0 will only count a single credit ev= en though it may use multiple buffers. : Data Response (WB) messages on BL.= WB is generally used to transmit data with coherency. For example, remot= e reads and writes, or cache to cache transfers will transmit their data us= ing WB.", "UMask": "0x10", @@ -12818,8 +15758,10 @@ }, { "BriefDescription": "VN0 Credit Used : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : NCB on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -12827,8 +15769,10 @@ }, { "BriefDescription": "VN0 Credit Used : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : REQ on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -12836,8 +15780,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -12845,8 +15791,10 @@ }, { "BriefDescription": "VN0 Credit Used : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : SNP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -12854,8 +15802,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -12863,8 +15813,10 @@ }, { "BriefDescription": "VN0 No Credits : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles= there were no VN0 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -12872,8 +15824,10 @@ }, { "BriefDescription": "VN0 No Credits : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycle= s there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -12881,8 +15835,10 @@ }, { "BriefDescription": "VN0 No Credits : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycle= s there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -12890,8 +15846,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -12899,8 +15857,10 @@ }, { "BriefDescription": "VN0 No Credits : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycle= s there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -12908,8 +15868,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -12917,8 +15879,10 @@ }, { "BriefDescription": "VN1 Credit Used : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : WB on BL : Number of times= a VN1 credit was used on the WB message channel. In order for a request t= o be transferred across QPI, it must be guaranteed to have a flit buffer on= the remote socket to sink into. There are two credit pools, VNA and VN1. = VNA is a shared pool used to achieve high performance. The VN1 pool has r= eserved entries for each message class and is used to prevent deadlock. Re= quests first attempt to acquire a VNA credit, and then fall back to VN1 if = they fail. This counts the number of times a VN1 credit was used. Note th= at a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that = case uses 9 credits. A transfer on VN1 will only count a single credit eve= n though it may use multiple buffers. : Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote= reads and writes, or cache to cache transfers will transmit their data usi= ng WB.", "UMask": "0x10", @@ -12926,8 +15890,10 @@ }, { "BriefDescription": "VN1 Credit Used : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : NCB on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messa= ges on BL. NCB is generally used to transmit data without coherency. For = example, non-coherent read data returns.", "UMask": "0x20", @@ -12935,8 +15901,10 @@ }, { "BriefDescription": "VN1 Credit Used : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : REQ on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Home (REQ) messages on AD. REQ is= generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -12944,8 +15912,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on AD. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x4", @@ -12953,8 +15923,10 @@ }, { "BriefDescription": "VN1 Credit Used : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : SNP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP = is used for outgoing snoops.", "UMask": "0x2", @@ -12962,8 +15934,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on BL. RSP= packets are used to transmit a variety of protocol flits including grants = and completions (CMP).", "UMask": "0x8", @@ -12971,8 +15945,10 @@ }, { "BriefDescription": "VN1 No Credits : WB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles= there were no VN1 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -12980,8 +15956,10 @@ }, { "BriefDescription": "VN1 No Credits : NCB on BL", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycle= s there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -12989,8 +15967,10 @@ }, { "BriefDescription": "VN1 No Credits : REQ on AD", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycle= s there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -12998,8 +15978,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -13007,8 +15989,10 @@ }, { "BriefDescription": "VN1 No Credits : SNP on AD", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycle= s there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -13016,8 +16000,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on BL", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -13025,168 +16011,210 @@ }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x82", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7E", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Counter": "0,1,2,3", "EventCode": "0x7D", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message is making arbitration= request", "UMask": "0x4", @@ -13194,8 +16222,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message arrived in ingress pi= peline", "UMask": "0x1", @@ -13203,8 +16233,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message took bypass path", "UMask": "0x2", @@ -13212,8 +16244,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was slotted into flit= (non bypass)", "UMask": "0x10", @@ -13221,8 +16255,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message lost arbitration", "UMask": "0x8", @@ -13230,8 +16266,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t became too old", "UMask": "0x20", @@ -13239,8 +16277,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t was overwritten by new message while prefetch queue was full", "UMask": "0x20", @@ -13248,6 +16288,7 @@ }, { "BriefDescription": "Number of kfclks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -13256,8 +16297,10 @@ }, { "BriefDescription": "Direct packet attempts : D2C", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2C : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x1", @@ -13265,8 +16308,10 @@ }, { "BriefDescription": "Direct packet attempts : D2K", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2K : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x2", @@ -13274,70 +16319,87 @@ }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", @@ -13346,182 +16408,228 @@ }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_UPI_POWER_L1_NACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req Nack : Counts the number of times a l= ink sends/receives a LinkReqNAck. When the UPI links would like to change = power state, the Tx side initiates a request to the Rx side requesting to c= hange states. This requests can either be accepted or denied. If the Rx s= ide replies with an Ack, the power mode will change. If it replies with NA= ck, no change will take place. This can be filtered based on Rx and Tx. A= n Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx origi= nally requested the power change). A Tx LinkReqNAck refers to sending this= command (meaning the peer agent's Tx originally requested the power change= and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "L1 Req (same as L1 Ack).", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_UPI_POWER_L1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number= of times a link sends/receives a LinkReqAck. When the UPI links would lik= e to change power state, the Tx side initiates a request to the Rx side req= uesting to change states. This requests can either be accepted or denied. = If the Rx side replies with an Ack, the power mode will change. If it rep= lies with NAck, no change will take place. This can be filtered based on R= x and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent'= s Tx originally requested the power change). A Tx LinkReqAck refers to sen= ding this command (meaning the peer agent's Tx originally requested the pow= er change and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles s= pent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lane= s, decreasing our bandwidth in order to save power. It increases snoop and= data transfer latencies and decreases overall bandwidth. This mode can be= very useful in NUMA optimized workloads that largely only utilize UPI for = snoops and their responses. Use edge detect to count the number of instanc= es when the UPI link entered L0p. Link power states are per link and per d= irection, so for example the Tx direction could be in one state while Rx wa= s in another.", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMa= sk specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcod= e (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Ena= ble R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enabl= e Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even un= der specific opcode match_en cases. Note: If Message Class is disabled, we = expect opcode to also be disabled.", "UMask": "0xe", @@ -13529,8 +16637,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Matc= h based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class E= nable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S= : Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single = Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, = LLCRD) even under specific opcode match_en cases. Note: If Message Class is= disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -13538,8 +16648,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard : Matches on Receive path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xf", @@ -13547,8 +16659,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -13556,8 +16670,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Requ= est : Matches on Receive path of a UPI port. Match based on UMask specific = bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V:= Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-D= ata Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer= control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific= opcode match_en cases. Note: If Message Class is disabled, we expect opcod= e to also be disabled.", "UMask": "0x8", @@ -13565,8 +16681,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Requ= est, Match Opcode : Matches on Receive path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0x108", @@ -13574,8 +16692,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - Conflict : Matches on Receive path of a UPI port. Match based on UMa= sk specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcod= e (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Ena= ble R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enabl= e Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even un= der specific opcode match_en cases. Note: If Message Class is disabled, we = expect opcode to also be disabled.", "UMask": "0x1aa", @@ -13583,8 +16703,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - Invalid : Matches on Receive path of a UPI port. Match based on UMas= k specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode= (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enab= le R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable= Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even und= er specific opcode match_en cases. Note: If Message Class is disabled, we e= xpect opcode to also be disabled.", "UMask": "0x12a", @@ -13592,8 +16714,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - Data : Matches on Receive path of a UPI port. Match based on UMask s= pecific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4= -bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable = R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Li= nk Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even under = specific opcode match_en cases. Note: If Message Class is disabled, we expe= ct opcode to also be disabled.", "UMask": "0xc", @@ -13601,8 +16725,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - Data, Match Opcode : Matches on Receive path of a UPI port. Match ba= sed on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enabl= e W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Da= ta Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot= Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCR= D) even under specific opcode match_en cases. Note: If Message Class is dis= abled, we expect opcode to also be disabled.", "UMask": "0x10c", @@ -13610,8 +16736,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - No Data : Matches on Receive path of a UPI port. Match based on UMas= k specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode= (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enab= le R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable= Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even und= er specific opcode match_en cases. Note: If Message Class is disabled, we e= xpect opcode to also be disabled.", "UMask": "0xa", @@ -13619,8 +16747,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Resp= onse - No Data, Match Opcode : Matches on Receive path of a UPI port. Match= based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class En= able W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S:= Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single S= lot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, L= LCRD) even under specific opcode match_en cases. Note: If Message Class is = disabled, we expect opcode to also be disabled.", "UMask": "0x10a", @@ -13628,8 +16758,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= ", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Snoo= p : Matches on Receive path of a UPI port. Match based on UMask specific bi= ts: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V: O= pcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-Dat= a Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer c= ontrol types are excluded (LL CTRL, slot NULL, LLCRD) even under specific o= pcode match_en cases. Note: If Message Class is disabled, we expect opcode = to also be disabled.", "UMask": "0x9", @@ -13637,8 +16769,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= , Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Snoo= p, Match Opcode : Matches on Receive path of a UPI port. Match based on UMa= sk specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcod= e (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Ena= ble R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enabl= e Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even un= der specific opcode match_en cases. Note: If Message Class is disabled, we = expect opcode to also be disabled.", "UMask": "0x109", @@ -13646,8 +16780,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Write= back", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Writ= eback : Matches on Receive path of a UPI port. Match based on UMask specifi= c bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) = V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non= -Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Lay= er control types are excluded (LL CTRL, slot NULL, LLCRD) even under specif= ic opcode match_en cases. Note: If Message Class is disabled, we expect opc= ode to also be disabled.", "UMask": "0xd", @@ -13655,8 +16791,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Write= back, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Writ= eback, Match Opcode : Matches on Receive path of a UPI port. Match based on= UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: O= pcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr= Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr E= nable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) eve= n under specific opcode match_en cases. Note: If Message Class is disabled,= we expect opcode to also be disabled.", "UMask": "0x10d", @@ -13664,8 +16802,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", @@ -13673,8 +16813,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", @@ -13682,8 +16824,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", @@ -13691,46 +16835,57 @@ }, { "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", "EventCode": "0x0B", "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CRC Errors Detected : Number of CRC errors d= etected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for err= or detection. This counts the number of flits where the CRC was able to de= tect an error. After an error has been detected, the UPI agent will send a= request to the transmitting socket to resend the flit (as well as any flit= s that came after it).", "Unit": "UPI" }, { "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "LLR Requests Sent : Number of LLR Requests w= ere transmitted. This should generally be <=3D the number of CRC errors de= tected. If multiple errors are detected before the Rx side receives a LLC_= REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs.", "Unit": "UPI" }, { "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Consumed : Counts the number of t= imes that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Consumed : Counts the number of t= imes that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VNA Credit Consumed : Counts the number of t= imes that an RxQ VNA credit was consumed (i.e. message uses a VNA credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -13740,6 +16895,7 @@ }, { "BriefDescription": "Valid Flits Received : Null FLITs received fr= om any slot", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -13749,8 +16905,10 @@ }, { "BriefDescription": "Valid Flits Received : Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Data : Shows legal fl= it time (hides impact of L0p and L0c). : Count Data Flits (which consume al= l slots), but how much to count is based on Slot0-2 mask, so count can be 0= -3 depending on which slots are enabled for counting..", "UMask": "0x8", @@ -13758,8 +16916,10 @@ }, { "BriefDescription": "Valid Flits Received : Null FLITs received fr= om any slot", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Null FLITs received f= rom any slot : Shows legal flit time (hides impact of L0p and L0c).", "UMask": "0x47", @@ -13767,8 +16927,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables counting of LLC= RD (with non-zero payload). This only applies to slot 2 since LLCRD is only= allowed in slot 2", "UMask": "0x10", @@ -13776,8 +16938,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal = flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. E= nables counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -13785,6 +16949,7 @@ }, { "BriefDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -13794,8 +16959,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Emp= ty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Em= pty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all= zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dua= l slot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -13803,8 +16970,10 @@ }, { "BriefDescription": "Valid Flits Received : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Protocol Header : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables count of protoc= ol headers in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -13812,8 +16981,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits d= etermine types of headers to count.", "UMask": "0x1", @@ -13821,8 +16992,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits d= etermine types of headers to count.", "UMask": "0x2", @@ -13830,8 +17003,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits d= etermine types of headers to count.", "UMask": "0x4", @@ -13839,8 +17014,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x1", @@ -13848,8 +17025,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x2", @@ -13857,8 +17036,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x4", @@ -13866,8 +17047,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x1", @@ -13875,8 +17058,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x2", @@ -13884,8 +17069,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x4", @@ -13893,118 +17080,147 @@ }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -14013,30 +17229,38 @@ }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass : Matches on Transmit path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xe", @@ -14044,8 +17268,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -14053,8 +17279,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard : Matches on Transmit path of a UPI port. Match based on= UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: O= pcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr= Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr E= nable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) eve= n under specific opcode match_en cases. Note: If Message Class is disabled,= we expect opcode to also be disabled.", "UMask": "0xf", @@ -14062,8 +17290,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. = Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Cla= ss Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enab= le S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Sin= gle Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NU= LL, LLCRD) even under specific opcode match_en cases. Note: If Message Clas= s is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -14071,8 +17301,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Req= uest : Matches on Transmit path of a UPI port. Match based on UMask specifi= c bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) = V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non= -Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Lay= er control types are excluded (LL CTRL, slot NULL, LLCRD) even under specif= ic opcode match_en cases. Note: If Message Class is disabled, we expect opc= ode to also be disabled.", "UMask": "0x8", @@ -14080,8 +17312,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Req= uest, Match Opcode : Matches on Transmit path of a UPI port. Match based on= UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: O= pcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr= Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr E= nable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) eve= n under specific opcode match_en cases. Note: If Message Class is disabled,= we expect opcode to also be disabled.", "UMask": "0x108", @@ -14089,8 +17323,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - Conflict : Matches on Transmit path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0x1aa", @@ -14098,8 +17334,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - Invalid : Matches on Transmit path of a UPI port. Match based on UM= ask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opco= de (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr En= able R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enab= le Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even u= nder specific opcode match_en cases. Note: If Message Class is disabled, we= expect opcode to also be disabled.", "UMask": "0x12a", @@ -14107,8 +17345,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - Data : Matches on Transmit path of a UPI port. Match based on UMask= specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode = (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enabl= e R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable = Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even unde= r specific opcode match_en cases. Note: If Message Class is disabled, we ex= pect opcode to also be disabled.", "UMask": "0xc", @@ -14116,8 +17356,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - Data, Match Opcode : Matches on Transmit path of a UPI port. Match = based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Ena= ble W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: = Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Sl= ot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, LL= CRD) even under specific opcode match_en cases. Note: If Message Class is d= isabled, we expect opcode to also be disabled.", "UMask": "0x10c", @@ -14125,8 +17367,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - No Data : Matches on Transmit path of a UPI port. Match based on UM= ask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opco= de (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr En= able R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enab= le Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even u= nder specific opcode match_en cases. Note: If Message Class is disabled, we= expect opcode to also be disabled.", "UMask": "0xa", @@ -14134,8 +17378,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Res= ponse - No Data, Match Opcode : Matches on Transmit path of a UPI port. Mat= ch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class = Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable = S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single= Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL,= LLCRD) even under specific opcode match_en cases. Note: If Message Class i= s disabled, we expect opcode to also be disabled.", "UMask": "0x10a", @@ -14143,8 +17389,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Sno= op : Matches on Transmit path of a UPI port. Match based on UMask specific = bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit) V:= Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: Non-D= ata Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link Layer= control types are excluded (LL CTRL, slot NULL, LLCRD) even under specific= opcode match_en cases. Note: If Message Class is disabled, we expect opcod= e to also be disabled.", "UMask": "0x9", @@ -14152,8 +17400,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Sno= op, Match Opcode : Matches on Transmit path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0x109", @@ -14161,8 +17411,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Wri= teback : Matches on Transmit path of a UPI port. Match based on UMask speci= fic bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcode (4-bit= ) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Enable R: N= on-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enable Link L= ayer control types are excluded (LL CTRL, slot NULL, LLCRD) even under spec= ific opcode match_en cases. Note: If Message Class is disabled, we expect o= pcode to also be disabled.", "UMask": "0xd", @@ -14170,8 +17422,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Wri= teback, Match Opcode : Matches on Transmit path of a UPI port. Match based = on UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W:= Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data H= dr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr= Enable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) e= ven under specific opcode match_en cases. Note: If Message Class is disable= d, we expect opcode to also be disabled.", "UMask": "0x10d", @@ -14179,14 +17433,17 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number = of times that an incoming flit was able to bypass the Tx flit buffer and pa= ss directly out the UPI Link. Generally, when data is transmitted across UP= I, it will bypass the TxQ and pass directly to the link. However, the TxQ = will be used with L0p and when LLR occurs, increasing latency to transfer o= ut to the link.", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -14196,6 +17453,7 @@ }, { "BriefDescription": "Valid Flits Sent : Null FLITs transmitted to = any slot", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -14205,8 +17463,10 @@ }, { "BriefDescription": "Valid Flits Sent : Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Data : Shows legal flit t= ime (hides impact of L0p and L0c). : Count Data Flits (which consume all sl= ots), but how much to count is based on Slot0-2 mask, so count can be 0-3 d= epending on which slots are enabled for counting..", "UMask": "0x8", @@ -14214,8 +17474,10 @@ }, { "BriefDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit t= ime (hides impact of L0p and L0c).", "UMask": "0x47", @@ -14223,8 +17485,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows l= egal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (= with non-zero payload). This only applies to slot 2 since LLCRD is only all= owed in slot 2", "UMask": "0x10", @@ -14232,8 +17496,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit= time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enabl= es counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -14241,6 +17507,7 @@ }, { "BriefDescription": "Valid Flits Sent : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -14250,8 +17517,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty = : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zer= os is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual sl= ot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -14259,8 +17528,10 @@ }, { "BriefDescription": "Valid Flits Sent : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Protocol Header : Shows l= egal flit time (hides impact of L0p and L0c). : Enables count of protocol h= eaders in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -14268,8 +17539,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits deter= mine types of headers to count.", "UMask": "0x1", @@ -14277,8 +17550,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits deter= mine types of headers to count.", "UMask": "0x2", @@ -14286,8 +17561,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits deter= mine types of headers to count.", "UMask": "0x4", @@ -14295,37 +17572,46 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Allocations : Number of alloc= ations into the UPI Tx Flit Buffer. Generally, when data is transmitted ac= ross UPI, it will bypass the TxQ and pass directly to the link. However, t= he TxQ will be used with L0p and when LLR occurs, increasing latency to tra= nsfer out to the link. This event can be used in conjunction with the Flit= Buffer Occupancy event in order to calculate the average flit buffer lifet= ime.", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the n= umber of flits in the TxQ. Generally, when data is transmitted across UPI,= it will bypass the TxQ and pass directly to the link. However, the TxQ wi= ll be used with L0p and when LLR occurs, increasing latency to transfer out= to the link. This can be used with the cycles not empty event to track ave= rage occupancy, or the allocations event to track average lifetime in the T= xQ.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VNA Credits Pending Return - Occupancy : Num= ber of VNA credits in the Rx side that are waitng to be returned back acros= s the link.", "Unit": "UPI" }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", @@ -14333,16 +17619,20 @@ }, { "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", @@ -14350,8 +17640,10 @@ }, { "BriefDescription": "Message Received : IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", "UMask": "0x4", @@ -14359,8 +17651,10 @@ }, { "BriefDescription": "Message Received : MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", "UMask": "0x2", @@ -14368,8 +17662,10 @@ }, { "BriefDescription": "Message Received : VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", "UMask": "0x1", @@ -14377,160 +17673,200 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times = an IDI Lock/SplitLock sequence was started", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", "UMask": "0x1", @@ -14538,32 +17874,40 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json b/tools= /perf/pmu-events/arch/x86/icelakex/uncore-io.json index 1b8a719b81a5..3c3c2cf51e1d 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-io.json @@ -1,70 +1,87 @@ [ { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x23", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x25", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x26", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x27", "Unit": "iio_free_running" }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -73,6 +90,7 @@ }, { "BriefDescription": "Free running counter that increments for IIO = clocktick", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", @@ -82,8 +100,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PortMask": "0xFF", @@ -92,6 +112,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -103,6 +124,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", "FCMask": "0x04", @@ -114,6 +136,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", "FCMask": "0x04", @@ -125,6 +148,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", "FCMask": "0x04", @@ -136,6 +160,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", "FCMask": "0x04", @@ -147,6 +172,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", "FCMask": "0x04", @@ -158,6 +184,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", "FCMask": "0x04", @@ -169,6 +196,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", "FCMask": "0x04", @@ -180,6 +208,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", "FCMask": "0x04", @@ -191,8 +220,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", @@ -201,6 +232,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -211,6 +243,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", "FCMask": "0x04", @@ -221,6 +254,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", "FCMask": "0x04", @@ -231,6 +265,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", "FCMask": "0x04", @@ -241,6 +276,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", "FCMask": "0x04", @@ -251,6 +287,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", "FCMask": "0x04", @@ -261,6 +298,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", "FCMask": "0x04", @@ -271,6 +309,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", "FCMask": "0x04", @@ -281,6 +320,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", "FCMask": "0x04", @@ -291,8 +331,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -302,8 +344,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -313,8 +357,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -324,8 +370,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -335,8 +383,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -346,8 +396,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -357,8 +409,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -368,8 +422,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -379,8 +435,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -390,8 +448,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -401,8 +461,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -412,8 +474,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -423,8 +487,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -434,8 +500,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -445,8 +513,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -456,8 +526,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -467,8 +539,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -478,8 +552,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -489,8 +565,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -500,8 +578,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -511,8 +591,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -522,8 +604,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -533,8 +617,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -544,8 +630,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -555,8 +643,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -566,8 +656,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -577,8 +669,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -588,8 +682,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -599,8 +695,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -610,8 +708,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -621,8 +721,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -632,8 +734,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -643,8 +747,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -654,8 +760,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -665,8 +773,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -676,8 +786,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -687,8 +799,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -698,8 +812,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -709,8 +825,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -720,8 +838,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -731,8 +851,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -742,8 +864,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -753,6 +877,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -764,6 +889,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -775,6 +901,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -786,6 +913,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -797,6 +925,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -808,6 +937,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -819,6 +949,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -830,6 +961,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -841,8 +973,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -852,8 +986,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -863,6 +999,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -874,6 +1011,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -885,6 +1023,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -896,6 +1035,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -907,6 +1047,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -918,6 +1059,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -929,6 +1071,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -940,6 +1083,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -951,8 +1095,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -962,8 +1108,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -973,8 +1121,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -984,8 +1134,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -995,8 +1147,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1006,8 +1160,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1017,8 +1173,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1028,8 +1186,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1039,8 +1199,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1050,8 +1212,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1061,8 +1225,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1072,8 +1238,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1083,8 +1251,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1094,8 +1264,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1105,8 +1277,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1116,8 +1290,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1127,8 +1303,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1138,8 +1316,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1149,8 +1329,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1160,8 +1342,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1171,8 +1355,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1182,8 +1368,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1193,8 +1381,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1204,8 +1394,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1215,8 +1407,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1226,8 +1420,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1237,8 +1433,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1248,8 +1446,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1259,8 +1459,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1270,8 +1472,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1281,8 +1485,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1292,8 +1498,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1303,6 +1511,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -1314,6 +1523,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -1325,6 +1535,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -1336,6 +1547,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -1347,6 +1559,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -1358,6 +1571,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -1369,6 +1583,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -1380,6 +1595,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -1391,8 +1607,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1402,8 +1620,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1413,6 +1633,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1424,6 +1645,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1435,6 +1657,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1446,6 +1669,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1457,6 +1681,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1468,6 +1693,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1479,6 +1705,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1490,6 +1717,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1501,8 +1729,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1512,8 +1742,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1523,6 +1755,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1534,6 +1767,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1545,6 +1779,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1556,6 +1791,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1567,6 +1803,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1578,6 +1815,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1589,6 +1827,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1600,6 +1839,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1611,8 +1851,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1622,8 +1864,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1633,8 +1877,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1644,8 +1890,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1655,8 +1903,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1666,8 +1916,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1677,8 +1929,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1688,8 +1942,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1699,8 +1955,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1710,8 +1968,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1721,8 +1981,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1732,8 +1994,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1743,8 +2007,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1754,8 +2020,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1765,8 +2033,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1776,8 +2046,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1787,8 +2059,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1798,8 +2072,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1809,8 +2085,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1820,8 +2098,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1831,8 +2111,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1842,8 +2124,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1853,8 +2137,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1864,8 +2150,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1875,8 +2163,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1886,8 +2176,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1897,8 +2189,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1908,8 +2202,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1919,8 +2215,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1930,8 +2228,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1941,8 +2241,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1952,8 +2254,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1963,8 +2267,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1974,8 +2280,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1985,8 +2293,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1996,8 +2306,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2007,8 +2319,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2018,8 +2332,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2029,8 +2345,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2040,8 +2358,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2051,8 +2371,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2062,8 +2384,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2073,8 +2397,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", "UMask": "0x10", @@ -2082,8 +2408,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", "UMask": "0x8", @@ -2091,8 +2419,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", "UMask": "0x4", @@ -2100,8 +2430,10 @@ }, { "BriefDescription": ": IOTLB lookups all", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups all : Some transactions have= to look up IOTLB multiple times. Counts every time a request looks up IOT= LB.", "UMask": "0x2", @@ -2109,8 +2441,10 @@ }, { "BriefDescription": ": Context cache hits", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", "UMask": "0x80", @@ -2118,8 +2452,10 @@ }, { "BriefDescription": ": Context cache lookups", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", "UMask": "0x40", @@ -2127,8 +2463,10 @@ }, { "BriefDescription": ": IOTLB lookups first", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", "UMask": "0x1", @@ -2136,8 +2474,10 @@ }, { "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a = transaction misses IOTLB, it does a page walk to look up memory and bring i= n the relevant page translation. Counts when this page translation is writt= en to IOTLB.", "UMask": "0x20", @@ -2145,8 +2485,10 @@ }, { "BriefDescription": ": Cycles PWT full", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU = has reached its maximum limit for outstanding page walks.", "UMask": "0x80", @@ -2154,8 +2496,10 @@ }, { "BriefDescription": ": IOMMU memory access", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", "UMask": "0x40", @@ -2163,8 +2507,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -2172,8 +2518,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -2181,8 +2529,10 @@ }, { "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", "UMask": "0x2", @@ -2190,8 +2540,10 @@ }, { "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", "UMask": "0x10", @@ -2199,8 +2551,10 @@ }, { "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", "UMask": "0x20", @@ -2208,8 +2562,10 @@ }, { "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", "UMask": "0x1", @@ -2217,8 +2573,10 @@ }, { "BriefDescription": ": Interrupt Entry cache hit", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache hit : Counts each ti= me a transaction's first look up hits the IEC.", "UMask": "0x80", @@ -2226,8 +2584,10 @@ }, { "BriefDescription": ": Interrupt Entry cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache lookup : Counts the = number of transaction looks up that interrupt remapping cache.", "UMask": "0x40", @@ -2235,8 +2595,10 @@ }, { "BriefDescription": ": Device-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Device-selective Context cache invalidatio= n cycles : Counts number of Device selective context cache invalidation eve= nts", "UMask": "0x20", @@ -2244,8 +2606,10 @@ }, { "BriefDescription": ": Domain-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective Context cache invalidatio= n cycles : Counts number of Domain selective context cache invalidation eve= nts", "UMask": "0x10", @@ -2253,8 +2617,10 @@ }, { "BriefDescription": ": Context cache global invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache global invalidation cycles := Counts number of Context Cache global invalidation events", "UMask": "0x8", @@ -2262,8 +2628,10 @@ }, { "BriefDescription": ": Domain-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective IOTLB invalidation cycles= : Counts number of Domain selective invalidation events", "UMask": "0x2", @@ -2271,8 +2639,10 @@ }, { "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", "UMask": "0x1", @@ -2280,8 +2650,10 @@ }, { "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Page-selective IOTLB invalidation cycles := Counts number of Page-selective within Domain Invalidation events", "UMask": "0x4", @@ -2289,8 +2661,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", "UMask": "0x1", @@ -2298,8 +2672,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x8", @@ -2307,8 +2683,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x4", @@ -2316,8 +2694,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", "UMask": "0x2", @@ -2325,8 +2705,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x10", @@ -2334,8 +2716,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x20", @@ -2343,8 +2727,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", "UMask": "0x1", @@ -2352,8 +2738,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x8", @@ -2361,8 +2749,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x4", @@ -2370,8 +2760,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", "UMask": "0x2", @@ -2379,8 +2771,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x10", @@ -2388,8 +2782,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x20", @@ -2397,15 +2793,19 @@ }, { "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_IIO_NOTHING", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Occupancy of outbound request queue : To devi= ce", + "Counter": "2,3", "EventCode": "0xC5", "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2415,8 +2815,10 @@ }, { "BriefDescription": ": Passing data to be written", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2426,8 +2828,10 @@ }, { "BriefDescription": ": Issuing final read or write of line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2436,8 +2840,10 @@ }, { "BriefDescription": ": Processing response from IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2446,8 +2852,10 @@ }, { "BriefDescription": ": Issuing to IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2456,8 +2864,10 @@ }, { "BriefDescription": ": Request Ownership", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2467,8 +2877,10 @@ }, { "BriefDescription": ": Writing line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2478,8 +2890,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = From ITC", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2489,8 +2903,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = Completion allocations", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2499,8 +2915,10 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = Drop request", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2510,6 +2928,7 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", @@ -2521,8 +2940,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2531,8 +2952,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2541,8 +2964,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2551,8 +2976,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2561,8 +2988,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2571,8 +3000,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2581,8 +3012,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2591,8 +3024,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2601,15 +3036,19 @@ }, { "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2619,8 +3058,10 @@ }, { "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2630,16 +3071,20 @@ }, { "BriefDescription": "PWT occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", "Unit": "IIO" }, { "BriefDescription": "PCIe Request - cacheline complete : Passing d= ata to be written", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2649,8 +3094,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Issuing f= inal read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2660,8 +3107,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Request O= wnership", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2671,8 +3120,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Writing l= ine", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2682,8 +3133,10 @@ }, { "BriefDescription": "PCIe Request complete : Passing data to be wr= itten", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2693,8 +3146,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing final read or= write of line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2704,8 +3159,10 @@ }, { "BriefDescription": "PCIe Request complete : Processing response f= rom IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2715,8 +3172,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2726,8 +3185,10 @@ }, { "BriefDescription": "PCIe Request complete : Request Ownership", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2737,8 +3198,10 @@ }, { "BriefDescription": "PCIe Request complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2748,8 +3211,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2759,8 +3224,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2770,8 +3237,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2781,8 +3250,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2792,16 +3263,20 @@ }, { "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_IIO_SYMBOL_TIMES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Symbol Times on Link : Gen1 - increment once= every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1n= S", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2811,8 +3286,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2822,8 +3299,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2833,8 +3312,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2844,8 +3325,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2855,8 +3338,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -2866,8 +3351,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -2877,8 +3364,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -2888,8 +3377,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -2899,8 +3390,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -2910,8 +3403,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2921,8 +3416,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2932,8 +3429,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2943,8 +3442,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2954,8 +3455,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2965,8 +3468,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -2976,8 +3481,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -2987,8 +3494,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -2998,8 +3507,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3009,8 +3520,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3020,8 +3533,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3031,8 +3546,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3042,8 +3559,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3053,8 +3572,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3064,8 +3585,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3075,8 +3598,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3086,8 +3611,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3097,8 +3624,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3108,8 +3637,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3119,8 +3650,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3130,8 +3663,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3141,8 +3676,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3152,8 +3689,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3163,8 +3702,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3174,8 +3715,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3185,8 +3728,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3196,8 +3741,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3207,8 +3754,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3218,8 +3767,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3229,8 +3780,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3240,8 +3793,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3251,8 +3806,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3262,6 +3819,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3273,6 +3831,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3284,6 +3843,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3295,6 +3855,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3306,6 +3867,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3317,6 +3879,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -3328,6 +3891,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -3339,6 +3903,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -3350,8 +3915,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3361,8 +3928,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3372,6 +3941,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3383,6 +3953,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3394,6 +3965,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3405,6 +3977,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3416,6 +3989,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -3427,6 +4001,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -3438,6 +4013,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -3449,6 +4025,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -3460,8 +4037,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3471,8 +4050,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3482,8 +4063,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3493,8 +4076,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3504,8 +4089,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3515,8 +4102,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3526,8 +4115,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3537,8 +4128,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3548,8 +4141,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3559,8 +4154,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3570,8 +4167,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3581,8 +4180,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3592,8 +4193,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3603,8 +4206,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3614,8 +4219,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3625,8 +4232,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3636,8 +4245,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3647,8 +4258,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3658,8 +4271,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3669,8 +4284,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3680,8 +4297,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3691,8 +4310,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3702,8 +4323,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3713,8 +4336,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3724,8 +4349,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3735,8 +4362,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3746,8 +4375,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3757,8 +4388,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3768,8 +4401,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3779,8 +4414,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3790,8 +4427,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3801,6 +4440,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -3812,6 +4452,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -3823,6 +4464,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -3834,6 +4476,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -3845,6 +4488,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -3856,6 +4500,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -3867,6 +4512,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -3878,6 +4524,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -3889,8 +4536,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3900,8 +4549,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3911,6 +4562,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3922,6 +4574,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3933,6 +4586,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3944,6 +4598,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3955,6 +4610,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3966,6 +4622,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -3977,6 +4634,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -3988,6 +4646,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -3999,8 +4658,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4010,8 +4671,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4021,6 +4684,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -4032,6 +4696,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -4043,6 +4708,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -4054,6 +4720,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -4065,6 +4732,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -4076,6 +4744,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -4087,6 +4756,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -4098,6 +4768,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -4109,8 +4780,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4120,8 +4793,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4131,8 +4806,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4142,8 +4819,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4153,8 +4832,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4164,8 +4845,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4175,8 +4858,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4186,8 +4871,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4197,8 +4884,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4208,8 +4897,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4219,8 +4910,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4230,8 +4923,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4241,8 +4936,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4252,8 +4949,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4263,8 +4962,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4274,8 +4975,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4285,8 +4988,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4296,8 +5001,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4307,8 +5014,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4318,8 +5027,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4329,8 +5040,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4340,8 +5053,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4351,8 +5066,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4362,8 +5079,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4373,8 +5092,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4384,8 +5105,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4395,8 +5118,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4406,8 +5131,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4417,8 +5144,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4428,8 +5157,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4439,8 +5170,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4448,8 +5181,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4457,8 +5192,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4466,8 +5203,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4475,8 +5214,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4484,8 +5225,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4493,8 +5236,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4502,8 +5247,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4511,8 +5258,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4520,8 +5269,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4529,8 +5280,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4538,8 +5291,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4547,8 +5302,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4556,8 +5313,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4565,8 +5324,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4574,8 +5335,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4583,8 +5346,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4592,8 +5357,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4601,8 +5368,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4610,8 +5379,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4619,8 +5390,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4628,8 +5401,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4637,8 +5412,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4646,8 +5423,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4655,8 +5434,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4664,8 +5445,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4673,8 +5456,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4682,8 +5467,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4691,8 +5478,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4700,8 +5489,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4709,8 +5500,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4718,8 +5511,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4727,8 +5522,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4736,8 +5533,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4745,8 +5544,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4754,8 +5555,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4763,8 +5566,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4772,8 +5577,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4781,8 +5588,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4790,8 +5599,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4799,8 +5610,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4808,8 +5621,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4817,8 +5632,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4826,8 +5643,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4835,8 +5654,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4844,8 +5665,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4853,8 +5676,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4862,8 +5687,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4871,8 +5698,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4880,8 +5709,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4889,8 +5720,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4898,8 +5731,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4907,8 +5742,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4916,8 +5753,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4925,8 +5764,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4934,8 +5775,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4943,8 +5786,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4952,8 +5797,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4961,8 +5808,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4970,8 +5819,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4979,8 +5830,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4988,8 +5841,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4997,8 +5852,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5006,8 +5863,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5015,8 +5874,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5024,8 +5885,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5033,8 +5896,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5042,8 +5907,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5051,8 +5918,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -5060,8 +5929,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -5069,8 +5940,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -5078,8 +5951,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -5087,8 +5962,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -5096,8 +5973,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -5105,8 +5984,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -5114,8 +5995,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5123,8 +6006,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5132,8 +6017,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5141,8 +6028,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5150,8 +6039,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -5159,8 +6050,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -5168,8 +6061,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -5177,8 +6072,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -5186,8 +6083,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -5195,8 +6094,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5204,8 +6105,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5213,8 +6116,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5222,8 +6127,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5231,6 +6138,7 @@ }, { "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", @@ -5239,6 +6147,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", @@ -5246,8 +6155,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -5255,8 +6166,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -5264,8 +6177,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -5273,8 +6188,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -5282,8 +6199,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -5291,8 +6210,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : If the CHA TOR has too many PMM transactions, this signal will th= rottle outgoing MS2IDI traffic", "UMask": "0x10", @@ -5300,8 +6221,10 @@ }, { "BriefDescription": "Distress signal asserted : PMM Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2P_DISTRESS_ASSERTED.PMM_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : PMM Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If another CHA TOR has too many PMM transactions, this signal wi= ll throttle outgoing MS2IDI traffic", "UMask": "0x20", @@ -5309,8 +6232,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -5318,8 +6243,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -5327,8 +6254,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -5336,8 +6265,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5345,8 +6276,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5354,8 +6287,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5363,8 +6298,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5372,8 +6309,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5381,8 +6320,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5390,8 +6331,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5399,8 +6342,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5408,8 +6353,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5417,8 +6364,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5426,8 +6375,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5435,8 +6386,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5444,8 +6397,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5453,8 +6408,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5462,8 +6419,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5471,8 +6430,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5480,8 +6441,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -5489,8 +6452,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -5498,8 +6463,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x1", @@ -5507,8 +6474,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x2", @@ -5516,8 +6485,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x4", @@ -5525,8 +6496,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x8", @@ -5534,8 +6507,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", @@ -5543,8 +6518,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", @@ -5552,8 +6529,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", "UMask": "0x8", @@ -5561,8 +6540,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", "UMask": "0x10", @@ -5570,8 +6551,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", "UMask": "0x20", @@ -5579,8 +6562,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x1", @@ -5588,8 +6573,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x2", @@ -5597,8 +6584,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x4", @@ -5606,8 +6595,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x8", @@ -5615,8 +6606,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", "UMask": "0x10", @@ -5624,8 +6617,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", "UMask": "0x20", @@ -5633,912 +6628,1140 @@ }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -6546,8 +7769,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -6555,8 +7780,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -6564,8 +7791,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -6573,8 +7802,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -6582,8 +7813,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -6591,8 +7824,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -6600,8 +7835,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -6609,8 +7846,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -6618,95 +7857,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2P_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2PCIe" }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x80", @@ -6714,8 +7977,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x1", @@ -6723,8 +7988,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x2", @@ -6732,8 +7999,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x4", @@ -6741,8 +8010,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x20", @@ -6750,8 +8021,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x40", @@ -6759,8 +8032,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x8", @@ -6768,8 +8043,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x10", @@ -6777,8 +8054,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x80", @@ -6786,8 +8065,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x1", @@ -6795,8 +8076,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x2", @@ -6804,8 +8087,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x4", @@ -6813,8 +8098,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x20", @@ -6822,8 +8109,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x40", @@ -6831,8 +8120,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x8", @@ -6840,8 +8131,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x10", @@ -6849,8 +8142,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6858,8 +8153,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -6867,8 +8164,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -6876,8 +8175,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6885,8 +8186,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -6894,8 +8197,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -6903,8 +8208,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6912,8 +8219,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -6921,8 +8230,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -6930,8 +8241,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -6939,8 +8252,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -6948,8 +8263,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6957,8 +8274,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -6966,8 +8285,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -6975,8 +8296,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -6984,8 +8307,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6993,8 +8318,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -7002,8 +8329,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -7011,8 +8340,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -7020,8 +8351,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7029,8 +8362,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -7038,8 +8373,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -7047,8 +8384,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -7056,8 +8395,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -7065,16 +8406,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7082,8 +8427,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -7091,8 +8438,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -7100,8 +8449,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -7109,8 +8460,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -7118,8 +8471,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7127,8 +8482,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -7136,8 +8493,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -7145,8 +8504,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -7154,8 +8515,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7163,8 +8526,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -7172,8 +8537,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -7181,8 +8548,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -7190,8 +8559,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -7199,8 +8570,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7208,8 +8581,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -7217,8 +8592,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -7226,8 +8603,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -7235,8 +8614,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7244,8 +8625,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7253,8 +8636,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7262,8 +8647,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7271,8 +8658,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7280,8 +8669,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7289,8 +8680,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7298,8 +8691,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7307,8 +8702,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7316,8 +8713,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7325,8 +8724,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7334,8 +8735,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7343,8 +8746,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7352,8 +8757,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7361,8 +8768,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7370,8 +8779,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7379,8 +8790,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7388,8 +8801,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7397,8 +8812,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7406,8 +8823,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7415,8 +8834,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7424,8 +8845,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7433,8 +8856,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7442,8 +8867,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7451,8 +8878,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7460,8 +8889,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7469,8 +8900,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7478,8 +8911,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7487,8 +8922,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7496,8 +8933,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7505,8 +8944,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7514,8 +8955,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7523,8 +8966,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7532,8 +8977,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7541,8 +8988,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7550,8 +8999,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7559,8 +9010,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7568,8 +9021,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7577,8 +9032,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7586,8 +9043,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7595,8 +9054,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7604,8 +9065,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7613,8 +9076,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7622,8 +9087,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7631,24 +9098,30 @@ }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "Counter": "0,1", "EventCode": "0x2D", "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x1", @@ -7656,8 +9129,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x10", @@ -7665,8 +9140,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x2", @@ -7674,8 +9151,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x20", @@ -7683,8 +9162,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x4", @@ -7692,8 +9173,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x40", @@ -7701,8 +9184,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x80", @@ -7710,8 +9195,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x8", @@ -7719,8 +9206,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x1", @@ -7728,8 +9217,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x10", @@ -7737,8 +9228,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x2", @@ -7746,8 +9239,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x20", @@ -7755,8 +9250,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x4", @@ -7764,8 +9261,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x40", @@ -7773,8 +9272,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x80", @@ -7782,8 +9283,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x8", @@ -7791,8 +9294,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x1", @@ -7800,8 +9305,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x10", @@ -7809,8 +9316,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x8", @@ -7818,8 +9327,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x80", @@ -7827,8 +9338,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x4", @@ -7836,8 +9349,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x40", @@ -7845,8 +9360,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7854,8 +9371,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -7863,8 +9382,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -7872,8 +9393,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7881,8 +9404,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -7890,8 +9415,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -7899,8 +9426,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7908,8 +9437,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -7917,8 +9448,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -7926,8 +9459,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -7935,8 +9470,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -7944,8 +9481,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7953,8 +9492,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -7962,8 +9503,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -7971,8 +9514,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -7980,8 +9525,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7989,8 +9536,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -7998,8 +9547,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -8007,8 +9558,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -8016,8 +9569,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -8025,8 +9580,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8034,8 +9591,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -8043,8 +9602,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -8052,8 +9613,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -8061,8 +9624,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8070,8 +9635,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -8079,8 +9646,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8088,8 +9657,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -8097,8 +9668,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -8106,8 +9679,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8115,8 +9690,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -8124,8 +9701,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8133,8 +9712,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -8142,8 +9723,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8151,8 +9734,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -8160,8 +9745,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -8169,8 +9756,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -8178,8 +9767,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -8187,8 +9778,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8196,8 +9789,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -8205,8 +9800,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -8214,8 +9811,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -8223,8 +9822,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -8232,8 +9833,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -8241,8 +9844,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -8250,8 +9855,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -8259,8 +9866,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -8268,8 +9877,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -8277,8 +9888,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -8286,8 +9899,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -8295,8 +9910,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -8304,8 +9921,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -8313,8 +9932,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -8322,8 +9943,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -8331,8 +9954,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8340,8 +9965,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -8349,8 +9976,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8358,8 +9987,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -8367,8 +9998,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -8376,8 +10009,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8385,8 +10020,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -8394,8 +10031,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -8403,8 +10042,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -8412,8 +10053,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -8421,8 +10064,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -8430,8 +10075,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -8439,8 +10086,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -8448,8 +10097,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -8457,8 +10108,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -8466,8 +10119,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -8475,8 +10130,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -8484,8 +10141,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -8493,8 +10152,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -8502,8 +10163,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -8511,8 +10174,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -8520,8 +10185,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -8529,8 +10196,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -8538,8 +10207,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -8547,8 +10218,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -8556,8 +10229,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -8565,8 +10240,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8574,8 +10251,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -8583,8 +10262,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8592,8 +10273,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8601,8 +10284,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8610,8 +10295,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8619,8 +10306,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -8628,8 +10317,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8637,8 +10328,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8646,8 +10339,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -8655,8 +10350,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -8664,8 +10361,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8673,8 +10372,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8682,8 +10383,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8691,8 +10394,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8700,8 +10405,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -8709,8 +10416,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -8718,8 +10427,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8727,8 +10438,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8736,8 +10449,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -8745,8 +10460,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -8754,8 +10471,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8763,8 +10482,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -8772,8 +10493,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -8781,8 +10504,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -8790,8 +10515,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8799,8 +10526,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -8808,8 +10537,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8817,8 +10548,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -8826,8 +10559,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8835,8 +10570,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -8844,8 +10581,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -8853,8 +10592,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -8862,8 +10603,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -8871,8 +10614,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8880,8 +10625,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8889,8 +10636,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8898,8 +10647,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -8907,8 +10658,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -8916,8 +10669,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8925,8 +10680,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -8934,8 +10691,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -8943,8 +10702,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -8952,8 +10713,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8961,8 +10724,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -8970,8 +10735,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -8979,8 +10746,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -8988,8 +10757,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -8997,8 +10768,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -9006,8 +10779,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -9015,8 +10790,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -9024,8 +10801,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -9033,8 +10812,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -9042,8 +10823,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -9051,8 +10834,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -9060,8 +10845,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9069,8 +10856,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9078,8 +10867,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9087,8 +10878,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9096,8 +10889,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9105,8 +10900,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9114,8 +10911,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9123,8 +10922,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9132,8 +10933,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9141,8 +10944,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9150,8 +10955,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9159,8 +10966,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -9168,8 +10977,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9177,8 +10988,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9186,8 +10999,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -9195,8 +11010,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -9204,8 +11021,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -9213,8 +11032,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -9222,8 +11043,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -9231,8 +11054,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -9240,8 +11065,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -9249,8 +11076,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json index 814d9599474d..87604c953c0f 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count : All Activates", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -10,8 +11,10 @@ }, { "BriefDescription": "DRAM Activate Count : Activate due to Bypass", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Activate Count : Activate due to Bypass= : Counts the number of DRAM Activate commands sent on this channel. Activ= ate commands are issued to open up a page on the DRAM devices so that it ca= n be read or written to with a CAS. One can calculate the number of Page M= isses by subtracting the number of Page Miss precharges from the number of = Activates.", "UMask": "0x8", @@ -19,6 +22,7 @@ }, { "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -28,6 +32,7 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -37,8 +42,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CA= S commands w/auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total= number or DRAM Read CAS commands issued on this channel. This includes bo= th regular RD CAS commands as well as those with explicit Precharge. AutoP= re is only used in systems that are using closed page policy. We do not fi= lter based on major mode, as RD_CAS is not issued during WMM (with the exce= ption of underfills).", "UMask": "0x2", @@ -46,8 +53,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0x8", @@ -55,8 +64,10 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of DRAM Read CAS com= mands issued on this channel. This includes both regular RD CAS commands a= s well as those with implicit Precharge. We do not filter based on major = mode, as RD_CAS is not issued during WMM (with the exception of underfills)= .", "UMask": "0x1", @@ -64,8 +75,10 @@ }, { "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total of DRAM Read CAS commands i= ssued due to an underfill", "UMask": "0x4", @@ -73,6 +86,7 @@ }, { "BriefDescription": "All DRAM write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -82,8 +96,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x10", @@ -91,8 +107,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/ auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x20", @@ -100,28 +118,34 @@ }, { "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Free running counter that increments for the = Memory Controller", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "imc_free_running" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -131,6 +155,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", "PerPkg": "1", @@ -140,6 +165,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -149,6 +175,7 @@ }, { "BriefDescription": "Half clockticks for IMC", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", @@ -156,37 +183,46 @@ }, { "BriefDescription": "UNC_M_PARITY_ERRORS", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M_PARITY_ERRORS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.TOTAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "PMM Commands : All", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.ALL", "PerPkg": "1", @@ -196,22 +232,27 @@ }, { "BriefDescription": "PMM Commands : Misc Commands (error, flow ACK= s)", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.MISC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "PMM Commands : Misc GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.MISC_GNT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "PMM Commands : Reads - RPQ", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.RD", "PerPkg": "1", @@ -221,14 +262,17 @@ }, { "BriefDescription": "PMM Commands : RPQ GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.RPQ_GNTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "PMM Commands : Underfill reads", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.UFILL_RD", "PerPkg": "1", @@ -238,14 +282,17 @@ }, { "BriefDescription": "PMM Commands : Underfill GNTs", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.WPQ_GNTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "PMM Commands : Writes", + "Counter": "0,1,2,3", "EventCode": "0xEA", "EventName": "UNC_M_PMM_CMD1.WR", "PerPkg": "1", @@ -255,84 +302,105 @@ }, { "BriefDescription": "PMM Commands - Part 2 : Expected No data pack= et (ERID matched NDP encoding)", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.NODATA_EXP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : Unexpected No data pa= cket (ERID matched a Read, but data was a NDP)", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.NODATA_UNEXP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : Opportunistic Reads", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.OPP_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : ECC Errors", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.PMM_ECC_ERROR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : ERID detectable parit= y error", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.PMM_ERID_ERROR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.PMM_ERID_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot = 0", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.REQS_SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "PMM Commands - Part 2 : Read Requests - Slot = 1", + "Counter": "0,1,2,3", "EventCode": "0xEB", "EventName": "UNC_M_PMM_CMD2.REQS_SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "PMM Read Queue Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M_PMM_RPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Read Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M_PMM_RPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Read Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M_PMM_RPQ_INSERTS", "PerPkg": "1", @@ -341,6 +409,7 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -350,8 +419,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x4", @@ -359,8 +430,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x2", @@ -368,34 +441,43 @@ }, { "BriefDescription": "PMM Write Queue Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M_PMM_WPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PMM_WPQ_FLUSH", + "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "UNC_M_PMM_WPQ_FLUSH", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PMM_WPQ_FLUSH_CYC", + "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "UNC_M_PMM_WPQ_FLUSH_CYC", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Write Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0xE7", "EventName": "UNC_M_PMM_WPQ_INSERTS", "PerPkg": "1", @@ -404,6 +486,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -413,8 +496,10 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Write Pending Queue Occupancy : Accumula= tes the per cycle occupancy of the PMM Write Pending Queue.", "UMask": "0x2", @@ -422,8 +507,10 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Write Pending Queue Occupancy : Accumula= tes the per cycle occupancy of the PMM Write Pending Queue.", "UMask": "0x4", @@ -431,16 +518,20 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Channel PPD Cycles : Number of cycles when a= ll the ranks in the channel are in PPD mode. If IBT=3Doff is enabled, then= this can be used to count those cycles. If it is not enabled, then this c= an count the number of cycles when that could have been taken advantage of.= ", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x1", @@ -448,8 +539,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x2", @@ -457,8 +550,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x4", @@ -466,8 +561,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x8", @@ -475,8 +572,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -484,8 +583,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -493,16 +594,20 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Clock-Enabled Self-Refresh : Counts the numb= er of cycles when the iMC is in self-refresh and the iMC still has a clock.= This happens in some package C-states. For example, the PCU may ask the = iMC to enter self-refresh even though some of the cores are still processin= g. One use of this is for Monroe technology. Self-refresh is required dur= ing package C3 and C6, but there is no clock in the iMC at this time, so it= is not possible to count these cases.", "Unit": "iMC" }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -510,8 +615,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -519,6 +626,7 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -528,8 +636,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = page miss : Counts the number of DRAM Precharge commands sent on this chann= el. : Pages Misses are due to precharges from bank scheduler (rd/wr request= s)", "UMask": "0xc", @@ -537,6 +647,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -546,6 +657,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to r= ead", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -555,6 +667,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to w= rite", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -564,52 +677,66 @@ }, { "BriefDescription": "Read Data Buffer Full", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NOT_EMPTY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x1", @@ -617,8 +744,10 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x2", @@ -626,6 +755,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", @@ -635,6 +765,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", @@ -644,6 +775,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -652,6 +784,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -660,749 +793,930 @@ }, { "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Acc= epted", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FMRD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FMWR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Accepts", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Rejects", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NMRD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NMWR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM read completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM write completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Accepts", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Rejects", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Scoreboard Accesses Rej= ected", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM read completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM write completions", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Alloc", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.ALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Dealloc", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_CANARY.FM_RD_STARVED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FMRD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FMTGRWR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_CANARY.FM_WR_STARVED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FMWR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_CANARY.NM_RD_STARVED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NMRD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_CANARY.NM_WR_STARVED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NMWR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Valid", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Reject", + "Counter": "0,1,2,3", "EventCode": "0xD9", "EventName": "UNC_M_SB_CANARY.VLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M_SB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M_SB_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Reads", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Writes", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M_SB_INSERTS.WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Reads", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0xDA", "EventName": "UNC_M_SB_PREF_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xDA", "EventName": "UNC_M_SB_PREF_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : Persistent Mem", + "Counter": "0,1,2,3", "EventCode": "0xDA", "EventName": "UNC_M_SB_PREF_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_PREF_OCCUPANCY.PMM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Me= m", + "Counter": "0,1,2,3", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.CANARY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : FM r= equests rejected due to full address conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : NM r= equests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : Patr= ol requests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_ALLOC.FM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_ALLOC.FM_TGR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FMTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_ALLOC.FM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_ALLOC.NM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_ALLOC.NM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_DEALLOC.FM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_DEALLOC.FM_TGR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FMTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_DEALLOC.FM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xDE", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xDE", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xDE", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_DEALLOC.NM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_DEALLOC.NM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xDE", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xDE", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_OCC.FM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_OCC.FM_TGR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FMTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_OCC.FM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_OCC.NM_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NMRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M_SB_STRV_OCC.NM_WR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xD8", "EventName": "UNC_M_SB_STRV_OCC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.NEW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.OCC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", "EventCode": "0xDD", "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "2LM Tag Check : Hit in Near Memory Cache", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", @@ -1411,6 +1725,7 @@ }, { "BriefDescription": "2LM Tag Check : Miss, no data in this line", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", @@ -1419,6 +1734,7 @@ }, { "BriefDescription": "2LM Tag Check : Miss, existing data may be ev= icted to Far Memory", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", @@ -1427,6 +1743,7 @@ }, { "BriefDescription": "2LM Tag Check : Read Hit in Near Memory Cache= ", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.NM_RD_HIT", "PerPkg": "1", @@ -1435,6 +1752,7 @@ }, { "BriefDescription": "2LM Tag Check : Write Hit in Near Memory Cach= e", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M_TAGCHK.NM_WR_HIT", "PerPkg": "1", @@ -1443,24 +1761,30 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x1", @@ -1468,8 +1792,10 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x2", @@ -1477,6 +1803,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", @@ -1486,6 +1813,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", @@ -1495,6 +1823,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -1503,6 +1832,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -1511,8 +1841,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -1520,8 +1852,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -1529,8 +1863,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -1538,8 +1874,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/icelakex/uncore-power.json index 920cab6ffe37..03984d61ab29 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clockticks of the power control unit (PCU)", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Clockticks of the power control unit (PCU) := The PCU runs off a fixed 1 GHz clock. This event counts the number of pcl= k cycles measured while the counter was enabled. The pclk, like the Memory= Controller's dclk, counts at a constant rate making it a good measure of a= ctual wall time.", @@ -8,147 +9,185 @@ }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C3 : Counts the = number of cycles when the package was in C3. This event can be used in con= junction with edge detect to count C3 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State : C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C0 and C1 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0x40", @@ -156,8 +195,10 @@ }, { "BriefDescription": "Number of cores in C-State : C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C3 : This is an= occupancy event that tracks the number of cores that are in the chosen C-S= tate. It can be used by itself to get the average number of cores in that = C-state with thresholding to generate histograms, or with other PCU events = and occupancy triggering to capture other details.", "UMask": "0x80", @@ -165,8 +206,10 @@ }, { "BriefDescription": "Number of cores in C-State : C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C6 and C7 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0xc0", @@ -174,32 +217,40 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" diff --git a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json index e3227c7f2fe9..9df790d4361f 100644 --- a/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/icelakex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -156,6 +175,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index bb16463d9701..9056784e23f7 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -15,7 +15,7 @@ GenuineIntel-6-A[DE],v1.02,graniterapids,core GenuineIntel-6-(3C|45|46),v35,haswell,core GenuineIntel-6-3F,v28,haswellx,core GenuineIntel-6-7[DE],v1.22,icelake,core -GenuineIntel-6-6[AC],v1.24,icelakex,core +GenuineIntel-6-6[AC],v1.26,icelakex,core GenuineIntel-6-3A,v24,ivybridge,core GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E7981B9AA6 for ; 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Thu, 20 Jun 2024 11:19:56 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:32 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-19-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 18/37] perf vendor events: Update ivybridge metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/ivybridge/cache.json | 104 +++++++++++++++ .../arch/x86/ivybridge/counter.json | 17 +++ .../arch/x86/ivybridge/floating-point.json | 17 +++ .../arch/x86/ivybridge/frontend.json | 30 +++++ .../arch/x86/ivybridge/ivb-metrics.json | 68 +++++----- .../pmu-events/arch/x86/ivybridge/memory.json | 19 +++ .../arch/x86/ivybridge/metricgroups.json | 11 ++ .../pmu-events/arch/x86/ivybridge/other.json | 4 + .../arch/x86/ivybridge/pipeline.json | 126 ++++++++++++++++++ .../arch/x86/ivybridge/uncore-cache.json | 25 ++++ .../x86/ivybridge/uncore-interconnect.json | 9 ++ .../arch/x86/ivybridge/virtual-memory.json | 18 +++ 12 files changed, 417 insertions(+), 31 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivybridge/counter.json diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/cache.json index 46570b522095..563ec3f71c5a 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -18,6 +20,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_E", "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_M", "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.MISS", "PublicDescription": "Not rejected writebacks that missed LLC.", @@ -75,6 +84,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "L2 cache lines filling L2.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "L2 cache lines in E state filling L2.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "L2 cache lines in I state filling L2.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "L2 cache lines in S state filling L2.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Dirty L2 cache lines filling the L2", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DIRTY_ALL", "PublicDescription": "Dirty L2 cache lines filling the L2.", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", @@ -147,6 +165,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts all L2 code requests.", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", @@ -163,6 +183,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", @@ -171,6 +192,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts all L2 store RFO requests.", @@ -179,6 +201,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", @@ -187,6 +210,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", @@ -211,6 +237,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", @@ -219,6 +246,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "RFO requests that hit L2 cache.", @@ -227,6 +255,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", @@ -235,6 +264,7 @@ }, { "BriefDescription": "RFOs that access cache lines in any state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.ALL", "PublicDescription": "RFOs that access cache lines in any state.", @@ -243,6 +273,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "PublicDescription": "RFOs that hit cache lines in M state.", @@ -251,6 +282,7 @@ }, { "BriefDescription": "RFOs that miss cache lines", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.MISS", "PublicDescription": "RFOs that miss cache lines.", @@ -259,6 +291,7 @@ }, { "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", @@ -267,6 +300,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "Transactions accessing L2 pipe.", @@ -275,6 +309,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "L2 cache accesses when fetching instructions= .", @@ -283,6 +318,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests that access L2 cac= he.", @@ -291,6 +327,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "L1D writebacks that access L2 cache.", @@ -299,6 +336,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "L2 fill requests that access L2 cache.", @@ -307,6 +345,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "L2 writebacks that access L2 cache.", @@ -315,6 +354,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "PublicDescription": "RFO requests that access L2 cache.", @@ -323,6 +363,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", @@ -331,6 +372,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", @@ -339,6 +381,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", @@ -347,6 +390,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", "PEBS": "1", @@ -355,6 +399,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", "PEBS": "1", @@ -363,6 +408,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", @@ -371,6 +417,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "PEBS": "1", @@ -379,6 +426,7 @@ }, { "BriefDescription": "Retired load uops which data sources missed L= LC but serviced from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", "PublicDescription": "Retired load uops whose data source was loca= l memory (cross-socket snoop not needed or missed).", @@ -387,6 +435,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", @@ -395,6 +444,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", @@ -403,6 +453,7 @@ }, { "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", @@ -411,6 +462,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", @@ -419,6 +471,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", @@ -427,6 +480,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", @@ -435,6 +489,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", "PEBS": "1", @@ -443,6 +498,7 @@ }, { "BriefDescription": "All retired load uops. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", @@ -451,6 +507,7 @@ }, { "BriefDescription": "All retired store uops. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", @@ -459,6 +516,7 @@ }, { "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", @@ -467,6 +525,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", @@ -475,6 +534,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", @@ -483,6 +543,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", @@ -491,6 +552,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", @@ -499,6 +561,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", @@ -507,6 +570,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Demand code read requests sent to uncore.", @@ -515,6 +579,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Demand data read requests sent to uncore.", @@ -523,6 +588,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", @@ -531,6 +597,7 @@ }, { "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", @@ -539,6 +606,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -547,6 +615,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -556,6 +625,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -565,6 +635,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -574,6 +645,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -583,6 +655,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -591,6 +664,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -599,6 +673,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -608,6 +683,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -616,6 +692,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -625,6 +702,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -634,6 +712,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -643,6 +722,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -652,6 +732,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -661,6 +742,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -670,6 +752,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -679,6 +762,7 @@ }, { "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -688,6 +772,7 @@ }, { "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -697,6 +782,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -706,6 +792,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -715,6 +802,7 @@ }, { "BriefDescription": "Counts all writebacks from the core to the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -724,6 +812,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -733,6 +822,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -742,6 +832,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -751,6 +842,7 @@ }, { "BriefDescription": "Counts all demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -760,6 +852,7 @@ }, { "BriefDescription": "Counts all demand data reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -769,6 +862,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -778,6 +872,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -787,6 +882,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -796,6 +892,7 @@ }, { "BriefDescription": "Counts all demand rfo's", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -805,6 +902,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -814,6 +912,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -823,6 +922,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -832,6 +932,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -841,6 +942,7 @@ }, { "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -850,6 +952,7 @@ }, { "BriefDescription": "Counts non-temporal stores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -859,6 +962,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/counter.json b/tools/= perf/pmu-events/arch/x86/ivybridge/counter.json new file mode 100644 index 000000000000..35bb154900d7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivybridge/counter.json @@ -0,0 +1,17 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "ARB", + "CountersNumFixed": "1", + "CountersNumGeneric": "2" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b= /tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json index 89c6d47cc077..336fa00ad006 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "Number of SIMD FP assists due to input value= s.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "Number of SIMD FP assists due to output valu= es.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "Number of X87 FP assists due to input values= .", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "Number of X87 FP assists due to output value= s.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIV= s, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish= an FADD used in the middle of a transcendental flow from a s", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "PublicDescription": "Counts number of X87 uops executed.", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "SampleAfterValue": "1000003", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_STORE", "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", @@ -118,6 +133,7 @@ }, { "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", @@ -126,6 +142,7 @@ }, { "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_SINGLE", "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools= /perf/pmu-events/arch/x86/ivybridge/frontend.json index 4ee100024ca9..0d6c829a6023 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "Number of DSB to MITE switches.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Cycles DSB to MITE switches caused delay.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.EXCEED_DSB_LINES", "PublicDescription": "DSB Fill encountered > 3 DSB lines.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFETCH_STALL", "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", @@ -110,6 +123,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "PublicDescription": "Counts cycles the IDQ is empty.", @@ -118,6 +132,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", @@ -143,6 +160,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -152,6 +170,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -161,6 +180,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -197,6 +220,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", @@ -205,6 +229,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -221,6 +247,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/to= ols/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json index 5f3f0b5aebad..77d37db98b70 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json @@ -90,7 +90,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -100,7 +100,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -121,7 +121,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -151,7 +151,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1= + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD= _UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_U= OPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + M= EM_LOAD_UOPS_RETIRED.LLC_MISS))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP= _MISS * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT = + MEM_LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + = MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSN= P_MISS + MEM_LOAD_UOPS_RETIRED.LLC_MISS)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -172,7 +172,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 += MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_U= OPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOP= S_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM= _LOAD_UOPS_RETIRED.LLC_MISS))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -181,7 +181,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -218,7 +218,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -227,7 +227,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES= .WALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -236,7 +236,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER= _CORE / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -246,7 +246,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -320,7 +320,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -340,7 +340,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_it= lb_misses", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -447,12 +447,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -473,7 +473,7 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -485,7 +485,7 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -497,7 +497,13 @@ "MetricName": "tma_info_memory_l2mpki" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -549,7 +555,7 @@ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cm= ask\\=3D1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" @@ -568,13 +574,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -669,7 +675,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -678,7 +684,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -696,7 +702,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY= .STALLS_L2_PENDING) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -716,7 +722,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "29 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD= _UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIR= ED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT= _RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOP= S_RETIRED.LLC_MISS))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -765,7 +771,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -775,7 +781,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -784,7 +790,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -922,7 +928,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -930,7 +936,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -959,7 +965,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -987,7 +993,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/p= erf/pmu-events/arch/x86/ivybridge/memory.json index fd1fe491c577..40f40384d58b 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -30,6 +33,7 @@ }, { "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -52,6 +57,7 @@ }, { "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -63,6 +69,7 @@ }, { "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -74,6 +81,7 @@ }, { "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -85,6 +93,7 @@ }, { "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -96,6 +105,7 @@ }, { "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -104,6 +114,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", @@ -120,6 +132,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +142,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +162,7 @@ }, { "BriefDescription": "Counts LLC replacements", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +172,7 @@ }, { "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +182,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +192,7 @@ }, { "BriefDescription": "Number of any page walk that had a miss in LL= C.", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "PAGE_WALKS.LLC_MISS", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/metricgroups.json b/t= ools/perf/pmu-events/arch/x86/ivybridge/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/pe= rf/pmu-events/arch/x86/ivybridge/other.json index e80e99d064ba..2e796d533c13 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools= /perf/pmu-events/arch/x86/ivybridge/pipeline.json index 30a3da9cd22b..da05eaaae22c 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Divide operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -11,6 +12,7 @@ }, { "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "PublicDescription": "Speculative and retired macro-conditional br= anches.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "PublicDescription": "Speculative and retired direct near calls.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "Not taken macro-conditional branches.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", @@ -90,6 +101,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired direct near ca= lls.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired indirect calls= .", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", @@ -122,6 +137,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Branch instructions at retirement.", @@ -129,6 +145,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -137,6 +154,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Number of far branches retired.", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", @@ -193,6 +217,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -201,6 +226,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", @@ -209,6 +235,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", @@ -217,6 +244,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -225,6 +253,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", @@ -233,6 +262,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", @@ -241,6 +271,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", @@ -249,6 +280,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", @@ -257,6 +289,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", @@ -265,6 +298,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Mispredicted branch instructions at retireme= nt.", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -303,6 +341,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", @@ -312,6 +351,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -319,6 +359,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -326,12 +367,14 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", @@ -341,6 +384,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -348,6 +392,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2" @@ -355,6 +400,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", "SampleAfterValue": "2000003", @@ -362,6 +408,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", @@ -370,6 +417,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", @@ -377,6 +425,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -385,6 +434,7 @@ }, { "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -394,6 +444,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -402,6 +453,7 @@ }, { "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -411,6 +463,7 @@ }, { "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -420,6 +473,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -428,6 +482,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -437,6 +492,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -445,6 +501,7 @@ }, { "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -454,6 +511,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -462,6 +520,7 @@ }, { "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -471,6 +530,7 @@ }, { "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -479,6 +539,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -487,6 +548,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -495,6 +557,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "PublicDescription": "Stall cycles due to IQ is full.", @@ -503,6 +566,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", @@ -510,12 +574,14 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PublicDescription": "Number of instructions at retirement.", @@ -523,6 +589,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", @@ -532,6 +599,7 @@ }, { "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -541,6 +609,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -549,6 +618,7 @@ }, { "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc.)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -558,6 +628,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -566,6 +637,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", @@ -574,6 +646,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", @@ -582,6 +655,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", @@ -590,6 +664,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", @@ -598,6 +673,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -607,6 +683,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -616,6 +693,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -623,6 +701,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -632,6 +711,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", @@ -640,6 +720,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Number of self-modifying-code machine clears= detected.", @@ -648,6 +729,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "SampleAfterValue": "1000003", @@ -655,6 +737,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -662,6 +745,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "SampleAfterValue": "100003", @@ -669,6 +753,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", @@ -677,6 +762,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -684,6 +770,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -691,6 +778,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", @@ -699,6 +787,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Count cases of saving new LBR records by har= dware.", @@ -707,6 +796,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Cycles the RS is empty for the thread.", @@ -715,6 +805,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -725,6 +816,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Cycles which a Uop is dispatched on port 0.", @@ -734,6 +826,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", @@ -742,6 +835,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Cycles which a Uop is dispatched on port 1.", @@ -751,6 +845,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", @@ -759,6 +854,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Cycles which a Uop is dispatched on port 2.", @@ -768,6 +864,7 @@ { "AnyThread": "1", "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -775,6 +872,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Cycles which a Uop is dispatched on port 3.", @@ -784,6 +882,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", @@ -792,6 +891,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Cycles which a Uop is dispatched on port 4.", @@ -801,6 +901,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", @@ -809,6 +910,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Cycles which a Uop is dispatched on port 5.", @@ -818,6 +920,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", @@ -826,6 +929,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", @@ -834,6 +938,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -843,6 +948,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -852,6 +958,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -861,6 +968,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -870,6 +978,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -879,6 +988,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -888,6 +998,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -897,6 +1008,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -906,6 +1018,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -915,6 +1028,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -924,6 +1038,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", @@ -932,6 +1047,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", @@ -941,6 +1057,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -951,6 +1068,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", @@ -959,6 +1077,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", @@ -967,6 +1086,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", @@ -975,6 +1095,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -985,6 +1106,7 @@ }, { "BriefDescription": "Retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -994,6 +1116,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -1003,6 +1126,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1011,6 +1135,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1020,6 +1145,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "10", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json b/t= ools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json index be9a3ed1a940..8379dae91be4 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -129,6 +145,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", @@ -137,6 +154,7 @@ }, { "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", @@ -153,6 +172,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", @@ -193,6 +217,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.j= son b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json index c3252c094a9c..ba340e858ed4 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles weighted by number of requests pending= in Coherency Tracker.", + "Counter": "0", "EventCode": "0x83", "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts cycles weighted by the number of reque= sts waiting for data returning from the memory controller. Accounts for coh= erent and non-coherent requests initiated by IA cores, processor graphic un= its, or LLC.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with at least half of the requests out= standing are waiting for data return from memory controller. Account for co= herent and non-coherent requests initiated by IA Cores, Processor Graphics = Unit, or LLC.", + "Counter": "0,1", "CounterMask": "10", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0,1", "CounterMask": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of LLC evictions allocated.= ", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", "PerPkg": "1", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Counts the number of allocated write entries,= include full, partial, and LLC evictions.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", @@ -67,6 +75,7 @@ }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "Fixed", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json index b97f15cb20fc..8c6128eff958 100644 --- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Page walk for a large page completed for Dema= nd load.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "PublicDescription": "Cycles PMH is busy with this walk.", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -79,6 +89,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", @@ -95,6 +107,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", @@ -103,6 +116,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Number of cache load STLB hits. No page walk= .", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", @@ -119,6 +134,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "Cycle PMH is busy with a walk.", @@ -127,6 +143,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", @@ -135,6 +152,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9555A1B9AA8 for ; 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Thu, 20 Jun 2024 11:19:59 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:33 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-20-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 19/37] perf vendor events: Update ivytown metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/ivytown/cache.json | 118 ++++++ .../pmu-events/arch/x86/ivytown/counter.json | 52 +++ .../arch/x86/ivytown/floating-point.json | 17 + .../pmu-events/arch/x86/ivytown/frontend.json | 30 ++ .../arch/x86/ivytown/ivt-metrics.json | 68 ++-- .../pmu-events/arch/x86/ivytown/memory.json | 41 ++ .../arch/x86/ivytown/metricgroups.json | 11 + .../pmu-events/arch/x86/ivytown/other.json | 4 + .../pmu-events/arch/x86/ivytown/pipeline.json | 126 ++++++ .../arch/x86/ivytown/uncore-cache.json | 349 ++++++++++++++++ .../arch/x86/ivytown/uncore-interconnect.json | 385 ++++++++++++++++++ .../arch/x86/ivytown/uncore-io.json | 61 +++ .../arch/x86/ivytown/uncore-memory.json | 198 +++++++++ .../arch/x86/ivytown/uncore-power.json | 74 ++++ .../arch/x86/ivytown/virtual-memory.json | 20 + 15 files changed, 1523 insertions(+), 31 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/ivytown/counter.json diff --git a/tools/perf/pmu-events/arch/x86/ivytown/cache.json b/tools/perf= /pmu-events/arch/x86/ivytown/cache.json index 0e8e77253978..4b2128f1a765 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts the number of lines brought into the = L1 data cache.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -18,6 +20,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Increments the number of outstanding L1D mis= ses every cycle. Set Cmask =3D 1 and Edge =3D1 to count occurrences.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_E", "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in E state.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_M", "PublicDescription": "Not rejected writebacks from L1D to L2 cache= lines in M state.", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.MISS", "PublicDescription": "Not rejected writebacks that missed LLC.", @@ -75,6 +84,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "L2 cache lines filling L2.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "PublicDescription": "L2 cache lines in E state filling L2.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "PublicDescription": "L2 cache lines in I state filling L2.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "PublicDescription": "L2 cache lines in S state filling L2.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by demand.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by demand.", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Dirty L2 cache lines filling the L2", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DIRTY_ALL", "PublicDescription": "Dirty L2 cache lines filling the L2.", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_CLEAN", "PublicDescription": "Clean L2 cache lines evicted by the MLC pref= etcher.", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_DIRTY", "PublicDescription": "Dirty L2 cache lines evicted by the MLC pref= etcher.", @@ -147,6 +165,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts all L2 code requests.", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts any demand and L1 HW prefetch data lo= ad requests to L2.", @@ -163,6 +183,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts all L2 HW prefetcher requests.", @@ -171,6 +192,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts all L2 store RFO requests.", @@ -179,6 +201,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Number of instruction fetches that hit the L= 2 cache.", @@ -187,6 +210,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Number of instruction fetches that missed th= e L2 cache.", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Demand Data Read requests that hit L2 cache.= ", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts all L2 HW prefetcher requests that hi= t L2.", @@ -211,6 +237,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts all L2 HW prefetcher requests that mi= ssed L2.", @@ -219,6 +246,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "RFO requests that hit L2 cache.", @@ -227,6 +255,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the number of store RFO requests that= miss the L2 cache.", @@ -235,6 +264,7 @@ }, { "BriefDescription": "RFOs that access cache lines in any state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.ALL", "PublicDescription": "RFOs that access cache lines in any state.", @@ -243,6 +273,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "PublicDescription": "RFOs that hit cache lines in M state.", @@ -251,6 +282,7 @@ }, { "BriefDescription": "RFOs that miss cache lines", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.MISS", "PublicDescription": "RFOs that miss cache lines.", @@ -259,6 +291,7 @@ }, { "BriefDescription": "L2 or LLC HW prefetches that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "PublicDescription": "Any MLC or LLC HW prefetch accessing L2, inc= luding rejects.", @@ -267,6 +300,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "PublicDescription": "Transactions accessing L2 pipe.", @@ -275,6 +309,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "PublicDescription": "L2 cache accesses when fetching instructions= .", @@ -283,6 +318,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests that access L2 cac= he.", @@ -291,6 +327,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "PublicDescription": "L1D writebacks that access L2 cache.", @@ -299,6 +336,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "PublicDescription": "L2 fill requests that access L2 cache.", @@ -307,6 +345,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "L2 writebacks that access L2 cache.", @@ -315,6 +354,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "PublicDescription": "RFO requests that access L2 cache.", @@ -323,6 +363,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D is locked.", @@ -331,6 +372,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts each cache miss condition = for references to the last level cache.", @@ -339,6 +381,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from = the core that reference a cache line in the last level cache.", @@ -347,6 +390,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", "PEBS": "1", @@ -355,6 +399,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", "PEBS": "1", @@ -363,6 +408,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", @@ -371,6 +417,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "PEBS": "1", @@ -379,6 +426,7 @@ }, { "BriefDescription": "Retired load uops whose data source was local= DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", "SampleAfterValue": "100007", @@ -386,6 +434,7 @@ }, { "BriefDescription": "Retired load uops whose data source was remot= e DRAM (Snoop not needed, Snoop Miss, or Snoop Hit data not forwarded).", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", "SampleAfterValue": "100007", @@ -393,6 +442,7 @@ }, { "BriefDescription": "Data forwarded from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_FWD", "SampleAfterValue": "100007", @@ -400,6 +450,7 @@ }, { "BriefDescription": "Remote cache HITM.", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM", "SampleAfterValue": "100007", @@ -407,6 +458,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", @@ -415,6 +467,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", @@ -423,6 +476,7 @@ }, { "BriefDescription": "Retired load uops which data sources followin= g L1 data-cache miss.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "PEBS": "1", @@ -431,6 +485,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", @@ -439,6 +494,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache misses as dat= a sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", "PEBS": "1", @@ -447,6 +503,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", @@ -455,6 +512,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", "PEBS": "1", @@ -463,6 +521,7 @@ }, { "BriefDescription": "All retired load uops. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", @@ -471,6 +530,7 @@ }, { "BriefDescription": "All retired store uops. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", @@ -479,6 +539,7 @@ }, { "BriefDescription": "Retired load uops with locked access. (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", @@ -487,6 +548,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", @@ -495,6 +557,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", @@ -503,6 +566,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", @@ -511,6 +575,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event)", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", @@ -519,6 +584,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Data read requests sent to uncore (demand an= d prefetch).", @@ -527,6 +593,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Demand code read requests sent to uncore.", @@ -535,6 +602,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Demand data read requests sent to uncore.", @@ -543,6 +611,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Demand RFO read requests sent to uncore, inc= luding regular RFOs, locks, ItoM.", @@ -551,6 +620,7 @@ }, { "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Cases when offcore requests buffer cannot ta= ke more entries for core.", @@ -559,6 +629,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Offcore outstanding cacheable data read tran= sactions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -567,6 +638,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -576,6 +648,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -585,6 +658,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -594,6 +668,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -603,6 +678,7 @@ }, { "BriefDescription": "Offcore outstanding code reads transactions i= n SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Offcore outstanding Demand Code Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -611,6 +687,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Offcore outstanding Demand Data Read transac= tions in SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -619,6 +696,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -628,6 +706,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Offcore outstanding RFO store transactions i= n SQ to uncore. Set Cmask=3D1 to count cycles.", @@ -636,6 +715,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -645,6 +725,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -654,6 +735,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -663,6 +745,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -672,6 +755,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit the L= LC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -681,6 +765,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -690,6 +775,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -699,6 +785,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -708,6 +795,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -717,6 +805,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -726,6 +815,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -735,6 +825,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -744,6 +835,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -753,6 +845,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -762,6 +855,7 @@ }, { "BriefDescription": "Counts all writebacks from the core to the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -771,6 +865,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -780,6 +875,7 @@ }, { "BriefDescription": "Counts all demand data reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -789,6 +885,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -798,6 +895,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -807,6 +905,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -816,6 +915,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -825,6 +925,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -834,6 +935,7 @@ }, { "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", @@ -843,6 +945,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", @@ -852,6 +955,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -861,6 +965,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -870,6 +975,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -879,6 +985,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -888,6 +995,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -897,6 +1005,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -906,6 +1015,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -915,6 +1025,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -924,6 +1035,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -933,6 +1045,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -942,6 +1055,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -951,6 +1065,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -960,6 +1075,7 @@ }, { "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -969,6 +1085,7 @@ }, { "BriefDescription": "Counts non-temporal stores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -978,6 +1095,7 @@ }, { "BriefDescription": "Split locks in SQ", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/counter.json b/tools/pe= rf/pmu-events/arch/x86/ivytown/counter.json new file mode 100644 index 000000000000..b4e46a693f7e --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/ivytown/counter.json @@ -0,0 +1,52 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "HA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R3QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json b/t= ools/perf/pmu-events/arch/x86/ivytown/floating-point.json index 89c6d47cc077..336fa00ad006 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= ", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "PublicDescription": "Number of SIMD FP assists due to input value= s.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "PublicDescription": "Number of SIMD FP assists due to output valu= es.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "PublicDescription": "Number of X87 FP assists due to input values= .", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "PublicDescription": "Number of X87 FP assists due to output value= s.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked double-precision uops issued this cycle.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational p= acked single-precision uops issued this cycle.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "PublicDescription": "Counts number of SSE* or AVX-128 double prec= ision FP scalar uops executed.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "PublicDescription": "Number of SSE* or AVX-128 FP Computational s= calar single-precision uops issued this cycle.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIV= s, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish= an FADD used in the middle of a transcendental flow from a s", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "PublicDescription": "Counts number of X87 uops executed.", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED", "SampleAfterValue": "1000003", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Number of SIMD Move Elimination candidate uop= s that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_STORE", "PublicDescription": "Number of assists associated with 256-bit AV= X store operations.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", @@ -118,6 +133,7 @@ }, { "BriefDescription": "number of AVX-256 Computational FP double pre= cision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "PublicDescription": "Counts 256-bit packed double-precision float= ing-point instructions.", @@ -126,6 +142,7 @@ }, { "BriefDescription": "number of GSSE-256 Computational FP single pr= ecision uops issued this cycle", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_SINGLE", "PublicDescription": "Counts 256-bit packed single-precision float= ing-point instructions.", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json b/tools/p= erf/pmu-events/arch/x86/ivytown/frontend.json index 4ee100024ca9..0d6c829a6023 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of front end re-steers due to BPU mis= prediction.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "Number of DSB to MITE switches.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Cycles DSB to MITE switches caused delay.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.EXCEED_DSB_LINES", "PublicDescription": "DSB Fill encountered > 3 DSB lines.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Reads. both cacheable and noncacheable, including UC fet= ches.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Cycles where a code-fetch stalled due to L1 i= nstruction-cache miss or an iTLB miss", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.IFETCH_STALL", "PublicDescription": "Cycles where a code-fetch stalled due to L1 = instruction-cache miss or an iTLB miss.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Number of Instruction Cache, Streaming Buffe= r and Victim Cache Misses. Includes UC accesses.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Increment each cycle. # of uops delivered to= IDQ from DSB path. Set Cmask =3D 1 to count cycles.", @@ -110,6 +123,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "PublicDescription": "Counts cycles the IDQ is empty.", @@ -118,6 +132,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "PublicDescription": "Number of uops delivered to IDQ from any pat= h.", @@ -126,6 +141,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -135,6 +151,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MITE path. Set Cmask =3D 1 to count cycles.", @@ -143,6 +160,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -152,6 +170,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -161,6 +180,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by DSB. Set Cmask =3D 1 to count cycles. Add Edge=3D1 to c= ount # of delivery.", @@ -179,6 +200,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ when MS_busy by MITE. Set Cmask =3D 1 to count cycles.", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -197,6 +220,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Increment each cycle # of uops delivered to = IDQ from MS by either DSB or MITE. Set Cmask =3D 1 to count cycles.", @@ -205,6 +229,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Count issue pipeline slots where no uop was = delivered from the front end to the back end when there is no back-end stal= l.", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -221,6 +247,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json b/tool= s/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json index e6f5b05a71b5..8fe0512c938f 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/ivt-metrics.json @@ -90,7 +90,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "66 * OTHER_ASSISTS.ANY_WB_ASSIST / tma_info_thread_= slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -100,7 +100,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -121,7 +121,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -151,7 +151,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(60 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM * (1= + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD= _UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_U= OPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + M= EM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.R= EMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC= _MISS_RETIRED.REMOTE_FWD))) + 43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS= * (1 + MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM= _LOAD_UOPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_L= OAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MIS= S + MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETI= RED.REMOTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOP= S_LLC_MISS_RETIRED.REMOTE_FWD)))) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -172,7 +172,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "43 * (MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT * (1 += MEM_LOAD_UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_U= OPS_RETIRED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOP= S_LLC_HIT_RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM= _LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REM= OTE_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_M= ISS_RETIRED.REMOTE_FWD))) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -181,7 +181,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -218,7 +218,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -227,7 +227,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * DTLB_STORE_MISSES.STLB_HIT + DTLB_STORE_MISSES= .WALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_UOPS_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load", @@ -236,7 +236,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "(200 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_= HITM + 60 * OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE) / tma_info= _thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -246,7 +246,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_system_dram_bw_use, tma_mem_ba= ndwidth, tma_sq_full, tma_store_latency, tma_streaming_stores", @@ -320,7 +320,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -340,7 +340,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses.", "MetricExpr": "ICACHE.IFETCH_STALL / tma_info_thread_clks - tma_it= lb_misses", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "ScaleUnit": "100%" @@ -447,12 +447,12 @@ "MetricThreshold": "tma_info_inst_mix_ipstore < 8" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, t= ma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, = tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -473,7 +473,7 @@ "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -485,7 +485,7 @@ "MetricName": "tma_info_memory_l1mpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -497,7 +497,13 @@ "MetricName": "tma_info_memory_l2mpki" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -549,7 +555,7 @@ "MetricThreshold": "tma_info_memory_tlb_page_walks_utilization > 0= .5" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (cpu@UOPS_EXECUTED.CORE\\,cm= ask\\=3D1@ / 2 if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" @@ -568,13 +574,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -689,7 +695,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -698,7 +704,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -716,7 +722,7 @@ { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(CYCLE_ACTIVITY.STALLS_L1D_PENDING - CYCLE_ACTIVITY= .STALLS_L2_PENDING) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_UOPS_RETIRED.L2_HIT_PS", @@ -736,7 +742,7 @@ "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "41 * (MEM_LOAD_UOPS_RETIRED.LLC_HIT * (1 + MEM_LOAD= _UOPS_RETIRED.HIT_LFB / (MEM_LOAD_UOPS_RETIRED.L2_HIT + MEM_LOAD_UOPS_RETIR= ED.LLC_HIT + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT + MEM_LOAD_UOPS_LLC_HIT= _RETIRED.XSNP_HITM + MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS + MEM_LOAD_UOP= S_LLC_MISS_RETIRED.LOCAL_DRAM + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM = + MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_HITM + MEM_LOAD_UOPS_LLC_MISS_RETIR= ED.REMOTE_FWD))) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_UOPS_RETIRED.L3_HIT_PS. Related metric= s: tma_mem_latency", @@ -794,7 +800,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -804,7 +810,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_system_dram_bw_u= se, tma_sq_full", @@ -813,7 +819,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_l3_hit_latency", @@ -951,7 +957,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(cpu@UOPS_EXECUTED.CORE\\,cmask\\=3D3@ / 2 if #SMT_= on else UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -978,7 +984,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1007,7 +1013,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_system_dram_bw_use, tma_mem_bandwidth", @@ -1035,7 +1041,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_UOPS_RETIRED.LOCK_= LOADS / MEM_UOPS_RETIRED.ALL_STORES) + (1 - MEM_UOPS_RETIRED.LOCK_LOADS / M= EM_UOPS_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/memory.json b/tools/per= f/pmu-events/arch/x86/ivytown/memory.json index 138d1aa0b32d..73b7e63e3b66 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Loads with latency value being above 128", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -30,6 +33,7 @@ }, { "BriefDescription": "Loads with latency value being above 256", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Loads with latency value being above 32", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -52,6 +57,7 @@ }, { "BriefDescription": "Loads with latency value being above 4", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -63,6 +69,7 @@ }, { "BriefDescription": "Loads with latency value being above 512", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -74,6 +81,7 @@ }, { "BriefDescription": "Loads with latency value being above 64", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -85,6 +93,7 @@ }, { "BriefDescription": "Loads with latency value being above 8", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -96,6 +105,7 @@ }, { "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -104,6 +114,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "PublicDescription": "Speculative cache-line split load uops dispa= tched to L1D.", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "PublicDescription": "Speculative cache-line split Store-address u= ops dispatched to L1D.", @@ -120,6 +132,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +142,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.REMOTE_HIT_FOR= WARD", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +162,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hits the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +172,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +182,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +192,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC the data is found in M state in remote cache and f= orwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -183,6 +202,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", @@ -192,6 +212,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -201,6 +222,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -210,6 +232,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -219,6 +242,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -228,6 +252,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -237,6 +262,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -246,6 +272,7 @@ }, { "BriefDescription": "Counts demand data reads that miss in the LLC= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -255,6 +282,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -264,6 +292,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -273,6 +302,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -282,6 +312,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -291,6 +322,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the LLC and the data is found in M state in remote cache and forwarded fr= om there.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -300,6 +332,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -309,6 +342,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -318,6 +352,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -327,6 +362,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -336,6 +372,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -345,6 +382,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -354,6 +392,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -363,6 +402,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -372,6 +412,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/metricgroups.json b/too= ls/perf/pmu-events/arch/x86/ivytown/metricgroups.json index 8c808347f6da..4193c90c3459 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/other.json b/tools/perf= /pmu-events/arch/x86/ivytown/other.json index e80e99d064ba..2e796d533c13 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/other.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "PublicDescription": "Unhalted core cycles when the thread is in r= ing 0.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "PublicDescription": "Unhalted core cycles when the thread is not = in ring 0.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "PublicDescription": "Cycles in which the L1D and L2 are locked, d= ue to a UC lock or split lock.", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json b/tools/p= erf/pmu-events/arch/x86/ivytown/pipeline.json index 30a3da9cd22b..da05eaaae22c 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Divide operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -11,6 +12,7 @@ }, { "BriefDescription": "Cycles when divider is busy executing divide = operations", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "PublicDescription": "Cycles that the divider is active, includes = INT and FP. Set 'edge =3D1, cmask=3D1' to count the number of divides.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Speculative and retired branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "PublicDescription": "Speculative and retired macro-conditional br= anches.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "PublicDescription": "Speculative and retired macro-unconditional = branches excluding calls and indirects.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "PublicDescription": "Speculative and retired direct near calls.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Speculative and retired indirect branches ex= cluding calls and returns.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "Not taken macro-conditional branches.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "Taken speculative and retired macro-conditio= nal branches.", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "PublicDescription": "Taken speculative and retired macro-conditio= nal branch instructions excluding calls and indirects.", @@ -90,6 +101,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired direct near ca= lls.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Taken speculative and retired indirect branc= hes excluding calls and returns.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired indirect calls= .", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "PublicDescription": "Taken speculative and retired indirect branc= hes with return mnemonic.", @@ -122,6 +137,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PublicDescription": "Branch instructions at retirement.", @@ -129,6 +145,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -137,6 +154,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PublicDescription": "Number of far branches retired.", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "PublicDescription": "Counts the number of not taken branch instru= ctions retired.", @@ -193,6 +217,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "Counts all near executed branches (not neces= sarily retired).", @@ -201,6 +226,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "PublicDescription": "Speculative and retired mispredicted macro c= onditional branches.", @@ -209,6 +235,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Mispredicted indirect branches excluding cal= ls and returns.", @@ -217,6 +244,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -225,6 +253,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "PublicDescription": "Not taken speculative and retired mispredict= ed macro conditional branches.", @@ -233,6 +262,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "PublicDescription": "Taken speculative and retired mispredicted m= acro conditional branches.", @@ -241,6 +271,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches excluding calls and returns.", @@ -249,6 +280,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect calls.", @@ -257,6 +289,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "PublicDescription": "Taken speculative and retired mispredicted i= ndirect branches with return mnemonic.", @@ -265,6 +298,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Mispredicted branch instructions at retireme= nt.", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -303,6 +341,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "PublicDescription": "Increments at the frequency of XCLK (100 MHz= ) when not halted.", @@ -312,6 +351,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -319,6 +359,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -326,12 +367,14 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Reference cycles when the thread is unhalted= . (counts at 100 MHz rate)", @@ -341,6 +384,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted. (counts at 100 MHz rate)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -348,6 +392,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2" @@ -355,6 +400,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", "SampleAfterValue": "2000003", @@ -362,6 +408,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "Counts the number of thread cycles while the= thread is not in a halt state. The thread enters the halt state when it is= running the HLT instruction. The core frequency may change from time to ti= me due to power or thermal throttling.", @@ -370,6 +417,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "PublicDescription": "Core cycles when at least one thread on the = physical core is not in halt state.", @@ -377,6 +425,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -385,6 +434,7 @@ }, { "BriefDescription": "Cycles with pending L1 cache miss loads.", + "Counter": "2", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -394,6 +444,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss load* is outstandi= ng.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -402,6 +453,7 @@ }, { "BriefDescription": "Cycles with pending L2 cache miss loads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -411,6 +463,7 @@ }, { "BriefDescription": "Cycles with pending memory loads.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_LDM_PENDING", @@ -420,6 +473,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -428,6 +482,7 @@ }, { "BriefDescription": "This event increments by 1 for every cycle wh= ere there was no execute for this thread.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_EXECUTE", @@ -437,6 +492,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -445,6 +501,7 @@ }, { "BriefDescription": "Execution stalls due to L1 data cache misses", + "Counter": "2", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -454,6 +511,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss load* is= outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -462,6 +520,7 @@ }, { "BriefDescription": "Execution stalls due to L2 cache misses.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -471,6 +530,7 @@ }, { "BriefDescription": "Execution stalls due to memory subsystem.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_LDM_PENDING", @@ -479,6 +539,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -487,6 +548,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -495,6 +557,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "PublicDescription": "Stall cycles due to IQ is full.", @@ -503,6 +566,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", @@ -510,12 +574,14 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PublicDescription": "Number of instructions at retirement.", @@ -523,6 +589,7 @@ }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", @@ -532,6 +599,7 @@ }, { "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc.)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -541,6 +609,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -549,6 +618,7 @@ }, { "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc.)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -558,6 +628,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -566,6 +637,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Loads blocked by overlapping with store buff= er that cannot be forwarded.", @@ -574,6 +646,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "False dependencies in MOB due to partial com= pare on address.", @@ -582,6 +655,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for H/W prefetch.", @@ -590,6 +664,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Non-SW-prefetch load dispatches that hit fil= l buffer allocated for S/W prefetch.", @@ -598,6 +673,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -607,6 +683,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -616,6 +693,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -623,6 +701,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -632,6 +711,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Counts the number of executed AVX masked loa= d operations that refer to an illegal address range with the mask bits set = to 0.", @@ -640,6 +720,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Number of self-modifying-code machine clears= detected.", @@ -648,6 +729,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_ELIMINATED", "SampleAfterValue": "1000003", @@ -655,6 +737,7 @@ }, { "BriefDescription": "Number of integer Move Elimination candidate = uops that were not eliminated.", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "MOVE_ELIMINATION.INT_NOT_ELIMINATED", "SampleAfterValue": "1000003", @@ -662,6 +745,7 @@ }, { "BriefDescription": "Number of times any microcode assist is invok= ed by HW upon uop writeback.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY_WB_ASSIST", "SampleAfterValue": "100003", @@ -669,6 +753,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Cycles Allocation is stalled due to Resource= Related reason.", @@ -677,6 +762,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -684,6 +770,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -691,6 +778,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Cycles stalled due to no store buffers avail= able (not including draining form sync).", @@ -699,6 +787,7 @@ }, { "BriefDescription": "Count cases of saving new LBR", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Count cases of saving new LBR records by har= dware.", @@ -707,6 +796,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Cycles the RS is empty for the thread.", @@ -715,6 +805,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -725,6 +816,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Cycles which a Uop is dispatched on port 0.", @@ -734,6 +826,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 0.", @@ -742,6 +835,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Cycles which a Uop is dispatched on port 1.", @@ -751,6 +845,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 1.", @@ -759,6 +854,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Cycles which a Uop is dispatched on port 2.", @@ -768,6 +864,7 @@ { "AnyThread": "1", "BriefDescription": "Uops dispatched to port 2, loads and stores p= er core (speculative and retired).", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -775,6 +872,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Cycles which a Uop is dispatched on port 3.", @@ -784,6 +882,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", "PublicDescription": "Cycles per core when load or STA uops are di= spatched to port 3.", @@ -792,6 +891,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Cycles which a Uop is dispatched on port 4.", @@ -801,6 +901,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 4.", @@ -809,6 +910,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Cycles which a Uop is dispatched on port 5.", @@ -818,6 +920,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", "PublicDescription": "Cycles per core when uops are dispatched to = port 5.", @@ -826,6 +929,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts total number of uops to be executed p= er-core each cycle.", @@ -834,6 +938,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -843,6 +948,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -852,6 +958,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -861,6 +968,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -870,6 +978,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -879,6 +988,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -888,6 +998,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -897,6 +1008,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -906,6 +1018,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -915,6 +1028,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -924,6 +1038,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Counts total number of uops to be executed p= er-thread each cycle. Set Cmask =3D 1, INV =3D1 to count stall cycles.", @@ -932,6 +1047,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Increments each cycle the # of Uops issued b= y the RAT to RS. Set Cmask =3D 1, Inv =3D 1, Any=3D 1to count stalled cycle= s of this core.", @@ -941,6 +1057,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -951,6 +1068,7 @@ }, { "BriefDescription": "Number of flags-merge uops being allocated.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.FLAGS_MERGE", "PublicDescription": "Number of flags-merge uops allocated. Such u= ops adds delay.", @@ -959,6 +1077,7 @@ }, { "BriefDescription": "Number of Multiply packed/scalar single preci= sion uops allocated", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SINGLE_MUL", "PublicDescription": "Number of multiply packed/scalar single prec= ision uops allocated.", @@ -967,6 +1086,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "PublicDescription": "Number of slow LEA or similar uops allocated= . Such uop has 3 sources (e.g. 2 sources + immediate) regardless if as a re= sult of LEA instruction or not.", @@ -975,6 +1095,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -985,6 +1106,7 @@ }, { "BriefDescription": "Retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -994,6 +1116,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -1003,6 +1126,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -1011,6 +1135,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -1020,6 +1145,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "10", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/ivytown/uncore-cache.json index 8bf2706eb6d5..64442287ab66 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-cache.json @@ -1,12 +1,14 @@ [ { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "1,2,3", "EventCode": "0x1f", "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Cache Lookups; Any Request", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Cache Lookups; Lookups that Match NID", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", "PerPkg": "1", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in M state", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", "PerPkg": "1", @@ -96,6 +107,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", @@ -105,6 +117,7 @@ }, { "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", @@ -114,6 +127,7 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Cbo Misc", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", @@ -132,6 +147,7 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", @@ -141,6 +157,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 0", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.AGE0", "PerPkg": "1", @@ -150,6 +167,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 1", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.AGE1", "PerPkg": "1", @@ -159,6 +177,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 2", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.AGE2", "PerPkg": "1", @@ -168,6 +187,7 @@ }, { "BriefDescription": "LRU Queue; LRU Age 3", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.AGE3", "PerPkg": "1", @@ -177,6 +197,7 @@ }, { "BriefDescription": "LRU Queue; LRU Bits Decremented", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.LRU_DECREMENT", "PerPkg": "1", @@ -186,6 +207,7 @@ }, { "BriefDescription": "LRU Queue; Non-0 Aged Victim", + "Counter": "0,1", "EventCode": "0x3c", "EventName": "UNC_C_QLRU.VICTIM_NON_ZERO", "PerPkg": "1", @@ -195,6 +217,7 @@ }, { "BriefDescription": "AD Ring In Use; Counterclockwise", + "Counter": "2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.CCW", "PerPkg": "1", @@ -204,6 +227,7 @@ }, { "BriefDescription": "AD Ring In Use; Clockwise", + "Counter": "2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.CW", "PerPkg": "1", @@ -213,6 +237,7 @@ }, { "BriefDescription": "AD Ring In Use; Down", + "Counter": "2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.DOWN", "PerPkg": "1", @@ -222,6 +247,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_EVEN", "PerPkg": "1", @@ -231,6 +257,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_VR0_ODD", "PerPkg": "1", @@ -240,6 +267,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_EVEN", "PerPkg": "1", @@ -249,6 +277,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_VR1_ODD", "PerPkg": "1", @@ -258,6 +287,7 @@ }, { "BriefDescription": "AD Ring In Use; Up", + "Counter": "2,3", "EventCode": "0x1B", "EventName": "UNC_C_RING_AD_USED.UP", "PerPkg": "1", @@ -267,6 +297,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_VR0_EVEN", "PerPkg": "1", @@ -276,6 +307,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_VR0_ODD", "PerPkg": "1", @@ -285,6 +317,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_VR1_EVEN", "PerPkg": "1", @@ -294,6 +327,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_VR1_ODD", "PerPkg": "1", @@ -303,6 +337,7 @@ }, { "BriefDescription": "AK Ring In Use; Counterclockwise", + "Counter": "2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.CCW", "PerPkg": "1", @@ -312,6 +347,7 @@ }, { "BriefDescription": "AK Ring In Use; Clockwise", + "Counter": "2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.CW", "PerPkg": "1", @@ -321,6 +357,7 @@ }, { "BriefDescription": "AK Ring In Use; Down", + "Counter": "2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.DOWN", "PerPkg": "1", @@ -330,6 +367,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_EVEN", "PerPkg": "1", @@ -339,6 +377,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_VR0_ODD", "PerPkg": "1", @@ -348,6 +387,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_EVEN", "PerPkg": "1", @@ -357,6 +397,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_VR1_ODD", "PerPkg": "1", @@ -366,6 +407,7 @@ }, { "BriefDescription": "AK Ring In Use; Up", + "Counter": "2,3", "EventCode": "0x1C", "EventName": "UNC_C_RING_AK_USED.UP", "PerPkg": "1", @@ -375,6 +417,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_VR0_EVEN", "PerPkg": "1", @@ -384,6 +427,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_VR0_ODD", "PerPkg": "1", @@ -393,6 +437,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_VR1_EVEN", "PerPkg": "1", @@ -402,6 +447,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_VR1_ODD", "PerPkg": "1", @@ -411,6 +457,7 @@ }, { "BriefDescription": "BL Ring in Use; Counterclockwise", + "Counter": "2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.CCW", "PerPkg": "1", @@ -420,6 +467,7 @@ }, { "BriefDescription": "BL Ring in Use; Clockwise", + "Counter": "2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.CW", "PerPkg": "1", @@ -429,6 +477,7 @@ }, { "BriefDescription": "BL Ring in Use; Down", + "Counter": "2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.DOWN", "PerPkg": "1", @@ -438,6 +487,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_EVEN", "PerPkg": "1", @@ -447,6 +497,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_VR0_ODD", "PerPkg": "1", @@ -456,6 +507,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_EVEN", "PerPkg": "1", @@ -465,6 +517,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_VR1_ODD", "PerPkg": "1", @@ -474,6 +527,7 @@ }, { "BriefDescription": "BL Ring in Use; Up", + "Counter": "2,3", "EventCode": "0x1D", "EventName": "UNC_C_RING_BL_USED.UP", "PerPkg": "1", @@ -483,6 +537,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even on Vring 0", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_VR0_EVEN", "PerPkg": "1", @@ -492,6 +547,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd on Vring 0", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_VR0_ODD", "PerPkg": "1", @@ -501,6 +557,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even on VRing 1", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_VR1_EVEN", "PerPkg": "1", @@ -510,6 +567,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd on VRing 1", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_VR1_ODD", "PerPkg": "1", @@ -519,6 +577,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AD_IRQ", "PerPkg": "1", @@ -527,6 +586,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK", "PerPkg": "1", @@ -535,6 +595,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Acknowledgements to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK_CORE", "PerPkg": "1", @@ -543,6 +604,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL", "PerPkg": "1", @@ -551,6 +613,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Data Responses to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL_CORE", "PerPkg": "1", @@ -559,6 +622,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV", "PerPkg": "1", @@ -567,6 +631,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.: Snoops of processor's cache.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV_CORE", "PerPkg": "1", @@ -575,6 +640,7 @@ }, { "BriefDescription": "IV Ring in Use; Any", + "Counter": "2,3", "EventCode": "0x1e", "EventName": "UNC_C_RING_IV_USED.ANY", "PerPkg": "1", @@ -584,6 +650,7 @@ }, { "BriefDescription": "IV Ring in Use; Down", + "Counter": "2,3", "EventCode": "0x1e", "EventName": "UNC_C_RING_IV_USED.DOWN", "PerPkg": "1", @@ -593,6 +660,7 @@ }, { "BriefDescription": "IV Ring in Use; Up", + "Counter": "2,3", "EventCode": "0x1e", "EventName": "UNC_C_RING_IV_USED.UP", "PerPkg": "1", @@ -601,6 +669,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_IPQ", "PerPkg": "1", @@ -608,6 +677,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_IRQ", "PerPkg": "1", @@ -615,6 +685,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV", "PerPkg": "1", @@ -622,6 +693,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", @@ -629,6 +701,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "PerPkg": "1", @@ -638,6 +711,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", @@ -647,6 +721,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", "PerPkg": "1", @@ -656,6 +731,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.PRQ", "PerPkg": "1", @@ -665,6 +741,7 @@ }, { "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IPQ", "PerPkg": "1", @@ -674,6 +751,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ", "PerPkg": "1", @@ -683,6 +761,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJ", "PerPkg": "1", @@ -692,6 +771,7 @@ }, { "BriefDescription": "Ingress Allocations: IRQ Rejected", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED", "PerPkg": "1", @@ -701,6 +781,7 @@ }, { "BriefDescription": "Ingress Allocations; VFIFO", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.VFIFO", "PerPkg": "1", @@ -710,6 +791,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IPQ", "PerPkg": "1", @@ -719,6 +801,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IRQ", "PerPkg": "1", @@ -728,6 +811,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", @@ -737,6 +821,7 @@ }, { "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -746,6 +831,7 @@ }, { "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", "PerPkg": "1", @@ -755,6 +841,7 @@ }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", "PerPkg": "1", @@ -764,6 +851,7 @@ }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -773,6 +861,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -782,6 +871,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", @@ -791,6 +881,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", @@ -800,6 +891,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No IIO Credits= ", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -809,6 +901,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -818,6 +911,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", @@ -827,6 +921,7 @@ }, { "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", "PerPkg": "1", @@ -836,6 +931,7 @@ }, { "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", "PerPkg": "1", @@ -845,6 +941,7 @@ }, { "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -854,6 +951,7 @@ }, { "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -863,6 +961,7 @@ }, { "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", "PerPkg": "1", @@ -872,6 +971,7 @@ }, { "BriefDescription": "ISMQ Retries; No WB Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.WB_CREDITS", "PerPkg": "1", @@ -881,6 +981,7 @@ }, { "BriefDescription": "Ingress Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -890,6 +991,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -899,6 +1001,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJ", "PerPkg": "1", @@ -908,6 +1011,7 @@ }, { "BriefDescription": "IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED", "PerPkg": "1", @@ -917,6 +1021,7 @@ }, { "BriefDescription": "Ingress Occupancy; VFIFO", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO", "PerPkg": "1", @@ -926,6 +1031,7 @@ }, { "BriefDescription": "TOR Inserts; All", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.ALL", "PerPkg": "1", @@ -935,6 +1041,7 @@ }, { "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", @@ -944,6 +1051,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL", "PerPkg": "1", @@ -953,6 +1061,7 @@ }, { "BriefDescription": "TOR Inserts; Local Memory - Opcode Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOCAL_OPCODE", "PerPkg": "1", @@ -962,6 +1071,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL", "PerPkg": "1", @@ -971,6 +1081,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Local Memory - Opcode = Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -980,6 +1091,7 @@ }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", @@ -989,6 +1101,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE", "PerPkg": "1", @@ -998,6 +1111,7 @@ }, { "BriefDescription": "TOR Inserts; Misses to Remote Memory - Opcode= Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1007,6 +1121,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", @@ -1016,6 +1131,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", @@ -1025,6 +1141,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", @@ -1034,6 +1151,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", @@ -1043,6 +1161,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", @@ -1052,6 +1171,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", @@ -1061,6 +1181,7 @@ }, { "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", @@ -1070,6 +1191,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE", "PerPkg": "1", @@ -1079,6 +1201,7 @@ }, { "BriefDescription": "TOR Inserts; Remote Memory - Opcode Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REMOTE_OPCODE", "PerPkg": "1", @@ -1088,6 +1211,7 @@ }, { "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", @@ -1097,6 +1221,7 @@ }, { "BriefDescription": "TOR Occupancy; Any", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.ALL", "PerPkg": "1", @@ -1106,6 +1231,7 @@ }, { "BriefDescription": "TOR Occupancy; Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", "PerPkg": "1", @@ -1115,6 +1241,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -1124,6 +1251,7 @@ }, { "BriefDescription": "TOR Occupancy; Local Memory - Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOCAL_OPCODE", "PerPkg": "1", @@ -1133,6 +1261,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", "PerPkg": "1", @@ -1142,6 +1271,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL", "PerPkg": "1", @@ -1151,6 +1281,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Local Memory - Opcod= e Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_LOCAL_OPCODE", "PerPkg": "1", @@ -1160,6 +1291,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", "PerPkg": "1", @@ -1169,6 +1301,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE", "PerPkg": "1", @@ -1178,6 +1311,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses to Remote Memory - Opco= de Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_REMOTE_OPCODE", "PerPkg": "1", @@ -1187,6 +1321,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", "PerPkg": "1", @@ -1196,6 +1331,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", "PerPkg": "1", @@ -1205,6 +1341,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", "PerPkg": "1", @@ -1214,6 +1351,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", "PerPkg": "1", @@ -1223,6 +1361,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", "PerPkg": "1", @@ -1232,6 +1371,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_WB", "PerPkg": "1", @@ -1241,6 +1381,7 @@ }, { "BriefDescription": "TOR Occupancy; Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", @@ -1250,6 +1391,7 @@ }, { "BriefDescription": "TOR Occupancy", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -1259,6 +1401,7 @@ }, { "BriefDescription": "TOR Occupancy; Remote Memory - Opcode Matched= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.REMOTE_OPCODE", "PerPkg": "1", @@ -1268,6 +1411,7 @@ }, { "BriefDescription": "TOR Occupancy; Writebacks", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.WB", "PerPkg": "1", @@ -1277,6 +1421,7 @@ }, { "BriefDescription": "Onto AD Ring", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AD", "PerPkg": "1", @@ -1285,6 +1430,7 @@ }, { "BriefDescription": "Onto AK Ring", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.AK", "PerPkg": "1", @@ -1293,6 +1439,7 @@ }, { "BriefDescription": "Onto BL Ring", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED.BL", "PerPkg": "1", @@ -1301,6 +1448,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", "PerPkg": "1", @@ -1310,6 +1458,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CORE", "PerPkg": "1", @@ -1319,6 +1468,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", "PerPkg": "1", @@ -1328,6 +1478,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CORE", "PerPkg": "1", @@ -1337,6 +1488,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", "PerPkg": "1", @@ -1346,6 +1498,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", @@ -1355,6 +1508,7 @@ }, { "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", "PerPkg": "1", @@ -1364,6 +1518,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AD Ring (to core)", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AD_CORE", "PerPkg": "1", @@ -1373,6 +1528,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AK_BOTH", "PerPkg": "1", @@ -1382,6 +1538,7 @@ }, { "BriefDescription": "Injection Starvation; Onto IV Ring", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.IV", "PerPkg": "1", @@ -1391,6 +1548,7 @@ }, { "BriefDescription": "BT Bypass", + "Counter": "0,1,2,3", "EventCode": "0x52", "EventName": "UNC_H_BT_BYPASS", "PerPkg": "1", @@ -1399,6 +1557,7 @@ }, { "BriefDescription": "BT Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE", "PerPkg": "1", @@ -1407,6 +1566,7 @@ }, { "BriefDescription": "BT Cycles Not Empty: Local", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE.LOCAL", "PerPkg": "1", @@ -1416,6 +1576,7 @@ }, { "BriefDescription": "BT Cycles Not Empty: Remote", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_H_BT_CYCLES_NE.REMOTE", "PerPkg": "1", @@ -1425,6 +1586,7 @@ }, { "BriefDescription": "BT Occupancy; Local", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.LOCAL", "PerPkg": "1", @@ -1434,6 +1596,7 @@ }, { "BriefDescription": "BT Occupancy; Reads Local", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.READS_LOCAL", "PerPkg": "1", @@ -1443,6 +1606,7 @@ }, { "BriefDescription": "BT Occupancy; Reads Remote", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.READS_REMOTE", "PerPkg": "1", @@ -1452,6 +1616,7 @@ }, { "BriefDescription": "BT Occupancy; Remote", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.REMOTE", "PerPkg": "1", @@ -1461,6 +1626,7 @@ }, { "BriefDescription": "BT Occupancy; Writes Local", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.WRITES_LOCAL", "PerPkg": "1", @@ -1470,6 +1636,7 @@ }, { "BriefDescription": "BT Occupancy; Writes Remote", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_H_BT_OCCUPANCY.WRITES_REMOTE", "PerPkg": "1", @@ -1479,6 +1646,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_BL_HAZARD", "PerPkg": "1", @@ -1488,6 +1656,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Snoop Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.INCOMING_SNP_HAZARD", "PerPkg": "1", @@ -1497,6 +1666,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.RSPACKCFLT_HAZARD", "PerPkg": "1", @@ -1506,6 +1676,7 @@ }, { "BriefDescription": "BT to HT Not Issued; Incoming Data Hazard", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_H_BT_TO_HT_NOT_ISSUED.WBMDATA_HAZARD", "PerPkg": "1", @@ -1515,6 +1686,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "PerPkg": "1", @@ -1524,6 +1696,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "PerPkg": "1", @@ -1533,6 +1706,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_H_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", @@ -1540,6 +1714,7 @@ }, { "BriefDescription": "Conflict Checks; Acknowledge Conflicts", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.ACKCNFLTS", "PerPkg": "1", @@ -1549,6 +1724,7 @@ }, { "BriefDescription": "Conflict Checks; Cmp Fwds", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.CMP_FWDS", "PerPkg": "1", @@ -1558,6 +1734,7 @@ }, { "BriefDescription": "Conflict Checks; Conflict Detected", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT", "PerPkg": "1", @@ -1567,6 +1744,7 @@ }, { "BriefDescription": "Conflict Checks; Last in conflict chain", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.LAST", "PerPkg": "1", @@ -1576,6 +1754,7 @@ }, { "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_H_DIRECT2CORE_COUNT", "PerPkg": "1", @@ -1584,6 +1763,7 @@ }, { "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", "PerPkg": "1", @@ -1592,6 +1772,7 @@ }, { "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1600,6 +1781,7 @@ }, { "BriefDescription": "Directory Lat Opt Return", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_H_DIRECTORY_LAT_OPT", "PerPkg": "1", @@ -1608,6 +1790,7 @@ }, { "BriefDescription": "Directory Lookups: Any state", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -1617,6 +1800,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", "PerPkg": "1", @@ -1626,6 +1810,7 @@ }, { "BriefDescription": "Directory Lookups: Snoop A", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_A", "PerPkg": "1", @@ -1635,6 +1820,7 @@ }, { "BriefDescription": "Directory Lookups: Snoop S", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNOOP_S", "PerPkg": "1", @@ -1644,6 +1830,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", "PerPkg": "1", @@ -1653,6 +1840,7 @@ }, { "BriefDescription": "Directory Lookups: A State", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -1662,6 +1850,7 @@ }, { "BriefDescription": "Directory Lookups: I State", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -1671,6 +1860,7 @@ }, { "BriefDescription": "Directory Lookups: S State", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -1680,6 +1870,7 @@ }, { "BriefDescription": "Directory Updates: A2I", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.A2I", "PerPkg": "1", @@ -1689,6 +1880,7 @@ }, { "BriefDescription": "Directory Updates: A2S", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.A2S", "PerPkg": "1", @@ -1698,6 +1890,7 @@ }, { "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1707,6 +1900,7 @@ }, { "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", "PerPkg": "1", @@ -1716,6 +1910,7 @@ }, { "BriefDescription": "Directory Updates: I2A", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.I2A", "PerPkg": "1", @@ -1725,6 +1920,7 @@ }, { "BriefDescription": "Directory Updates: I2S", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.I2S", "PerPkg": "1", @@ -1734,6 +1930,7 @@ }, { "BriefDescription": "Directory Updates: S2A", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.S2A", "PerPkg": "1", @@ -1743,6 +1940,7 @@ }, { "BriefDescription": "Directory Updates: S2I", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.S2I", "PerPkg": "1", @@ -1752,6 +1950,7 @@ }, { "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_H_DIRECTORY_UPDATE.SET", "PerPkg": "1", @@ -1761,6 +1960,7 @@ }, { "BriefDescription": "AD QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_H_IGR_AD_QPI2_ACCUMULATOR", "PerPkg": "1", @@ -1769,6 +1969,7 @@ }, { "BriefDescription": "BL QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_H_IGR_BL_QPI2_ACCUMULATOR", "PerPkg": "1", @@ -1777,6 +1978,7 @@ }, { "BriefDescription": "AD QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_H_IGR_CREDITS_AD_QPI2", "PerPkg": "1", @@ -1785,6 +1987,7 @@ }, { "BriefDescription": "BL QPI Link 2 Credit Accumulator", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_H_IGR_CREDITS_BL_QPI2", "PerPkg": "1", @@ -1793,6 +1996,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", "PerPkg": "1", @@ -1802,6 +2006,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", "PerPkg": "1", @@ -1811,6 +2016,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", "PerPkg": "1", @@ -1820,6 +2026,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", "PerPkg": "1", @@ -1829,6 +2036,7 @@ }, { "BriefDescription": "HA to iMC Normal Priority Reads Issued; Norma= l Priority", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_H_IMC_READS.NORMAL", "PerPkg": "1", @@ -1838,6 +2046,7 @@ }, { "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", @@ -1845,6 +2054,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.ALL", "PerPkg": "1", @@ -1854,6 +2064,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.FULL", "PerPkg": "1", @@ -1863,6 +2074,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", @@ -1872,6 +2084,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -1881,6 +2094,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", @@ -1890,6 +2104,7 @@ }, { "BriefDescription": "IODC Conflicts; Any Conflict", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_H_IODC_CONFLICTS.ANY", "PerPkg": "1", @@ -1898,6 +2113,7 @@ }, { "BriefDescription": "IODC Conflicts; Last Conflict", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_H_IODC_CONFLICTS.LAST", "PerPkg": "1", @@ -1906,6 +2122,7 @@ }, { "BriefDescription": "IODC Conflicts: Remote InvItoE - Same RTID", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_INVI2E_SAME_RTID", "PerPkg": "1", @@ -1914,6 +2131,7 @@ }, { "BriefDescription": "IODC Conflicts: Remote (Other) - Same Addr", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_H_IODC_CONFLICTS.REMOTE_OTHER_SAME_ADDR", "PerPkg": "1", @@ -1922,6 +2140,7 @@ }, { "BriefDescription": "IODC Inserts", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_H_IODC_INSERTS", "PerPkg": "1", @@ -1930,6 +2149,7 @@ }, { "BriefDescription": "Num IODC 0 Length Writes", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_H_IODC_OLEN_WBMTOI", "PerPkg": "1", @@ -1938,6 +2158,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.INVITOE_LOCAL", "PerPkg": "1", @@ -1947,6 +2168,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.READS_LOCAL", "PerPkg": "1", @@ -1956,6 +2178,7 @@ }, { "BriefDescription": "OSB Snoop Broadcast; Remote", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_H_OSB.REMOTE", "PerPkg": "1", @@ -1965,6 +2188,7 @@ }, { "BriefDescription": "OSB Early Data Return; All", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.ALL", "PerPkg": "1", @@ -1974,6 +2198,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_I", "PerPkg": "1", @@ -1983,6 +2208,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Local S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_LOCAL_S", "PerPkg": "1", @@ -1992,6 +2218,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote I", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_I", "PerPkg": "1", @@ -2001,6 +2228,7 @@ }, { "BriefDescription": "OSB Early Data Return; Reads to Remote S", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_H_OSB_EDR.READS_REMOTE_S", "PerPkg": "1", @@ -2010,6 +2238,7 @@ }, { "BriefDescription": "Read and Write Requests; Local InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -2019,6 +2248,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote InvItoEs", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -2028,6 +2258,7 @@ }, { "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", @@ -2037,6 +2268,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -2046,6 +2278,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -2055,6 +2288,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", @@ -2064,6 +2298,7 @@ }, { "BriefDescription": "Read and Write Requests; Local Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -2073,6 +2308,7 @@ }, { "BriefDescription": "Read and Write Requests; Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -2082,6 +2318,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CCW", "PerPkg": "1", @@ -2091,6 +2328,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2100,6 +2338,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2109,6 +2348,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -2118,6 +2358,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -2127,6 +2368,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3E", "EventName": "UNC_H_RING_AD_USED.CW", "PerPkg": "1", @@ -2136,6 +2378,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2145,6 +2388,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2154,6 +2398,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -2163,6 +2408,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_VR1_ODD", "PerPkg": "1", @@ -2172,6 +2418,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CCW", "PerPkg": "1", @@ -2181,6 +2428,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2190,6 +2438,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2199,6 +2448,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -2208,6 +2458,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -2217,6 +2468,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x3F", "EventName": "UNC_H_RING_AK_USED.CW", "PerPkg": "1", @@ -2226,6 +2478,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2235,6 +2488,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2244,6 +2498,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -2253,6 +2508,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_VR1_ODD", "PerPkg": "1", @@ -2262,6 +2518,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW", "PerPkg": "1", @@ -2271,6 +2528,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2280,6 +2538,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2289,6 +2548,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -2298,6 +2558,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -2307,6 +2568,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW", "PerPkg": "1", @@ -2316,6 +2578,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2325,6 +2588,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2334,6 +2598,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -2343,6 +2608,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_VR1_ODD", "PerPkg": "1", @@ -2352,6 +2618,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -2361,6 +2628,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -2370,6 +2638,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -2379,6 +2648,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -2388,6 +2658,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -2397,6 +2668,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -2406,6 +2678,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -2415,6 +2688,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", @@ -2424,6 +2698,7 @@ }, { "BriefDescription": "Snoop Responses Received; RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", "PerPkg": "1", @@ -2433,6 +2708,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspI", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -2442,6 +2718,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -2451,6 +2728,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspS", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPS", "PerPkg": "1", @@ -2460,6 +2738,7 @@ }, { "BriefDescription": "Snoop Responses Received; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -2469,6 +2748,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*Fwd*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -2478,6 +2758,7 @@ }, { "BriefDescription": "Snoop Responses Received; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", "PerPkg": "1", @@ -2487,6 +2768,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Other", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.OTHER", "PerPkg": "1", @@ -2496,6 +2778,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPCNFLCT", "PerPkg": "1", @@ -2505,6 +2788,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPI", "PerPkg": "1", @@ -2514,6 +2798,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPIFWD", "PerPkg": "1", @@ -2523,6 +2808,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPS", "PerPkg": "1", @@ -2532,6 +2818,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPSFWD", "PerPkg": "1", @@ -2541,6 +2828,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxFWDxWB", "PerPkg": "1", @@ -2550,6 +2838,7 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_H_SNP_RESP_RECV_LOCAL.RSPxWB", "PerPkg": "1", @@ -2559,6 +2848,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", "PerPkg": "1", @@ -2568,6 +2858,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", "PerPkg": "1", @@ -2577,6 +2868,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", "PerPkg": "1", @@ -2586,6 +2878,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", "PerPkg": "1", @@ -2595,6 +2888,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", "PerPkg": "1", @@ -2604,6 +2898,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", "PerPkg": "1", @@ -2613,6 +2908,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", "PerPkg": "1", @@ -2622,6 +2918,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", "PerPkg": "1", @@ -2631,6 +2928,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", "PerPkg": "1", @@ -2640,6 +2938,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", "PerPkg": "1", @@ -2649,6 +2948,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", "PerPkg": "1", @@ -2658,6 +2958,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", "PerPkg": "1", @@ -2667,6 +2968,7 @@ }, { "BriefDescription": "Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_H_TRACKER_CYCLES_NE", "PerPkg": "1", @@ -2675,6 +2977,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_H_TxR_AD.HOM", "PerPkg": "1", @@ -2684,6 +2987,7 @@ }, { "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", "PerPkg": "1", @@ -2693,6 +2997,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -2702,6 +3007,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -2711,6 +3017,7 @@ }, { "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", "PerPkg": "1", @@ -2720,6 +3027,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -2729,6 +3037,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -2738,6 +3047,7 @@ }, { "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.ALL", "PerPkg": "1", @@ -2747,6 +3057,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", "PerPkg": "1", @@ -2756,6 +3067,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", "PerPkg": "1", @@ -2765,6 +3077,7 @@ }, { "BriefDescription": "AD Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -2774,6 +3087,7 @@ }, { "BriefDescription": "AD Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -2783,6 +3097,7 @@ }, { "BriefDescription": "Outbound Ring Transactions on AK: CRD Transac= tions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_H_TxR_AK.CRD_CBO", "PerPkg": "1", @@ -2791,6 +3106,7 @@ }, { "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", "PerPkg": "1", @@ -2800,6 +3116,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -2809,6 +3126,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -2818,6 +3136,7 @@ }, { "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", "PerPkg": "1", @@ -2827,6 +3146,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -2836,6 +3156,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -2845,6 +3166,7 @@ }, { "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.ALL", "PerPkg": "1", @@ -2854,6 +3176,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", "PerPkg": "1", @@ -2863,6 +3186,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", "PerPkg": "1", @@ -2872,6 +3196,7 @@ }, { "BriefDescription": "AK Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -2881,6 +3206,7 @@ }, { "BriefDescription": "AK Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -2890,6 +3216,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CACHE", "PerPkg": "1", @@ -2899,6 +3226,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CORE", "PerPkg": "1", @@ -2908,6 +3236,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_QPI", "PerPkg": "1", @@ -2917,6 +3246,7 @@ }, { "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", "PerPkg": "1", @@ -2926,6 +3256,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -2935,6 +3266,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -2944,6 +3276,7 @@ }, { "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", "PerPkg": "1", @@ -2953,6 +3286,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -2962,6 +3296,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -2971,6 +3306,7 @@ }, { "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.ALL", "PerPkg": "1", @@ -2980,6 +3316,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", "PerPkg": "1", @@ -2989,6 +3326,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", "PerPkg": "1", @@ -2998,6 +3336,7 @@ }, { "BriefDescription": "BL Egress Occupancy: All", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL", "PerPkg": "1", @@ -3006,6 +3345,7 @@ }, { "BriefDescription": "BL Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -3015,6 +3355,7 @@ }, { "BriefDescription": "BL Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -3024,6 +3365,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -3033,6 +3375,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -3042,6 +3385,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -3051,6 +3395,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -3060,6 +3405,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -3069,6 +3415,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -3078,6 +3425,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -3087,6 +3435,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.jso= n b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json index 914d2cfb3d3d..b805dfc6a625 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Address Match (Conflict) Count; Conflict Merg= es", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Address Match (Conflict) Count; Conflict Stal= ls", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Outstanding Write Ownership Occupancy; Any So= urce", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Outstanding Write Ownership Occupancy; Select= Source", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Outstanding Read Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Outstanding Read Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Outstanding Write Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", "PerPkg": "1", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Outstanding Write Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -109,12 +121,14 @@ }, { "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Number of clocks in the IRP.", "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0xb", "EventName": "UNC_I_RxR_AK_CYCLES_FULL", "PerPkg": "1", @@ -123,6 +137,7 @@ }, { "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", "EventCode": "0xa", "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", @@ -130,6 +145,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0xc", "EventName": "UNC_I_RxR_AK_OCCUPANCY", "PerPkg": "1", @@ -137,6 +153,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -145,6 +162,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", @@ -152,6 +170,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -159,6 +178,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -167,6 +187,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", @@ -174,6 +195,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -181,6 +203,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -189,6 +212,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", @@ -196,6 +220,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -204,6 +229,7 @@ }, { "BriefDescription": "Tickle Count; Ownership Lost", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", "PerPkg": "1", @@ -213,6 +239,7 @@ }, { "BriefDescription": "Tickle Count; Data Returned", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", "PerPkg": "1", @@ -222,6 +249,7 @@ }, { "BriefDescription": "Inbound Transaction Count: Read Prefetches", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", "PerPkg": "1", @@ -231,6 +259,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.RD_PREFETCHES", "PerPkg": "1", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", @@ -249,6 +279,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -258,6 +289,7 @@ }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -266,6 +298,7 @@ }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -274,6 +307,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xe", "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", "PerPkg": "1", @@ -282,6 +316,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xf", "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", "PerPkg": "1", @@ -290,6 +325,7 @@ }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xd", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", @@ -298,6 +334,7 @@ }, { "BriefDescription": "Write Ordering Stalls", + "Counter": "0,1", "EventCode": "0x1a", "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", "PerPkg": "1", @@ -306,6 +343,7 @@ }, { "BriefDescription": "Number of qfclks", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", @@ -314,6 +352,7 @@ }, { "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", @@ -322,6 +361,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", @@ -331,6 +371,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_MISS", "PerPkg": "1", @@ -340,6 +381,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", @@ -349,6 +391,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT Miss, Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT_MISS", "PerPkg": "1", @@ -358,6 +401,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_MISS", "PerPkg": "1", @@ -367,6 +411,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT I= nvalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_HIT", "PerPkg": "1", @@ -376,6 +421,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT M= iss and Invalid", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT_MISS", "PerPkg": "1", @@ -385,6 +431,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS_RBT_HIT", "PerPkg": "1", @@ -394,6 +441,7 @@ }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", @@ -401,198 +449,231 @@ "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MATCH_MASK", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyDataC", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp11flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.AnyResp9flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_Cmp", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_E_FrcAckCnflt", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_Cmp", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_F_FrcAckCnflt", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.DataC_M", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbEData", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbIData", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.DRS.WbSData", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.AnyReq", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.AnyResp", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwd", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdI", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdIWb", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdS", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespFwdSWb", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespIWb", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.HOM.RespSWb", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyInt", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg11flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCB.AnyMsg9flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg1or2flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.AnyMsg3flits", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NCS.NcRd", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.NDR.AnyCmp", "PerPkg": "1", "Unit": "QPI" }, { + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_MESSAGE.SNP.AnySnp", "PerPkg": "1", @@ -600,6 +681,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -608,6 +690,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xf", "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", @@ -616,6 +699,7 @@ }, { "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", @@ -624,6 +708,7 @@ }, { "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", "PerPkg": "1", @@ -633,6 +718,7 @@ }, { "BriefDescription": "CRC Errors Detected; Normal Operations", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", "PerPkg": "1", @@ -642,6 +728,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", "PerPkg": "1", @@ -651,6 +738,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", "PerPkg": "1", @@ -660,6 +748,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", "PerPkg": "1", @@ -669,6 +758,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", "PerPkg": "1", @@ -678,6 +768,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", "PerPkg": "1", @@ -687,6 +778,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", "PerPkg": "1", @@ -696,6 +788,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.DRS", "PerPkg": "1", @@ -705,6 +798,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.HOM", "PerPkg": "1", @@ -714,6 +808,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCB", "PerPkg": "1", @@ -723,6 +818,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NCS", "PerPkg": "1", @@ -732,6 +828,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.NDR", "PerPkg": "1", @@ -741,6 +838,7 @@ }, { "BriefDescription": "VN1 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN1.SNP", "PerPkg": "1", @@ -750,6 +848,7 @@ }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", @@ -758,6 +857,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", @@ -766,6 +866,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN0", "PerPkg": "1", @@ -775,6 +876,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_Q_RxL_CYCLES_NE_DRS.VN1", "PerPkg": "1", @@ -784,6 +886,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN0", "PerPkg": "1", @@ -793,6 +896,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_RxL_CYCLES_NE_HOM.VN1", "PerPkg": "1", @@ -802,6 +906,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN0", "PerPkg": "1", @@ -811,6 +916,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL_CYCLES_NE_NCB.VN1", "PerPkg": "1", @@ -820,6 +926,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN0", "PerPkg": "1", @@ -829,6 +936,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_Q_RxL_CYCLES_NE_NCS.VN1", "PerPkg": "1", @@ -838,6 +946,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN0", "PerPkg": "1", @@ -847,6 +956,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_RxL_CYCLES_NE_NDR.VN1", "PerPkg": "1", @@ -856,6 +966,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN0", "PerPkg": "1", @@ -865,6 +976,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_RxL_CYCLES_NE_SNP.VN1", "PerPkg": "1", @@ -874,6 +986,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.DATA", "PerPkg": "1", @@ -883,6 +996,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", @@ -892,6 +1006,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Non-Data protocol T= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA", "PerPkg": "1", @@ -901,6 +1016,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", @@ -910,6 +1026,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", @@ -919,6 +1036,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", @@ -928,6 +1046,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", @@ -937,6 +1056,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", @@ -946,6 +1066,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", @@ -955,6 +1076,7 @@ }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", @@ -964,6 +1086,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", @@ -973,6 +1096,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -982,6 +1106,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -991,6 +1116,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", @@ -1000,6 +1126,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -1009,6 +1136,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -1018,6 +1146,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", @@ -1026,6 +1155,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS", "PerPkg": "1", @@ -1034,6 +1164,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN0", "PerPkg": "1", @@ -1043,6 +1174,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS.VN1", "PerPkg": "1", @@ -1052,6 +1184,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_Q_RxL_INSERTS_HOM", "PerPkg": "1", @@ -1060,6 +1193,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN0", "PerPkg": "1", @@ -1069,6 +1203,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_Q_RxL_INSERTS_HOM.VN1", "PerPkg": "1", @@ -1078,6 +1213,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_Q_RxL_INSERTS_NCB", "PerPkg": "1", @@ -1086,6 +1222,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN0", "PerPkg": "1", @@ -1095,6 +1232,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_Q_RxL_INSERTS_NCB.VN1", "PerPkg": "1", @@ -1104,6 +1242,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_Q_RxL_INSERTS_NCS", "PerPkg": "1", @@ -1112,6 +1251,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN0", "PerPkg": "1", @@ -1121,6 +1261,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_Q_RxL_INSERTS_NCS.VN1", "PerPkg": "1", @@ -1130,6 +1271,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_Q_RxL_INSERTS_NDR", "PerPkg": "1", @@ -1138,6 +1280,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN0", "PerPkg": "1", @@ -1147,6 +1290,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_Q_RxL_INSERTS_NDR.VN1", "PerPkg": "1", @@ -1156,6 +1300,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_Q_RxL_INSERTS_SNP", "PerPkg": "1", @@ -1164,6 +1309,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN0", "PerPkg": "1", @@ -1173,6 +1319,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_Q_RxL_INSERTS_SNP.VN1", "PerPkg": "1", @@ -1182,6 +1329,7 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", @@ -1190,6 +1338,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", "PerPkg": "1", @@ -1198,6 +1347,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN0", "PerPkg": "1", @@ -1207,6 +1357,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS.VN1", "PerPkg": "1", @@ -1216,6 +1367,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", "PerPkg": "1", @@ -1224,6 +1376,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN0", "PerPkg": "1", @@ -1233,6 +1386,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM.VN1", "PerPkg": "1", @@ -1242,6 +1396,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", "PerPkg": "1", @@ -1250,6 +1405,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN0", "PerPkg": "1", @@ -1259,6 +1415,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB.VN1", "PerPkg": "1", @@ -1268,6 +1425,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", "PerPkg": "1", @@ -1276,6 +1434,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN0", "PerPkg": "1", @@ -1285,6 +1444,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS.VN1", "PerPkg": "1", @@ -1294,6 +1454,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", "PerPkg": "1", @@ -1302,6 +1463,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN0", "PerPkg": "1", @@ -1311,6 +1473,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR.VN1", "PerPkg": "1", @@ -1320,6 +1483,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", "PerPkg": "1", @@ -1328,6 +1492,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN0", "PerPkg": "1", @@ -1337,6 +1502,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP.VN1", "PerPkg": "1", @@ -1346,6 +1512,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_DRS", "PerPkg": "1", @@ -1355,6 +1522,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_HOM", "PerPkg": "1", @@ -1364,6 +1532,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCB", "PerPkg": "1", @@ -1373,6 +1542,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NCS", "PerPkg": "1", @@ -1382,6 +1552,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_NDR", "PerPkg": "1", @@ -1391,6 +1562,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.BGF_SNP", "PerPkg": "1", @@ -1400,6 +1572,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; Egress Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.EGRESS_CREDITS", "PerPkg": "1", @@ -1409,6 +1582,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN0; GV", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS_VN0.GV", "PerPkg": "1", @@ -1418,6 +1592,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - H= OM", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_DRS", "PerPkg": "1", @@ -1427,6 +1602,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_HOM", "PerPkg": "1", @@ -1436,6 +1612,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - S= NP", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCB", "PerPkg": "1", @@ -1445,6 +1622,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= DR", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NCS", "PerPkg": "1", @@ -1454,6 +1632,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_NDR", "PerPkg": "1", @@ -1463,6 +1642,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI on VN1; BGF Stall - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_Q_RxL_STALLS_VN1.BGF_SNP", "PerPkg": "1", @@ -1472,6 +1652,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -1480,6 +1661,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", @@ -1488,6 +1670,7 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", @@ -1496,6 +1679,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", "PerPkg": "1", @@ -1505,6 +1689,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", "PerPkg": "1", @@ -1514,6 +1699,7 @@ }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", @@ -1522,6 +1708,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of data fli= ts transmitted over QPI. Each flit contains 64b of data. This includes bo= th DRS and NCB data flits (coherent and non-coherent). This can be used to= calculate the data bandwidth of the QPI link. One can get a good picture = of the QPI-link characteristics by evaluating the protocol flits, data flit= s, and idle/null flits. This does not include the header flits that go in = data packets.", @@ -1530,6 +1717,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach flit is made up of 80 bits of information (in addition to some ECC data= ). In full-width (L0) mode, flits are made up of four fits, each of which = contains 20 bits of data (along with some additional ECC data). In half-w= idth (L0p) mode, the fits are only 10 bits, and therefore it takes twice as= many fits to transmit a flit. When one talks about QPI speed (for example= , 8.0 GT/s), the transfers here refer to fits. Therefore, in L0, the syste= m will transfer 1 flit at the rate of 1/4th the QPI speed. One can calcula= te the bandwidth of the link by taking: flits*80b/time. Note that this is = not the same as data bandwidth. For example, when we are transferring a 64= B cacheline across QPI, we will break it into 9 flits -- 1 with header info= rmation and 8 with 64 bits of actual data and an additional 16 bits of othe= r information. To calculate data bandwidth, one should therefore do: data = flits * 8B / time (for L0) or 4B instead of 8B for L0p.; Number of non-NULL= non-data flits transmitted across QPI. This basically tracks the protocol= overhead on the QPI link. One can get a good picture of the QPI-link char= acteristics by evaluating the protocol flits, data flits, and idle/null fli= ts. This includes the header flits for data packets.", @@ -1538,6 +1726,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of flits transmitted over QPI on the DRS (Da= ta Response) channel. DRS flits are used to transmit data with coherency.", @@ -1546,6 +1735,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of data flits transmitted over QPI on the DR= S (Data Response) channel. DRS flits are used to transmit data with cohere= ncy. This does not count data flits transmitted over the NCB channel which= transmits non-coherent data. This includes only the data flits (not the h= eader).", @@ -1554,6 +1744,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the total number of protocol flits transmitted over QPI on th= e DRS (Data Response) channel. DRS flits are used to transmit data with co= herency. This does not count data flits transmitted over the NCB channel w= hich transmits non-coherent data. This includes only the header flits (not= the data). This includes extended headers.", @@ -1562,6 +1753,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of flits transmitted over QPI on the home channel.= ", @@ -1570,6 +1762,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of non-request flits transmitted over QPI on the h= ome channel. These are most commonly snoop responses, and this event can b= e used as a proxy for that.", @@ -1578,6 +1771,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of data request transmitted over QPI on the home c= hannel. This basically counts the number of remote memory requests transmi= tted over QPI. In conjunction with the local read count in the Home Agent,= one can calculate the number of LLC Misses.", @@ -1586,6 +1780,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three groups that allow us to track flits. = It includes filters for SNP, HOM, and DRS message classes. Each flit is m= ade up of 80 bits of information (in addition to some ECC data). In full-w= idth (L0) mode, flits are made up of four fits, each of which contains 20 b= its of data (along with some additional ECC data). In half-width (L0p) mo= de, the fits are only 10 bits, and therefore it takes twice as many fits to= transmit a flit. When one talks about QPI speed (for example, 8.0 GT/s), = the transfers here refer to fits. Therefore, in L0, the system will transf= er 1 flit at the rate of 1/4th the QPI speed. One can calculate the bandwi= dth of the link by taking: flits*80b/time. Note that this is not the same = as data bandwidth. For example, when we are transferring a 64B cacheline a= cross QPI, we will break it into 9 flits -- 1 with header information and 8= with 64 bits of actual data and an additional 16 bits of other information= . To calculate data bandwidth, one should therefore do: data flits * 8B / = time.; Counts the number of snoop request flits transmitted over QPI. Thes= e requests are contained in the snoop channel. This does not include snoop= responses, which are transmitted on the home channel.", @@ -1594,6 +1789,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", @@ -1603,6 +1799,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -1612,6 +1809,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -1621,6 +1819,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", @@ -1630,6 +1829,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -1639,6 +1839,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -1648,6 +1849,7 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", @@ -1656,6 +1858,7 @@ }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", @@ -1664,6 +1867,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1673,6 +1877,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - HOM; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1682,6 +1887,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1691,6 +1897,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD HOM; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_Q_TxR_AD_HOM_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1700,6 +1907,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1709,6 +1917,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1718,6 +1927,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1727,6 +1937,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD NDR; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_Q_TxR_AD_NDR_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1736,6 +1947,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1745,6 +1957,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - SNP; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1754,6 +1967,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1763,6 +1977,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AD SNP; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_Q_TxR_AD_SNP_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1772,6 +1987,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED", "PerPkg": "1", @@ -1780,6 +1996,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1789,6 +2006,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1798,6 +2016,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY", "PerPkg": "1", @@ -1806,6 +2025,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1815,6 +2035,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - AK NDR: for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_Q_TxR_AK_NDR_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1824,6 +2045,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1833,6 +2055,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1842,6 +2065,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - DRS; for Shar= ed VN", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_ACQUIRED.VN_SHR", "PerPkg": "1", @@ -1851,6 +2075,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1860,6 +2085,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1869,6 +2095,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL DRS; for S= hared VN", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_Q_TxR_BL_DRS_CREDIT_OCCUPANCY.VN_SHR", "PerPkg": "1", @@ -1878,6 +2105,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1887,6 +2115,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCB; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1896,6 +2125,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1905,6 +2135,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCB; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_Q_TxR_BL_NCB_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1914,6 +2145,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN0", "PerPkg": "1", @@ -1923,6 +2155,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - NCS; for VN1", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_ACQUIRED.VN1", "PerPkg": "1", @@ -1932,6 +2165,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN0", "PerPkg": "1", @@ -1941,6 +2175,7 @@ }, { "BriefDescription": "R3QPI Egress Credit Occupancy - BL NCS; for V= N1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_Q_TxR_BL_NCS_CREDIT_OCCUPANCY.VN1", "PerPkg": "1", @@ -1950,6 +2185,7 @@ }, { "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", @@ -1958,6 +2194,7 @@ }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", @@ -1966,6 +2203,7 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_R3_CLOCKTICKS", "PerPkg": "1", @@ -1974,6 +2212,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO10", "PerPkg": "1", @@ -1983,6 +2222,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO11", "PerPkg": "1", @@ -1992,6 +2232,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO12", "PerPkg": "1", @@ -2001,6 +2242,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO13", "PerPkg": "1", @@ -2010,6 +2252,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO14", "PerPkg": "1", @@ -2019,6 +2262,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO8", "PerPkg": "1", @@ -2028,6 +2272,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2c", "EventName": "UNC_R3_C_HI_AD_CREDITS_EMPTY.CBO9", "PerPkg": "1", @@ -2037,6 +2282,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO0", "PerPkg": "1", @@ -2046,6 +2292,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO1", "PerPkg": "1", @@ -2055,6 +2302,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO2", "PerPkg": "1", @@ -2064,6 +2312,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO3", "PerPkg": "1", @@ -2073,6 +2322,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO4", "PerPkg": "1", @@ -2082,6 +2332,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO5", "PerPkg": "1", @@ -2091,6 +2342,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO6", "PerPkg": "1", @@ -2100,6 +2352,7 @@ }, { "BriefDescription": "CBox AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2b", "EventName": "UNC_R3_C_LO_AD_CREDITS_EMPTY.CBO7", "PerPkg": "1", @@ -2109,6 +2362,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2f", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA0", "PerPkg": "1", @@ -2118,6 +2372,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2f", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.HA1", "PerPkg": "1", @@ -2127,6 +2382,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2f", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCB", "PerPkg": "1", @@ -2136,6 +2392,7 @@ }, { "BriefDescription": "HA/R2 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2f", "EventName": "UNC_R3_HA_R2_BL_CREDITS_EMPTY.R2_NCS", "PerPkg": "1", @@ -2145,6 +2402,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2154,6 +2412,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2163,6 +2422,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2172,6 +2432,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2181,6 +2442,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2190,6 +2452,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2199,6 +2462,7 @@ }, { "BriefDescription": "QPI0 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x29", "EventName": "UNC_R3_QPI0_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2208,6 +2472,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2217,6 +2482,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2226,6 +2492,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2235,6 +2502,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2244,6 +2512,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2253,6 +2522,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2262,6 +2532,7 @@ }, { "BriefDescription": "QPI0 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_R3_QPI0_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2271,6 +2542,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2280,6 +2552,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2289,6 +2562,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2298,6 +2572,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2307,6 +2582,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2316,6 +2592,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2325,6 +2602,7 @@ }, { "BriefDescription": "QPI1 AD Credits Empty", + "Counter": "0,1", "EventCode": "0x2a", "EventName": "UNC_R3_QPI1_AD_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2334,6 +2612,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_HOM", "PerPkg": "1", @@ -2343,6 +2622,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_NDR", "PerPkg": "1", @@ -2352,6 +2632,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN0_SNP", "PerPkg": "1", @@ -2361,6 +2642,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_HOM", "PerPkg": "1", @@ -2370,6 +2652,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_NDR", "PerPkg": "1", @@ -2379,6 +2662,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VN1_SNP", "PerPkg": "1", @@ -2388,6 +2672,7 @@ }, { "BriefDescription": "QPI1 BL Credits Empty", + "Counter": "0,1", "EventCode": "0x2e", "EventName": "UNC_R3_QPI1_BL_CREDITS_EMPTY.VNA", "PerPkg": "1", @@ -2397,6 +2682,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW", "PerPkg": "1", @@ -2406,6 +2692,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2415,6 +2702,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2424,6 +2712,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW", "PerPkg": "1", @@ -2433,6 +2722,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2442,6 +2732,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2451,6 +2742,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW", "PerPkg": "1", @@ -2460,6 +2752,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2469,6 +2762,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2478,6 +2772,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW", "PerPkg": "1", @@ -2487,6 +2782,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2496,6 +2792,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2505,6 +2802,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW", "PerPkg": "1", @@ -2514,6 +2812,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -2523,6 +2822,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -2532,6 +2832,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW", "PerPkg": "1", @@ -2541,6 +2842,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -2550,6 +2852,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_VR0_ODD", "PerPkg": "1", @@ -2559,6 +2862,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2", "EventCode": "0xA", "EventName": "UNC_R3_RING_IV_USED.ANY", "PerPkg": "1", @@ -2568,6 +2872,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2", "EventCode": "0xa", "EventName": "UNC_R3_RING_IV_USED.CCW", "PerPkg": "1", @@ -2577,6 +2882,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2", "EventCode": "0xa", "EventName": "UNC_R3_RING_IV_USED.CW", "PerPkg": "1", @@ -2586,6 +2892,7 @@ }, { "BriefDescription": "AD Ingress Bypassed", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_R3_RxR_AD_BYPASSED", "PerPkg": "1", @@ -2594,6 +2901,7 @@ }, { "BriefDescription": "Ingress Bypassed", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_R3_RxR_BYPASSED.AD", "PerPkg": "1", @@ -2603,6 +2911,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", "PerPkg": "1", @@ -2612,6 +2921,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", "PerPkg": "1", @@ -2621,6 +2931,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", "PerPkg": "1", @@ -2630,6 +2941,7 @@ }, { "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.DRS", "PerPkg": "1", @@ -2639,6 +2951,7 @@ }, { "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.HOM", "PerPkg": "1", @@ -2648,6 +2961,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCB", "PerPkg": "1", @@ -2657,6 +2971,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCS", "PerPkg": "1", @@ -2666,6 +2981,7 @@ }, { "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NDR", "PerPkg": "1", @@ -2675,6 +2991,7 @@ }, { "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.SNP", "PerPkg": "1", @@ -2684,6 +3001,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -2693,6 +3011,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", "PerPkg": "1", @@ -2702,6 +3021,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", "PerPkg": "1", @@ -2711,6 +3031,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", "PerPkg": "1", @@ -2720,6 +3041,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", "PerPkg": "1", @@ -2729,6 +3051,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", "PerPkg": "1", @@ -2738,6 +3061,7 @@ }, { "BriefDescription": "Egress NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_TxR_NACK_CCW.AD", "PerPkg": "1", @@ -2747,6 +3071,7 @@ }, { "BriefDescription": "Egress NACK; BL CW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_TxR_NACK_CCW.AK", "PerPkg": "1", @@ -2756,6 +3081,7 @@ }, { "BriefDescription": "Egress NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R3_TxR_NACK_CCW.BL", "PerPkg": "1", @@ -2765,6 +3091,7 @@ }, { "BriefDescription": "Egress NACK; AD CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK_CW.AD", "PerPkg": "1", @@ -2774,6 +3101,7 @@ }, { "BriefDescription": "Egress NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK_CW.AK", "PerPkg": "1", @@ -2783,6 +3111,7 @@ }, { "BriefDescription": "Egress NACK; AK CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R3_TxR_NACK_CW.BL", "PerPkg": "1", @@ -2792,6 +3121,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2801,6 +3131,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2810,6 +3141,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -2819,6 +3151,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -2828,6 +3161,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -2837,6 +3171,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -2846,6 +3181,7 @@ }, { "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", @@ -2855,6 +3191,7 @@ }, { "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", @@ -2864,6 +3201,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", @@ -2873,6 +3211,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", "PerPkg": "1", @@ -2882,6 +3221,7 @@ }, { "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", "PerPkg": "1", @@ -2891,6 +3231,7 @@ }, { "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", "PerPkg": "1", @@ -2900,6 +3241,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -2909,6 +3251,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -2918,6 +3261,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -2927,6 +3271,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -2936,6 +3281,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -2945,6 +3291,7 @@ }, { "BriefDescription": "VN1 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_R3_VN1_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -2954,6 +3301,7 @@ }, { "BriefDescription": "VN1 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.DRS", "PerPkg": "1", @@ -2963,6 +3311,7 @@ }, { "BriefDescription": "VN1 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.HOM", "PerPkg": "1", @@ -2972,6 +3321,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCB", "PerPkg": "1", @@ -2981,6 +3331,7 @@ }, { "BriefDescription": "VN1 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NCS", "PerPkg": "1", @@ -2990,6 +3341,7 @@ }, { "BriefDescription": "VN1 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.NDR", "PerPkg": "1", @@ -2999,6 +3351,7 @@ }, { "BriefDescription": "VN1 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x38", "EventName": "UNC_R3_VN1_CREDITS_USED.SNP", "PerPkg": "1", @@ -3008,6 +3361,7 @@ }, { "BriefDescription": "VNA credit Acquisitions", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", "PerPkg": "1", @@ -3016,6 +3370,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.AD", "PerPkg": "1", @@ -3025,6 +3380,7 @@ }, { "BriefDescription": "VNA credit Acquisitions; HOM Message Class", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED.BL", "PerPkg": "1", @@ -3034,6 +3390,7 @@ }, { "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -3043,6 +3400,7 @@ }, { "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -3052,6 +3410,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -3061,6 +3420,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -3070,6 +3430,7 @@ }, { "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -3079,6 +3440,7 @@ }, { "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -3088,6 +3450,7 @@ }, { "BriefDescription": "Cycles with no VNA credits available", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", "PerPkg": "1", @@ -3096,6 +3459,7 @@ }, { "BriefDescription": "Cycles with 1 or more VNA credits in use", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", "PerPkg": "1", @@ -3103,12 +3467,14 @@ "Unit": "R3QPI" }, { + "Counter": "0,1", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", "Unit": "UBOX" }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", @@ -3118,6 +3484,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", "PerPkg": "1", @@ -3127,6 +3494,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", @@ -3136,6 +3504,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", "PerPkg": "1", @@ -3145,6 +3514,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", @@ -3154,6 +3524,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", @@ -3163,6 +3534,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", @@ -3172,6 +3544,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", @@ -3181,6 +3554,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", @@ -3190,6 +3564,7 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", @@ -3198,6 +3573,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", @@ -3207,6 +3583,7 @@ }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", "PerPkg": "1", @@ -3214,6 +3591,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", @@ -3223,6 +3601,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", @@ -3232,6 +3611,7 @@ }, { "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", @@ -3241,6 +3621,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", @@ -3250,6 +3631,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", @@ -3259,6 +3641,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", @@ -3268,6 +3651,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", @@ -3277,6 +3661,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json b/tools/= perf/pmu-events/arch/x86/ivytown/uncore-io.json index 5887e6ebcfa8..0bc6641fb6a5 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_R2_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -18,6 +20,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -27,6 +30,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -36,6 +40,7 @@ }, { "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -45,6 +50,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -54,6 +60,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -63,6 +70,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -72,6 +80,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW", "PerPkg": "1", @@ -81,6 +90,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -90,6 +100,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -99,6 +110,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -108,6 +120,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -117,6 +130,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW", "PerPkg": "1", @@ -126,6 +140,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -135,6 +150,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_VR0_ODD", "PerPkg": "1", @@ -144,6 +160,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -153,6 +170,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_VR1_ODD", "PerPkg": "1", @@ -162,6 +180,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW", "PerPkg": "1", @@ -171,6 +190,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -180,6 +200,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -189,6 +210,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -198,6 +220,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -207,6 +230,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW", "PerPkg": "1", @@ -216,6 +240,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -225,6 +250,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_VR0_ODD", "PerPkg": "1", @@ -234,6 +260,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -243,6 +270,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_VR1_ODD", "PerPkg": "1", @@ -252,6 +280,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW", "PerPkg": "1", @@ -261,6 +290,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even = on VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_EVEN", "PerPkg": "1", @@ -270,6 +300,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd o= n VRing 0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_VR0_ODD", "PerPkg": "1", @@ -279,6 +310,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even = on VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_EVEN", "PerPkg": "1", @@ -288,6 +320,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd o= n VRing 1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_VR1_ODD", "PerPkg": "1", @@ -297,6 +330,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW", "PerPkg": "1", @@ -306,6 +340,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRin= g 0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_VR0_EVEN", "PerPkg": "1", @@ -315,6 +350,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing= 0", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_VR0_ODD", "PerPkg": "1", @@ -324,6 +360,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even on VRin= g 1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_VR1_EVEN", "PerPkg": "1", @@ -333,6 +370,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd on VRing= 1", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_VR1_ODD", "PerPkg": "1", @@ -342,6 +380,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_R2_RING_IV_USED.ANY", "PerPkg": "1", @@ -351,6 +390,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Counterclockwise", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_R2_RING_IV_USED.CCW", "PerPkg": "1", @@ -360,6 +400,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Clockwise", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_R2_RING_IV_USED.CW", "PerPkg": "1", @@ -369,6 +410,7 @@ }, { "BriefDescription": "AK Ingress Bounced", + "Counter": "0", "EventCode": "0x12", "EventName": "UNC_R2_RxR_AK_BOUNCES", "PerPkg": "1", @@ -377,6 +419,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Counterclockwise", + "Counter": "0", "EventCode": "0x12", "EventName": "UNC_R2_RxR_AK_BOUNCES.CCW", "PerPkg": "1", @@ -386,6 +429,7 @@ }, { "BriefDescription": "AK Ingress Bounced; Clockwise", + "Counter": "0", "EventCode": "0x12", "EventName": "UNC_R2_RxR_AK_BOUNCES.CW", "PerPkg": "1", @@ -395,6 +439,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -404,6 +449,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -413,6 +459,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCB", "PerPkg": "1", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R2_RxR_INSERTS.NCS", "PerPkg": "1", @@ -431,6 +479,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R2_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -440,6 +489,7 @@ }, { "BriefDescription": "Egress Cycles Full; AD", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", "PerPkg": "1", @@ -449,6 +499,7 @@ }, { "BriefDescription": "Egress Cycles Full; AK", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", "PerPkg": "1", @@ -458,6 +509,7 @@ }, { "BriefDescription": "Egress Cycles Full; BL", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", "PerPkg": "1", @@ -467,6 +519,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AD", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AD", "PerPkg": "1", @@ -476,6 +529,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AK", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AK", "PerPkg": "1", @@ -485,6 +539,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; BL", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.BL", "PerPkg": "1", @@ -494,6 +549,7 @@ }, { "BriefDescription": "Egress CCW NACK; AD CCW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_TxR_NACK_CCW.AD", "PerPkg": "1", @@ -503,6 +559,7 @@ }, { "BriefDescription": "Egress CCW NACK; AK CCW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_TxR_NACK_CCW.AK", "PerPkg": "1", @@ -512,6 +569,7 @@ }, { "BriefDescription": "Egress CCW NACK; BL CCW", + "Counter": "0,1", "EventCode": "0x28", "EventName": "UNC_R2_TxR_NACK_CCW.BL", "PerPkg": "1", @@ -521,6 +579,7 @@ }, { "BriefDescription": "Egress CW NACK; AD CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.AD", "PerPkg": "1", @@ -530,6 +589,7 @@ }, { "BriefDescription": "Egress CW NACK; AK CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.AK", "PerPkg": "1", @@ -539,6 +599,7 @@ }, { "BriefDescription": "Egress CW NACK; BL CW", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACK_CW.BL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json b/to= ols/perf/pmu-events/arch/x86/ivytown/uncore-memory.json index 65509342d56a..1406d220df2d 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Write", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M_BYP_CMDS.ACT", "PerPkg": "1", @@ -36,6 +40,7 @@ }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M_BYP_CMDS.CAS", "PerPkg": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M_BYP_CMDS.PRE", "PerPkg": "1", @@ -52,6 +58,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -61,6 +68,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -70,6 +78,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -79,6 +88,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", "PerPkg": "1", @@ -87,6 +97,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -96,6 +107,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Read CAS is= sued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", "PerPkg": "1", @@ -104,6 +116,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -113,6 +126,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", @@ -122,6 +136,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -131,12 +146,14 @@ }, { "BriefDescription": "DRAM Clockticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_DCLOCKTICKS", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", @@ -145,6 +162,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -154,6 +172,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -163,6 +182,7 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", @@ -171,6 +191,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", @@ -180,6 +201,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", @@ -189,6 +211,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", @@ -198,6 +221,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", @@ -207,6 +231,7 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "PerPkg": "1", @@ -223,6 +249,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", @@ -232,6 +259,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", @@ -241,6 +269,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", @@ -250,6 +279,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", @@ -259,6 +289,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", @@ -268,6 +299,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", @@ -277,6 +309,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", @@ -286,6 +319,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", @@ -295,6 +329,7 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", @@ -302,6 +337,7 @@ "Unit": "iMC" }, { + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", "PerPkg": "1", @@ -309,6 +345,7 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "PerPkg": "1", @@ -317,6 +354,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", @@ -326,6 +364,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", @@ -335,6 +374,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", @@ -344,6 +384,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", @@ -353,6 +394,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", @@ -362,6 +404,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", @@ -371,6 +414,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", @@ -380,6 +424,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", @@ -389,6 +434,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", @@ -398,6 +444,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", @@ -407,6 +454,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", "PerPkg": "1", @@ -416,6 +464,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", @@ -425,6 +474,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -434,6 +484,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -443,6 +494,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -452,6 +504,7 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", "PerPkg": "1", @@ -460,6 +513,7 @@ }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", "PerPkg": "1", @@ -468,6 +522,7 @@ }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_RD_CAS_PRIO.MED", "PerPkg": "1", @@ -476,6 +531,7 @@ }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", "PerPkg": "1", @@ -484,6 +540,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", "PerPkg": "1", @@ -492,6 +549,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", "PerPkg": "1", @@ -500,6 +558,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", "PerPkg": "1", @@ -508,6 +567,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", "PerPkg": "1", @@ -516,6 +576,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", "PerPkg": "1", @@ -524,6 +585,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", "PerPkg": "1", @@ -532,6 +594,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", "PerPkg": "1", @@ -540,6 +603,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", "PerPkg": "1", @@ -548,6 +612,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", "PerPkg": "1", @@ -556,6 +621,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", "PerPkg": "1", @@ -564,6 +630,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", "PerPkg": "1", @@ -572,6 +639,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", "PerPkg": "1", @@ -580,6 +648,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", "PerPkg": "1", @@ -588,6 +657,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", "PerPkg": "1", @@ -596,6 +666,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", "PerPkg": "1", @@ -604,6 +675,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", "PerPkg": "1", @@ -612,6 +684,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", "PerPkg": "1", @@ -620,6 +693,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK1", "PerPkg": "1", @@ -628,6 +702,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK2", "PerPkg": "1", @@ -636,6 +711,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK3", "PerPkg": "1", @@ -644,6 +720,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK4", "PerPkg": "1", @@ -652,6 +729,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK5", "PerPkg": "1", @@ -660,6 +738,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK6", "PerPkg": "1", @@ -668,6 +747,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK7", "PerPkg": "1", @@ -676,6 +756,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK0", "PerPkg": "1", @@ -684,6 +765,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK1", "PerPkg": "1", @@ -692,6 +774,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK2", "PerPkg": "1", @@ -700,6 +783,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK3", "PerPkg": "1", @@ -708,6 +792,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK4", "PerPkg": "1", @@ -716,6 +801,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK5", "PerPkg": "1", @@ -724,6 +810,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK6", "PerPkg": "1", @@ -732,6 +819,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK7", "PerPkg": "1", @@ -740,6 +828,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", "PerPkg": "1", @@ -748,6 +837,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", "PerPkg": "1", @@ -756,6 +846,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", "PerPkg": "1", @@ -764,6 +855,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", "PerPkg": "1", @@ -772,6 +864,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", "PerPkg": "1", @@ -780,6 +873,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", "PerPkg": "1", @@ -788,6 +882,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", "PerPkg": "1", @@ -796,6 +891,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", "PerPkg": "1", @@ -804,6 +900,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", "PerPkg": "1", @@ -812,6 +909,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", "PerPkg": "1", @@ -820,6 +918,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", "PerPkg": "1", @@ -828,6 +927,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", "PerPkg": "1", @@ -836,6 +936,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", "PerPkg": "1", @@ -844,6 +945,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", "PerPkg": "1", @@ -852,6 +954,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", "PerPkg": "1", @@ -860,6 +963,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", "PerPkg": "1", @@ -868,6 +972,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", "PerPkg": "1", @@ -876,6 +981,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", "PerPkg": "1", @@ -884,6 +990,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", "PerPkg": "1", @@ -892,6 +999,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", "PerPkg": "1", @@ -900,6 +1008,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", "PerPkg": "1", @@ -908,6 +1017,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", "PerPkg": "1", @@ -916,6 +1026,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", "PerPkg": "1", @@ -924,6 +1035,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", "PerPkg": "1", @@ -932,6 +1044,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", "PerPkg": "1", @@ -940,6 +1053,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", "PerPkg": "1", @@ -948,6 +1062,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", "PerPkg": "1", @@ -956,6 +1071,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", "PerPkg": "1", @@ -964,6 +1080,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", "PerPkg": "1", @@ -972,6 +1089,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", "PerPkg": "1", @@ -980,6 +1098,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", "PerPkg": "1", @@ -988,6 +1107,7 @@ }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", "PerPkg": "1", @@ -996,6 +1116,7 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", @@ -1004,6 +1125,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -1012,6 +1134,7 @@ }, { "BriefDescription": "VMSE MXB write buffer occupancy", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M_VMSE_MXB_WR_OCCUPANCY", "PerPkg": "1", @@ -1019,6 +1142,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n RMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.RMM", "PerPkg": "1", @@ -1027,6 +1151,7 @@ }, { "BriefDescription": "VMSE WR PUSH issued; VMSE write PUSH issued i= n WMM", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M_VMSE_WR_PUSH.WMM", "PerPkg": "1", @@ -1035,6 +1160,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", "PerPkg": "1", @@ -1043,6 +1169,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", "PerPkg": "1", @@ -1051,6 +1178,7 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", "PerPkg": "1", @@ -1059,6 +1187,7 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", @@ -1067,6 +1196,7 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", @@ -1075,6 +1205,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS", "PerPkg": "1", @@ -1083,6 +1214,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", @@ -1091,6 +1223,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", @@ -1099,6 +1232,7 @@ }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_M_WRONG_MM", "PerPkg": "1", @@ -1106,6 +1240,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", "PerPkg": "1", @@ -1114,6 +1249,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", "PerPkg": "1", @@ -1122,6 +1258,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", "PerPkg": "1", @@ -1130,6 +1267,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", "PerPkg": "1", @@ -1138,6 +1276,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", "PerPkg": "1", @@ -1146,6 +1285,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", "PerPkg": "1", @@ -1154,6 +1294,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", "PerPkg": "1", @@ -1162,6 +1303,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", "PerPkg": "1", @@ -1170,6 +1312,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", "PerPkg": "1", @@ -1178,6 +1321,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", "PerPkg": "1", @@ -1186,6 +1330,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", "PerPkg": "1", @@ -1194,6 +1339,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", "PerPkg": "1", @@ -1202,6 +1348,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", "PerPkg": "1", @@ -1210,6 +1357,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", "PerPkg": "1", @@ -1218,6 +1366,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", "PerPkg": "1", @@ -1226,6 +1375,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", "PerPkg": "1", @@ -1234,6 +1384,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK0", "PerPkg": "1", @@ -1242,6 +1393,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK1", "PerPkg": "1", @@ -1250,6 +1402,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK2", "PerPkg": "1", @@ -1258,6 +1411,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK3", "PerPkg": "1", @@ -1266,6 +1420,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK4", "PerPkg": "1", @@ -1274,6 +1429,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK5", "PerPkg": "1", @@ -1282,6 +1438,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK6", "PerPkg": "1", @@ -1290,6 +1447,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK7", "PerPkg": "1", @@ -1298,6 +1456,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK0", "PerPkg": "1", @@ -1306,6 +1465,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK1", "PerPkg": "1", @@ -1314,6 +1474,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK2", "PerPkg": "1", @@ -1322,6 +1483,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK3", "PerPkg": "1", @@ -1330,6 +1492,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK4", "PerPkg": "1", @@ -1338,6 +1501,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK5", "PerPkg": "1", @@ -1346,6 +1510,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK6", "PerPkg": "1", @@ -1354,6 +1519,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK7", "PerPkg": "1", @@ -1362,6 +1528,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", "PerPkg": "1", @@ -1370,6 +1537,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", "PerPkg": "1", @@ -1378,6 +1546,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", "PerPkg": "1", @@ -1386,6 +1555,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", "PerPkg": "1", @@ -1394,6 +1564,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", "PerPkg": "1", @@ -1402,6 +1573,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", "PerPkg": "1", @@ -1410,6 +1582,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", "PerPkg": "1", @@ -1418,6 +1591,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", "PerPkg": "1", @@ -1426,6 +1600,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", "PerPkg": "1", @@ -1434,6 +1609,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", "PerPkg": "1", @@ -1442,6 +1618,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", "PerPkg": "1", @@ -1450,6 +1627,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", "PerPkg": "1", @@ -1458,6 +1636,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", "PerPkg": "1", @@ -1466,6 +1645,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", "PerPkg": "1", @@ -1474,6 +1654,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", "PerPkg": "1", @@ -1482,6 +1663,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", "PerPkg": "1", @@ -1490,6 +1672,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", "PerPkg": "1", @@ -1498,6 +1681,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", "PerPkg": "1", @@ -1506,6 +1690,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", "PerPkg": "1", @@ -1514,6 +1699,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", "PerPkg": "1", @@ -1522,6 +1708,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", "PerPkg": "1", @@ -1530,6 +1717,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", "PerPkg": "1", @@ -1538,6 +1726,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", "PerPkg": "1", @@ -1546,6 +1735,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", "PerPkg": "1", @@ -1554,6 +1744,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", "PerPkg": "1", @@ -1562,6 +1753,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", "PerPkg": "1", @@ -1570,6 +1762,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", "PerPkg": "1", @@ -1578,6 +1771,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", "PerPkg": "1", @@ -1586,6 +1780,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", "PerPkg": "1", @@ -1594,6 +1789,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", "PerPkg": "1", @@ -1602,6 +1798,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", "PerPkg": "1", @@ -1610,6 +1807,7 @@ }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json b/too= ls/perf/pmu-events/arch/x86/ivytown/uncore-power.json index ad6c531a9e38..a4bdffe7c1f8 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 800 MHz clock. Thi= s event counts the number of pclk cycles measured while the counter was ena= bled. The pclk, like the Memory Controller's dclk, counts at a constant ra= te making it a good measure of actual wall time.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Core 0 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Core 10 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7a", "EventName": "UNC_P_CORE10_TRANSITION_CYCLES", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Core 11 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7b", "EventName": "UNC_P_CORE11_TRANSITION_CYCLES", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Core 12 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7c", "EventName": "UNC_P_CORE12_TRANSITION_CYCLES", "PerPkg": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Core 13 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7d", "EventName": "UNC_P_CORE13_TRANSITION_CYCLES", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Core 14 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7e", "EventName": "UNC_P_CORE14_TRANSITION_CYCLES", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Core 1 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Core 2 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Core 3 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Core 4 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Core 5 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Core 6 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Core 7 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", "PerPkg": "1", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Core 8 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_CORE8_TRANSITION_CYCLES", "PerPkg": "1", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Core 9 C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_P_CORE9_TRANSITION_CYCLES", "PerPkg": "1", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE0", "PerPkg": "1", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE1", "PerPkg": "1", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 10", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE10", "PerPkg": "1", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 11", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE11", "PerPkg": "1", @@ -160,6 +180,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 12", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE12", "PerPkg": "1", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 13", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE13", "PerPkg": "1", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 14", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE14", "PerPkg": "1", @@ -184,6 +207,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE2", "PerPkg": "1", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 3", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE3", "PerPkg": "1", @@ -200,6 +225,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 4", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE4", "PerPkg": "1", @@ -208,6 +234,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 5", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE5", "PerPkg": "1", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 6", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE6", "PerPkg": "1", @@ -224,6 +252,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 7", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE7", "PerPkg": "1", @@ -232,6 +261,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 8", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE8", "PerPkg": "1", @@ -240,6 +270,7 @@ }, { "BriefDescription": "Deep C State Rejection - Core 9", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_P_DELAYED_C_STATE_ABORT_CORE9", "PerPkg": "1", @@ -248,6 +279,7 @@ }, { "BriefDescription": "Core 0 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_P_DEMOTIONS_CORE0", "PerPkg": "1", @@ -256,6 +288,7 @@ }, { "BriefDescription": "Core 1 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_P_DEMOTIONS_CORE1", "PerPkg": "1", @@ -264,6 +297,7 @@ }, { "BriefDescription": "Core 10 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_DEMOTIONS_CORE10", "PerPkg": "1", @@ -272,6 +306,7 @@ }, { "BriefDescription": "Core 11 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_P_DEMOTIONS_CORE11", "PerPkg": "1", @@ -280,6 +315,7 @@ }, { "BriefDescription": "Core 12 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_P_DEMOTIONS_CORE12", "PerPkg": "1", @@ -288,6 +324,7 @@ }, { "BriefDescription": "Core 13 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_P_DEMOTIONS_CORE13", "PerPkg": "1", @@ -296,6 +333,7 @@ }, { "BriefDescription": "Core 14 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_P_DEMOTIONS_CORE14", "PerPkg": "1", @@ -304,6 +342,7 @@ }, { "BriefDescription": "Core 2 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", @@ -312,6 +351,7 @@ }, { "BriefDescription": "Core 3 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_P_DEMOTIONS_CORE3", "PerPkg": "1", @@ -320,6 +360,7 @@ }, { "BriefDescription": "Core 4 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_P_DEMOTIONS_CORE4", "PerPkg": "1", @@ -328,6 +369,7 @@ }, { "BriefDescription": "Core 5 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_P_DEMOTIONS_CORE5", "PerPkg": "1", @@ -336,6 +378,7 @@ }, { "BriefDescription": "Core 6 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_P_DEMOTIONS_CORE6", "PerPkg": "1", @@ -344,6 +387,7 @@ }, { "BriefDescription": "Core 7 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_P_DEMOTIONS_CORE7", "PerPkg": "1", @@ -352,6 +396,7 @@ }, { "BriefDescription": "Core 8 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_P_DEMOTIONS_CORE8", "PerPkg": "1", @@ -360,6 +405,7 @@ }, { "BriefDescription": "Core 9 C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_P_DEMOTIONS_CORE9", "PerPkg": "1", @@ -368,6 +414,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_P_FREQ_BAND0_CYCLES", "PerPkg": "1", @@ -376,6 +423,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_P_FREQ_BAND1_CYCLES", "PerPkg": "1", @@ -384,6 +432,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_P_FREQ_BAND2_CYCLES", "PerPkg": "1", @@ -392,6 +441,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_P_FREQ_BAND3_CYCLES", "PerPkg": "1", @@ -400,6 +450,7 @@ }, { "BriefDescription": "Current Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", "PerPkg": "1", @@ -408,6 +459,7 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", @@ -416,6 +468,7 @@ }, { "BriefDescription": "OS Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", "PerPkg": "1", @@ -424,6 +477,7 @@ }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", @@ -432,6 +486,7 @@ }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", @@ -440,6 +495,7 @@ }, { "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES", "PerPkg": "1", @@ -448,6 +504,7 @@ }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", @@ -456,6 +513,7 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", @@ -464,6 +522,7 @@ }, { "BriefDescription": "Package C State Exit Latency", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_P_PKG_C_EXIT_LATENCY", "PerPkg": "1", @@ -472,6 +531,7 @@ }, { "BriefDescription": "Package C State Exit Latency", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_P_PKG_C_EXIT_LATENCY_SEL", "PerPkg": "1", @@ -480,6 +540,7 @@ }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C0_CYCLES", "PerPkg": "1", @@ -488,6 +549,7 @@ }, { "BriefDescription": "Package C State Residency - C2", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C2_CYCLES", "PerPkg": "1", @@ -496,6 +558,7 @@ }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C3_CYCLES", "PerPkg": "1", @@ -504,6 +567,7 @@ }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_P_PKG_C_STATE_RESIDENCY_C6_CYCLES", "PerPkg": "1", @@ -512,6 +576,7 @@ }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "Filter": "occ_sel=3D1", @@ -521,6 +586,7 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "Filter": "occ_sel=3D2", @@ -530,6 +596,7 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "Filter": "occ_sel=3D3", @@ -539,6 +606,7 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", @@ -547,6 +615,7 @@ }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", @@ -555,6 +624,7 @@ }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", @@ -563,6 +633,7 @@ }, { "BriefDescription": "Cycles Changing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE", "PerPkg": "1", @@ -571,6 +642,7 @@ }, { "BriefDescription": "Cycles Decreasing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE", "PerPkg": "1", @@ -579,6 +651,7 @@ }, { "BriefDescription": "Cycles Increasing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE", "PerPkg": "1", @@ -587,6 +660,7 @@ }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json index 410763dd4394..b9b70d8beb43 100644 --- a/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/ivytown/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_COMPLETED", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.DEMAND_LD_WALK_DURATION", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Page walk for a large page completed for Dema= nd load.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.LARGE_PAGE_WALK_COMPLETED", "SampleAfterValue": "100003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes an page walk of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page w= alk of any page size from demand loads.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts load operations that missed 1st level= DTLB but hit the 2nd level.", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside= buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Misses in all TLB levels that caused page wa= lk completed of any size by demand loads.", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Demand load cycles page miss handler (PMH) is= busy with this walk.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "Cycle PMH is busy with a walk due to demand = loads.", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of= any page size (4K/2M/4M/1G).", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Store operations that miss the first TLB lev= el but hit the second and do not cause page walks.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Miss in all TLB levels causes a page walk th= at completes of any page size (4K/2M/4M/1G).", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "PublicDescription": "Cycles PMH is busy with this walk.", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes = 4k/2M/4M pages.", @@ -101,6 +114,7 @@ }, { "BriefDescription": "Completed page walks in ITLB due to STLB load= misses for large pages", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_PAGE_WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB due to STLB loa= d misses for large pages.", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all ITLB levels that cause page wa= lks.", @@ -117,6 +132,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Number of cache load STLB hits. No page walk= .", @@ -125,6 +141,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Misses in all ITLB levels that cause complet= ed page walks.", @@ -133,6 +150,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "Cycle PMH is busy with a walk.", @@ -141,6 +159,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific e= ntries.", @@ -149,6 +168,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C621B9AD2 for ; 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Thu, 20 Jun 2024 11:20:01 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:34 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-21-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 20/37] perf vendor events: Update jaketown metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/jaketown/cache.json | 123 +++++++++++ .../pmu-events/arch/x86/jaketown/counter.json | 52 +++++ .../arch/x86/jaketown/floating-point.json | 15 ++ .../arch/x86/jaketown/frontend.json | 32 +++ .../arch/x86/jaketown/jkt-metrics.json | 24 +- .../pmu-events/arch/x86/jaketown/memory.json | 35 +++ .../arch/x86/jaketown/metricgroups.json | 11 + .../pmu-events/arch/x86/jaketown/other.json | 6 + .../arch/x86/jaketown/pipeline.json | 127 +++++++++++ .../arch/x86/jaketown/uncore-cache.json | 205 +++++++++++++++++ .../x86/jaketown/uncore-interconnect.json | 207 ++++++++++++++++++ .../arch/x86/jaketown/uncore-io.json | 36 +++ .../arch/x86/jaketown/uncore-memory.json | 51 +++++ .../arch/x86/jaketown/uncore-power.json | 39 ++++ .../arch/x86/jaketown/virtual-memory.json | 16 ++ 15 files changed, 967 insertions(+), 12 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/jaketown/counter.json diff --git a/tools/perf/pmu-events/arch/x86/jaketown/cache.json b/tools/per= f/pmu-events/arch/x86/jaketown/cache.json index b9769d39940c..ab3713c469e3 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Allocated L1D data cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALLOCATED_IN_M", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALL_M_REPLACEMENT", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.EVICTION", "SampleAfterValue": "2000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D data line replacements.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xBF", "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -46,6 +52,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles.", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -62,6 +70,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -84,6 +95,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_S", "SampleAfterValue": "200003", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.MISS", "SampleAfterValue": "200003", @@ -105,6 +119,7 @@ }, { "BriefDescription": "L2 cache lines filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", @@ -113,6 +128,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", @@ -120,6 +136,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "SampleAfterValue": "100003", @@ -127,6 +144,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "SampleAfterValue": "100003", @@ -134,6 +152,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -141,6 +160,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100003", @@ -148,6 +168,7 @@ }, { "BriefDescription": "Dirty L2 cache lines filling the L2.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", @@ -155,6 +176,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", @@ -162,6 +184,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_DIRTY", "SampleAfterValue": "100003", @@ -169,6 +192,7 @@ }, { "BriefDescription": "L2 code requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "SampleAfterValue": "200003", @@ -176,6 +200,7 @@ }, { "BriefDescription": "Demand Data Read requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -183,6 +208,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "SampleAfterValue": "200003", @@ -190,6 +216,7 @@ }, { "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "SampleAfterValue": "200003", @@ -197,6 +224,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -204,6 +232,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -211,6 +240,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "SampleAfterValue": "200003", @@ -218,6 +248,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "SampleAfterValue": "200003", @@ -225,6 +256,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "SampleAfterValue": "200003", @@ -232,6 +264,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -239,6 +272,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -246,6 +280,7 @@ }, { "BriefDescription": "RFOs that access cache lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.ALL", "SampleAfterValue": "200003", @@ -253,6 +288,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -260,6 +296,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -267,6 +304,7 @@ }, { "BriefDescription": "RFOs that miss cache lines.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.MISS", "SampleAfterValue": "200003", @@ -274,6 +312,7 @@ }, { "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "SampleAfterValue": "200003", @@ -281,6 +320,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "SampleAfterValue": "200003", @@ -288,6 +328,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions.= ", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "SampleAfterValue": "200003", @@ -295,6 +336,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -302,6 +344,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "SampleAfterValue": "200003", @@ -309,6 +352,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "SampleAfterValue": "200003", @@ -316,6 +360,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "SampleAfterValue": "200003", @@ -323,6 +368,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "SampleAfterValue": "200003", @@ -330,6 +376,7 @@ }, { "BriefDescription": "Cycles when L1D is locked.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "SampleAfterValue": "2000003", @@ -337,6 +384,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100003", @@ -344,6 +392,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "100003", @@ -351,6 +400,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a non-modified state.", @@ -359,6 +409,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", "PublicDescription": "This event counts retired load uops that hit= in the last-level cache (L3) and were found in a non-modified state in a n= eighboring core's private cache (same package). Since the last level cache= is inclusive, hits to the L3 may require snooping the private L2 caches of= any cores on the same socket that have the line. In this case, a snoop wa= s required, and another L2 had the line in a modified state, so the line ha= d to be invalidated in that L2 cache and transferred to the requesting L2.", @@ -367,6 +418,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "SampleAfterValue": "20011", @@ -374,6 +426,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "SampleAfterValue": "100003", @@ -381,6 +434,7 @@ }, { "BriefDescription": "Data from local DRAM either Snoop not needed = or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM", "SampleAfterValue": "100007", @@ -388,6 +442,7 @@ }, { "BriefDescription": "Data from remote DRAM either Snoop not needed= or Snoop Miss (RspI)", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.REMOTE_DRAM", "SampleAfterValue": "100007", @@ -395,6 +450,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", @@ -403,6 +459,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", @@ -411,6 +468,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", @@ -419,6 +477,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PublicDescription": "This event counts retired load uops that hit= in the last-level (L3) cache without snoops required.", @@ -427,6 +486,7 @@ }, { "BriefDescription": "Miss in last-level (L3) cache. Excludes Unkno= wn data-source.", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_MISS", "SampleAfterValue": "100007", @@ -434,6 +494,7 @@ }, { "BriefDescription": "All retired load uops.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", @@ -443,6 +504,7 @@ }, { "BriefDescription": "All retired store uops.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", @@ -452,6 +514,7 @@ }, { "BriefDescription": "Retired load uops with locked access.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", @@ -460,6 +523,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", @@ -469,6 +533,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", @@ -478,6 +543,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", @@ -486,6 +552,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB.", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", @@ -494,6 +561,7 @@ }, { "BriefDescription": "Demand and prefetch data reads.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "SampleAfterValue": "100003", @@ -501,6 +569,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", @@ -508,6 +577,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -515,6 +585,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "SampleAfterValue": "100003", @@ -522,6 +593,7 @@ }, { "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -529,6 +601,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "SampleAfterValue": "2000003", @@ -536,6 +609,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -544,6 +618,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -552,6 +627,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -560,6 +636,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -567,6 +644,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", @@ -575,6 +653,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "SampleAfterValue": "2000003", @@ -582,6 +661,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -591,6 +671,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -600,6 +681,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -609,6 +691,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -618,6 +701,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -627,6 +711,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit the L= LC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -636,6 +721,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -645,6 +731,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -654,6 +741,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -663,6 +751,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -672,6 +761,7 @@ }, { "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -690,6 +781,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -699,6 +791,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -708,6 +801,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -717,6 +811,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -726,6 +821,7 @@ }, { "BriefDescription": "Counts all demand & prefetch prefetch RFOs", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -735,6 +831,7 @@ }, { "BriefDescription": "Counts all writebacks from the core to the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -744,6 +841,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -753,6 +851,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -762,6 +861,7 @@ }, { "BriefDescription": "Counts all demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -771,6 +871,7 @@ }, { "BriefDescription": "Counts all demand data reads that hit in the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -780,6 +881,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -789,6 +891,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -798,6 +901,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -807,6 +911,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoop returned a clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -816,6 +921,7 @@ }, { "BriefDescription": "Counts all demand rfo's", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -825,6 +931,7 @@ }, { "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", @@ -834,6 +941,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", @@ -843,6 +951,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -852,6 +961,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -861,6 +971,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -870,6 +981,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -879,6 +991,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -888,6 +1001,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -897,6 +1011,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -906,6 +1021,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -915,6 +1031,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -924,6 +1041,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -933,6 +1051,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -942,6 +1061,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -951,6 +1071,7 @@ }, { "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -960,6 +1081,7 @@ }, { "BriefDescription": "Counts non-temporal stores", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -969,6 +1091,7 @@ }, { "BriefDescription": "Split locks in SQ.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/counter.json b/tools/p= erf/pmu-events/arch/x86/jaketown/counter.json new file mode 100644 index 000000000000..fac24dfeb23f --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/jaketown/counter.json @@ -0,0 +1,52 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "R3QPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "R2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "HA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json b/= tools/perf/pmu-events/arch/x86/jaketown/floating-point.json index 79e8f403c426..8b570829e2e0 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles with any input/output SSE or FP assist= .", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= .", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "SampleAfterValue": "2000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "SampleAfterValue": "2000003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "SampleAfterValue": "2000003", @@ -58,6 +66,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "SampleAfterValue": "2000003", @@ -65,6 +74,7 @@ }, { "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIV= s, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish= an FADD used in the middle of a transcendental flow from a s.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", @@ -72,6 +82,7 @@ }, { "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_STORE", "SampleAfterValue": "100003", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", @@ -86,6 +98,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", @@ -93,6 +106,7 @@ }, { "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "SampleAfterValue": "2000003", @@ -100,6 +114,7 @@ }, { "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_SINGLE", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json b/tools/= perf/pmu-events/arch/x86/jaketown/frontend.json index 754ee2749485..3cb468da7011 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/frontend.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.EXCEED_DSB_LINES", "SampleAfterValue": "2000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.OTHER_CANCEL", "SampleAfterValue": "2000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", @@ -59,6 +67,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -75,6 +85,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -83,6 +94,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -99,6 +112,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "SampleAfterValue": "2000003", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "SampleAfterValue": "2000003", @@ -113,6 +128,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "SampleAfterValue": "2000003", @@ -120,6 +136,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -128,6 +145,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "SampleAfterValue": "2000003", @@ -135,6 +153,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -144,6 +163,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -152,6 +172,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -161,6 +182,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", @@ -168,6 +190,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", @@ -175,6 +198,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -184,6 +208,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", @@ -191,6 +216,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", @@ -199,6 +225,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -207,6 +234,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -216,6 +244,7 @@ }, { "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", @@ -225,6 +254,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -233,6 +263,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -241,6 +272,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json b/too= ls/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json index fc8c3f785be1..f8c18741b360 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/jkt-metrics.json @@ -73,7 +73,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -94,7 +94,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -124,7 +124,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -152,7 +152,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -226,7 +226,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -296,13 +296,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -419,7 +419,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -458,7 +458,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -468,7 +468,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_info_system_dram_bw_use", @@ -477,7 +477,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: ", @@ -525,7 +525,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/memory.json b/tools/pe= rf/pmu-events/arch/x86/jaketown/memory.json index a71e630fd030..41200f0e0df6 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads with latency value being above 128.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Loads with latency value being above 256.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -39,6 +43,7 @@ }, { "BriefDescription": "Loads with latency value being above 32.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -49,6 +54,7 @@ }, { "BriefDescription": "Loads with latency value being above 4 .", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -59,6 +65,7 @@ }, { "BriefDescription": "Loads with latency value being above 512.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -69,6 +76,7 @@ }, { "BriefDescription": "Loads with latency value being above 64.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Loads with latency value being above 8.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -89,6 +98,7 @@ }, { "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", @@ -111,6 +123,7 @@ }, { "BriefDescription": "This event counts all LLC misses for all dema= nd and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -120,6 +133,7 @@ }, { "BriefDescription": "Counts all local dram accesses for all demand= and L2 prefetches. LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +143,7 @@ }, { "BriefDescription": "This event counts all remote cache-to-cache t= ransfers (includes HITM and HIT-Forward) for all demand and L2 prefetches. = LLC prefetches are excluded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DEMAND_MLC_PREF_READS.LLC_MISS.= REMOTE_HITM_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +153,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +173,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +183,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C the data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +193,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the LL= C and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -183,6 +203,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -192,6 +213,7 @@ }, { "BriefDescription": "Counts demand data reads that miss in the LLC= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -201,6 +223,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -210,6 +233,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_DRAM= ", "MSRIndex": "0x1a6,0x1a7", @@ -219,6 +243,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC t= he data is found in M state in remote cache and forwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -228,6 +253,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC a= nd the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.REMOTE_HIT_= FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -237,6 +263,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from remote & local dram= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -246,6 +273,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote & local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -255,6 +283,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -264,6 +293,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from local dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -273,6 +303,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from remote dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -282,6 +313,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC the data is found in M state in remote cache and f= orwarded from there", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -291,6 +323,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data forwarded from remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -300,6 +333,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss in the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", @@ -309,6 +343,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.ANY_RESPONS= E", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json b/to= ols/perf/pmu-events/arch/x86/jaketown/metricgroups.json index a2c27794c0d8..7dc7eb0d3dd3 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/other.json b/tools/per= f/pmu-events/arch/x86/jaketown/other.json index 9f96121baef8..42692fa24b6c 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/other.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Valid instructions written to IQ per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json b/tools/= perf/pmu-events/arch/x86/jaketown/pipeline.json index d0edfdec9f01..ca0694c33de1 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "AGU_BYPASS_CANCEL.COUNT", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide operations executed.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Cycles when divider is busy executing divide = operations.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "SampleAfterValue": "2000003", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Speculative and retired branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls.= ", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -116,12 +132,14 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "SampleAfterValue": "400009" }, { "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -138,6 +157,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "SampleAfterValue": "100007", @@ -145,6 +165,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -153,6 +174,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -161,6 +183,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -169,6 +192,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "SampleAfterValue": "400009", @@ -176,6 +200,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", @@ -183,6 +208,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -190,6 +216,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -197,6 +224,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -204,6 +232,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -212,6 +241,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -219,6 +249,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -226,6 +257,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -233,6 +265,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -240,6 +273,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -247,6 +281,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", @@ -254,12 +289,14 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "SampleAfterValue": "400009" }, { "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -268,6 +305,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -276,6 +314,7 @@ }, { "BriefDescription": "Direct and indirect mispredicted near call in= structions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -284,6 +323,7 @@ }, { "BriefDescription": "Mispredicted not taken branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NOT_TAKEN", "PEBS": "1", @@ -292,6 +332,7 @@ }, { "BriefDescription": "Mispredicted taken branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN", "PEBS": "1", @@ -300,6 +341,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -307,6 +349,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "2000003", @@ -315,6 +358,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -322,6 +366,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -329,6 +374,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", "SampleAfterValue": "2000003", @@ -336,6 +382,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "2000003", @@ -344,6 +391,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -351,6 +399,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -359,12 +408,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003" @@ -372,12 +423,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", + "Counter": "2", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -386,6 +439,7 @@ }, { "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -394,6 +448,7 @@ }, { "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", @@ -402,6 +457,7 @@ }, { "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -410,6 +466,7 @@ }, { "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -418,6 +475,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000003", @@ -425,6 +483,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", @@ -432,6 +491,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", "SampleAfterValue": "2000003", @@ -439,12 +499,14 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", + "Counter": "1", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", @@ -453,6 +515,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RAT_STALL_CYCLES", "SampleAfterValue": "2000003", @@ -460,6 +523,7 @@ }, { "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -469,6 +533,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -477,6 +542,7 @@ }, { "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -486,6 +552,7 @@ }, { "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL_BLOCK", "SampleAfterValue": "100003", @@ -493,6 +560,7 @@ }, { "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "SampleAfterValue": "100003", @@ -500,6 +568,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", @@ -507,6 +576,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. See the table of not supported store forward= s in the Intel? 64 and IA-32 Architectures Optimization Reference Manual. = The penalty for blocked store forwarding is that the load must wait for the= store to complete before it can be issued.", @@ -515,6 +585,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", @@ -523,6 +594,7 @@ }, { "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", "SampleAfterValue": "100003", @@ -530,6 +602,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "SampleAfterValue": "100003", @@ -537,6 +610,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "SampleAfterValue": "100003", @@ -544,6 +618,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -552,6 +627,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -560,6 +636,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -567,6 +644,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -576,6 +654,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", @@ -584,6 +663,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", @@ -592,6 +672,7 @@ }, { "BriefDescription": "Retired instructions experiencing ITLB misses= .", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", "SampleAfterValue": "100003", @@ -599,6 +680,7 @@ }, { "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", "SampleAfterValue": "2000003", @@ -606,6 +688,7 @@ }, { "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", @@ -615,6 +698,7 @@ }, { "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", "SampleAfterValue": "2000003", @@ -622,6 +706,7 @@ }, { "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel? 64 and IA-32 Architectures Op= timization Reference Manual for more details about slow LEA instructions.", @@ -630,6 +715,7 @@ }, { "BriefDescription": "Resource-related stall cycles.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000003", @@ -637,6 +723,7 @@ }, { "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LB", "SampleAfterValue": "2000003", @@ -644,6 +731,7 @@ }, { "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LB_SB", "SampleAfterValue": "2000003", @@ -651,6 +739,7 @@ }, { "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MEM_RS", "SampleAfterValue": "2000003", @@ -658,6 +747,7 @@ }, { "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OOO_RSRC", "SampleAfterValue": "2000003", @@ -665,6 +755,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -672,6 +763,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -679,6 +771,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "SampleAfterValue": "2000003", @@ -686,6 +779,7 @@ }, { "BriefDescription": "Cycles with either free list is empty.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", "SampleAfterValue": "2000003", @@ -693,6 +787,7 @@ }, { "BriefDescription": "Resource stalls2 control structures full for = physical registers.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", "SampleAfterValue": "2000003", @@ -700,6 +795,7 @@ }, { "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.BOB_FULL", "SampleAfterValue": "2000003", @@ -707,6 +803,7 @@ }, { "BriefDescription": "Resource stalls out of order resources full.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.OOO_RSRC", "SampleAfterValue": "2000003", @@ -714,6 +811,7 @@ }, { "BriefDescription": "Count cases of saving new LBR.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "SampleAfterValue": "2000003", @@ -721,6 +819,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "SampleAfterValue": "2000003", @@ -728,6 +827,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -738,6 +838,7 @@ }, { "BriefDescription": "Uops dispatched from any thread.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_DISPATCHED.CORE", "SampleAfterValue": "2000003", @@ -745,6 +846,7 @@ }, { "BriefDescription": "Uops dispatched per thread.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_DISPATCHED.THREAD", "SampleAfterValue": "2000003", @@ -752,6 +854,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", @@ -760,6 +863,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -767,6 +871,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", @@ -775,6 +880,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -782,6 +888,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", @@ -790,6 +897,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -797,6 +905,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", @@ -805,6 +914,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -812,6 +922,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", @@ -820,6 +931,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -827,6 +939,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", @@ -835,6 +948,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -842,6 +956,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -850,6 +965,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -858,6 +974,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -866,6 +983,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -874,6 +992,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -882,6 +1001,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", @@ -891,6 +1011,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -900,6 +1021,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -909,6 +1031,7 @@ }, { "BriefDescription": "Actually retired uops.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -918,6 +1041,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -927,6 +1051,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -936,6 +1061,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -945,6 +1071,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "10", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/jaketown/uncore-cache.json index 63395e7ee0ce..8508becead5a 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-cache.json @@ -1,12 +1,14 @@ [ { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", "Unit": "CBOX" }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "1,2,3", "EventCode": "0x1f", "EventName": "UNC_C_COUNTER0_OCCUPANCY", "PerPkg": "1", @@ -14,6 +16,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_C_ISMQ_DRD_MISS_OCC", "PerPkg": "1", @@ -21,6 +24,7 @@ }, { "BriefDescription": "Cache Lookups; Data Read Request", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cache Lookups; RTID", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.NID", "PerPkg": "1", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Cache Lookups; External Snoop Request", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Cache Lookups; Write Requests", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", "PerPkg": "1", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.MISS", "PerPkg": "1", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in M state", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", "PerPkg": "1", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Lines Victimized; Victimized Lines that Match= NID", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.NID", "PerPkg": "1", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.S_STATE", "PerPkg": "1", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Cbo Misc; RFO HitS", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.RFO_HIT_S", "PerPkg": "1", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -120,6 +134,7 @@ }, { "BriefDescription": "Cbo Misc", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.STARTED", "PerPkg": "1", @@ -129,6 +144,7 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1", "EventCode": "0x39", "EventName": "UNC_C_MISC.WC_ALIASING", "PerPkg": "1", @@ -138,6 +154,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Even", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_EVEN", "PerPkg": "1", @@ -147,6 +164,7 @@ }, { "BriefDescription": "AD Ring In Use; Down and Odd", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.DOWN_ODD", "PerPkg": "1", @@ -156,6 +174,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Even", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_EVEN", "PerPkg": "1", @@ -165,6 +184,7 @@ }, { "BriefDescription": "AD Ring In Use; Up and Odd", + "Counter": "2,3", "EventCode": "0x1b", "EventName": "UNC_C_RING_AD_USED.UP_ODD", "PerPkg": "1", @@ -174,6 +194,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Even", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_EVEN", "PerPkg": "1", @@ -183,6 +204,7 @@ }, { "BriefDescription": "AK Ring In Use; Down and Odd", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.DOWN_ODD", "PerPkg": "1", @@ -192,6 +214,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Even", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_EVEN", "PerPkg": "1", @@ -201,6 +224,7 @@ }, { "BriefDescription": "AK Ring In Use; Up and Odd", + "Counter": "2,3", "EventCode": "0x1c", "EventName": "UNC_C_RING_AK_USED.UP_ODD", "PerPkg": "1", @@ -210,6 +234,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Even", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_EVEN", "PerPkg": "1", @@ -219,6 +244,7 @@ }, { "BriefDescription": "BL Ring in Use; Down and Odd", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.DOWN_ODD", "PerPkg": "1", @@ -228,6 +254,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Even", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_EVEN", "PerPkg": "1", @@ -237,6 +264,7 @@ }, { "BriefDescription": "BL Ring in Use; Up and Odd", + "Counter": "2,3", "EventCode": "0x1d", "EventName": "UNC_C_RING_BL_USED.UP_ODD", "PerPkg": "1", @@ -246,6 +274,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Acknowledgements to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.AK_CORE", "PerPkg": "1", @@ -254,6 +283,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Data Responses to core", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.BL_CORE", "PerPkg": "1", @@ -262,6 +292,7 @@ }, { "BriefDescription": "Number of LLC responses that bounced on the R= ing.; Snoops of processor's cache.", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_C_RING_BOUNCES.IV_CORE", "PerPkg": "1", @@ -270,6 +301,7 @@ }, { "BriefDescription": "BL Ring in Use; Any", + "Counter": "2,3", "EventCode": "0x1e", "EventName": "UNC_C_RING_IV_USED.ANY", "PerPkg": "1", @@ -278,6 +310,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AD_CACHE", "PerPkg": "1", @@ -285,6 +318,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.AK_CORE", "PerPkg": "1", @@ -292,6 +326,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.BL_CORE", "PerPkg": "1", @@ -299,6 +334,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_C_RING_SINK_STARVED.IV_CORE", "PerPkg": "1", @@ -306,6 +342,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_C_RING_SRC_THRTL", "PerPkg": "1", @@ -313,6 +350,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IRQ", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IPQ", "PerPkg": "1", @@ -322,6 +360,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; IPQ", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.IRQ", "PerPkg": "1", @@ -331,6 +370,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ", "PerPkg": "1", @@ -340,6 +380,7 @@ }, { "BriefDescription": "Ingress Arbiter Blocking Cycles; ISMQ_BID", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_C_RxR_EXT_STARVED.ISMQ_BIDS", "PerPkg": "1", @@ -349,6 +390,7 @@ }, { "BriefDescription": "Ingress Allocations; IPQ", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IPQ", "PerPkg": "1", @@ -358,6 +400,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ", "PerPkg": "1", @@ -367,6 +410,7 @@ }, { "BriefDescription": "Ingress Allocations; IRQ Rejected", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.IRQ_REJECTED", "PerPkg": "1", @@ -376,6 +420,7 @@ }, { "BriefDescription": "Ingress Allocations; VFIFO", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_C_RxR_INSERTS.VFIFO", "PerPkg": "1", @@ -385,6 +430,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IPQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IPQ", "PerPkg": "1", @@ -394,6 +440,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; IRQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.IRQ", "PerPkg": "1", @@ -403,6 +450,7 @@ }, { "BriefDescription": "Ingress Internal Starvation Cycles; ISMQ", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_C_RxR_INT_STARVED.ISMQ", "PerPkg": "1", @@ -412,6 +460,7 @@ }, { "BriefDescription": "Probe Queue Retries; Address Conflict", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -421,6 +470,7 @@ }, { "BriefDescription": "Probe Queue Retries; Any Reject", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.ANY", "PerPkg": "1", @@ -430,6 +480,7 @@ }, { "BriefDescription": "Probe Queue Retries; No Egress Credits", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.FULL", "PerPkg": "1", @@ -439,6 +490,7 @@ }, { "BriefDescription": "Probe Queue Retries; No QPI Credits", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_C_RxR_IPQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -448,6 +500,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Address Confli= ct", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ADDR_CONFLICT", "PerPkg": "1", @@ -456,6 +509,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; Any Reject", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.ANY", "PerPkg": "1", @@ -464,6 +518,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No Egress Cred= its", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.FULL", "PerPkg": "1", @@ -472,6 +527,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No QPI Credits= ", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -480,6 +536,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects; No RTIDs", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_C_RxR_IRQ_RETRY.RTID", "PerPkg": "1", @@ -488,6 +545,7 @@ }, { "BriefDescription": "ISMQ Retries; Any Reject", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.ANY", "PerPkg": "1", @@ -497,6 +555,7 @@ }, { "BriefDescription": "ISMQ Retries; No Egress Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.FULL", "PerPkg": "1", @@ -506,6 +565,7 @@ }, { "BriefDescription": "ISMQ Retries; No IIO Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.IIO_CREDITS", "PerPkg": "1", @@ -515,6 +575,7 @@ }, { "BriefDescription": "ISMQ Retries; No QPI Credits", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.QPI_CREDITS", "PerPkg": "1", @@ -524,6 +585,7 @@ }, { "BriefDescription": "ISMQ Retries; No RTIDs", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_C_RxR_ISMQ_RETRY.RTID", "PerPkg": "1", @@ -533,6 +595,7 @@ }, { "BriefDescription": "Ingress Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -542,6 +605,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -551,6 +615,7 @@ }, { "BriefDescription": "Ingress Occupancy; IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.IRQ_REJECTED", "PerPkg": "1", @@ -560,6 +625,7 @@ }, { "BriefDescription": "Ingress Occupancy; VFIFO", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_C_RxR_OCCUPANCY.VFIFO", "PerPkg": "1", @@ -569,6 +635,7 @@ }, { "BriefDescription": "TOR Inserts; Evictions", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICTION", "PerPkg": "1", @@ -578,6 +645,7 @@ }, { "BriefDescription": "TOR Inserts; Miss All", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_ALL", "PerPkg": "1", @@ -587,6 +655,7 @@ }, { "BriefDescription": "TOR Inserts; Miss Opcode Match", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS_OPCODE", "PerPkg": "1", @@ -596,6 +665,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_ALL", "PerPkg": "1", @@ -605,6 +675,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Evictions", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_EVICTION", "PerPkg": "1", @@ -614,6 +685,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Miss All", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_ALL", "PerPkg": "1", @@ -623,6 +695,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched Miss", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_MISS_OPCODE", "PerPkg": "1", @@ -632,6 +705,7 @@ }, { "BriefDescription": "TOR Inserts; NID and Opcode Matched", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_OPCODE", "PerPkg": "1", @@ -641,6 +715,7 @@ }, { "BriefDescription": "TOR Inserts; NID Matched Writebacks", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.NID_WB", "PerPkg": "1", @@ -650,6 +725,7 @@ }, { "BriefDescription": "TOR Inserts; Opcode Match", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.OPCODE", "PerPkg": "1", @@ -659,6 +735,7 @@ }, { "BriefDescription": "TOR Inserts; Writebacks", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WB", "PerPkg": "1", @@ -668,6 +745,7 @@ }, { "BriefDescription": "TOR Occupancy; Any", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.ALL", "PerPkg": "1", @@ -677,6 +755,7 @@ }, { "BriefDescription": "TOR Occupancy; Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICTION", "PerPkg": "1", @@ -686,6 +765,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_ALL", "PerPkg": "1", @@ -695,6 +775,7 @@ }, { "BriefDescription": "TOR Occupancy; Miss Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS_OPCODE", "PerPkg": "1", @@ -704,6 +785,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_ALL", "PerPkg": "1", @@ -713,6 +795,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_EVICTION", "PerPkg": "1", @@ -722,6 +805,7 @@ }, { "BriefDescription": "TOR Occupancy; NID Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_ALL", "PerPkg": "1", @@ -731,6 +815,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_MISS_OPCODE", "PerPkg": "1", @@ -740,6 +825,7 @@ }, { "BriefDescription": "TOR Occupancy; NID and Opcode Matched", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.NID_OPCODE", "PerPkg": "1", @@ -749,6 +835,7 @@ }, { "BriefDescription": "TOR Occupancy; Opcode Match", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.OPCODE", "PerPkg": "1", @@ -757,6 +844,7 @@ "Unit": "CBOX" }, { + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_C_TxR_ADS_USED", "PerPkg": "1", @@ -764,6 +852,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CACHE", "PerPkg": "1", @@ -773,6 +862,7 @@ }, { "BriefDescription": "Egress Allocations; AD - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AD_CORE", "PerPkg": "1", @@ -782,6 +872,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CACHE", "PerPkg": "1", @@ -791,6 +882,7 @@ }, { "BriefDescription": "Egress Allocations; AK - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.AK_CORE", "PerPkg": "1", @@ -800,6 +892,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Cacheno", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CACHE", "PerPkg": "1", @@ -809,6 +902,7 @@ }, { "BriefDescription": "Egress Allocations; BL - Corebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.BL_CORE", "PerPkg": "1", @@ -818,6 +912,7 @@ }, { "BriefDescription": "Egress Allocations; IV - Cachebo", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_C_TxR_INSERTS.IV_CACHE", "PerPkg": "1", @@ -827,6 +922,7 @@ }, { "BriefDescription": "Injection Starvation; Onto AK Ring", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.AK", "PerPkg": "1", @@ -836,6 +932,7 @@ }, { "BriefDescription": "Injection Starvation; Onto BL Ring", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_C_TxR_STARVED.BL", "PerPkg": "1", @@ -845,6 +942,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.NOT_TAKEN", "PerPkg": "1", @@ -854,6 +952,7 @@ }, { "BriefDescription": "HA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_BYPASS_IMC.TAKEN", "PerPkg": "1", @@ -863,6 +962,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_H_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the HA. This = will be slightly different than the count in the Ubox because of enable/fre= eze delays. The HA is on the other side of the die from the fixed Ubox ucl= k counter, so the drift could be somewhat larger than in units that are clo= ser like the QPI Agent.", @@ -870,6 +970,7 @@ }, { "BriefDescription": "Conflict Checks; Conflict Detected", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.CONFLICT", "PerPkg": "1", @@ -878,6 +979,7 @@ }, { "BriefDescription": "Conflict Checks; No Conflict", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_H_CONFLICT_CYCLES.NO_CONFLICT", "PerPkg": "1", @@ -886,6 +988,7 @@ }, { "BriefDescription": "Direct2Core Messages Sent", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_H_DIRECT2CORE_COUNT", "PerPkg": "1", @@ -894,6 +997,7 @@ }, { "BriefDescription": "Cycles when Direct2Core was Disabled", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_H_DIRECT2CORE_CYCLES_DISABLED", "PerPkg": "1", @@ -902,6 +1006,7 @@ }, { "BriefDescription": "Number of Reads that had Direct2Core Overridd= en", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -910,6 +1015,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.NO_SNP", "PerPkg": "1", @@ -919,6 +1025,7 @@ }, { "BriefDescription": "Directory Lookups; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_H_DIRECTORY_LOOKUP.SNP", "PerPkg": "1", @@ -928,6 +1035,7 @@ }, { "BriefDescription": "Directory Updates; Any Directory Update", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -937,6 +1045,7 @@ }, { "BriefDescription": "Directory Updates; Directory Clear", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.CLEAR", "PerPkg": "1", @@ -946,6 +1055,7 @@ }, { "BriefDescription": "Directory Updates; Directory Set", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_H_DIRECTORY_UPDATE.SET", "PerPkg": "1", @@ -955,6 +1065,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI0", "PerPkg": "1", @@ -964,6 +1075,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; AD to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.AD_QPI1", "PerPkg": "1", @@ -973,6 +1085,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI0", "PerPkg": "1", @@ -982,6 +1095,7 @@ }, { "BriefDescription": "Cycles without QPI Ingress Credits; BL to QPI= Link 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_IGR_NO_CREDIT_CYCLES.BL_QPI1", "PerPkg": "1", @@ -991,6 +1105,7 @@ }, { "BriefDescription": "Retry Events", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_H_IMC_RETRY", "PerPkg": "1", @@ -998,6 +1113,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; All Writes= ", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.ALL", "PerPkg": "1", @@ -1007,6 +1123,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Full Line = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.FULL", "PerPkg": "1", @@ -1016,6 +1133,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Full= Line", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.FULL_ISOCH", "PerPkg": "1", @@ -1025,6 +1143,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; Partial No= n-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -1034,6 +1153,7 @@ }, { "BriefDescription": "HA to iMC Full Line Writes Issued; ISOCH Part= ial", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_H_IMC_WRITES.PARTIAL_ISOCH", "PerPkg": "1", @@ -1043,6 +1163,7 @@ }, { "BriefDescription": "Read and Write Requests; Reads", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.READS", "PerPkg": "1", @@ -1052,6 +1173,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_H_REQUESTS.WRITES", "PerPkg": "1", @@ -1061,6 +1183,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -1070,6 +1193,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -1079,6 +1203,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -1088,6 +1213,7 @@ }, { "BriefDescription": "HA AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_H_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -1097,6 +1223,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -1106,6 +1233,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -1115,6 +1243,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -1124,6 +1253,7 @@ }, { "BriefDescription": "HA AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x3f", "EventName": "UNC_H_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -1133,6 +1263,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -1142,6 +1273,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -1151,6 +1283,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -1160,6 +1293,7 @@ }, { "BriefDescription": "HA BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_H_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -1169,6 +1303,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -1178,6 +1313,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -1187,6 +1323,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -1196,6 +1333,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Regular; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_H_RPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -1205,6 +1343,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -1214,6 +1353,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -1223,6 +1363,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -1232,6 +1373,7 @@ }, { "BriefDescription": "iMC RPQ Credits Empty - Special; Channel 3", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_H_RPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", @@ -1241,6 +1383,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 0", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION0", "PerPkg": "1", @@ -1250,6 +1393,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 1", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION1", "PerPkg": "1", @@ -1259,6 +1403,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 2", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION2", "PerPkg": "1", @@ -1268,6 +1413,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 3", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION3", "PerPkg": "1", @@ -1277,6 +1423,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 4", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION4", "PerPkg": "1", @@ -1286,6 +1433,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 5", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION5", "PerPkg": "1", @@ -1295,6 +1443,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 6", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION6", "PerPkg": "1", @@ -1304,6 +1453,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 0; TAD Re= gion 7", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_H_TAD_REQUESTS_G0.REGION7", "PerPkg": "1", @@ -1313,6 +1463,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 10", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION10", "PerPkg": "1", @@ -1322,6 +1473,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 11", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION11", "PerPkg": "1", @@ -1331,6 +1483,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 8", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION8", "PerPkg": "1", @@ -1340,6 +1493,7 @@ }, { "BriefDescription": "HA Requests to a TAD Region - Group 1; TAD Re= gion 9", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_H_TAD_REQUESTS_G1.REGION9", "PerPkg": "1", @@ -1349,6 +1503,7 @@ }, { "BriefDescription": "Tracker Allocations; All Requests", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_H_TRACKER_INSERTS.ALL", "PerPkg": "1", @@ -1358,6 +1513,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Non-data Resp= onses", + "Counter": "0,1,2,3", "EventCode": "0xf", "EventName": "UNC_H_TxR_AD.NDR", "PerPkg": "1", @@ -1367,6 +1523,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions; Snoops", + "Counter": "0,1,2,3", "EventCode": "0xf", "EventName": "UNC_H_TxR_AD.SNP", "PerPkg": "1", @@ -1376,6 +1533,7 @@ }, { "BriefDescription": "AD Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.ALL", "PerPkg": "1", @@ -1384,6 +1542,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -1392,6 +1551,7 @@ }, { "BriefDescription": "AD Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_H_TxR_AD_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -1400,6 +1560,7 @@ }, { "BriefDescription": "AD Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.ALL", "PerPkg": "1", @@ -1408,6 +1569,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -1416,6 +1578,7 @@ }, { "BriefDescription": "AD Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_H_TxR_AD_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -1424,6 +1587,7 @@ }, { "BriefDescription": "AD Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.ALL", "PerPkg": "1", @@ -1432,6 +1596,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED0", "PerPkg": "1", @@ -1440,6 +1605,7 @@ }, { "BriefDescription": "AD Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_H_TxR_AD_INSERTS.SCHED1", "PerPkg": "1", @@ -1448,6 +1614,7 @@ }, { "BriefDescription": "AD Egress Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_H_TxR_AD_OCCUPANCY.ALL", "PerPkg": "1", @@ -1456,6 +1623,7 @@ }, { "BriefDescription": "AD Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -1464,6 +1632,7 @@ }, { "BriefDescription": "AD Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_H_TxR_AD_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -1472,6 +1641,7 @@ }, { "BriefDescription": "AK Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.ALL", "PerPkg": "1", @@ -1480,6 +1650,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -1488,6 +1659,7 @@ }, { "BriefDescription": "AK Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_H_TxR_AK_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -1496,6 +1668,7 @@ }, { "BriefDescription": "AK Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.ALL", "PerPkg": "1", @@ -1504,6 +1677,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -1512,6 +1686,7 @@ }, { "BriefDescription": "AK Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_H_TxR_AK_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -1520,6 +1695,7 @@ }, { "BriefDescription": "AK Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.ALL", "PerPkg": "1", @@ -1528,6 +1704,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED0", "PerPkg": "1", @@ -1536,6 +1713,7 @@ }, { "BriefDescription": "AK Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_H_TxR_AK_INSERTS.SCHED1", "PerPkg": "1", @@ -1544,6 +1722,7 @@ }, { "BriefDescription": "Outbound NDR Ring Transactions", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_H_TxR_AK_NDR", "PerPkg": "1", @@ -1552,6 +1731,7 @@ }, { "BriefDescription": "AK Egress Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_H_TxR_AK_OCCUPANCY.ALL", "PerPkg": "1", @@ -1560,6 +1740,7 @@ }, { "BriefDescription": "AK Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -1568,6 +1749,7 @@ }, { "BriefDescription": "AK Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_H_TxR_AK_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -1576,6 +1758,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CACHE", "PerPkg": "1", @@ -1585,6 +1768,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_CORE", "PerPkg": "1", @@ -1594,6 +1778,7 @@ }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_H_TxR_BL.DRS_QPI", "PerPkg": "1", @@ -1603,6 +1788,7 @@ }, { "BriefDescription": "BL Egress Full; All", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.ALL", "PerPkg": "1", @@ -1611,6 +1797,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED0", "PerPkg": "1", @@ -1619,6 +1806,7 @@ }, { "BriefDescription": "BL Egress Full; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_H_TxR_BL_CYCLES_FULL.SCHED1", "PerPkg": "1", @@ -1627,6 +1815,7 @@ }, { "BriefDescription": "BL Egress Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.ALL", "PerPkg": "1", @@ -1635,6 +1824,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED0", "PerPkg": "1", @@ -1643,6 +1833,7 @@ }, { "BriefDescription": "BL Egress Not Empty; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TxR_BL_CYCLES_NE.SCHED1", "PerPkg": "1", @@ -1651,6 +1842,7 @@ }, { "BriefDescription": "BL Egress Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.ALL", "PerPkg": "1", @@ -1659,6 +1851,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED0", "PerPkg": "1", @@ -1667,6 +1860,7 @@ }, { "BriefDescription": "BL Egress Allocations; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_H_TxR_BL_INSERTS.SCHED1", "PerPkg": "1", @@ -1675,6 +1869,7 @@ }, { "BriefDescription": "BL Egress Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.ALL", "PerPkg": "1", @@ -1683,6 +1878,7 @@ }, { "BriefDescription": "BL Egress Occupancy; Scheduler 0", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED0", "PerPkg": "1", @@ -1691,6 +1887,7 @@ }, { "BriefDescription": "BL Egress Occupancy; Scheduler 1", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_TxR_BL_OCCUPANCY.SCHED1", "PerPkg": "1", @@ -1699,6 +1896,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN0", "PerPkg": "1", @@ -1708,6 +1906,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN1", "PerPkg": "1", @@ -1717,6 +1916,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN2", "PerPkg": "1", @@ -1726,6 +1926,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Regular; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_WPQ_CYCLES_NO_REG_CREDITS.CHN3", "PerPkg": "1", @@ -1735,6 +1936,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN0", "PerPkg": "1", @@ -1744,6 +1946,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN1", "PerPkg": "1", @@ -1753,6 +1956,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN2", "PerPkg": "1", @@ -1762,6 +1966,7 @@ }, { "BriefDescription": "HA iMC CHN0 WPQ Credits Empty - Special; Chan= nel 3", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_WPQ_CYCLES_NO_SPEC_CREDITS.CHN3", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.js= on b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json index 0fc907e5cf3c..36b1946f06f2 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Address Match (Conflict) Count; Conflict Merg= es", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_ADDRESS_MATCH.MERGE_COUNT", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Address Match (Conflict) Count; Conflict Stal= ls", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_ADDRESS_MATCH.STALL_COUNT", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Write Ack Pending Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.ANY", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Write Ack Pending Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_CACHE_ACK_PENDING_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Outstanding Write Ownership Occupancy; Any So= urce", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.ANY", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Outstanding Write Ownership Occupancy; Select= Source", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_CACHE_OWN_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Outstanding Read Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_CACHE_READ_OCCUPANCY.ANY", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Outstanding Read Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_CACHE_READ_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", "PerPkg": "1", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Outstanding Write Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.ANY", "PerPkg": "1", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Outstanding Write Occupancy; Select Source", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_CACHE_WRITE_OCCUPANCY.SOURCE", "PerPkg": "1", @@ -109,12 +121,14 @@ }, { "BriefDescription": "Clocks in the IRP", + "Counter": "0,1", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Number of clocks in the IRP.", "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0xB", "EventName": "UNC_I_RxR_AK_CYCLES_FULL", "PerPkg": "1", @@ -123,6 +137,7 @@ }, { "BriefDescription": "AK Ingress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_RxR_AK_INSERTS", "PerPkg": "1", @@ -130,6 +145,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0xC", "EventName": "UNC_I_RxR_AK_OCCUPANCY", "PerPkg": "1", @@ -137,6 +153,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_RxR_BL_DRS_CYCLES_FULL", "PerPkg": "1", @@ -145,6 +162,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - DRS", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_RxR_BL_DRS_INSERTS", "PerPkg": "1", @@ -152,6 +170,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_RxR_BL_DRS_OCCUPANCY", "PerPkg": "1", @@ -159,6 +178,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_RxR_BL_NCB_CYCLES_FULL", "PerPkg": "1", @@ -167,6 +187,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCB", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_RxR_BL_NCB_INSERTS", "PerPkg": "1", @@ -174,6 +195,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_RxR_BL_NCB_OCCUPANCY", "PerPkg": "1", @@ -181,6 +203,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_RxR_BL_NCS_CYCLES_FULL", "PerPkg": "1", @@ -189,6 +212,7 @@ }, { "BriefDescription": "BL Ingress Occupancy - NCS", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_RxR_BL_NCS_INSERTS", "PerPkg": "1", @@ -196,6 +220,7 @@ "Unit": "IRP" }, { + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_RxR_BL_NCS_OCCUPANCY", "PerPkg": "1", @@ -204,6 +229,7 @@ }, { "BriefDescription": "Tickle Count; Ownership Lost", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TICKLES.LOST_OWNERSHIP", "PerPkg": "1", @@ -213,6 +239,7 @@ }, { "BriefDescription": "Tickle Count; Data Returned", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_TICKLES.TOP_OF_QUEUE", "PerPkg": "1", @@ -222,6 +249,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.PD_PREFETCHES", "PerPkg": "1", @@ -231,6 +259,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.READS", "PerPkg": "1", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -249,6 +279,7 @@ }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_TxR_AD_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -257,6 +288,7 @@ }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_TxR_BL_STALL_CREDIT_CYCLES", "PerPkg": "1", @@ -265,6 +297,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxR_DATA_INSERTS_NCB", "PerPkg": "1", @@ -273,6 +306,7 @@ }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_TxR_DATA_INSERTS_NCS", "PerPkg": "1", @@ -281,6 +315,7 @@ }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxR_REQUEST_OCCUPANCY", "PerPkg": "1", @@ -289,6 +324,7 @@ }, { "BriefDescription": "Write Ordering Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_WRITE_ORDERING_STALL_CYCLES", "PerPkg": "1", @@ -297,6 +333,7 @@ }, { "BriefDescription": "Number of qfclks", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_Q_CLOCKTICKS", "PerPkg": "1", @@ -305,6 +342,7 @@ }, { "BriefDescription": "Count of CTO Events", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_Q_CTO_COUNT", "PerPkg": "1", @@ -313,6 +351,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s Credits", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS", "PerPkg": "1", @@ -322,6 +361,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - Egres= s and RBT", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_CREDITS_RBT", "PerPkg": "1", @@ -331,6 +371,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Failure - RBT N= ot Set", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.FAILURE_RBT", "PerPkg": "1", @@ -340,6 +381,7 @@ }, { "BriefDescription": "Direct 2 Core Spawning; Spawn Success", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_Q_DIRECT2CORE.SUCCESS", "PerPkg": "1", @@ -349,6 +391,7 @@ }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_Q_L1_POWER_CYCLES", "PerPkg": "1", @@ -357,6 +400,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_Q_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -365,6 +409,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xf", "EventName": "UNC_Q_RxL0_POWER_CYCLES", "PerPkg": "1", @@ -373,6 +418,7 @@ }, { "BriefDescription": "Rx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_BYPASSED", "PerPkg": "1", @@ -381,6 +427,7 @@ }, { "BriefDescription": "CRC Errors Detected; LinkInit", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.LINK_INIT", "PerPkg": "1", @@ -390,6 +437,7 @@ }, { "BriefDescription": "CRC Errors Detected; Normal Operations", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_CRC_ERRORS.NORMAL_OP", "PerPkg": "1", @@ -399,6 +447,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; DRS", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.DRS", "PerPkg": "1", @@ -408,6 +457,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; HOM", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.HOM", "PerPkg": "1", @@ -417,6 +467,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCB", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCB", "PerPkg": "1", @@ -426,6 +477,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NCS", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NCS", "PerPkg": "1", @@ -435,6 +487,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; NDR", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.NDR", "PerPkg": "1", @@ -444,6 +497,7 @@ }, { "BriefDescription": "VN0 Credit Consumed; SNP", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VN0.SNP", "PerPkg": "1", @@ -453,6 +507,7 @@ }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_Q_RxL_CREDITS_CONSUMED_VNA", "PerPkg": "1", @@ -461,6 +516,7 @@ }, { "BriefDescription": "RxQ Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_Q_RxL_CYCLES_NE", "PerPkg": "1", @@ -469,6 +525,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.DATA", "PerPkg": "1", @@ -478,6 +535,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Idle and Null Flits= ", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.IDLE", "PerPkg": "1", @@ -487,6 +545,7 @@ }, { "BriefDescription": "Flits Received - Group 0; Non-Data protocol T= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_RxL_FLITS_G0.NON_DATA", "PerPkg": "1", @@ -496,6 +555,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Flits (both Hea= der and Data)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS", "PerPkg": "1", @@ -505,6 +565,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_DATA", "PerPkg": "1", @@ -514,6 +575,7 @@ }, { "BriefDescription": "Flits Received - Group 1; DRS Header Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", @@ -523,6 +585,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM", "PerPkg": "1", @@ -532,6 +595,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Non-Request Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", @@ -541,6 +605,7 @@ }, { "BriefDescription": "Flits Received - Group 1; HOM Request Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.HOM_REQ", "PerPkg": "1", @@ -550,6 +615,7 @@ }, { "BriefDescription": "Flits Received - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_RxL_FLITS_G1.SNP", "PerPkg": "1", @@ -559,6 +625,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent Rx Fli= ts", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB", "PerPkg": "1", @@ -568,6 +635,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent data R= x Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -577,6 +645,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent non-da= ta Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -586,6 +655,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Coherent standa= rd Rx Flits", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NCS", "PerPkg": "1", @@ -595,6 +665,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -604,6 +675,7 @@ }, { "BriefDescription": "Flits Received - Group 2; Non-Data Response R= x Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_Q_RxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -613,6 +685,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_Q_RxL_INSERTS", "PerPkg": "1", @@ -621,6 +694,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - DRS", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_Q_RxL_INSERTS_DRS", "PerPkg": "1", @@ -629,6 +703,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - HOM", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_Q_RxL_INSERTS_HOM", "PerPkg": "1", @@ -637,6 +712,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCB", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_Q_RxL_INSERTS_NCB", "PerPkg": "1", @@ -645,6 +721,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NCS", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_Q_RxL_INSERTS_NCS", "PerPkg": "1", @@ -653,6 +730,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - NDR", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_Q_RxL_INSERTS_NDR", "PerPkg": "1", @@ -661,6 +739,7 @@ }, { "BriefDescription": "Rx Flit Buffer Allocations - SNP", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_Q_RxL_INSERTS_SNP", "PerPkg": "1", @@ -669,6 +748,7 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_Q_RxL_OCCUPANCY", "PerPkg": "1", @@ -677,6 +757,7 @@ }, { "BriefDescription": "RxQ Occupancy - DRS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_Q_RxL_OCCUPANCY_DRS", "PerPkg": "1", @@ -685,6 +766,7 @@ }, { "BriefDescription": "RxQ Occupancy - HOM", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_Q_RxL_OCCUPANCY_HOM", "PerPkg": "1", @@ -693,6 +775,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_Q_RxL_OCCUPANCY_NCB", "PerPkg": "1", @@ -701,6 +784,7 @@ }, { "BriefDescription": "RxQ Occupancy - NCS", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_Q_RxL_OCCUPANCY_NCS", "PerPkg": "1", @@ -709,6 +793,7 @@ }, { "BriefDescription": "RxQ Occupancy - NDR", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_Q_RxL_OCCUPANCY_NDR", "PerPkg": "1", @@ -717,6 +802,7 @@ }, { "BriefDescription": "RxQ Occupancy - SNP", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_Q_RxL_OCCUPANCY_SNP", "PerPkg": "1", @@ -725,6 +811,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - HOM", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_DRS", "PerPkg": "1", @@ -734,6 +821,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - DRS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_HOM", "PerPkg": "1", @@ -743,6 +831,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - SNP", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_NCB", "PerPkg": "1", @@ -752,6 +841,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NDR", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_NCS", "PerPkg": "1", @@ -761,6 +851,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCS", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_NDR", "PerPkg": "1", @@ -770,6 +861,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; BGF Stall - NCB", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.BGF_SNP", "PerPkg": "1", @@ -779,6 +871,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; Egress Credits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.EGRESS_CREDITS", "PerPkg": "1", @@ -788,6 +881,7 @@ }, { "BriefDescription": "Stalls Sending to R3QPI; GV", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_Q_RxL_STALLS.GV", "PerPkg": "1", @@ -797,6 +891,7 @@ }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_Q_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -805,6 +900,7 @@ }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_Q_TxL0_POWER_CYCLES", "PerPkg": "1", @@ -813,6 +909,7 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_Q_TxL_BYPASSED", "PerPkg": "1", @@ -821,6 +918,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is al= most full", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.ALMOST_FULL", "PerPkg": "1", @@ -830,6 +928,7 @@ }, { "BriefDescription": "Cycles Stalled with no LLR Credits; LLR is fu= ll", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_Q_TxL_CRC_NO_CREDITS.FULL", "PerPkg": "1", @@ -839,6 +938,7 @@ }, { "BriefDescription": "Tx Flit Buffer Cycles not Empty", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_Q_TxL_CYCLES_NE", "PerPkg": "1", @@ -847,6 +947,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Data Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 wi= th header information and 8 with 64 bits of actual 'data' and an additional= 16 bits of other information. To calculate 'data' bandwidth, one should t= herefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", @@ -855,6 +956,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Idle and Null Fl= its", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.IDLE", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 wi= th header information and 8 with 64 bits of actual 'data' and an additional= 16 bits of other information. To calculate 'data' bandwidth, one should t= herefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", @@ -863,6 +965,7 @@ }, { "BriefDescription": "Flits Transferred - Group 0; Non-Data protoco= l Tx Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G0.NON_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. It includes filters for Idle, protocol, and Data Flits. E= ach 'flit' is made up of 80 bits of information (in addition to some ECC da= ta). In full-width (L0) mode, flits are made up of four 'fits', each of wh= ich contains 20 bits of data (along with some additional ECC data). In ha= lf-width (L0p) mode, the fits are only 10 bits, and therefore it takes twic= e as many fits to transmit a flit. When one talks about QPI 'speed' (for e= xample, 8.0 GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0,= the system will transfer 1 'flit' at the rate of 1/4th the QPI speed. One= can calculate the bandwidth of the link by taking: flits*80b/time. Note t= hat this is not the same as 'data' bandwidth. For example, when we are tra= nsferring a 64B cacheline across QPI, we will break it into 9 flits -- 1 wi= th header information and 8 with 64 bits of actual 'data' and an additional= 16 bits of other information. To calculate 'data' bandwidth, one should t= herefore do: data flits * 8B / time (for L0) or 4B instead of 8B for L0p.", @@ -871,6 +974,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Flits (both = Header and Data)", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -879,6 +983,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Data Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_DATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -887,6 +992,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; DRS Header Flits= ", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.DRS_NONDATA", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -895,6 +1001,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -903,6 +1010,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Non-Request = Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_NONREQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -911,6 +1019,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; HOM Request Flit= s", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.HOM_REQ", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -919,6 +1028,7 @@ }, { "BriefDescription": "Flits Transferred - Group 1; SNP Flits", + "Counter": "0,1,2,3", "EventName": "UNC_Q_TxL_FLITS_G1.SNP", "PerPkg": "1", "PublicDescription": "Counts the number of flits transmitted acros= s the QPI Link. This is one of three 'groups' that allow us to track flits= . It includes filters for SNP, HOM, and DRS message classes. Each 'flit' = is made up of 80 bits of information (in addition to some ECC data). In fu= ll-width (L0) mode, flits are made up of four 'fits', each of which contain= s 20 bits of data (along with some additional ECC data). In half-width (L= 0p) mode, the fits are only 10 bits, and therefore it takes twice as many f= its to transmit a flit. When one talks about QPI 'speed' (for example, 8.0= GT/s), the 'transfers' here refer to 'fits'. Therefore, in L0, the system= will transfer 1 'flit' at the rate of 1/4th the QPI speed. One can calcul= ate the bandwidth of the link by taking: flits*80b/time. Note that this is= not the same as 'data' bandwidth. For example, when we are transferring a= 64B cacheline across QPI, we will break it into 9 flits -- 1 with header i= nformation and 8 with 64 bits of actual 'data' and an additional 16 bits of= other information. To calculate 'data' bandwidth, one should therefore do= : data flits * 8B / time.", @@ -927,6 +1037,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent Byp= ass Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB", "PerPkg": "1", @@ -936,6 +1047,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent dat= a Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_DATA", "PerPkg": "1", @@ -945,6 +1057,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent non= -data Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCB_NONDATA", "PerPkg": "1", @@ -954,6 +1067,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Coherent sta= ndard Tx Flits", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NCS", "PerPkg": "1", @@ -963,6 +1077,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AD", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AD", "PerPkg": "1", @@ -972,6 +1087,7 @@ }, { "BriefDescription": "Flits Transferred - Group 2; Non-Data Respons= e Tx Flits - AK", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_Q_TxL_FLITS_G2.NDR_AK", "PerPkg": "1", @@ -981,6 +1097,7 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_Q_TxL_INSERTS", "PerPkg": "1", @@ -989,6 +1106,7 @@ }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_Q_TxL_OCCUPANCY", "PerPkg": "1", @@ -997,6 +1115,7 @@ }, { "BriefDescription": "VNA Credits Returned", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_Q_VNA_CREDIT_RETURNS", "PerPkg": "1", @@ -1005,6 +1124,7 @@ }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_Q_VNA_CREDIT_RETURN_OCCUPANCY", "PerPkg": "1", @@ -1013,6 +1133,7 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_R3_CLOCKTICKS", "PerPkg": "1", @@ -1021,6 +1142,7 @@ }, { "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -1030,6 +1152,7 @@ }, { "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -1039,6 +1162,7 @@ }, { "BriefDescription": "to IIO BL Credit Acquired", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_R3_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -1048,6 +1172,7 @@ }, { "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -1057,6 +1182,7 @@ }, { "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -1066,6 +1192,7 @@ }, { "BriefDescription": "to IIO BL Credit Rejected", + "Counter": "0,1", "EventCode": "0x21", "EventName": "UNC_R3_IIO_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -1075,6 +1202,7 @@ }, { "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -1084,6 +1212,7 @@ }, { "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -1093,6 +1222,7 @@ }, { "BriefDescription": "to IIO BL Credit In Use", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_R3_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -1102,6 +1232,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -1111,6 +1242,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -1120,6 +1252,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -1129,6 +1262,7 @@ }, { "BriefDescription": "R3 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x7", "EventName": "UNC_R3_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -1138,6 +1272,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -1147,6 +1282,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -1156,6 +1292,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -1165,6 +1302,7 @@ }, { "BriefDescription": "R3 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x8", "EventName": "UNC_R3_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -1174,6 +1312,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -1183,6 +1322,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -1192,6 +1332,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -1201,6 +1342,7 @@ }, { "BriefDescription": "R3 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2", "EventCode": "0x9", "EventName": "UNC_R3_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -1210,6 +1352,7 @@ }, { "BriefDescription": "R3 IV Ring in Use; Any", + "Counter": "0,1,2", "EventCode": "0xa", "EventName": "UNC_R3_RING_IV_USED.ANY", "PerPkg": "1", @@ -1219,6 +1362,7 @@ }, { "BriefDescription": "Ingress Bypassed", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_R3_RxR_BYPASSED.AD", "PerPkg": "1", @@ -1228,6 +1372,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; DRS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.DRS", "PerPkg": "1", @@ -1237,6 +1382,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; HOM", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.HOM", "PerPkg": "1", @@ -1246,6 +1392,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -1255,6 +1402,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -1264,6 +1412,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NDR", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.NDR", "PerPkg": "1", @@ -1273,6 +1422,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; SNP", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R3_RxR_CYCLES_NE.SNP", "PerPkg": "1", @@ -1282,6 +1432,7 @@ }, { "BriefDescription": "Ingress Allocations; DRS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.DRS", "PerPkg": "1", @@ -1291,6 +1442,7 @@ }, { "BriefDescription": "Ingress Allocations; HOM", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.HOM", "PerPkg": "1", @@ -1300,6 +1452,7 @@ }, { "BriefDescription": "Ingress Allocations; NCB", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCB", "PerPkg": "1", @@ -1309,6 +1462,7 @@ }, { "BriefDescription": "Ingress Allocations; NCS", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NCS", "PerPkg": "1", @@ -1318,6 +1472,7 @@ }, { "BriefDescription": "Ingress Allocations; NDR", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.NDR", "PerPkg": "1", @@ -1327,6 +1482,7 @@ }, { "BriefDescription": "Ingress Allocations; SNP", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_R3_RxR_INSERTS.SNP", "PerPkg": "1", @@ -1336,6 +1492,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; DRS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.DRS", "PerPkg": "1", @@ -1345,6 +1502,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; HOM", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.HOM", "PerPkg": "1", @@ -1354,6 +1512,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NCB", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NCB", "PerPkg": "1", @@ -1363,6 +1522,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NCS", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NCS", "PerPkg": "1", @@ -1372,6 +1532,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; NDR", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.NDR", "PerPkg": "1", @@ -1381,6 +1542,7 @@ }, { "BriefDescription": "Ingress Occupancy Accumulator; SNP", + "Counter": "0", "EventCode": "0x13", "EventName": "UNC_R3_RxR_OCCUPANCY.SNP", "PerPkg": "1", @@ -1390,6 +1552,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; DRS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -1399,6 +1562,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; HOM Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -1408,6 +1572,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCB Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -1417,6 +1582,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NCS Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -1426,6 +1592,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; NDR Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -1435,6 +1602,7 @@ }, { "BriefDescription": "VN0 Credit Acquisition Failed on DRS; SNP Mes= sage Class", + "Counter": "0,1", "EventCode": "0x37", "EventName": "UNC_R3_VN0_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -1444,6 +1612,7 @@ }, { "BriefDescription": "VN0 Credit Used; DRS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.DRS", "PerPkg": "1", @@ -1453,6 +1622,7 @@ }, { "BriefDescription": "VN0 Credit Used; HOM Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.HOM", "PerPkg": "1", @@ -1462,6 +1632,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCB Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCB", "PerPkg": "1", @@ -1471,6 +1642,7 @@ }, { "BriefDescription": "VN0 Credit Used; NCS Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NCS", "PerPkg": "1", @@ -1480,6 +1652,7 @@ }, { "BriefDescription": "VN0 Credit Used; NDR Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.NDR", "PerPkg": "1", @@ -1489,6 +1662,7 @@ }, { "BriefDescription": "VN0 Credit Used; SNP Message Class", + "Counter": "0,1", "EventCode": "0x36", "EventName": "UNC_R3_VN0_CREDITS_USED.SNP", "PerPkg": "1", @@ -1498,6 +1672,7 @@ }, { "BriefDescription": "VNA credit Acquisitions", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R3_VNA_CREDITS_ACQUIRED", "PerPkg": "1", @@ -1506,6 +1681,7 @@ }, { "BriefDescription": "VNA Credit Reject; DRS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -1515,6 +1691,7 @@ }, { "BriefDescription": "VNA Credit Reject; HOM Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.HOM", "PerPkg": "1", @@ -1524,6 +1701,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCB Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -1533,6 +1711,7 @@ }, { "BriefDescription": "VNA Credit Reject; NCS Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -1542,6 +1721,7 @@ }, { "BriefDescription": "VNA Credit Reject; NDR Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.NDR", "PerPkg": "1", @@ -1551,6 +1731,7 @@ }, { "BriefDescription": "VNA Credit Reject; SNP Message Class", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R3_VNA_CREDITS_REJECT.SNP", "PerPkg": "1", @@ -1560,6 +1741,7 @@ }, { "BriefDescription": "Cycles with no VNA credits available", + "Counter": "0,1", "EventCode": "0x31", "EventName": "UNC_R3_VNA_CREDIT_CYCLES_OUT", "PerPkg": "1", @@ -1568,6 +1750,7 @@ }, { "BriefDescription": "Cycles with 1 or more VNA credits in use", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R3_VNA_CREDIT_CYCLES_USED", "PerPkg": "1", @@ -1575,12 +1758,14 @@ "Unit": "R3QPI" }, { + "Counter": "0,1", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", "Unit": "UBOX" }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", "PerPkg": "1", @@ -1590,6 +1775,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", "PerPkg": "1", @@ -1599,6 +1785,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", "PerPkg": "1", @@ -1608,6 +1795,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", "PerPkg": "1", @@ -1617,6 +1805,7 @@ }, { "BriefDescription": "VLW Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", "PerPkg": "1", @@ -1626,6 +1815,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.DISABLE", "PerPkg": "1", @@ -1635,6 +1825,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.ENABLE", "PerPkg": "1", @@ -1644,6 +1835,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_DISABLE", "PerPkg": "1", @@ -1653,6 +1845,7 @@ }, { "BriefDescription": "Filter Match", + "Counter": "0,1", "EventCode": "0x41", "EventName": "UNC_U_FILTER_MATCH.U2C_ENABLE", "PerPkg": "1", @@ -1662,6 +1855,7 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", "PerPkg": "1", @@ -1670,6 +1864,7 @@ }, { "BriefDescription": "MsgCh Requests by Size; 4B Requests", + "Counter": "0,1", "EventCode": "0x47", "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.4B", "PerPkg": "1", @@ -1679,6 +1874,7 @@ }, { "BriefDescription": "MsgCh Requests by Size; 8B Requests", + "Counter": "0,1", "EventCode": "0x47", "EventName": "UNC_U_MSG_CHNL_SIZE_COUNT.8B", "PerPkg": "1", @@ -1688,6 +1884,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; ACK to Deassert", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ACK_TO_DEASSERT", "PerPkg": "1", @@ -1697,6 +1894,7 @@ }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", "PerPkg": "1", @@ -1706,6 +1904,7 @@ }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS.COUNT", "PerPkg": "1", @@ -1714,6 +1913,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Correctable Machine Check= ", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.CMC", "PerPkg": "1", @@ -1723,6 +1923,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Livelock", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LIVELOCK", "PerPkg": "1", @@ -1732,6 +1933,7 @@ }, { "BriefDescription": "Monitor Sent to T0; LTError", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.LTERROR", "PerPkg": "1", @@ -1741,6 +1943,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T0", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T0", "PerPkg": "1", @@ -1750,6 +1953,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Monitor T1", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.MONITOR_T1", "PerPkg": "1", @@ -1759,6 +1963,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Other", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.OTHER", "PerPkg": "1", @@ -1768,6 +1973,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Trap", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.TRAP", "PerPkg": "1", @@ -1777,6 +1983,7 @@ }, { "BriefDescription": "Monitor Sent to T0; Uncorrectable Machine Che= ck", + "Counter": "0,1", "EventCode": "0x43", "EventName": "UNC_U_U2C_EVENTS.UMC", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json b/tools= /perf/pmu-events/arch/x86/jaketown/uncore-io.json index b1ce5f77675e..c49f11aca14e 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_R2_CLOCKTICKS", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; DRS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.DRS", "PerPkg": "1", @@ -18,6 +20,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCB", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCB", "PerPkg": "1", @@ -27,6 +30,7 @@ }, { "BriefDescription": "R2PCIe IIO Credit Acquired; NCS", + "Counter": "0,1", "EventCode": "0x33", "EventName": "UNC_R2_IIO_CREDITS_ACQUIRED.NCS", "PerPkg": "1", @@ -36,6 +40,7 @@ }, { "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; DRS", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R2_IIO_CREDITS_REJECT.DRS", "PerPkg": "1", @@ -45,6 +50,7 @@ }, { "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCB", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCB", "PerPkg": "1", @@ -54,6 +60,7 @@ }, { "BriefDescription": "R2PCIe IIO Failed to Acquire a Credit; NCS", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_R2_IIO_CREDITS_REJECT.NCS", "PerPkg": "1", @@ -63,6 +70,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; DRS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.DRS", "PerPkg": "1", @@ -72,6 +80,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCB", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCB", "PerPkg": "1", @@ -81,6 +90,7 @@ }, { "BriefDescription": "R2PCIe IIO Credits in Use; NCS", + "Counter": "0,1", "EventCode": "0x32", "EventName": "UNC_R2_IIO_CREDITS_USED.NCS", "PerPkg": "1", @@ -90,6 +100,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_EVEN", "PerPkg": "1", @@ -99,6 +110,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CCW_ODD", "PerPkg": "1", @@ -108,6 +120,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_EVEN", "PerPkg": "1", @@ -117,6 +130,7 @@ }, { "BriefDescription": "R2 AD Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_R2_RING_AD_USED.CW_ODD", "PerPkg": "1", @@ -126,6 +140,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_EVEN", "PerPkg": "1", @@ -135,6 +150,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CCW_ODD", "PerPkg": "1", @@ -144,6 +160,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_EVEN", "PerPkg": "1", @@ -153,6 +170,7 @@ }, { "BriefDescription": "R2 AK Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_R2_RING_AK_USED.CW_ODD", "PerPkg": "1", @@ -162,6 +180,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_EVEN", "PerPkg": "1", @@ -171,6 +190,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Counterclockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CCW_ODD", "PerPkg": "1", @@ -180,6 +200,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Even", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_EVEN", "PerPkg": "1", @@ -189,6 +210,7 @@ }, { "BriefDescription": "R2 BL Ring in Use; Clockwise and Odd", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_R2_RING_BL_USED.CW_ODD", "PerPkg": "1", @@ -198,6 +220,7 @@ }, { "BriefDescription": "R2 IV Ring in Use; Any", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_R2_RING_IV_USED.ANY", "PerPkg": "1", @@ -207,6 +230,7 @@ }, { "BriefDescription": "AK Ingress Bounced", + "Counter": "0", "EventCode": "0x12", "EventName": "UNC_R2_RxR_AK_BOUNCES", "PerPkg": "1", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; DRS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.DRS", "PerPkg": "1", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCB", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCB", "PerPkg": "1", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Ingress Cycles Not Empty; NCS", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_R2_RxR_CYCLES_NE.NCS", "PerPkg": "1", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Egress Cycles Full; AD", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AD", "PerPkg": "1", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Egress Cycles Full; AK", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.AK", "PerPkg": "1", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Egress Cycles Full; BL", + "Counter": "0", "EventCode": "0x25", "EventName": "UNC_R2_TxR_CYCLES_FULL.BL", "PerPkg": "1", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AD", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AD", "PerPkg": "1", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; AK", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.AK", "PerPkg": "1", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Egress Cycles Not Empty; BL", + "Counter": "0", "EventCode": "0x23", "EventName": "UNC_R2_TxR_CYCLES_NE.BL", "PerPkg": "1", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Egress NACK; AD", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACKS.AD", "PerPkg": "1", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Egress NACK; AK", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACKS.AK", "PerPkg": "1", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Egress NACK; BL", + "Counter": "0,1", "EventCode": "0x26", "EventName": "UNC_R2_TxR_NACKS.BL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json index 6dcc9415a462..c94e22cdb535 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM Re= ads (RD_CAS + Underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM RD= _CAS (w/ and w/out auto-pre)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; Underfill R= ead Issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; All DRAM WR= _CAS (both Modes)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.; DRAM WR_CAS= (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "uclks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Uncore Fixed Counter - uclks", @@ -72,6 +81,7 @@ }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -98,6 +110,7 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", "PerPkg": "1", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", "PerPkg": "1", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", "PerPkg": "1", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", "PerPkg": "1", @@ -133,6 +149,7 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", "PerPkg": "1", @@ -142,6 +159,7 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", "PerPkg": "1", @@ -150,6 +168,7 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "PerPkg": "1", @@ -158,6 +177,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", "PerPkg": "1", @@ -167,6 +187,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", "PerPkg": "1", @@ -176,6 +197,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", "PerPkg": "1", @@ -185,6 +207,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", "PerPkg": "1", @@ -194,6 +217,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", "PerPkg": "1", @@ -203,6 +227,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", "PerPkg": "1", @@ -212,6 +237,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", "PerPkg": "1", @@ -221,6 +247,7 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", "PerPkg": "1", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", "PerPkg": "1", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "PerPkg": "1", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", "PerPkg": "1", @@ -255,6 +285,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", "PerPkg": "1", @@ -264,6 +295,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", "PerPkg": "1", @@ -273,6 +305,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", "PerPkg": "1", @@ -282,6 +315,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", "PerPkg": "1", @@ -291,6 +325,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", "PerPkg": "1", @@ -300,6 +335,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", "PerPkg": "1", @@ -309,6 +345,7 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", "PerPkg": "1", @@ -318,6 +355,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", "PerPkg": "1", @@ -327,6 +365,7 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", "PerPkg": "1", @@ -336,6 +375,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", "PerPkg": "1", @@ -345,6 +385,7 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharges due to p= age miss", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -354,6 +395,7 @@ }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL", "PerPkg": "1", @@ -362,6 +404,7 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", "PerPkg": "1", @@ -370,6 +413,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -378,6 +422,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY", "PerPkg": "1", @@ -386,6 +431,7 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", "PerPkg": "1", @@ -394,6 +440,7 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", "PerPkg": "1", @@ -402,6 +449,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS", "PerPkg": "1", @@ -410,6 +458,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", @@ -418,6 +467,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", "PerPkg": "1", @@ -426,6 +476,7 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/jaketown/uncore-power.json index 6f98fc1728e6..1dffd2999d70 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 800 MHz clock. Thi= s event counts the number of pclk cycles measured while the counter was ena= bled. The pclk, like the Memory Controller's dclk, counts at a constant ra= te making it a good measure of actual wall time.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_P_CORE0_TRANSITION_CYCLES", "PerPkg": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_CORE1_TRANSITION_CYCLES", "PerPkg": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_CORE2_TRANSITION_CYCLES", "PerPkg": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_CORE3_TRANSITION_CYCLES", "PerPkg": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_CORE4_TRANSITION_CYCLES", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_P_CORE5_TRANSITION_CYCLES", "PerPkg": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_CORE6_TRANSITION_CYCLES", "PerPkg": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_P_CORE7_TRANSITION_CYCLES", "PerPkg": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_P_DEMOTIONS_CORE0", "PerPkg": "1", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x1f", "EventName": "UNC_P_DEMOTIONS_CORE1", "PerPkg": "1", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_P_DEMOTIONS_CORE2", "PerPkg": "1", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_P_DEMOTIONS_CORE3", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_P_DEMOTIONS_CORE4", "PerPkg": "1", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_P_DEMOTIONS_CORE5", "PerPkg": "1", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_P_DEMOTIONS_CORE6", "PerPkg": "1", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Core C State Demotions", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_P_DEMOTIONS_CORE7", "PerPkg": "1", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_P_FREQ_BAND0_CYCLES", "PerPkg": "1", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xc", "EventName": "UNC_P_FREQ_BAND1_CYCLES", "PerPkg": "1", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xd", "EventName": "UNC_P_FREQ_BAND2_CYCLES", "PerPkg": "1", @@ -160,6 +180,7 @@ }, { "BriefDescription": "Frequency Residency", + "Counter": "0,1,2,3", "EventCode": "0xe", "EventName": "UNC_P_FREQ_BAND3_CYCLES", "PerPkg": "1", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Current Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_FREQ_MAX_CURRENT_CYCLES", "PerPkg": "1", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", "PerPkg": "1", @@ -184,6 +207,7 @@ }, { "BriefDescription": "OS Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_FREQ_MAX_OS_CYCLES", "PerPkg": "1", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", "PerPkg": "1", @@ -200,6 +225,7 @@ }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", "PerPkg": "1", @@ -208,6 +234,7 @@ }, { "BriefDescription": "Perf P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_P_FREQ_MIN_PERF_P_CYCLES", "PerPkg": "1", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventName": "UNC_P_FREQ_TRANS_CYCLES", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", @@ -223,6 +251,7 @@ }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", "PerPkg": "1", @@ -231,6 +260,7 @@ }, { "BriefDescription": "Number of cores in C0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", "Filter": "occ_sel=3D1", @@ -240,6 +270,7 @@ }, { "BriefDescription": "Number of cores in C0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", "Filter": "occ_sel=3D2", @@ -249,6 +280,7 @@ }, { "BriefDescription": "Number of cores in C0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", "Filter": "occ_sel=3D3", @@ -258,6 +290,7 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xa", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", "PerPkg": "1", @@ -266,6 +299,7 @@ }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", "PerPkg": "1", @@ -274,6 +308,7 @@ }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0xb", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", "PerPkg": "1", @@ -282,6 +317,7 @@ }, { "BriefDescription": "Cycles Changing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_P_VOLT_TRANS_CYCLES_CHANGE", "PerPkg": "1", @@ -290,6 +326,7 @@ }, { "BriefDescription": "Cycles Decreasing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_P_VOLT_TRANS_CYCLES_DECREASE", "PerPkg": "1", @@ -298,6 +335,7 @@ }, { "BriefDescription": "Cycles Increasing Voltage", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_P_VOLT_TRANS_CYCLES_INCREASE", "PerPkg": "1", @@ -306,6 +344,7 @@ }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_P_VR_HOT_CYCLES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json index fa08d355b97e..e0f6eb95455d 100644 --- a/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/jaketown/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -45,6 +51,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -52,6 +59,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", @@ -59,6 +67,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -66,6 +75,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", @@ -73,6 +83,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -80,6 +91,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -87,6 +99,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -94,6 +107,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", @@ -102,6 +116,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", @@ -109,6 +124,7 @@ }, { "BriefDescription": "STLB flush attempts.", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yw1-f202.google.com (mail-yw1-f202.google.com [209.85.128.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46C8F1AD9D4 for ; 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Thu, 20 Jun 2024 11:20:03 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:35 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-22-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 21/37] perf vendor events: Add knightslanding counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/knightslanding/cache.json | 213 +++++++++ .../arch/x86/knightslanding/counter.json | 37 ++ .../x86/knightslanding/floating-point.json | 3 + .../arch/x86/knightslanding/frontend.json | 7 + .../arch/x86/knightslanding/memory.json | 101 +++++ .../arch/x86/knightslanding/pipeline.json | 45 ++ .../arch/x86/knightslanding/uncore-cache.json | 421 ++++++++++++++++++ .../arch/x86/knightslanding/uncore-io.json | 24 + .../x86/knightslanding/uncore-memory.json | 14 + .../x86/knightslanding/virtual-memory.json | 7 + 10 files changed, 872 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/knightslanding/counter.j= son diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json b/too= ls/perf/pmu-events/arch/x86/knightslanding/cache.json index 8da3a5a7be73..a9f905bc19d2 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/cache.json @@ -1,12 +1,14 @@ [ { "BriefDescription": "Counts the number of MEC requests that were n= ot accepted into the L2Q because of any L2 queue reject condition. There i= s no concept of at-ret here. It might include requests due to instructions = in the speculative path.", + "Counter": "0,1", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ALL", "SampleAfterValue": "200003" }, { "BriefDescription": "This event counts the number of core cycles t= he fetch stalls because of an icache miss. This is a cumulative count of cy= cles the NIP stalled for all icache misses.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "SampleAfterValue": "200003", @@ -14,6 +16,7 @@ }, { "BriefDescription": "Counts the number of L2HWP allocated into XQ = GP", + "Counter": "0,1", "EventCode": "0x3E", "EventName": "L2_PREFETCHER.ALLOC_XQ", "SampleAfterValue": "100007", @@ -21,6 +24,7 @@ }, { "BriefDescription": "Counts the number of L2 cache misses", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_REQUESTS.MISS", "SampleAfterValue": "200003", @@ -28,6 +32,7 @@ }, { "BriefDescription": "Counts the total number of L2 cache reference= s.", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "L2_REQUESTS.REFERENCE", "SampleAfterValue": "200003", @@ -35,12 +40,14 @@ }, { "BriefDescription": "Counts the number of MEC requests from the L2= Q that reference a cache line (cacheable requests) excluding SW prefetches = filling only to L2 cache and L1 evictions (automatically excludes L2HWP, UC= , WC) that were rejected - Multiple repeated rejects should be counted mult= iple times", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REQUESTS_REJECT.ALL", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts all the load micro-ops retired", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PublicDescription": "This event counts the number of load micro-o= ps retired.", @@ -49,6 +56,7 @@ }, { "BriefDescription": "Counts all the store micro-ops retired", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PublicDescription": "This event counts the number of store micro-= ops retired.", @@ -57,6 +65,7 @@ }, { "BriefDescription": "Counts the loads retired that get the data fr= om the other core in the same tile in M state (Precise Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.HITM", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in L1 D cache", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", "PublicDescription": "This event counts the number of load micro-o= ps retired that miss in L1 Data cache. Note that prefetch misses will not b= e counted.", @@ -75,6 +85,7 @@ }, { "BriefDescription": "Counts the number of load micro-ops retired t= hat hit in the L2 (Precise Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", @@ -85,6 +96,7 @@ }, { "BriefDescription": "Counts the number of load micro-ops retired t= hat miss in the L2 (Precise Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", @@ -95,6 +107,7 @@ }, { "BriefDescription": "Counts the number of load micro-ops retired t= hat caused micro TLB miss", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.UTLB_MISS_LOADS", "SampleAfterValue": "200003", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Counts the matrix events specified by MSR_OFF= CORE_RESPx", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "SampleAfterValue": "100007", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from snoop request hit with data f= orwarded from it Far(not in the same quadrant as the request)-other tile L2= in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -127,6 +143,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -136,6 +153,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Far(not in the same quadrant as the request)-other tile= 's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from snoop request hit with data f= orwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -154,6 +173,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -163,6 +183,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from a snoop request hit with data= forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -172,6 +193,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -181,6 +203,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -190,6 +213,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -199,6 +223,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses which hit its own tile's L2 with d= ata in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -208,6 +233,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that are outstanding, per weighted cycle, from the time of the= request to when any response is received. The outstanding response should = be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -217,6 +243,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -226,6 +253,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from snoop request hit with= data forwarded from it Far(not in the same quadrant as the request)-other = tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -235,6 +263,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -244,6 +273,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -253,6 +283,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from snoop request hit with= data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +293,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +303,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +313,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -289,6 +323,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +333,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +343,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses which hit its own tile's L2= with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +353,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The outstanding response = should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -325,6 +363,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +373,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from snoop request hit with data forwarded from it Far(not in t= he same quadrant as the request)-other tile L2 in E/F/M state. Valid only i= n SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -343,6 +383,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +393,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +403,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from snoop request hit with data forwarded from its Near-other = tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +413,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +423,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +433,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +443,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -406,6 +453,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +463,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.OUTSTANDING", "MSRIndex": "0x1a6", @@ -424,6 +473,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for an= y response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +483,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from snoop request hit with data forwarded from it Far(not in the s= ame quadrant as the request)-other tile L2 in E/F/M state. Valid only in SN= C4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +493,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in E/F state. Valid only fo= r SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +503,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Far(not in th= e same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +513,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from snoop request hit with data forwarded from its Near-other tile= L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +523,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +533,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from a snoop request hit with data forwarded from its Near-other ti= le's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -487,6 +543,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +553,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +563,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +573,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +583,7 @@ }, { "BriefDescription": "Counts any Read request that are outstanding= , per weighted cycle, from the time of the request to when any response is = received. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.OUTSTANDING", "MSRIndex": "0x1a6", @@ -532,6 +593,7 @@ }, { "BriefDescription": "Counts any request that accounts for any resp= onse", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -541,6 +603,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from snoop request hit with data forwarded from it Far(not in the same qu= adrant as the request)-other tile L2 in E/F/M state. Valid only in SNC4 Clu= ster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -550,6 +613,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in E/F state. Valid only for SNC4= cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -559,6 +623,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Far(not in the same= quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -568,6 +633,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from snoop request hit with data forwarded from its Near-other tile L2 in= E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -577,6 +643,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -586,6 +653,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from a snoop request hit with data forwarded from its Near-other tile's L= 2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -595,6 +663,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -604,6 +673,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -613,6 +683,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -622,6 +693,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -631,6 +703,7 @@ }, { "BriefDescription": "Accounts for responses which miss its own til= e's L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -640,6 +713,7 @@ }, { "BriefDescription": "Counts any request that are outstanding, per = weighted cycle, from the time of the request to when any response is receiv= ed. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OUTSTANDING", "MSRIndex": "0x1a6", @@ -649,6 +723,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -658,6 +733,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from snoop request hit with data forwarded from= it Far(not in the same quadrant as the request)-other tile L2 in E/F/M sta= te. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -667,6 +743,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in E/F = state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -676,6 +753,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Far(not in the same quadrant as the request)-other tile's L2 in M st= ate.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -685,6 +763,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from snoop request hit with data forwarded from= its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -694,6 +773,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -703,6 +783,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from a snoop request hit with data forwarded fr= om its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -712,6 +793,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in E stat= e", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -721,6 +803,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in F stat= e", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -730,6 +813,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in M stat= e", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -739,6 +823,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses which hit its own tile's L2 with data in S stat= e", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -748,6 +833,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that are outstanding, per weighted cycle, from the time of the request to w= hen any response is received. The outstanding response should be programmed= only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -757,6 +843,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -766,6 +853,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from snoop request hit with data forwarded from it = Far(not in the same quadrant as the request)-other tile L2 in E/F/M state. = Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -775,6 +863,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in E/F stat= e. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -784,6 +873,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Far(not in the same quadrant as the request)-other tile's L2 in M state.= ", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -793,6 +883,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from snoop request hit with data forwarded from its= Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -802,6 +893,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -811,6 +903,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from a snoop request hit with data forwarded from i= ts Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -820,6 +913,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -829,6 +923,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -838,6 +933,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -847,6 +943,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -856,6 +953,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= are outstanding, per weighted cycle, from the time of the request to when = any response is received. The outstanding response should be programmed onl= y on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.OUTSTANDING", "MSRIndex": "0x1a6", @@ -865,6 +963,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -874,6 +973,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from snoop request hit with data forwarded = from it Far(not in the same quadrant as the request)-other tile L2 in E/F/M= state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -883,6 +983,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -892,6 +993,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Far(not in the same quadrant as the request)-other tile's L2 in = M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -901,6 +1003,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from snoop request hit with data forwarded = from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -910,6 +1013,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_E_F= ", "MSRIndex": "0x1a6,0x1a7", @@ -919,6 +1023,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from a snoop request hit with data forwarde= d from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -928,6 +1033,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in E = state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -937,6 +1043,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in F = state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -946,6 +1053,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in M = state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -955,6 +1063,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses which hit its own tile's L2 with data in S = state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -964,6 +1073,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that are outstanding, per weighted cycle, from the time of the request = to when any response is received. The outstanding response should be progra= mmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -973,6 +1083,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -982,6 +1093,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -991,6 +1103,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Far(not in the same quadrant as the request)-other tile's= L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1000,6 +1113,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_E_F= ", "MSRIndex": "0x1a6,0x1a7", @@ -1009,6 +1123,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from a snoop request hit with data f= orwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1018,6 +1133,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1027,6 +1143,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1036,6 +1153,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1045,6 +1163,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses which hit its own tile's L2 with dat= a in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1054,6 +1173,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that are outstanding, per weighted cycle, from the time of the r= equest to when any response is received. The outstanding response should be= programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1063,6 +1183,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1072,6 +1193,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from snoop request hit with data forwarded from it Far(n= ot in the same quadrant as the request)-other tile L2 in E/F/M state. Valid= only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1081,6 +1203,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in E/F state. Va= lid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1090,6 +1213,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Fa= r(not in the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1099,6 +1223,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from snoop request hit with data forwarded from its Near= -other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1108,6 +1233,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1117,6 +1243,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from a snoop request hit with data forwarded from its Ne= ar-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1126,6 +1253,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1135,6 +1263,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1144,6 +1273,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1153,6 +1283,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1162,6 +1293,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that are = outstanding, per weighted cycle, from the time of the request to when any r= esponse is received. The outstanding response should be programmed only on = PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1171,6 +1303,7 @@ }, { "BriefDescription": "Counts Full streaming stores (WC and should b= e programmed on PMC1) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.FULL_STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1180,6 +1313,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1189,6 +1323,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from snoop= request hit with data forwarded from it Far(not in the same quadrant as th= e request)-other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1198,6 +1333,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in E/F state. Valid only for SNC4 cluster mod= e.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1207,6 +1343,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Far(not in the same quadrant as= the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1216,6 +1353,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from snoop= request hit with data forwarded from its Near-other tile L2 in E/F/M state= ", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1225,6 +1363,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in E/F sta= te.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1234,6 +1373,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from a sno= op request hit with data forwarded from its Near-other tile's L2 in M state= .", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1243,6 +1383,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1252,6 +1393,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1261,6 +1403,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1270,6 +1413,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses which hit = its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1279,6 +1423,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that are outstanding, per weighted cyc= le, from the time of the request to when any response is received. The outs= tanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1288,6 +1433,7 @@ }, { "BriefDescription": "Counts Partial streaming stores (WC and shoul= d be programmed on PMC1) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_STREAMING_STORES.ANY_RESPON= SE", "MSRIndex": "0x1a7", @@ -1297,6 +1443,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.ANY_RESPONSE", "MSRIndex": "0x1a7", @@ -1306,6 +1453,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from snoop request h= it with data forwarded from it Far(not in the same quadrant as the request)= -other tile L2 in E/F/M state. Valid only in SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE", "MSRIndex": "0x1a7", @@ -1315,6 +1463,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a7", @@ -1324,6 +1473,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Far(not in the same quadrant as the reque= st)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a7", @@ -1333,6 +1483,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from snoop request h= it with data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a7", @@ -1342,6 +1493,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_E_F= ", "MSRIndex": "0x1a7", @@ -1351,6 +1503,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from a snoop request= hit with data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a7", @@ -1360,6 +1513,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a7", @@ -1369,6 +1523,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a7", @@ -1378,6 +1533,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a7", @@ -1387,6 +1543,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses which hit its own ti= le's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a7", @@ -1396,6 +1553,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1405,6 +1563,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from snoop request hit with data forwarded from it Far(not in t= he same quadrant as the request)-other tile L2 in E/F/M state. Valid only i= n SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1414,6 +1573,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1423,6 +1583,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1432,6 +1593,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from snoop request hit with data forwarded from its Near-other = tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1441,6 +1603,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1450,6 +1613,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1459,6 +1623,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1468,6 +1633,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1477,6 +1643,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1486,6 +1653,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1495,6 +1663,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1504,6 +1673,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1513,6 +1683,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from snoop request hit with data forwarded from it Far(not in t= he same quadrant as the request)-other tile L2 in E/F/M state. Valid only i= n SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1522,6 +1693,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in E/F state. Valid onl= y for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1531,6 +1703,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Far(not i= n the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1540,6 +1713,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from snoop request hit with data forwarded from its Near-other = tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1549,6 +1723,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1558,6 +1733,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from a snoop request hit with data forwarded from its Near-othe= r tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1567,6 +1743,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1576,6 +1753,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1585,6 +1763,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that are outstan= ding, per weighted cycle, from the time of the request to when any response= is received. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1594,6 +1773,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1603,6 +1783,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1612,6 +1793,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Far(not in the same quadrant as the request)-other= tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1621,6 +1803,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from snoop request hit with d= ata forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1630,6 +1813,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1639,6 +1823,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from a snoop request hit with= data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1648,6 +1833,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1657,6 +1843,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1666,6 +1853,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1675,6 +1863,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses which hit its own tile's L2 w= ith data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1684,6 +1873,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1693,6 +1883,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from snoop request hit with data forwarded from it Far(not in the= same quadrant as the request)-other tile L2 in E/F/M state. Valid only in = SNC4 Cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1702,6 +1893,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in E/F state. Valid only = for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1711,6 +1903,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Far(not in = the same quadrant as the request)-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1720,6 +1913,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from snoop request hit with data forwarded from its Near-other ti= le L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1729,6 +1923,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1738,6 +1933,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from a snoop request hit with data forwarded from its Near-other = tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1747,6 +1943,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1756,6 +1953,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1765,6 +1963,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1774,6 +1973,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses which hit its own tile's L2 with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1783,6 +1983,7 @@ }, { "BriefDescription": "Counts Software Prefetches that are outstandi= ng, per weighted cycle, from the time of the request to when any response i= s received. The outstanding response should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.OUTSTANDING", "MSRIndex": "0x1a6", @@ -1792,6 +1993,7 @@ }, { "BriefDescription": "Counts all streaming stores (WC and should be= programmed on PMC1) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a7", @@ -1801,6 +2003,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for any response", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1810,6 +2013,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in E/F state. Valid only for SNC4 cluster mode.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1819,6 +2023,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Far(not in the same quadrant as the request)-oth= er tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_FAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1828,6 +2033,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from snoop request hit with= data forwarded from its Near-other tile L2 in E/F/M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE", "MSRIndex": "0x1a6,0x1a7", @@ -1837,6 +2043,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in E/F state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_E_F", "MSRIndex": "0x1a6,0x1a7", @@ -1846,6 +2053,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from a snoop request hit wi= th data forwarded from its Near-other tile's L2 in M state.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_NEAR_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1855,6 +2063,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in E state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_E", "MSRIndex": "0x1a6,0x1a7", @@ -1864,6 +2073,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in F state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_F", "MSRIndex": "0x1a6,0x1a7", @@ -1873,6 +2083,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in M state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_M", "MSRIndex": "0x1a6,0x1a7", @@ -1882,6 +2093,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses which hit its own tile's L2= with data in S state", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.L2_HIT_THIS_TILE_S", "MSRIndex": "0x1a6,0x1a7", @@ -1891,6 +2103,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that are outstanding, per weighted cycle, from the time= of the request to when any response is received. The outstanding response = should be programmed only on PMC0.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.OUTSTANDING", "MSRIndex": "0x1a6", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/counter.json b/t= ools/perf/pmu-events/arch/x86/knightslanding/counter.json new file mode 100644 index 000000000000..4ce9f30a4fe5 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/knightslanding/counter.json @@ -0,0 +1,37 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "2" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "EDC_ECLK", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "EDC_UCLK", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC_DCLK", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC_UCLK", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json index 089aa3ef345d..29c0ff23957a 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of floating operations reti= red that required microcode assists", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "This event counts the number of times that t= he pipeline stalled due to FP operations needing assists.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of packed SSE, AVX, AVX2, A= VX-512 micro-ops (both floating point and integer) except for loads (memory= -to-register mov-type micro-ops), packed byte and word multiplies.", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.PACKED_SIMD", "PublicDescription": "The length of the packed operation (128bits,= 256bits or 512bits) is not taken into account when updating the counter; a= ll count the same (+1). \r\nMask (k) registers are ignored. For example: a = micro-op operating with a mask that only enables one element or even zero e= lements will still trigger this counter (+1)\r\nThis event is defined at th= e micro-op level and not instruction level. Most instructions are implement= ed with one micro-op but not all.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of scalar SSE, AVX, AVX2, A= VX-512 micro-ops except for loads (memory-to-register mov-type micro ops), = division, sqrt.", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.SCALAR_SIMD", "PublicDescription": "This event is defined at the micro-op level = and not instruction level. Most instructions are implemented with one micro= -op but not all.", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json b/= tools/perf/pmu-events/arch/x86/knightslanding/frontend.json index 9001f5019848..63343a0d1e86 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of times the front end rest= eers for any branch as a result of another branch handling mechanism in the= front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of times the front end rest= eers for conditional branches as a result of another branch handling mechan= ism in the front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of times the front end rest= eers for RET branches as a result of another branch handling mechanism in t= he front end.", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Counts all instruction fetches, including unc= acheable fetches.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -29,6 +33,7 @@ }, { "BriefDescription": "Counts all instruction fetches that hit the i= nstruction cache.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "200003", @@ -36,6 +41,7 @@ }, { "BriefDescription": "Counts all instruction fetches that miss the = instruction cache or produce memory requests. An instruction fetch miss is = counted only once and not once for every cycle it is outstanding.", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Counts the number of times the MSROM starts a= flow of uops.", + "Counter": "0,1", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "SampleAfterValue": "200003", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json b/to= ols/perf/pmu-events/arch/x86/knightslanding/memory.json index b0361f6f0dd9..7e4518986bb9 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of times the machine clears= due to memory ordering hazards", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Far or Other tile= L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Counts Demand code reads and prefetch code re= ad requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for responses from MCDRAM (local and far)= ", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Counts Demand cacheable data and L1 prefetch = data read requests that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Counts any Prefetch requests that accounts fo= r data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_PF_L2.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for da= ta responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for re= sponses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Counts any Read request that accounts for da= ta responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_READ.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Counts any request that accounts for data res= ponses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Counts any request that accounts for response= s from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Counts any request that accounts for data res= ponses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Counts Demand cacheable data write requests = that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -359,6 +399,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -368,6 +409,7 @@ }, { "BriefDescription": "Counts Bus locks and split lock requests that= accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.BUS_LOCKS.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -377,6 +419,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -386,6 +429,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -395,6 +439,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -404,6 +449,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -413,6 +459,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Far or Other tile L2 hit f= ar.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Counts demand code reads and prefetch code re= ads that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -431,6 +479,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -440,6 +489,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -449,6 +499,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -458,6 +509,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -467,6 +519,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Far or Other tile L= 2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -476,6 +529,7 @@ }, { "BriefDescription": "Counts demand cacheable data and L1 prefetch = data reads that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -485,6 +539,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -494,6 +549,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -503,6 +559,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -512,6 +569,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -521,6 +579,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -530,6 +589,7 @@ }, { "BriefDescription": "Counts Demand cacheable data writes that acco= unts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -539,6 +599,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from DDR (= local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -548,6 +609,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -557,6 +619,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -566,6 +629,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from MCDRA= M (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -575,6 +639,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -584,6 +649,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for data responses from = MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -593,6 +659,7 @@ }, { "BriefDescription": "Counts Partial reads (UC or WC and is valid o= nly for Outstanding response type). that accounts for responses from any N= ON_DRAM system address. This includes MMIO transactions", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -602,6 +669,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_FAR", "MSRIndex": "0x1a7", @@ -611,6 +679,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from DRAM Local= .", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.DDR_NEAR", "MSRIndex": "0x1a7", @@ -620,6 +689,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for responses from MCDRAM (local a= nd far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM", "MSRIndex": "0x1a7", @@ -629,6 +699,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Far= or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_FAR", "MSRIndex": "0x1a7", @@ -638,6 +709,7 @@ }, { "BriefDescription": "Counts Partial writes (UC or WT or WP and sho= uld be programmed on PMC1) that accounts for data responses from MCDRAM Loc= al.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.MCDRAM_NEAR", "MSRIndex": "0x1a7", @@ -647,6 +719,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -656,6 +729,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -665,6 +739,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -674,6 +749,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -683,6 +759,7 @@ }, { "BriefDescription": "Counts L1 data HW prefetches that accounts fo= r data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -692,6 +769,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -701,6 +779,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -710,6 +789,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -719,6 +799,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -728,6 +809,7 @@ }, { "BriefDescription": "Counts L2 code HW prefetches that accounts fo= r data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -737,6 +819,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -746,6 +829,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -755,6 +839,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +849,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -773,6 +859,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Far or Other= tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -782,6 +869,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -791,6 +879,7 @@ }, { "BriefDescription": "Counts L2 data RFO prefetches (includes PREFE= TCHW instruction) that accounts for responses from any NON_DRAM system addr= ess. This includes MMIO transactions", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -800,6 +889,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -809,6 +899,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -818,6 +909,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -827,6 +919,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = responses from MCDRAM (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -836,6 +929,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Far or Other tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -845,6 +939,7 @@ }, { "BriefDescription": "Counts Software Prefetches that accounts for = data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_SOFTWARE.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -854,6 +949,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from DDR (local and far)", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR", "MSRIndex": "0x1a6,0x1a7", @@ -863,6 +959,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -872,6 +969,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from DRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.DDR_NEAR", "MSRIndex": "0x1a6,0x1a7", @@ -881,6 +979,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for responses from MCDRAM (local and far)= ", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM", "MSRIndex": "0x1a6,0x1a7", @@ -890,6 +989,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Far or Oth= er tile L2 hit far.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_FAR", "MSRIndex": "0x1a6,0x1a7", @@ -899,6 +999,7 @@ }, { "BriefDescription": "Counts UC code reads (valid only for Outstand= ing response type) that accounts for data responses from MCDRAM Local.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.UC_CODE_READS.MCDRAM_NEAR", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json b/= tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json index 5b2e71750976..37d679ed8061 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of branch instructions reti= red (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Counts the number of branch instructions reti= red that were near indirect CALL or near indirect JMP. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Counts the number of branch instructions reti= red that were conditional jumps and predicted taken. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -79,6 +89,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near CALL b= ranch instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CALL", "PEBS": "1", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Counts the number of mispredicted far branch = instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -95,6 +107,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", @@ -103,6 +116,7 @@ }, { "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were near indirect CALL or near indirect JMP. (Precis= e Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -119,6 +134,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near relati= ve CALL branch instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.REL_CALL", "PEBS": "1", @@ -127,6 +143,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired. (Precise Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired that were conditional jumps and predicted taken. (Precise = Event)", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -143,6 +161,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000003", @@ -150,12 +169,14 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter", "SampleAfterValue": "2000003", @@ -163,12 +184,14 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles the number of core cycles when divider= is busy. Does not imply a stall waiting for the divider.", + "Counter": "0,1", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.ALL", "PublicDescription": "This event counts cycles when the divider is= busy. More specifically cycles when the divide unit is unable to accept a = new divide uop because it is busy processing a previously dispatched uop. T= he cycles will be counted irrespective of whether or not another divide uop= is waiting to enter the divide unit (from the RS). This event counts integ= er divides, x87 divides, divss, divsd, sqrtss, sqrtsd event and does not co= unt vector divides.", @@ -177,6 +200,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps.", "SampleAfterValue": "2000003", @@ -184,12 +208,14 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed", + "Counter": "0,1", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of instructions retired (Pr= ecise Event)", + "Counter": "0", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_PS", "PEBS": "2", @@ -197,6 +223,7 @@ }, { "BriefDescription": "Counts all machine clears", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.ALL", "SampleAfterValue": "200003", @@ -204,6 +231,7 @@ }, { "BriefDescription": "Counts the number of times that the machine c= lears due to program modifying data within 1K of a recently fetched code pa= ge", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "200003", @@ -211,6 +239,7 @@ }, { "BriefDescription": "Counts the total number of core cycles when n= o micro-ops are allocated for any reason.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.ALL", "SampleAfterValue": "200003", @@ -218,6 +247,7 @@ }, { "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the alloc pipe is stalled waiting for a mispredicte= d branch to retire.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", "PublicDescription": "This event counts the number of core cycles = when no uops are allocated and the alloc pipe is stalled waiting for a misp= redicted branch to retire.", @@ -226,6 +256,7 @@ }, { "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated, the IQ is empty, and no other condition is blocking al= location.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", "PublicDescription": "This event counts the number of core cycles = when no uops are allocated, the instruction queue is empty and the alloc pi= pe is stalled waiting for instructions to be fetched.", @@ -234,6 +265,7 @@ }, { "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and a RATstall (caused by reservation station full) is = asserted.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.RAT_STALL", "SampleAfterValue": "200003", @@ -241,6 +273,7 @@ }, { "BriefDescription": "Counts the number of core cycles when no micr= o-ops are allocated and the ROB is full", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.ROB_FULL", "SampleAfterValue": "200003", @@ -248,6 +281,7 @@ }, { "BriefDescription": "Counts any retired load that was pushed into = the recycle queue for any reason.", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.ANY_LD", "SampleAfterValue": "200003", @@ -255,6 +289,7 @@ }, { "BriefDescription": "Counts any retired store that was pushed into= the recycle queue for any reason.", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.ANY_ST", "SampleAfterValue": "200003", @@ -262,6 +297,7 @@ }, { "BriefDescription": "Counts the number of occurrences a retired lo= ad gets blocked because its address overlaps with a store whose data is not= ready", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_BLOCK_STD_NOTREADY", "SampleAfterValue": "200003", @@ -269,6 +305,7 @@ }, { "BriefDescription": "Counts the number of occurrences a retired lo= ad gets blocked because its address partially overlaps with a store (Preci= se Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_BLOCK_ST_FORWARD", @@ -279,6 +316,7 @@ }, { "BriefDescription": "Counts the number of occurrences a retired lo= ad was pushed into the rehab queue because it sees a cache line split. Each= split should be counted only once. (Precise Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x03", "EventName": "RECYCLEQ.LD_SPLITS", @@ -289,6 +327,7 @@ }, { "BriefDescription": "Counts all the retired locked loads. It does = not include stores because we would double count if we count stores", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.LOCK", "SampleAfterValue": "200003", @@ -296,6 +335,7 @@ }, { "BriefDescription": "Counts the store micro-ops retired that were = pushed in the rehab queue because the store address buffer is full", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.STA_FULL", "SampleAfterValue": "200003", @@ -303,6 +343,7 @@ }, { "BriefDescription": "Counts the number of occurrences a retired st= ore that is a cache line split. Each split should be counted only once.", + "Counter": "0,1", "EventCode": "0x03", "EventName": "RECYCLEQ.ST_SPLITS", "PublicDescription": "This event counts the number of retired stor= e that experienced a cache line boundary split(Precise Event). Note that ea= ch spilt should be counted only once.", @@ -311,6 +352,7 @@ }, { "BriefDescription": "Counts the total number of core cycles alloca= tion pipeline is stalled when any one of the reservation stations is full.", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "RS_FULL_STALL.ALL", "SampleAfterValue": "200003", @@ -318,6 +360,7 @@ }, { "BriefDescription": "Counts the number of core cycles when allocat= ion pipeline is stalled and is waiting for a free MEC reservation station e= ntry.", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "RS_FULL_STALL.MEC", "SampleAfterValue": "200003", @@ -325,6 +368,7 @@ }, { "BriefDescription": "Counts the number of micro-ops retired", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PublicDescription": "This event counts the number of micro-ops (u= ops) retired. The processor decodes complex macro instructions into a seque= nce of simpler uops. Most instructions are composed of one or two uops. Som= e instructions are decoded into longer sequences such as repeat instruction= s, floating point transcendental instructions, and assists.", @@ -333,6 +377,7 @@ }, { "BriefDescription": "Counts the number of micro-ops retired that a= re from the complex flows issued by the micro-sequencer (MS).", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MS", "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.jso= n b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json index 120e4813d82a..1550b6457965 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IP= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IP= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IR= Q or PRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -PR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -PR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR6", "PerPkg": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR7", "PerPkg": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", "PerPkg": "1", @@ -129,6 +145,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED_EXT.TGR8", "PerPkg": "1", @@ -137,6 +154,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", @@ -153,6 +172,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR6", "PerPkg": "1", @@ -193,6 +217,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR7", "PerPkg": "1", @@ -201,6 +226,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", "PerPkg": "1", @@ -209,6 +235,7 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY_EXT.TGR8", "PerPkg": "1", @@ -217,6 +244,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", @@ -225,6 +253,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", @@ -233,6 +262,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", @@ -241,6 +271,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", @@ -249,6 +280,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", "PerPkg": "1", @@ -257,6 +289,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", @@ -265,6 +298,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR6", "PerPkg": "1", @@ -273,6 +307,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR7", "PerPkg": "1", @@ -281,6 +316,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", "PerPkg": "1", @@ -289,6 +325,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED_EXT.TGR8", "PerPkg": "1", @@ -297,6 +334,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", @@ -305,6 +343,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", @@ -313,6 +352,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", @@ -321,6 +361,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", @@ -329,6 +370,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", @@ -337,6 +379,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", @@ -345,6 +388,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR6", "PerPkg": "1", @@ -353,6 +397,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR7", "PerPkg": "1", @@ -361,6 +406,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", "PerPkg": "1", @@ -369,6 +415,7 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY_EXT.TGR8", "PerPkg": "1", @@ -377,6 +424,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", "PerPkg": "1", @@ -385,6 +433,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", "PerPkg": "1", @@ -393,6 +442,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", "PerPkg": "1", @@ -401,6 +451,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", "PerPkg": "1", @@ -409,6 +460,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", "PerPkg": "1", @@ -417,6 +469,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", "PerPkg": "1", @@ -425,6 +478,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", "PerPkg": "1", @@ -433,6 +487,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", "PerPkg": "1", @@ -441,6 +496,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR= 0_THRU_TGR7", "PerPkg": "1", @@ -449,6 +505,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", "PerPkg": "1", @@ -457,6 +514,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", "PerPkg": "1", @@ -465,6 +523,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", "PerPkg": "1", @@ -473,6 +532,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", "PerPkg": "1", @@ -481,6 +541,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", "PerPkg": "1", @@ -489,6 +550,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", "PerPkg": "1", @@ -497,6 +559,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", "PerPkg": "1", @@ -505,6 +568,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", "PerPkg": "1", @@ -513,6 +577,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", "PerPkg": "1", @@ -521,6 +586,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR= 0_THRU_TGR7", "PerPkg": "1", @@ -529,6 +595,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_H_AG0_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", "PerPkg": "1", @@ -537,6 +604,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", "PerPkg": "1", @@ -545,6 +613,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", "PerPkg": "1", @@ -553,6 +622,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", "PerPkg": "1", @@ -561,6 +631,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", "PerPkg": "1", @@ -569,6 +640,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", "PerPkg": "1", @@ -577,6 +649,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", "PerPkg": "1", @@ -585,6 +658,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR6", "PerPkg": "1", @@ -593,6 +667,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR7", "PerPkg": "1", @@ -601,6 +676,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", "PerPkg": "1", @@ -609,6 +685,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED_EXT.TGR8", "PerPkg": "1", @@ -617,6 +694,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", "PerPkg": "1", @@ -625,6 +703,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", "PerPkg": "1", @@ -633,6 +712,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", "PerPkg": "1", @@ -641,6 +721,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", "PerPkg": "1", @@ -649,6 +730,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", "PerPkg": "1", @@ -657,6 +739,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", "PerPkg": "1", @@ -665,6 +748,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR6", "PerPkg": "1", @@ -673,6 +757,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR7", "PerPkg": "1", @@ -681,6 +766,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", "PerPkg": "1", @@ -689,6 +775,7 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY_EXT.TGR8", "PerPkg": "1", @@ -697,6 +784,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR0", "PerPkg": "1", @@ -705,6 +793,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR1", "PerPkg": "1", @@ -713,6 +802,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR2", "PerPkg": "1", @@ -721,6 +811,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR3", "PerPkg": "1", @@ -729,6 +820,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR4", "PerPkg": "1", @@ -737,6 +829,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR5", "PerPkg": "1", @@ -745,6 +838,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 6", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR6", "PerPkg": "1", @@ -753,6 +847,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 7", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED.TGR7", "PerPkg": "1", @@ -761,6 +856,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 0-7", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.ANY_OF_TGR0_THRU_TGR7", "PerPkg": "1", @@ -769,6 +865,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired For Transgress= 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_H_AG1_BL_CRD_ACQUIRED_EXT.TGR8", "PerPkg": "1", @@ -777,6 +874,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", "PerPkg": "1", @@ -785,6 +883,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", "PerPkg": "1", @@ -793,6 +892,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", "PerPkg": "1", @@ -801,6 +901,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", "PerPkg": "1", @@ -809,6 +910,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", "PerPkg": "1", @@ -817,6 +919,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", "PerPkg": "1", @@ -825,6 +928,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR6", "PerPkg": "1", @@ -833,6 +937,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR7", "PerPkg": "1", @@ -841,6 +946,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 0-7", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.ANY_OF_TGR0_THRU_TGR7= ", "PerPkg": "1", @@ -849,6 +955,7 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy For Transgres= s 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY_EXT.TGR8", "PerPkg": "1", @@ -857,6 +964,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR0", "PerPkg": "1", @@ -865,6 +973,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR1", "PerPkg": "1", @@ -873,6 +982,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR2", "PerPkg": "1", @@ -881,6 +991,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR3", "PerPkg": "1", @@ -889,6 +1000,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR4", "PerPkg": "1", @@ -897,6 +1009,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR5", "PerPkg": "1", @@ -905,6 +1018,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR6", "PerPkg": "1", @@ -913,6 +1027,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD.TGR7", "PerPkg": "1", @@ -921,6 +1036,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.ANY_OF_TGR= 0_THRU_TGR7", "PerPkg": "1", @@ -929,6 +1045,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_AD_EXT.TGR8", "PerPkg": "1", @@ -937,6 +1054,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR0", "PerPkg": "1", @@ -945,6 +1063,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR1", "PerPkg": "1", @@ -953,6 +1072,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR2", "PerPkg": "1", @@ -961,6 +1081,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR3", "PerPkg": "1", @@ -969,6 +1090,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR4", "PerPkg": "1", @@ -977,6 +1099,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR5", "PerPkg": "1", @@ -985,6 +1108,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR6", "PerPkg": "1", @@ -993,6 +1117,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL.TGR7", "PerPkg": "1", @@ -1001,6 +1126,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 0-7", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.ANY_OF_TGR= 0_THRU_TGR7", "PerPkg": "1", @@ -1009,6 +1135,7 @@ }, { "BriefDescription": "Stall on No AD Transgress Credits For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_H_AG1_STALL_NO_CRD_EGRESS_HORZ_BL_EXT.TGR8", "PerPkg": "1", @@ -1017,6 +1144,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.E_STATE", "PerPkg": "1", @@ -1025,6 +1153,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for any transaction originating from the IPQ or = IRQ. This does not include lookups originating from the ISMQ.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.F_STATE", "PerPkg": "1", @@ -1033,6 +1162,7 @@ }, { "BriefDescription": "Lines Victimized that Match NID", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.LOCAL", "PerPkg": "1", @@ -1041,6 +1171,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Read transactions", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.M_STATE", "PerPkg": "1", @@ -1049,6 +1180,7 @@ }, { "BriefDescription": "Lines Victimized that Does Not Match NID", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.REMOTE", "PerPkg": "1", @@ -1057,6 +1189,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for only snoop requests coming from the remote s= ocket(s) through the IPQ.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_H_CACHE_LINES_VICTIMIZED.S_STATE", "PerPkg": "1", @@ -1065,6 +1198,7 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_H_CLOCK", "PerPkg": "1", @@ -1072,6 +1206,7 @@ }, { "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AD", "PerPkg": "1", @@ -1080,6 +1215,7 @@ }, { "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.AK", "PerPkg": "1", @@ -1088,6 +1224,7 @@ }, { "BriefDescription": "CMS Horizontal ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_H_EGRESS_HORZ_ADS_USED.BL", "PerPkg": "1", @@ -1096,6 +1233,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Bypass. AD ring", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AD", "PerPkg": "1", @@ -1104,6 +1242,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Bypass. AK ring", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_H_EGRESS_HORZ_BYPASS.AK", "PerPkg": "1", @@ -1112,6 +1251,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Bypass. BL ring", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_H_EGRESS_HORZ_BYPASS.BL", "PerPkg": "1", @@ -1120,6 +1260,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Bypass. IV ring", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_H_EGRESS_HORZ_BYPASS.IV", "PerPkg": "1", @@ -1128,6 +1269,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AD= ", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AD", "PerPkg": "1", @@ -1136,6 +1278,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full AK= ", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.AK", "PerPkg": "1", @@ -1144,6 +1287,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full BL= ", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.BL", "PerPkg": "1", @@ -1152,6 +1296,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full IV= ", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_FULL.IV", "PerPkg": "1", @@ -1160,6 +1305,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty AD", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AD", "PerPkg": "1", @@ -1168,6 +1314,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty AK", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.AK", "PerPkg": "1", @@ -1176,6 +1323,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty BL", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.BL", "PerPkg": "1", @@ -1184,6 +1332,7 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty IV", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_H_EGRESS_HORZ_CYCLES_NE.IV", "PerPkg": "1", @@ -1192,6 +1341,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts AD", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AD", "PerPkg": "1", @@ -1200,6 +1350,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts AK", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_H_EGRESS_HORZ_INSERTS.AK", "PerPkg": "1", @@ -1208,6 +1359,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts BL", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_H_EGRESS_HORZ_INSERTS.BL", "PerPkg": "1", @@ -1216,6 +1368,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts IV", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_H_EGRESS_HORZ_INSERTS.IV", "PerPkg": "1", @@ -1224,6 +1377,7 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_H_EGRESS_HORZ_NACK.AD", "PerPkg": "1", @@ -1232,6 +1386,7 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_H_EGRESS_HORZ_NACK.AK", "PerPkg": "1", @@ -1240,6 +1395,7 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_H_EGRESS_HORZ_NACK.BL", "PerPkg": "1", @@ -1248,6 +1404,7 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_H_EGRESS_HORZ_NACK.IV", "PerPkg": "1", @@ -1256,6 +1413,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy AD", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AD", "PerPkg": "1", @@ -1264,6 +1422,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy AK", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.AK", "PerPkg": "1", @@ -1272,6 +1431,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy BL", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.BL", "PerPkg": "1", @@ -1280,6 +1440,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy IV", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_H_EGRESS_HORZ_OCCUPANCY.IV", "PerPkg": "1", @@ -1288,6 +1449,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_H_EGRESS_HORZ_STARVED.AD", "PerPkg": "1", @@ -1296,6 +1458,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_H_EGRESS_HORZ_STARVED.AK", "PerPkg": "1", @@ -1304,6 +1467,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_H_EGRESS_HORZ_STARVED.BL", "PerPkg": "1", @@ -1312,6 +1476,7 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_H_EGRESS_HORZ_STARVED.IV", "PerPkg": "1", @@ -1320,6 +1485,7 @@ }, { "BriefDescription": "Counts number of cycles IV was blocked in the= TGR Egress due to SNP/GO Ordering requirements", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_DN", "PerPkg": "1", @@ -1328,6 +1494,7 @@ }, { "BriefDescription": "Counts number of cycles IV was blocked in the= TGR Egress due to SNP/GO Ordering requirements", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNP_GO_UP", "PerPkg": "1", @@ -1336,6 +1503,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG0", "PerPkg": "1", @@ -1344,6 +1512,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AD_AG1", "PerPkg": "1", @@ -1352,6 +1521,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG0", "PerPkg": "1", @@ -1360,6 +1530,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.AK_AG1", "PerPkg": "1", @@ -1368,6 +1539,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG0", "PerPkg": "1", @@ -1376,6 +1548,7 @@ }, { "BriefDescription": "CMS Vertical ADS Used", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_H_EGRESS_VERT_ADS_USED.BL_AG1", "PerPkg": "1", @@ -1384,6 +1557,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG0", "PerPkg": "1", @@ -1392,6 +1566,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. AD ring agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.AD_AG1", "PerPkg": "1", @@ -1400,6 +1575,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG0", "PerPkg": "1", @@ -1408,6 +1584,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. AK ring agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.AK_AG1", "PerPkg": "1", @@ -1416,6 +1593,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG0", "PerPkg": "1", @@ -1424,6 +1602,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. BL ring agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.BL_AG1", "PerPkg": "1", @@ -1432,6 +1611,7 @@ }, { "BriefDescription": "CMS Vertical Egress Bypass. IV ring agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_H_EGRESS_VERT_BYPASS.IV", "PerPkg": "1", @@ -1440,6 +1620,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD -= Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG0", "PerPkg": "1", @@ -1448,6 +1629,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AD -= Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AD_AG1", "PerPkg": "1", @@ -1456,6 +1638,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK -= Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG0", "PerPkg": "1", @@ -1464,6 +1647,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full AK -= Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.AK_AG1", "PerPkg": "1", @@ -1472,6 +1656,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL -= Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG0", "PerPkg": "1", @@ -1480,6 +1665,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full BL -= Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.BL_AG1", "PerPkg": "1", @@ -1488,6 +1674,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full IV -= Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_H_EGRESS_VERT_CYCLES_FULL.IV_AG0", "PerPkg": "1", @@ -1496,6 +1683,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG0", "PerPkg": "1", @@ -1504,6 +1692,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AD_AG1", "PerPkg": "1", @@ -1512,6 +1701,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG0", "PerPkg": "1", @@ -1520,6 +1710,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.AK_AG1", "PerPkg": "1", @@ -1528,6 +1719,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG0", "PerPkg": "1", @@ -1536,6 +1728,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.BL_AG1", "PerPkg": "1", @@ -1544,6 +1737,7 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_H_EGRESS_VERT_CYCLES_NE.IV_AG0", "PerPkg": "1", @@ -1552,6 +1746,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG0", "PerPkg": "1", @@ -1560,6 +1755,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.AD_AG1", "PerPkg": "1", @@ -1568,6 +1764,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG0", "PerPkg": "1", @@ -1576,6 +1773,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.AK_AG1", "PerPkg": "1", @@ -1584,6 +1782,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG0", "PerPkg": "1", @@ -1592,6 +1791,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.BL_AG1", "PerPkg": "1", @@ -1600,6 +1800,7 @@ }, { "BriefDescription": "CMS Vert Egress Allocations IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_H_EGRESS_VERT_INSERTS.IV_AG0", "PerPkg": "1", @@ -1608,6 +1809,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG0", "PerPkg": "1", @@ -1616,6 +1818,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.AD_AG1", "PerPkg": "1", @@ -1624,6 +1827,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs Onto AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG0", "PerPkg": "1", @@ -1632,6 +1836,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.AK_AG1", "PerPkg": "1", @@ -1640,6 +1845,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs Onto BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG0", "PerPkg": "1", @@ -1648,6 +1854,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.BL_AG1", "PerPkg": "1", @@ -1656,6 +1863,7 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_H_EGRESS_VERT_NACK.IV_AG0", "PerPkg": "1", @@ -1664,6 +1872,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG0", "PerPkg": "1", @@ -1672,6 +1881,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AD_AG1", "PerPkg": "1", @@ -1680,6 +1890,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG0", "PerPkg": "1", @@ -1688,6 +1899,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.AK_AG1", "PerPkg": "1", @@ -1696,6 +1908,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG0", "PerPkg": "1", @@ -1704,6 +1917,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.BL_AG1", "PerPkg": "1", @@ -1712,6 +1926,7 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_H_EGRESS_VERT_OCCUPANCY.IV_AG0", "PerPkg": "1", @@ -1720,6 +1935,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG0", "PerPkg": "1", @@ -1728,6 +1944,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.AD_AG1", "PerPkg": "1", @@ -1736,6 +1953,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation Onto= AK Ring", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG0", "PerPkg": "1", @@ -1744,6 +1962,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.AK_AG1", "PerPkg": "1", @@ -1752,6 +1971,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation Onto= BL Ring", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG0", "PerPkg": "1", @@ -1760,6 +1980,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.BL_AG1", "PerPkg": "1", @@ -1768,6 +1989,7 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_H_EGRESS_VERT_STARVED.IV_AG0", "PerPkg": "1", @@ -1776,6 +1998,7 @@ }, { "BriefDescription": "Counts cycles source throttling is asserted -= horizontal", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_H_FAST_ASSERTED.HORZ", "PerPkg": "1", @@ -1784,6 +2007,7 @@ }, { "BriefDescription": "Counts cycles source throttling is asserted -= vertical", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_H_FAST_ASSERTED.VERT", "PerPkg": "1", @@ -1791,6 +2015,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", "PerPkg": "1", @@ -1799,6 +2024,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", "PerPkg": "1", @@ -1807,6 +2033,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", "PerPkg": "1", @@ -1815,6 +2042,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AD ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", "PerPkg": "1", @@ -1823,6 +2051,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", "PerPkg": "1", @@ -1831,6 +2060,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", "PerPkg": "1", @@ -1839,6 +2069,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", "PerPkg": "1", @@ -1847,6 +2078,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al AK ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", "PerPkg": "1", @@ -1855,6 +2087,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", "PerPkg": "1", @@ -1863,6 +2096,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", "PerPkg": "1", @@ -1871,6 +2105,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", "PerPkg": "1", @@ -1879,6 +2114,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al BL ring is being used at this ring stop - Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", "PerPkg": "1", @@ -1887,6 +2123,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al IV ring is being used at this ring stop - Left", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", "PerPkg": "1", @@ -1895,6 +2132,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Horizont= al IV ring is being used at this ring stop - Right", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", "PerPkg": "1", @@ -1903,6 +2141,7 @@ }, { "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_INGRESS_INSERTS.IPQ", "PerPkg": "1", @@ -1911,6 +2150,7 @@ }, { "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_INGRESS_INSERTS.IRQ", "PerPkg": "1", @@ -1919,6 +2159,7 @@ }, { "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_INGRESS_INSERTS.IRQ_REJ", "PerPkg": "1", @@ -1927,6 +2168,7 @@ }, { "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_INGRESS_INSERTS.PRQ", "PerPkg": "1", @@ -1935,6 +2177,7 @@ }, { "BriefDescription": "Ingress Allocations. Counts number of allocat= ions per cycle into the specified Ingress queue. - PRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_H_INGRESS_INSERTS.PRQ_REJ", "PerPkg": "1", @@ -1943,6 +2186,7 @@ }, { "BriefDescription": "Cycles with the IPQ in Internal Starvation.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_INGRESS_INT_STARVED.IPQ", "PerPkg": "1", @@ -1951,6 +2195,7 @@ }, { "BriefDescription": "Cycles with the IRQ in Internal Starvation.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_INGRESS_INT_STARVED.IRQ", "PerPkg": "1", @@ -1959,6 +2204,7 @@ }, { "BriefDescription": "Cycles with the ISMQ in Internal Starvation.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_INGRESS_INT_STARVED.ISMQ", "PerPkg": "1", @@ -1967,6 +2213,7 @@ }, { "BriefDescription": "Ingress internal starvation cycles. Counts cy= cles in internal starvation. This occurs when one or more of the entries in= the ingress queue are being starved out by other entries in the queue.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_H_INGRESS_INT_STARVED.PRQ", "PerPkg": "1", @@ -1975,6 +2222,7 @@ }, { "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_H_INGRESS_OCCUPANCY.IPQ", "PerPkg": "1", @@ -1983,6 +2231,7 @@ }, { "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ", "PerPkg": "1", @@ -1991,6 +2240,7 @@ }, { "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - IRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_H_INGRESS_OCCUPANCY.IRQ_REJ", "PerPkg": "1", @@ -1999,6 +2249,7 @@ }, { "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - PRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ", "PerPkg": "1", @@ -2007,6 +2258,7 @@ }, { "BriefDescription": "Ingress Occupancy. Counts number of entries i= n the specified Ingress queue in each cycle. - PRQ Rejected", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_H_INGRESS_OCCUPANCY.PRQ_REJ", "PerPkg": "1", @@ -2015,6 +2267,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", @@ -2023,6 +2276,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", @@ -2031,6 +2285,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.AK_NON_UPI", "PerPkg": "1", @@ -2039,6 +2294,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", @@ -2047,6 +2303,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", @@ -2055,6 +2312,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", @@ -2063,6 +2321,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.BL_WB_VN0", "PerPkg": "1", @@ -2071,6 +2330,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_H_INGRESS_RETRY_IPQ0_REJECT.IV_NON_UPI", "PerPkg": "1", @@ -2079,6 +2339,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ALLOW_SNP", "PerPkg": "1", @@ -2087,6 +2348,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.ANY_REJECT_IPQ0", "PerPkg": "1", @@ -2095,6 +2357,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.PA_MATCH", "PerPkg": "1", @@ -2103,6 +2366,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_VICTIM", "PerPkg": "1", @@ -2111,6 +2375,7 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_H_INGRESS_RETRY_IPQ1_REJECT.SF_WAY", "PerPkg": "1", @@ -2119,6 +2384,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", @@ -2127,6 +2393,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", @@ -2135,6 +2402,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", @@ -2143,6 +2411,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", @@ -2151,6 +2420,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", @@ -2159,6 +2429,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", @@ -2167,6 +2438,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", @@ -2175,6 +2447,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_H_INGRESS_RETRY_IRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", @@ -2183,6 +2456,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", @@ -2191,6 +2465,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.ANY_REJECT_IRQ0", "PerPkg": "1", @@ -2199,6 +2474,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", @@ -2207,6 +2483,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_VICTIM", "PerPkg": "1", @@ -2215,6 +2492,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_H_INGRESS_RETRY_IRQ1_REJECT.SF_WAY", "PerPkg": "1", @@ -2223,6 +2501,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", @@ -2231,6 +2510,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", @@ -2239,6 +2519,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.AK_NON_UPI", "PerPkg": "1", @@ -2247,6 +2528,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", @@ -2255,6 +2537,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", @@ -2263,6 +2546,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", @@ -2271,6 +2555,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.BL_WB_VN0", "PerPkg": "1", @@ -2279,6 +2564,7 @@ }, { "BriefDescription": "ISMQ Rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_REJECT.IV_NON_UPI", "PerPkg": "1", @@ -2287,6 +2573,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_REQ_VN0", "PerPkg": "1", @@ -2295,6 +2582,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AD_RSP_VN0", "PerPkg": "1", @@ -2303,6 +2591,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.AK_NON_UPI", "PerPkg": "1", @@ -2311,6 +2600,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCB_VN0", "PerPkg": "1", @@ -2319,6 +2609,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_NCS_VN0", "PerPkg": "1", @@ -2327,6 +2618,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_RSP_VN0", "PerPkg": "1", @@ -2335,6 +2627,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.BL_WB_VN0", "PerPkg": "1", @@ -2343,6 +2636,7 @@ }, { "BriefDescription": "ISMQ Retries", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_H_INGRESS_RETRY_ISMQ0_RETRY.IV_NON_UPI", "PerPkg": "1", @@ -2351,6 +2645,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_REQ_VN0", "PerPkg": "1", @@ -2359,6 +2654,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AD_RSP_VN0", "PerPkg": "1", @@ -2367,6 +2663,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.AK_NON_UPI", "PerPkg": "1", @@ -2375,6 +2672,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCB_VN0", "PerPkg": "1", @@ -2383,6 +2681,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_NCS_VN0", "PerPkg": "1", @@ -2391,6 +2690,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_RSP_VN0", "PerPkg": "1", @@ -2399,6 +2699,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.BL_WB_VN0", "PerPkg": "1", @@ -2407,6 +2708,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_H_INGRESS_RETRY_OTHER0_RETRY.IV_NON_UPI", "PerPkg": "1", @@ -2415,6 +2717,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ALLOW_SNP", "PerPkg": "1", @@ -2423,6 +2726,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.ANY_REJECT_IRQ0", "PerPkg": "1", @@ -2431,6 +2735,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.PA_MATCH", "PerPkg": "1", @@ -2439,6 +2744,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_VICTIM", "PerPkg": "1", @@ -2447,6 +2753,7 @@ }, { "BriefDescription": "Other Queue Retries", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_H_INGRESS_RETRY_OTHER1_RETRY.SF_WAY", "PerPkg": "1", @@ -2455,6 +2762,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_REQ_VN0", "PerPkg": "1", @@ -2463,6 +2771,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AD_RSP_VN0", "PerPkg": "1", @@ -2471,6 +2780,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.AK_NON_UPI", "PerPkg": "1", @@ -2479,6 +2789,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCB_VN0", "PerPkg": "1", @@ -2487,6 +2798,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_NCS_VN0", "PerPkg": "1", @@ -2495,6 +2807,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_RSP_VN0", "PerPkg": "1", @@ -2503,6 +2816,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.BL_WB_VN0", "PerPkg": "1", @@ -2511,6 +2825,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_H_INGRESS_RETRY_PRQ0_REJECT.IV_NON_UPI", "PerPkg": "1", @@ -2519,6 +2834,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ALLOW_SNP", "PerPkg": "1", @@ -2527,6 +2843,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.ANY_REJECT_IRQ0", "PerPkg": "1", @@ -2535,6 +2852,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.PA_MATCH", "PerPkg": "1", @@ -2543,6 +2861,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_VICTIM", "PerPkg": "1", @@ -2551,6 +2870,7 @@ }, { "BriefDescription": "Ingress Request Queue Rejects", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_H_INGRESS_RETRY_PRQ1_REJECT.SF_WAY", "PerPkg": "1", @@ -2559,6 +2879,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_REQ_VN0", "PerPkg": "1", @@ -2567,6 +2888,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AD_RSP_VN0", "PerPkg": "1", @@ -2575,6 +2897,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.AK_NON_UPI", "PerPkg": "1", @@ -2583,6 +2906,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCB_VN0", "PerPkg": "1", @@ -2591,6 +2915,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_NCS_VN0", "PerPkg": "1", @@ -2599,6 +2924,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_RSP_VN0", "PerPkg": "1", @@ -2607,6 +2933,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.BL_WB_VN0", "PerPkg": "1", @@ -2615,6 +2942,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q0_RETRY.IV_NON_UPI", "PerPkg": "1", @@ -2623,6 +2951,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ALLOW_SNP", "PerPkg": "1", @@ -2631,6 +2960,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.ANY_REJECT_IRQ0", "PerPkg": "1", @@ -2639,6 +2969,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.PA_MATCH", "PerPkg": "1", @@ -2647,6 +2978,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_VICTIM", "PerPkg": "1", @@ -2655,6 +2987,7 @@ }, { "BriefDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (= everything except for ISMQ)", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_H_INGRESS_RETRY_REQ_Q1_RETRY.SF_WAY", "PerPkg": "1", @@ -2663,6 +2996,7 @@ }, { "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch= Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_MISS", "PerPkg": "1", @@ -2671,6 +3005,7 @@ }, { "BriefDescription": "Miscellaneous events in the Cbo. CV0 Prefetch= Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_VIC", "PerPkg": "1", @@ -2679,6 +3014,7 @@ }, { "BriefDescription": "Miscellaneous events in the Cbo. RFO HitS", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_H_MISC.RFO_HIT_S", "PerPkg": "1", @@ -2687,6 +3023,7 @@ }, { "BriefDescription": "Miscellaneous events in the Cbo. Silent Snoop= Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_H_MISC.RSPI_WAS_FSE", "PerPkg": "1", @@ -2695,6 +3032,7 @@ }, { "BriefDescription": "Miscellaneous events in the Cbo. Write Combin= ing Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_H_MISC.WC_ALIASING", "PerPkg": "1", @@ -2703,6 +3041,7 @@ }, { "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", "PerPkg": "1", @@ -2711,6 +3050,7 @@ }, { "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", "PerPkg": "1", @@ -2719,6 +3059,7 @@ }, { "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Data Responses to core.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", "PerPkg": "1", @@ -2727,6 +3068,7 @@ }, { "BriefDescription": "Number of incoming messages from the Horizont= al ring that were bounced, by ring type - Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", "PerPkg": "1", @@ -2735,6 +3077,7 @@ }, { "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AD", "PerPkg": "1", @@ -2743,6 +3086,7 @@ }, { "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AK", "PerPkg": "1", @@ -2751,6 +3095,7 @@ }, { "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Data Responses to core.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.BL", "PerPkg": "1", @@ -2759,6 +3104,7 @@ }, { "BriefDescription": "Number of incoming messages from the Vertical= ring that were bounced, by ring type - Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.IV", "PerPkg": "1", @@ -2767,6 +3113,7 @@ }, { "BriefDescription": "Horizontal ring sink starvation count - AD ri= ng", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", "PerPkg": "1", @@ -2775,6 +3122,7 @@ }, { "BriefDescription": "Horizontal ring sink starvation count - AK ri= ng", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", "PerPkg": "1", @@ -2783,6 +3131,7 @@ }, { "BriefDescription": "Horizontal ring sink starvation count - BL ri= ng", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", "PerPkg": "1", @@ -2791,6 +3140,7 @@ }, { "BriefDescription": "Horizontal ring sink starvation count - IV ri= ng", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", "PerPkg": "1", @@ -2799,6 +3149,7 @@ }, { "BriefDescription": "Vertical ring sink starvation count - AD ring= ", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", "PerPkg": "1", @@ -2807,6 +3158,7 @@ }, { "BriefDescription": "Vertical ring sink starvation count - AK ring= ", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", "PerPkg": "1", @@ -2815,6 +3167,7 @@ }, { "BriefDescription": "Vertical ring sink starvation count - BL ring= ", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", "PerPkg": "1", @@ -2823,6 +3176,7 @@ }, { "BriefDescription": "Vertical ring sink starvation count - IV ring= ", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", "PerPkg": "1", @@ -2831,6 +3185,7 @@ }, { "BriefDescription": "Counts cycles in throttle mode.", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_H_RING_SRC_THRTL", "PerPkg": "1", @@ -2838,6 +3193,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for any transaction originating from the IPQ or = IRQ. This does not include lookups originating from the ISMQ.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_SF_LOOKUP.ANY", "PerPkg": "1", @@ -2846,6 +3202,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Read transactions", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_SF_LOOKUP.DATA_READ", "PerPkg": "1", @@ -2854,6 +3211,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Filters for only snoop requests coming from the remote s= ocket(s) through the IPQ.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_SF_LOOKUP.REMOTE_SNOOP", "PerPkg": "1", @@ -2862,6 +3220,7 @@ }, { "BriefDescription": "Cache Lookups. Counts the number of times the= LLC was accessed. Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_H_SF_LOOKUP.WRITE", "PerPkg": "1", @@ -2870,6 +3229,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_BNC", "PerPkg": "1", @@ -2878,6 +3238,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.AD_CRD", "PerPkg": "1", @@ -2886,6 +3247,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_BNC", "PerPkg": "1", @@ -2894,6 +3256,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, because a message from the other queue has higher priorit= y", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_H_TG_INGRESS_BUSY_STARVED.BL_CRD", "PerPkg": "1", @@ -2902,6 +3265,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_BNC", "PerPkg": "1", @@ -2910,6 +3274,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.AD_CRD", "PerPkg": "1", @@ -2918,6 +3283,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.AK_BNC", "PerPkg": "1", @@ -2926,6 +3292,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_BNC", "PerPkg": "1", @@ -2934,6 +3301,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.BL_CRD", "PerPkg": "1", @@ -2942,6 +3310,7 @@ }, { "BriefDescription": "Transgress Ingress Bypass. Number of packets = bypassing the CMS Ingress .", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_H_TG_INGRESS_BYPASS.IV_BNC", "PerPkg": "1", @@ -2950,6 +3319,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_BNC", "PerPkg": "1", @@ -2958,6 +3328,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AD_CRD", "PerPkg": "1", @@ -2966,6 +3337,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.AK_BNC", "PerPkg": "1", @@ -2974,6 +3346,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_BNC", "PerPkg": "1", @@ -2982,6 +3355,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.BL_CRD", "PerPkg": "1", @@ -2990,6 +3364,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IFV", "PerPkg": "1", @@ -2998,6 +3373,7 @@ }, { "BriefDescription": "Transgress Injection Starvation. Counts cycle= s under injection starvation mode. This starvation is triggered when the C= MS Ingress cannot send a transaction onto the mesh for a long period of tim= e. In this case, the Ingress is unable to forward to the Egress due to a l= ack of credit.", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_H_TG_INGRESS_CRD_STARVED.IV_BNC", "PerPkg": "1", @@ -3006,6 +3382,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_BNC", "PerPkg": "1", @@ -3014,6 +3391,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.AD_CRD", "PerPkg": "1", @@ -3022,6 +3400,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.AK_BNC", "PerPkg": "1", @@ -3030,6 +3409,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_BNC", "PerPkg": "1", @@ -3038,6 +3418,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.BL_CRD", "PerPkg": "1", @@ -3046,6 +3427,7 @@ }, { "BriefDescription": "Transgress Ingress Allocations. Number of all= ocations into the CMS Ingress The Ingress is used to queue up requests rec= eived from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_H_TG_INGRESS_INSERTS.IV_BNC", "PerPkg": "1", @@ -3054,6 +3436,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_BNC", "PerPkg": "1", @@ -3062,6 +3445,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AD_CRD", "PerPkg": "1", @@ -3070,6 +3454,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.AK_BNC", "PerPkg": "1", @@ -3078,6 +3463,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_BNC", "PerPkg": "1", @@ -3086,6 +3472,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.BL_CRD", "PerPkg": "1", @@ -3094,6 +3481,7 @@ }, { "BriefDescription": "Transgress Ingress Occupancy. Occupancy event= for the Ingress buffers in the CMS The Ingress is used to queue up reques= ts received from the mesh", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_H_TG_INGRESS_OCCUPANCY.IV_BNC", "PerPkg": "1", @@ -3102,6 +3490,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -SF= /LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.EVICT", "PerPkg": "1", @@ -3110,6 +3499,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -Hi= t (Not a Miss)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.HIT", "PerPkg": "1", @@ -3118,6 +3508,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IP= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.IPQ", "PerPkg": "1", @@ -3126,6 +3517,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -IR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.IRQ", "PerPkg": "1", @@ -3134,6 +3526,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -Mi= ss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.MISS", "PerPkg": "1", @@ -3142,6 +3535,7 @@ }, { "BriefDescription": "Counts the number of entries successfully ins= erted into the TOR that match qualifications specified by the subevent -PR= Q", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_H_TOR_INSERTS.PRQ", "PerPkg": "1", @@ -3150,6 +3544,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.EVICT", "PerPkg": "1", @@ -3158,6 +3553,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -Hit (Not a Miss)", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.HIT", "PerPkg": "1", @@ -3166,6 +3562,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IPQ", "PerPkg": "1", @@ -3174,6 +3571,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IPQ hit", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_HIT", "PerPkg": "1", @@ -3182,6 +3580,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IPQ miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IPQ_MISS", "PerPkg": "1", @@ -3190,6 +3589,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IRQ or PRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IRQ", "PerPkg": "1", @@ -3198,6 +3598,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IRQ or PRQ hit", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_HIT", "PerPkg": "1", @@ -3206,6 +3607,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -IRQ or PRQ miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.IRQ_MISS", "PerPkg": "1", @@ -3214,6 +3616,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.MISS", "PerPkg": "1", @@ -3222,6 +3625,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -PRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.PRQ", "PerPkg": "1", @@ -3230,6 +3634,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -PRQ hit", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_HIT", "PerPkg": "1", @@ -3238,6 +3643,7 @@ }, { "BriefDescription": "For each cycle, this event accumulates the nu= mber of valid entries in the TOR that match qualifications specified by the= subevent -PRQ miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_H_TOR_OCCUPANCY.PRQ_MISS", "PerPkg": "1", @@ -3246,12 +3652,14 @@ }, { "BriefDescription": "Uncore Clocks", + "Counter": "0,1,2,3", "EventName": "UNC_H_U_CLOCKTICKS", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", "PerPkg": "1", @@ -3260,6 +3668,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", "PerPkg": "1", @@ -3268,6 +3677,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", "PerPkg": "1", @@ -3276,6 +3686,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AD ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", "PerPkg": "1", @@ -3284,6 +3695,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", "PerPkg": "1", @@ -3292,6 +3704,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", "PerPkg": "1", @@ -3300,6 +3713,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", "PerPkg": "1", @@ -3308,6 +3722,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= AK ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", "PerPkg": "1", @@ -3316,6 +3731,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", "PerPkg": "1", @@ -3324,6 +3740,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", "PerPkg": "1", @@ -3332,6 +3749,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", "PerPkg": "1", @@ -3340,6 +3758,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= BL ring is being used at this ring stop - Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", "PerPkg": "1", @@ -3348,6 +3767,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= IV ring is being used at this ring stop - Down", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", "PerPkg": "1", @@ -3356,6 +3776,7 @@ }, { "BriefDescription": "Counts the number of cycles that the Vertical= IV ring is being used at this ring stop - Up", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json b= /tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json index 898f7e425cd4..7df7650e1a57 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AD_0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_0", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AD_1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AD_1", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AK_0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_0", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. AK_1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.AK_1", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. BL_0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_0", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full. Counts the numbe= r of cycles when the M2PCIe Egress is full. BL_1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_EGRESS_CYCLES_FULL.BL_1", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AD_0", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_0", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AD_1", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AD_1", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AK_0", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_0", "PerPkg": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. AK_1", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.AK_1", "PerPkg": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. BL_0", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_0", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty. Counts the = number of cycles when the M2PCIe Egress is not empty. BL_1", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_EGRESS_CYCLES_NE.BL_1", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AD_0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AD_0", "PerPkg": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AD_1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AD_1", "PerPkg": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AK_0", "PerPkg": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AK_1", "PerPkg": "1", @@ -129,6 +145,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_CRD_0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_0", "PerPkg": "1", @@ -137,6 +154,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. AK_CRD_1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.AK_CRD_1", "PerPkg": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. BL_0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.BL_0", "PerPkg": "1", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Egress (to CMS) Ingress. Counts the number of= number of messages inserted into the the M2PCIe Egress queue. BL_1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_EGRESS_INSERTS.BL_1", "PerPkg": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.ALL", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_INGRESS_CYCLES_NE.ALL", "PerPkg": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_IDI", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_IDI", "PerPkg": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_NCB", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCB", "PerPkg": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "Ingress Queue Cycles Not Empty. Counts the nu= mber of cycles when the M2PCIe Ingress is not empty.CBO_NCS", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_INGRESS_CYCLES_NE.CBO_NCS", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.js= on b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json index fb752974179b..f137dfde8481 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of read requests and stream= ing stores that hit in MCDRAM cache and the data in MCDRAM is clean with re= spect to DDR. This event is only valid in cache and hybrid memory mode.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_EDC_ACCESS.HIT_CLEAN", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of read requests and stream= ing stores that hit in MCDRAM cache and the data in MCDRAM is dirty with re= spect to DDR. This event is only valid in cache and hybrid memory mode.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_EDC_ACCESS.HIT_DIRTY", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of read requests and stream= ing stores that miss in MCDRAM cache and the data evicted from the MCDRAM i= s clean with respect to DDR. This event is only valid in cache and hybrid m= emory mode.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_EDC_ACCESS.MISS_CLEAN", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of read requests and stream= ing stores that miss in MCDRAM cache and the data evicted from the MCDRAM i= s dirty with respect to DDR. This event is only valid in cache and hybrid m= emory mode.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_EDC_ACCESS.MISS_DIRTY", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of EDC Hits or Misses. Miss I", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_EDC_ACCESS.MISS_INVALID", "PerPkg": "1", @@ -41,12 +46,14 @@ }, { "BriefDescription": "ECLK count", + "Counter": "0,1,2,3", "EventName": "UNC_E_E_CLOCKTICKS", "PerPkg": "1", "Unit": "EDC_ECLK" }, { "BriefDescription": "Counts the number of read requests received b= y the MCDRAM controller. This event is valid in all three memory modes: fla= t, cache and hybrid. In cache and hybrid memory mode, this event counts all= read requests as well as streaming stores that hit or miss in the MCDRAM c= ache.", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_E_RPQ_INSERTS", "PerPkg": "1", @@ -55,12 +62,14 @@ }, { "BriefDescription": "UCLK count", + "Counter": "0,1,2,3", "EventName": "UNC_E_U_CLOCKTICKS", "PerPkg": "1", "Unit": "EDC_UCLK" }, { "BriefDescription": "Counts the number of write requests received = by the MCDRAM controller. This event is valid in all three memory modes: fl= at, cache and hybrid. In cache and hybrid memory mode, this event counts al= l streaming stores, writebacks and, read requests that miss in MCDRAM cache= .", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_E_WPQ_INSERTS", "PerPkg": "1", @@ -69,6 +78,7 @@ }, { "BriefDescription": "CAS All", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -77,6 +87,7 @@ }, { "BriefDescription": "CAS Reads", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -85,6 +96,7 @@ }, { "BriefDescription": "CAS Writes", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -93,12 +105,14 @@ }, { "BriefDescription": "DCLK count", + "Counter": "0,1,2,3", "EventName": "UNC_M_D_CLOCKTICKS", "PerPkg": "1", "Unit": "iMC_DCLK" }, { "BriefDescription": "UCLK count", + "Counter": "0,1,2,3", "EventName": "UNC_M_U_CLOCKTICKS", "PerPkg": "1", "Unit": "iMC_UCLK" diff --git a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.j= son b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json index 9be30a33b43b..cf3c5f4f4fb7 100644 --- a/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/knightslanding/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of load micro-ops retired t= hat cause a DTLB miss (Precise Event)", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts the total number of core cycles for al= l the page walks. The cycles for page walks started in speculative path wil= l also be included.", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.CYCLES", "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts the total number of core cycles for al= l the D-side page walks. The cycles for page walks started in speculative p= ath will also be included.", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "SampleAfterValue": "200003", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the total D-side page walks that are c= ompleted or started. The page walks started in the speculative path will al= so be counted", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_WALKS", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the total number of core cycles for al= l the I-side page walks. The cycles for page walks started in speculative p= ath will also be included.", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "PublicDescription": "This event counts every cycle when an I-side= (walks due to an instruction fetch) page walk is in progress.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the total I-side page walks that are c= ompleted.", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_WALKS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the total page walks that are complete= d (I-side and D-side)", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.WALKS", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 479F61BA080 for ; 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Thu, 20 Jun 2024 11:20:05 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:36 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-23-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 22/37] perf vendor events: Add lunarlake counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/lunarlake/cache.json | 20 +++++++++++ .../arch/x86/lunarlake/frontend.json | 3 ++ .../pmu-events/arch/x86/lunarlake/memory.json | 15 ++++++++ .../pmu-events/arch/x86/lunarlake/other.json | 6 ++++ .../arch/x86/lunarlake/pipeline.json | 36 +++++++++++++++++++ .../arch/x86/lunarlake/virtual-memory.json | 6 ++++ 6 files changed, 86 insertions(+) diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/lunarlake/cache.json index fb48be357c4e..759714618e08 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of L2 Cache Accesses Counts= the total number of L2 Cache Accesses - sum of hits, misses, rejects fron= t door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts the number of L2 Cache Accesses Count= s the total number of L2 Cache Accesses - sum of hits, misses, rejects fro= nt door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -68,6 +75,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -78,6 +86,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -88,6 +97,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", @@ -100,6 +110,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", @@ -124,6 +136,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", @@ -136,6 +149,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", @@ -148,6 +162,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", @@ -160,6 +175,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", @@ -172,6 +188,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", @@ -184,6 +201,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", @@ -196,6 +214,7 @@ }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", @@ -208,6 +227,7 @@ }, { "BriefDescription": "Counts the number of stores uops retired sam= e as MEM_UOPS_RETIRED.ALL_STORES", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json b/tools= /perf/pmu-events/arch/x86/lunarlake/frontend.json index 3a24934e8d6e..0327bece0f94 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump and the instruction cache registers bytes are not present= . -", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", @@ -17,6 +19,7 @@ }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were no operation was delivered to the back-end pipeline due = to instruction fetch limitations when the back-end could have accepted more= operations. Common examples include instruction cache misses or x86 instru= ction decode limitations.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were no operation was delivered to the back-end pipeline due= to instruction fetch limitations when the back-end could have accepted mor= e operations. Common examples include instruction cache misses or x86 instr= uction decode limitations. Software can use this event as the numerator for= the Frontend Bound metric (or top-level category) of the Top-down Microarc= hitecture Analysis method.", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/memory.json b/tools/p= erf/pmu-events/arch/x86/lunarlake/memory.json index 9c188d80b7b9..3d12e226d5ef 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", @@ -14,6 +15,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -27,6 +29,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -40,6 +43,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 2048 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", @@ -53,6 +57,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -66,6 +71,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -79,6 +85,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -92,6 +99,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -105,6 +113,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -118,6 +127,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -131,6 +141,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -142,6 +153,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +164,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -162,6 +175,7 @@ }, { "BriefDescription": "Counts demand reads for ownership, including = SWPREFETCHW which is an RFO were not supplied by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -172,6 +186,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that were no= t supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/other.json b/tools/pe= rf/pmu-events/arch/x86/lunarlake/other.json index 377f717db6cc..0b49b4684c4b 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/other.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts cacheable demand data reads Catch all = value for any response types - this includes response types not define in t= he OCR. If this is set all other response types will be ignored", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -11,6 +12,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -21,6 +23,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads were suppl= ied by DRAM.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -31,6 +34,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Counts demand reads for ownership, including = SWPREFETCHW which is an RFO Catch all value for any response types - this i= ncludes response types not define in the OCR. If this is set all other res= ponse types will be ignored", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +56,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that have an= y type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/lunarlake/pipeline.json index 2c9f85ec8c4a..220c2115fec9 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000003", "UMask": "0x2", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Core cycles when the core is not in a halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. This event is a component in many key event ratios.= The core frequency may change from time to time due to transitions associa= ted with Enhanced Intel SpeedStep Technology or TM2. For this reason this e= vent may have a changing ratio with regards to time. When the core frequenc= y is constant, this event can approximate elapsed time while the core was n= ot in the halt state. It is counted on a dedicated fixed counter, leaving t= he programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000003", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", @@ -100,6 +112,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in a halt = state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003", @@ -122,6 +137,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P]", @@ -130,6 +146,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "SampleAfterValue": "2000003", @@ -138,6 +155,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Counts the number of instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -164,6 +184,7 @@ }, { "BriefDescription": "Counts the number of occurrences a retired lo= ad gets blocked because its address partially overlaps with an older store = (size mismatch) - unknown_sta/bad_forward", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "1", @@ -173,6 +194,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -182,6 +204,7 @@ }, { "BriefDescription": "Counts the number of LBR entries recorded. Re= quires LBRs to be enabled in IA32_LBR_CTL.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBS": "1", @@ -191,6 +214,7 @@ }, { "BriefDescription": "LBR record is inserted", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", "PEBS": "1", @@ -200,6 +224,7 @@ }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were not consumed by the back-end pipeline due to lack of bac= k-end resources, as a result of memory subsystem delays, execution units li= mitations, or other conditions.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were not consumed by the back-end pipeline due to lack of ba= ck-end resources, as a result of memory subsystem delays, execution units l= imitations, or other conditions. Software can use this event as the numerat= or for the Backend Bound metric (or top-level category) of the Top-down Mic= roarchitecture Analysis method.", @@ -209,6 +234,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = Software can use this event as the denominator for the top-level metrics of= the TMA method. This architectural event is counted on a designated fixed = counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -217,6 +243,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod.", @@ -226,6 +253,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "SampleAfterValue": "1000003", @@ -233,6 +261,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", "SampleAfterValue": "1000003", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003", @@ -248,6 +278,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN_BE_BOUND.ALL_P", "SampleAfterValue": "1000003", @@ -256,6 +287,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of retiremen= t slots not consumed due to front end stalls", + "Counter": "37", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003", "UMask": "0x6", @@ -263,6 +295,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "TOPDOWN_FE_BOUND.ALL_P", "SampleAfterValue": "1000003", @@ -271,6 +304,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of consumed = retirement slots.", + "Counter": "38", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", "SampleAfterValue": "1000003", @@ -279,6 +313,7 @@ }, { "BriefDescription": "Counts the number of consumed retirement slot= s.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL_P", "PEBS": "1", @@ -288,6 +323,7 @@ }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that are utilized by operations that eventually get retired (commi= tted) by the processor pipeline. Usually, this event positively correlates = with higher performance for example, as measured by the instructions-per-c= ycle metric.", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that are utilized by operations that eventually get retired (comm= itted) by the processor pipeline. Usually, this event positively correlates= with higher performance for example, as measured by the instructions-per-= cycle metric. Software can use this event as the numerator for the Retiring= metric (or top-level category) of the Top-down Microarchitecture Analysis = method.", diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/lunarlake/virtual-memory.json index bb9458799f1c..59af79e3466e 100644 --- a/tools/perf/pmu-events/arch/x86/lunarlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/lunarlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3,4,5,6,7,8,9", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. 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Bring in the event updates v1.10: https://github.com/intel/perfmon/commit/3bee3dc150164df0bec5980ca5586930730= e5778 v1.09: https://github.com/intel/perfmon/commit/01c8c99f17a72460b2eaf7efe3495913f36= c9d42 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ New events are: EXE_ACTIVITY.2_3_PORTS_UTIL, FP_INST_RETIRED.128B_DP, FP_INST_RETIRED.128B_SP, FP_INST_RETIRED.256B_DP, FP_INST_RETIRED.32B_SP, FP_INST_RETIRED.64B_DP, FP_VINT_UOPS_EXECUTED.STD, L2_LINES_OUT.USELESS_HWPF, L2_RQSTS.SWPF_HIT, L2_RQSTS.SWPF_MISS, LOAD_HIT_PREFETCH.SWPF, MACHINE_CLEARS.ANY, MACHINE_CLEARS.MRN_NUKE, MISC_RETIRED.LBR_INSERTS, SW_PREFETCH_ACCESS.ANY. The metrics aren't updated as they require retirement latency support that is added in this series: https://lore.kernel.org/lkml/20240613033631.199800-1-weilin.wang@intel.com/ Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/meteorlake/cache.json | 223 +++++++++---- .../arch/x86/meteorlake/floating-point.json | 86 ++++- .../arch/x86/meteorlake/frontend.json | 69 ++-- .../arch/x86/meteorlake/memory.json | 62 ++-- .../pmu-events/arch/x86/meteorlake/other.json | 19 +- .../arch/x86/meteorlake/pipeline.json | 300 ++++++++++++++---- .../arch/x86/meteorlake/uncore-cache.json | 2 + .../x86/meteorlake/uncore-interconnect.json | 8 + .../arch/x86/meteorlake/uncore-memory.json | 16 + .../arch/x86/meteorlake/uncore-other.json | 1 + .../arch/x86/meteorlake/virtual-memory.json | 37 +++ 12 files changed, 641 insertions(+), 184 deletions(-) diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 9056784e23f7..1040f68fee94 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -21,7 +21,7 @@ GenuineIntel-6-3E,v24,ivytown,core GenuineIntel-6-2D,v24,jaketown,core GenuineIntel-6-(57|85),v16,knightslanding,core GenuineIntel-6-BD,v1.01,lunarlake,core -GenuineIntel-6-A[AC],v1.08,meteorlake,core +GenuineIntel-6-A[AC],v1.10,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-6-A7,v1.02,rocketlake,core diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/cache.json index af7acb15f661..908e3c7f6d6e 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.HWPF_MISS", "SampleAfterValue": "1000003", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -38,6 +42,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALLS", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -47,6 +52,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -56,6 +62,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -66,6 +73,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -75,6 +83,7 @@ }, { "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", @@ -84,6 +93,7 @@ }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -91,8 +101,19 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", + "EventCode": "0x26", + "EventName": "L2_LINES_OUT.USELESS_HWPF", + "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", + "SampleAfterValue": "200003", + "UMask": "0x4", + "Unit": "cpu_core" + }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_RQSTS.REFERENCES]", @@ -102,6 +123,7 @@ }, { "BriefDescription": "All requests that hit L2 cache. [This event i= s alias to L2_RQSTS.HIT]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.HIT", "PublicDescription": "Counts all requests that hit L2 cache. [This= event is alias to L2_RQSTS.HIT]", @@ -111,6 +133,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache [Thi= s event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_RQSTS.MISS]", @@ -120,6 +143,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -129,6 +153,7 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", @@ -138,6 +163,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -147,6 +173,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts demand requests to L2 cache.", @@ -156,6 +183,7 @@ }, { "BriefDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_HWPF", "SampleAfterValue": "200003", @@ -164,6 +192,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -173,6 +202,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -182,6 +212,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -191,6 +222,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -200,6 +232,7 @@ }, { "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", @@ -209,6 +242,7 @@ }, { "BriefDescription": "All requests that hit L2 cache. [This event i= s alias to L2_REQUEST.HIT]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.HIT", "PublicDescription": "Counts all requests that hit L2 cache. [This= event is alias to L2_REQUEST.HIT]", @@ -218,6 +252,7 @@ }, { "BriefDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.HWPF_MISS", "SampleAfterValue": "200003", @@ -226,6 +261,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache [Thi= s event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_REQUEST.MISS]", @@ -235,6 +271,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_REQUEST.ALL]", @@ -244,6 +281,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -253,6 +291,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -260,8 +299,29 @@ "UMask": "0x22", "Unit": "cpu_core" }, + { + "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_HIT", + "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", + "SampleAfterValue": "200003", + "UMask": "0xc8", + "Unit": "cpu_core" + }, + { + "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", + "EventCode": "0x24", + "EventName": "L2_RQSTS.SWPF_MISS", + "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", + "SampleAfterValue": "200003", + "UMask": "0x28", + "Unit": "cpu_core" + }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -271,6 +331,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", @@ -280,15 +341,17 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= core has access to an L3 cache, the LLC is the L3 cache, otherwise it is t= he L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41", "Unit": "cpu_atom" }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -298,15 +361,17 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th= e L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f", "Unit": "cpu_atom" }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -316,6 +381,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an instruction cache or TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", "SampleAfterValue": "1000003", @@ -324,6 +390,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -333,6 +400,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", "SampleAfterValue": "1000003", @@ -341,6 +409,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which missed all the caches.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", "SampleAfterValue": "1000003", @@ -349,6 +418,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an L1 demand load miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.ALL", "SampleAfterValue": "1000003", @@ -357,6 +427,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the L2 cache.", @@ -366,6 +437,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", "SampleAfterValue": "1000003", @@ -374,6 +446,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which missed all the local cache= s.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", "SampleAfterValue": "1000003", @@ -382,6 +455,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -393,6 +467,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -404,6 +479,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -415,6 +491,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -426,6 +503,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -437,6 +515,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -448,6 +527,7 @@ }, { "BriefDescription": "Retired load instructions that hit the STLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS", @@ -459,6 +539,7 @@ }, { "BriefDescription": "Retired store instructions that hit the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES", @@ -470,6 +551,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -481,6 +563,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -492,6 +575,7 @@ }, { "BriefDescription": "Completed demand load uops that miss the L1 d= -cache.", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "PublicDescription": "Number of completed demand load requests tha= t missed the L1 data cache including shadow misses (FB hits, merge to an on= going L1D miss)", @@ -501,6 +585,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -510,30 +595,9 @@ "UMask": "0x4", "Unit": "cpu_core" }, - { - "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions whose data = sources were L3 and cross-core snoop hits in on-pkg core cache.", - "SampleAfterValue": "20011", - "UMask": "0x2", - "Unit": "cpu_core" - }, - { - "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", - "Data_LA": "1", - "EventCode": "0xd2", - "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", - "PEBS": "1", - "PublicDescription": "Counts retired load instructions whose data = sources were HitM responses from shared L3.", - "SampleAfterValue": "20011", - "UMask": "0x4", - "Unit": "cpu_core" - }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -545,6 +609,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -556,6 +621,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -567,6 +633,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -578,6 +645,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -589,6 +657,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -600,6 +669,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -611,6 +681,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -622,6 +693,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -633,6 +705,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -644,6 +717,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -655,6 +729,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -666,69 +741,70 @@ }, { "BriefDescription": "Counts the number of load ops retired that mi= ss the L3 cache and hit in DRAM", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd4", "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LOCAL_DRAM", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load ops retired that hi= t the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x40", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1c", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of loads that hit in a writ= e combining buffer (WCB), excluding the first load that caused the WCB to a= llocate.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x20", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked for any of the following reasons: load buffer, store buffer or RSV fu= ll.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ALL", "SampleAfterValue": "20003", @@ -737,6 +813,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", "SampleAfterValue": "20003", @@ -745,6 +822,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.RSV", "SampleAfterValue": "20003", @@ -753,6 +831,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", "SampleAfterValue": "20003", @@ -761,6 +840,7 @@ }, { "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "MEM_STORE_RETIRED.L2_HIT", "SampleAfterValue": "200003", @@ -769,196 +849,197 @@ }, { "BriefDescription": "Counts the number of load ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x81", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of store ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x82", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", "MSRIndex": "0x3F6", "MSRValue": "0x400", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", "MSRIndex": "0x3F6", "MSRValue": "0x800", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x21", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x43", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x41", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x42", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of stores uops retired sam= e as MEM_UOPS_RETIRED.ALL_STORES", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x6", "Unit": "cpu_atom" }, { "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe5", "EventName": "MEM_UOP_RETIRED.ANY", "PublicDescription": "Number of retired micro-operations (uops) fo= r load or store memory accesses", @@ -968,6 +1049,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -978,6 +1060,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -988,6 +1071,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another cores caches, data forwarding is required as the data i= s modified.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -998,6 +1082,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1008,6 +1093,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1018,6 +1104,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another cores caches which forwarded the unmodified data to the= requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1028,6 +1115,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1038,6 +1126,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1048,6 +1137,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that resulte= d in a snoop hit in another cores caches, data forwarding is required as th= e data is modified.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1148,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -1067,6 +1158,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -1076,6 +1168,7 @@ }, { "BriefDescription": "Cacheable and Non-Cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and Non-Cacheable code= read requests.", @@ -1085,6 +1178,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -1094,6 +1188,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -1103,6 +1198,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -1113,6 +1209,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -1123,6 +1220,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding demand da= ta read request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -1132,6 +1230,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -1142,6 +1241,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "SampleAfterValue": "1000003", @@ -1150,6 +1250,7 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -1159,6 +1260,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -1166,17 +1268,9 @@ "UMask": "0x1", "Unit": "cpu_core" }, - { - "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", - "CounterMask": "6", - "EventCode": "0x20", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", - "SampleAfterValue": "2000003", - "UMask": "0x1", - "Unit": "cpu_core" - }, { "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", @@ -1186,6 +1280,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -1193,8 +1288,18 @@ "UMask": "0x10", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf", + "Unit": "cpu_core" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -1204,6 +1309,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -1213,6 +1319,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -1222,6 +1329,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", @@ -1231,6 +1339,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to an icache miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json = b/tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json index 30e604d2120f..28dc5e06ee31 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the f= loating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.FPDIV_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "This event counts the cycles the floating poi= nt divider is busy.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.FPDIV_ACTIVE", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -28,6 +31,7 @@ }, { "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.SSE_AVX_MIX", "SampleAfterValue": "1000003", @@ -36,6 +40,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is ali= as to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_0", "SampleAfterValue": "2000003", @@ -44,6 +49,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is ali= as to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_1", "SampleAfterValue": "2000003", @@ -52,6 +58,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is ali= as to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_5", "SampleAfterValue": "2000003", @@ -60,6 +67,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V0", "SampleAfterValue": "2000003", @@ -68,6 +76,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V1", "SampleAfterValue": "2000003", @@ -76,6 +85,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V2", "SampleAfterValue": "2000003", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -93,6 +104,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -102,6 +114,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -120,6 +134,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -129,6 +144,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -138,6 +154,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -147,6 +164,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -156,6 +174,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "PublicDescription": "Number of any Vector retired FP arithmetic i= nstructions. The DAZ and FTZ flags in the MXCSR register need to be set wh= en using these events.", @@ -165,53 +184,108 @@ }, { "BriefDescription": "Counts the number of all types of floating po= int operations per uop with all default weighting", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x3", "Unit": "cpu_atom" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP64]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.DP", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 32 bit single precision results [This event is alias to FP_F= LOPS_RETIRED.SP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP32", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 64 bit double precision results [This event is alias to FP_F= LOPS_RETIRED.DP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP64", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP32]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.SP", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the total number of floating point re= tired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x8", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 128 bit single precision floating point. This may b= e SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x4", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 256 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.256B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x20", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 32bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.32B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 64 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.64B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x2", + "Unit": "cpu_atom" + }, + { + "BriefDescription": "Counts the number of uops executed on floatin= g point and vector integer store data port.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xb2", + "EventName": "FP_VINT_UOPS_EXECUTED.STD", + "SampleAfterValue": "1000003", + "UMask": "0x1", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -221,9 +295,9 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and sse, including x87 sqrt).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x8", "Unit": "cpu_atom" diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json b/tool= s/perf/pmu-events/arch/x86/meteorlake/frontend.json index f3b7b211afb5..b6c52f7385fc 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Clears due to Unknown Branches.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of times the front-end is resteered w= hen it finds a branch instruction in a fetch line. This is called Unknown B= ranch which occurs for the first time a branch instruction is fetched or wh= en the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.MS_BUSY", "SampleAfterValue": "500009", @@ -36,6 +40,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -43,16 +48,9 @@ "UMask": "0x2", "Unit": "cpu_core" }, - { - "BriefDescription": "DSB_FILL.FB_STALL_OT", - "EventCode": "0x62", - "EventName": "DSB_FILL.FB_STALL_OT", - "SampleAfterValue": "1000003", - "UMask": "0x10", - "Unit": "cpu_core" - }, { "BriefDescription": "Retired ANT branches", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_ANT", "MSRIndex": "0x3F7", @@ -65,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -77,6 +76,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -89,15 +89,16 @@ }, { "BriefDescription": "Counts the number of instructions retired tha= t were tagged because empty issue slots were seen before the uop due to ITL= B miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x10", "Unit": "cpu_atom" }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -110,6 +111,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -122,6 +124,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -134,6 +137,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -146,6 +150,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -158,6 +163,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -170,6 +176,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -182,6 +189,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -194,6 +202,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -206,6 +215,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -218,6 +228,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -230,6 +241,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -242,6 +254,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -254,6 +267,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -266,6 +280,7 @@ }, { "BriefDescription": "Mispredicted Retired ANT branches", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.MISP_ANT", "MSRIndex": "0x3F7", @@ -278,6 +293,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.MS_FLOWS", "MSRIndex": "0x3F7", @@ -289,6 +305,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -301,6 +318,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "MSRIndex": "0x3F7", @@ -312,6 +330,7 @@ }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -320,6 +339,7 @@ }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump and the instruction cache registers bytes are not present= . -", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", @@ -328,6 +348,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The decode pipeline works at a 32= Byte granularity.", @@ -337,6 +358,7 @@ }, { "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x80", @@ -345,17 +367,9 @@ "UMask": "0x4", "Unit": "cpu_core" }, - { - "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", - "EventCode": "0x83", - "EventName": "ICACHE_TAG.HIT", - "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", - "SampleAfterValue": "200003", - "UMask": "0x1", - "Unit": "cpu_core" - }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", @@ -365,6 +379,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -375,6 +390,7 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -385,6 +401,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -394,6 +411,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -404,6 +422,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -414,6 +433,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -423,6 +443,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -433,6 +454,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -444,6 +466,7 @@ }, { "BriefDescription": "Uops initiated by MITE or Decode Stream Buffe= r (DSB) and delivered to Instruction Decode Queue (IDQ) while Microcode Seq= uencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = or Decode Stream Buffer (DSB) and delivered to Instruction Decode Queue (ID= Q) while the Microcode Sequencer (MS) is busy. Counting includes uops that = may 'bypass' the IDQ.", @@ -452,16 +475,18 @@ "Unit": "cpu_core" }, { - "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were no operation was delivered to the back-end pipeline due = to instruction fetch limitations when the back-end could have accepted more= operations. Common examples include instruction cache misses or x86 instru= ction decode limitations.", + "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that when no operation was delivered to the back-end pipeline due = to instruction fetch limitations when the back-end could have accepted more= operations. Common examples include instruction cache misses or x86 instru= ction decode limitations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", - "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were no operation was delivered to the back-end pipeline due= to instruction fetch limitations when the back-end could have accepted mor= e operations. Common examples include instruction cache misses or x86 instr= uction decode limitations. The count may be distributed among unhalted logi= cal processors (hyper-threads) who share the same physical core, in process= ors that support Intel Hyper-Threading Technology. Software can use this ev= ent as the numerator for the Frontend Bound metric (or top-level category) = of the Top-down Microarchitecture Analysis method.", + "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that when no operation was delivered to the back-end pipeline due= to instruction fetch limitations when the back-end could have accepted mor= e operations. Common examples include instruction cache misses or x86 instr= uction decode limitations. The count may be distributed among unhalted logi= cal processors (hyper-threads) who share the same physical core, in process= ors that support Intel Hyper-Threading Technology. Software can use this ev= ent as the numerator for the Frontend Bound metric (or top-level category) = of the Top-down Microarchitecture Analysis method.", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_core" }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", @@ -472,6 +497,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", @@ -483,6 +509,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", @@ -492,6 +519,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -502,6 +530,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json b/tools/= perf/pmu-events/arch/x86/meteorlake/memory.json index 617d0e255fd5..b464a8ab32ca 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to any number of reasons, incl= uding an L1 miss, WCB full, pagewalk, store address block or store data blo= ck, on a load that retires.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ANY_AT_RET", "SampleAfterValue": "1000003", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to a core bound stall includin= g a store address match, a DTLB miss or a page walk that detains the load f= rom retiring.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_BOUND_AT_RET", "SampleAfterValue": "1000003", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_MISS_AT_RET", "SampleAfterValue": "1000003", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", "PublicDescription": "Counts the number of cycles that the head (o= ldest load) of the load buffer and retirement are both stalled due to other= block cases such as pipeline conflicts, fences, etc.", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a page= walk.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.PGWALK_AT_RET", "SampleAfterValue": "1000003", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a stor= e address match.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ST_ADDR_AT_RET", "SampleAfterValue": "1000003", @@ -68,6 +76,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", @@ -94,6 +105,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", @@ -103,6 +115,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", @@ -113,6 +126,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "9", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", @@ -121,24 +135,9 @@ "UMask": "0x9", "Unit": "cpu_core" }, - { - "BriefDescription": "MEMORY_ORDERING.MD_NUKE", - "EventCode": "0x09", - "EventName": "MEMORY_ORDERING.MD_NUKE", - "SampleAfterValue": "100003", - "UMask": "0x1", - "Unit": "cpu_core" - }, - { - "BriefDescription": "Counts the number of memory ordering machine = clears due to memory renaming.", - "EventCode": "0x09", - "EventName": "MEMORY_ORDERING.MRN_NUKE", - "SampleAfterValue": "100003", - "UMask": "0x2", - "Unit": "cpu_core" - }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", @@ -152,6 +151,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -165,6 +165,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -178,6 +179,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 2048 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_2048", @@ -191,6 +193,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -204,6 +207,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -217,6 +221,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -230,6 +235,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -243,6 +249,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -256,6 +263,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -269,6 +277,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -280,24 +289,25 @@ }, { "BriefDescription": "Counts misaligned loads that are 4K page spli= ts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2", "Unit": "cpu_atom" }, { "BriefDescription": "Counts misaligned stores that are 4K page spl= its.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x4", "Unit": "cpu_atom" }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -308,6 +318,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -318,6 +329,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -328,6 +340,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that were no= t supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -338,6 +351,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -346,6 +360,7 @@ }, { "BriefDescription": "Cycles where data return is pending for a Dem= and Data Read request who miss L3 cache.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -356,21 +371,12 @@ }, { "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known by the requesti= ng core to have missed the L3 cache.", "SampleAfterValue": "2000003", "UMask": "0x10", "Unit": "cpu_core" - }, - { - "BriefDescription": "Cycles where the core is waiting on at least = 6 outstanding demand data read requests known to have missed the L3 cache.", - "CounterMask": "6", - "EventCode": "0x20", - "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", - "PublicDescription": "Cycles where the core is waiting on at least= 6 outstanding demand data read requests known to have missed the L3 cache.= Note that this event does not capture all elapsed cycles while the reques= ts are outstanding - only cycles from when the requests were known to have = missed the L3 cache.", - "SampleAfterValue": "2000003", - "UMask": "0x10", - "Unit": "cpu_core" } ] diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/other.json b/tools/p= erf/pmu-events/arch/x86/meteorlake/other.json index 0bc2cb2eabb3..53d23d8decc6 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/other.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.PAGE_FAULT", "SampleAfterValue": "1000003", @@ -9,16 +10,17 @@ }, { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xe4", "EventName": "LBR_INSERTS.ANY", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -29,6 +31,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -39,6 +42,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -49,6 +53,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -59,6 +64,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +75,7 @@ }, { "BriefDescription": "Counts demand read for ownership (RFO) reques= ts and software prefetches for exclusive ownership (PREFETCHW) that have an= y type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -79,6 +86,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -89,6 +97,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -99,6 +108,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -109,6 +119,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", "EventName": "RS.EMPTY", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -118,6 +129,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xa5", @@ -129,7 +141,8 @@ "Unit": "cpu_core" }, { - "BriefDescription": "RS.EMPTY_RESOURCE", + "BriefDescription": "Cycles when RS was empty and a resource alloc= ation stall is asserted", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", "EventName": "RS.EMPTY_RESOURCE", "SampleAfterValue": "1000003", @@ -138,6 +151,7 @@ }, { "BriefDescription": "Counts the number of issue slots in a UMWAIT = or TPAUSE instruction where no uop issues due to the instruction putting th= e CPU into the C0.1 activity state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x75", "EventName": "SERIALIZATION.C01_MS_SCB", "SampleAfterValue": "200003", @@ -146,6 +160,7 @@ }, { "BriefDescription": "Cycles the uncore cannot take further request= s", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json b/tool= s/perf/pmu-events/arch/x86/meteorlake/pipeline.json index 5ff4a7a32250..bc806c7330f4 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the d= ividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.DIV_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.DIV_ACTIVE", @@ -20,6 +22,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divi= der is busy.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware. Examples include AD (page Access Dirt= y), FP and AVX related assists.", @@ -38,15 +42,16 @@ }, { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of instructions in w= hich the instruction pointer (IP) of the processor is resteered due to a br= anch instruction and the branch instruction successfully retires. All bran= ch type instructions are accounted for.", "SampleAfterValue": "200003", "Unit": "cpu_atom" }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -56,15 +61,16 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e", "Unit": "cpu_atom" }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -75,6 +81,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -85,15 +92,16 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe", "Unit": "cpu_atom" }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -104,15 +112,16 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xbf", "Unit": "cpu_atom" }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -123,15 +132,16 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb", "Unit": "cpu_atom" }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -142,34 +152,35 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb", "Unit": "cpu_atom" }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf9", "Unit": "cpu_atom" }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -180,15 +191,16 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7", "Unit": "cpu_atom" }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -199,6 +211,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -209,15 +222,16 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of mispredicted bran= ch instructions retired. All branch type instructions are accounted for. = Prediction of the branch target address enables the processor to begin exec= uting instructions before the non-speculative execution path is known. The = branch prediction unit (BPU) predicts the target address based on the instr= uction pointer (IP) of the branch and on the execution path through which e= xecution reached this IP. A branch misprediction occurs when the predict= ion is wrong, and results in discarding all instructions executed in the sp= eculative path and re-fetching from the correct path.", "SampleAfterValue": "200003", "Unit": "cpu_atom" }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -227,6 +241,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= This precise event may be used to get the misprediction cost via the Retir= e_Latency field of PEBS. It fires on the instruction that immediately follo= ws the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_COST", "PEBS": "1", @@ -236,15 +251,16 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e", "Unit": "cpu_atom" }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -255,6 +271,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired. This precise event may be used to get the misprediction cost via t= he Retire_Latency field of PEBS. It fires on the instruction that immediate= ly follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_COST", "PEBS": "1", @@ -264,6 +281,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -274,6 +292,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired. This precise event may be used to get the misprediction = cost via the Retire_Latency field of PEBS. It fires on the instruction that= immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN_COST", "PEBS": "1", @@ -283,15 +302,16 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe", "Unit": "cpu_atom" }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -302,6 +322,7 @@ }, { "BriefDescription": "Mispredicted taken conditional branch instruc= tions retired. This precise event may be used to get the misprediction cost= via the Retire_Latency field of PEBS. It fires on the instruction that imm= ediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN_COST", "PEBS": "1", @@ -311,15 +332,16 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb", "Unit": "cpu_atom" }, { "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -330,15 +352,16 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb", "Unit": "cpu_atom" }, { "BriefDescription": "Mispredicted indirect CALL retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -349,6 +372,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL retired. This prec= ise event may be used to get the misprediction cost via the Retire_Latency = field of PEBS. It fires on the instruction that immediately follows the mis= predicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL_COST", "PEBS": "1", @@ -358,6 +382,7 @@ }, { "BriefDescription": "Mispredicted near indirect branch instruction= s retired (excluding returns). This precise event may be used to get the mi= sprediction cost via the Retire_Latency field of PEBS. It fires on the inst= ruction that immediately follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_COST", "PEBS": "1", @@ -367,15 +392,16 @@ }, { "BriefDescription": "Counts the number of mispredicted near taken = branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80", "Unit": "cpu_atom" }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -386,6 +412,7 @@ }, { "BriefDescription": "Mispredicted taken near branch instructions r= etired. This precise event may be used to get the misprediction cost via th= e Retire_Latency field of PEBS. It fires on the instruction that immediatel= y follows the mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN_COST", "PEBS": "1", @@ -395,6 +422,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -405,15 +433,16 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7", "Unit": "cpu_atom" }, { "BriefDescription": "Mispredicted ret instructions retired. This p= recise event may be used to get the misprediction cost via the Retire_Laten= cy field of PEBS. It fires on the instruction that immediately follows the = mispredicted branch.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET_COST", "PEBS": "1", @@ -423,6 +452,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 li= ght-weight slower wakeup time but more power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C01", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 light-weight slower wakeup time but more power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -432,6 +462,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.2 li= ght-weight faster wakeup time but less power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C02", "PublicDescription": "Counts core clocks when the thread is in the= C0.2 light-weight faster wakeup time but less power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -441,6 +472,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 or= C0.2 or running a PAUSE in C0 ACPI state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C0_WAIT", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions)= or running the PAUSE instruction.", @@ -450,6 +482,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000003", "UMask": "0x2", @@ -457,6 +490,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000003", @@ -464,6 +498,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -473,6 +508,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -482,6 +518,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.PAUSE", "SampleAfterValue": "2000003", @@ -490,6 +527,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xec", @@ -500,6 +538,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -509,6 +548,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3", @@ -516,6 +556,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the eight programmable counte= rs available for other events. Note: On all current platforms this event st= ops counting during 'throttling (TM)' states duty off periods the processor= is 'halted'. The counter update is done at a lower clock rate then the co= re clock the overflow status bit for this counter may appear 'sticky'. Aft= er the counter has overflowed and software clears the overflow status bit a= nd resets the counter to less than MAX. The reset value to the counter is n= ot clocked immediately so the overflow status bit will flip 'high (1)' and = generate another PMI (if enabled) after which the reset value gets clocked = into the counter. Therefore, software will get the interrupt, read the over= flow status bit '1 for bit 34 while the counter value is less than MAX. Sof= tware should ignore this case.", "SampleAfterValue": "2000003", @@ -524,6 +565,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -533,6 +575,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", @@ -542,6 +585,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2", @@ -549,6 +593,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -557,6 +602,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003", @@ -564,6 +610,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -572,6 +619,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -581,6 +629,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -590,6 +639,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -599,6 +649,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -608,6 +659,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -617,6 +669,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -626,6 +679,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -633,8 +687,18 @@ "UMask": "0x2", "Unit": "cpu_core" }, + { + "BriefDescription": "Cycles total of 2 or 3 uops are executed on a= ll ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "UMask": "0xc", + "Unit": "cpu_core" + }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -644,6 +708,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -653,6 +718,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -662,6 +728,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", @@ -671,6 +738,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -681,6 +749,7 @@ }, { "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", @@ -690,6 +759,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -699,6 +769,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "SampleAfterValue": "2000003", @@ -707,6 +778,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -716,14 +788,15 @@ }, { "BriefDescription": "Counts the number of instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", "SampleAfterValue": "2000003", "Unit": "cpu_atom" }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -733,6 +806,7 @@ }, { "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -742,6 +816,7 @@ }, { "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -752,6 +827,7 @@ }, { "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = precise distribution of samples across instructions retired. It utilizes th= e Precise Distribution of Instructions Retired (PDIR++) feature to fix bias= in how retired instructions get sampled. Use on Fixed Counter 0.", @@ -761,6 +837,7 @@ }, { "BriefDescription": "Iterations of Repeat string retired instructi= ons.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", "PEBS": "1", @@ -769,18 +846,9 @@ "UMask": "0x8", "Unit": "cpu_core" }, - { - "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "CounterMask": "1", - "EventCode": "0xad", - "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", - "PublicDescription": "Counts cycles the Backend cluster is recover= ing after a miss-speculation or a Store Buffer or Load Buffer drain stall.", - "SampleAfterValue": "2000003", - "UMask": "0x3", - "Unit": "cpu_core" - }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xad", @@ -792,6 +860,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -799,17 +868,9 @@ "UMask": "0x80", "Unit": "cpu_core" }, - { - "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread", - "EventCode": "0xad", - "EventName": "INT_MISC.RAT_STALLS", - "PublicDescription": "This event counts the number of cycles durin= g which Resource Allocation Table (RAT) external stall is sent to Instructi= on Decode Queue (IDQ) for the current thread. This also includes the cycles= during which the Allocator is serving another thread.", - "SampleAfterValue": "1000003", - "UMask": "0x8", - "Unit": "cpu_core" - }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -819,6 +880,7 @@ }, { "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", "MSRIndex": "0x3F7", @@ -829,6 +891,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -838,6 +901,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.128BIT", "SampleAfterValue": "1000003", @@ -846,6 +910,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.256BIT", "SampleAfterValue": "1000003", @@ -854,6 +919,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_128", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 128-bit vector instructions.", @@ -863,6 +929,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_256", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 256-bit vector instructions.", @@ -872,6 +939,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.MUL_256", "SampleAfterValue": "1000003", @@ -880,6 +948,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.SHUFFLES", "SampleAfterValue": "1000003", @@ -888,6 +957,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_128", "SampleAfterValue": "1000003", @@ -896,6 +966,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_256", "SampleAfterValue": "1000003", @@ -904,15 +975,16 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x4", "Unit": "cpu_atom" }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", @@ -922,15 +994,16 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -940,15 +1013,16 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2", "Unit": "cpu_atom" }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -956,8 +1030,19 @@ "UMask": "0x82", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", + "EventCode": "0x4c", + "EventName": "LOAD_HIT_PREFETCH.SWPF", + "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", + "SampleAfterValue": "100003", + "UMask": "0x1", + "Unit": "cpu_core" + }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", @@ -968,6 +1053,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -978,6 +1064,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -985,8 +1072,17 @@ "UMask": "0x1", "Unit": "cpu_core" }, + { + "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.ANY", + "SampleAfterValue": "20003", + "Unit": "cpu_atom" + }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -998,14 +1094,25 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", "UMask": "0x8", "Unit": "cpu_atom" }, + { + "BriefDescription": "Counts the number of machines clears due to m= emory renaming.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc3", + "EventName": "MACHINE_CLEARS.MRN_NUKE", + "SampleAfterValue": "1000003", + "UMask": "0x80", + "Unit": "cpu_atom" + }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -1014,6 +1121,7 @@ }, { "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine with the use of microcode due to SMC= , MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_= TRAP.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SLOW", "SampleAfterValue": "20003", @@ -1022,6 +1130,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -1030,6 +1139,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -1039,6 +1149,7 @@ }, { "BriefDescription": "LFENCE instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", "PublicDescription": "number of LFENCE retired instructions", @@ -1048,15 +1159,26 @@ }, { "BriefDescription": "Counts the number of Last Branch Record (LBR)= entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This= event is alias to LBR_INSERTS.ANY]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1", "Unit": "cpu_atom" }, + { + "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xcc", + "EventName": "MISC_RETIRED.LBR_INSERTS", + "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", + "SampleAfterValue": "100003", + "UMask": "0x20", + "Unit": "cpu_core" + }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -1065,6 +1187,7 @@ }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that were not consumed by the back-end pipeline due to lack of bac= k-end resources, as a result of memory subsystem delays, execution units li= mitations, or other conditions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that were not consumed by the back-end pipeline due to lack of ba= ck-end resources, as a result of memory subsystem delays, execution units l= imitations, or other conditions. The count is distributed among unhalted lo= gical processors (hyper-threads) who share the same physical core, in proce= ssors that support Intel Hyper-Threading Technology. Software can use this = event as the numerator for the Backend Bound metric (or top-level category)= of the Top-down Microarchitecture Analysis method.", @@ -1074,6 +1197,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= s.", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BAD_SPEC_SLOTS", "PublicDescription": "Number of slots of TMA method that were wast= ed due to incorrect speculation. It covers all types of control-flow or dat= a-related mis-speculations.", @@ -1083,6 +1207,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by (any type of) branch mispredictions. This event es= timates number of speculative operations that were issued but not retired a= s well as the out-of-order engine recovery past a branch misprediction.", @@ -1092,6 +1217,7 @@ }, { "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", "SampleAfterValue": "10000003", @@ -1100,6 +1226,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -1108,6 +1235,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -1117,6 +1245,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", @@ -1125,6 +1254,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", @@ -1133,6 +1263,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Fast Nukes such as Memory Ord= ering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -1141,6 +1272,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -1149,6 +1281,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -1157,6 +1290,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "SampleAfterValue": "1000003", @@ -1165,6 +1299,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003", @@ -1172,6 +1307,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to due to certain allocation rest= rictions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -1180,6 +1316,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL_P", "SampleAfterValue": "1000003", @@ -1187,6 +1324,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stall (sche= duler not being able to accept another uop). This could be caused by RSV f= ull or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -1195,6 +1333,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC and FPC RAT stalls - which= can be due to the FIQ and IEC reservation station stall (integer, FP and S= IMD scheduler not being able to accept another uop. )", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -1203,6 +1342,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to mrbl stall. A 'marble' refers= to a physical register file entry, also known as the physical destination = (PDST).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -1211,6 +1351,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -1219,6 +1360,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -1227,6 +1369,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_= P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003", @@ -1234,6 +1377,7 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL_P", "SampleAfterValue": "1000003", @@ -1241,6 +1385,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BAClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "SampleAfterValue": "1000003", @@ -1249,6 +1394,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "SampleAfterValue": "1000003", @@ -1257,6 +1403,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ms", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -1265,6 +1412,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -1273,6 +1421,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "SampleAfterValue": "1000003", @@ -1281,6 +1430,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to latency related stalls inclu= ding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "SampleAfterValue": "1000003", @@ -1289,6 +1439,7 @@ }, { "BriefDescription": "This event is deprecated. [This event is alia= s to TOPDOWN_FE_BOUND.ITLB_MISS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", @@ -1298,6 +1449,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to itlb miss [This event is ali= as to TOPDOWN_FE_BOUND.ITLB]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", "SampleAfterValue": "1000003", @@ -1306,6 +1458,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend that do not categorize into any oth= er common frontend stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -1314,6 +1467,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to predecode wrong", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -1321,23 +1475,24 @@ "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L_P]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", "SampleAfterValue": "1000003", "Unit": "cpu_atom" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL_P", - "PEBS": "1", "SampleAfterValue": "1000003", "Unit": "cpu_atom" }, { "BriefDescription": "Number of non dec-by-all uops decoded by deco= der", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UOPS_DECODED.DEC0_UOPS", "PublicDescription": "This event counts the number of not dec-by-a= ll uops decoded by decoder 0.", @@ -1347,6 +1502,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Number of uops dispatch to execution port 0= .", @@ -1356,6 +1512,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Number of uops dispatch to execution port 1= .", @@ -1365,6 +1522,7 @@ }, { "BriefDescription": "Uops executed on ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_2_3_10", "PublicDescription": "Number of uops dispatch to execution ports 2= , 3 and 10", @@ -1374,6 +1532,7 @@ }, { "BriefDescription": "Uops executed on ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Number of uops dispatch to execution ports 4= and 9", @@ -1383,6 +1542,7 @@ }, { "BriefDescription": "Uops executed on ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_5_11", "PublicDescription": "Number of uops dispatch to execution ports 5= and 11", @@ -1392,6 +1552,7 @@ }, { "BriefDescription": "Uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Number of uops dispatch to execution port 6= .", @@ -1401,6 +1562,7 @@ }, { "BriefDescription": "Uops executed on ports 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Number of uops dispatch to execution ports = 7 and 8.", @@ -1410,6 +1572,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -1419,6 +1582,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -1429,6 +1593,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -1439,6 +1604,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -1449,6 +1615,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -1459,6 +1626,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -1469,6 +1637,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -1479,6 +1648,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -1489,6 +1659,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -1499,6 +1670,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.STALLS", @@ -1510,6 +1682,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -1518,6 +1691,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -1527,6 +1701,7 @@ }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -1535,6 +1710,7 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xae", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -1544,6 +1720,7 @@ }, { "BriefDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xae", "EventName": "UOPS_ISSUED.CYCLES", @@ -1551,27 +1728,17 @@ "UMask": "0x1", "Unit": "cpu_core" }, - { - "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", - "CounterMask": "1", - "EventCode": "0xae", - "EventName": "UOPS_ISSUED.STALLS", - "Invert": "1", - "PublicDescription": "Counts cycles during which the Resource Allo= cation Table (RAT) does not issue any Uops to the reservation station (RS) = for the current thread.", - "SampleAfterValue": "1000003", - "UMask": "0x1", - "Unit": "cpu_core" - }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "2000003", "Unit": "cpu_atom" }, { "BriefDescription": "Cycles with retired uop(s).", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.CYCLES", @@ -1582,6 +1749,7 @@ }, { "BriefDescription": "Retired uops except the last uop of each inst= ruction.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.HEAVY", "PublicDescription": "Counts the number of retired micro-operation= s (uops) except the last uop of each instruction. An instruction that is de= coded into less than two uops does not contribute to the count.", @@ -1591,24 +1759,25 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x10", "Unit": "cpu_atom" }, { "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x1", "Unit": "cpu_atom" }, { "BriefDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "MSRIndex": "0x3F7", @@ -1619,6 +1788,7 @@ }, { "BriefDescription": "This event counts a subset of the Topdown Slo= ts event that are utilized by operations that eventually get retired (commi= tted) by the processor pipeline. Usually, this event positively correlates = with higher performance for example, as measured by the instructions-per-c= ycle metric.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "This event counts a subset of the Topdown Sl= ots event that are utilized by operations that eventually get retired (comm= itted) by the processor pipeline. Usually, this event positively correlates= with higher performance for example, as measured by the instructions-per-= cycle metric. Software can use this event as the numerator for the Retiring= metric (or top-level category) of the Top-down Microarchitecture Analysis = method.", @@ -1628,6 +1798,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALLS", @@ -1637,22 +1808,11 @@ "UMask": "0x2", "Unit": "cpu_core" }, - { - "BriefDescription": "Cycles with less than 10 actually retired uop= s.", - "CounterMask": "10", - "EventCode": "0xc2", - "EventName": "UOPS_RETIRED.TOTAL_CYCLES", - "Invert": "1", - "PublicDescription": "Counts the number of cycles using always tru= e condition (uops_ret < 16) applied to non PEBS uops retired event.", - "SampleAfterValue": "1000003", - "UMask": "0x2", - "Unit": "cpu_core" - }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in ms flows", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2", "Unit": "cpu_atom" diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/meteorlake/uncore-cache.json index 188843be4caf..f294852dfbe6 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of all entries allocated. Includes als= o retries.", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_HAC_CBO_TOR_ALLOCATION.ALL", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Asserted on coherent DRD + DRdPref allocatio= ns into the queue. Cacheable only", + "Counter": "0,1", "EventCode": "0x35", "EventName": "UNC_HAC_CBO_TOR_ALLOCATION.DRD", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-interconnect.json index 901d8510f90f..a2f4386a8379 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", "PerPkg": "1", @@ -9,14 +10,17 @@ }, { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, etc.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_HAC_ARB_COH_TRK_REQUESTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "HAC_ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_HAC_ARB_REQ_TRK_REQUEST.DRD", "PerPkg": "1", @@ -25,6 +29,7 @@ }, { "BriefDescription": "Number of all CMI transactions", + "Counter": "0,1", "EventCode": "0x8A", "EventName": "UNC_HAC_ARB_TRANSACTIONS.ALL", "PerPkg": "1", @@ -33,6 +38,7 @@ }, { "BriefDescription": "Number of all CMI reads", + "Counter": "0,1", "EventCode": "0x8A", "EventName": "UNC_HAC_ARB_TRANSACTIONS.READS", "PerPkg": "1", @@ -41,6 +47,7 @@ }, { "BriefDescription": "Number of all CMI writes not including Mflush= ", + "Counter": "0,1", "EventCode": "0x8A", "EventName": "UNC_HAC_ARB_TRANSACTIONS.WRITES", "PerPkg": "1", @@ -49,6 +56,7 @@ }, { "BriefDescription": "Total number of all outgoing entries allocate= d. Accounts for Coherent and non-coherent traffic.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_HAC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json index c9d248d1042e..783a4f7fd05b 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every CAS read command sent from the M= emory Controller 0 to DRAM (sum of all channels).", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Counts every read and write request entering = the Memory Controller 0.", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Counts every CAS write command sent from the = Memory Controller 0 to DRAM (sum of all channels).", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Counts every CAS read command sent from the M= emory Controller 1 to DRAM (sum of all channels).", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Counts every read and write request entering = the Memory Controller 1.", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Counts every CAS write command sent from the = Memory Controller 1 to DRAM (sum of all channels).", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "ACT command for a read request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x24", "EventName": "UNC_M_ACT_COUNT_RD", "PerPkg": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "ACT command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x26", "EventName": "UNC_M_ACT_COUNT_TOTAL", "PerPkg": "1", @@ -69,6 +77,7 @@ }, { "BriefDescription": "ACT command for a write request sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x25", "EventName": "UNC_M_ACT_COUNT_WR", "PerPkg": "1", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Read CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x22", "EventName": "UNC_M_CAS_COUNT_RD", "PerPkg": "1", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Write CAS command sent to DRAM", + "Counter": "0,1,2,3,4", "EventCode": "0x23", "EventName": "UNC_M_CAS_COUNT_WR", "PerPkg": "1", @@ -90,6 +101,7 @@ }, { "BriefDescription": "PRE command sent to DRAM due to page table id= le timer expiration", + "Counter": "0,1,2,3,4", "EventCode": "0x28", "EventName": "UNC_M_PRE_COUNT_IDLE", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "PRE command sent to DRAM for a read/write req= uest", + "Counter": "0,1,2,3,4", "EventCode": "0x27", "EventName": "UNC_M_PRE_COUNT_PAGE_MISS", "PerPkg": "1", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Number of bytes read from DRAM, in 32B chunks= . Counter increments by 1 after receiving 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3A", "EventName": "UNC_M_RD_DATA", "PerPkg": "1", @@ -111,6 +125,7 @@ }, { "BriefDescription": "Total number of read and write byte transfers= to/from DRAM, in 32B chunks. Counter increments by 1 after sending or rece= iving 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3C", "EventName": "UNC_M_TOTAL_DATA", "PerPkg": "1", @@ -118,6 +133,7 @@ }, { "BriefDescription": "Number of bytes written to DRAM, in 32B chunk= s. Counter increments by 1 after sending 32B chunk data.", + "Counter": "0,1,2,3,4", "EventCode": "0x3B", "EventName": "UNC_M_WR_DATA", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-other.json b/= tools/perf/pmu-events/arch/x86/meteorlake/uncore-other.json index 2af92e43b28a..1ac5b5ef8094 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json index 55798e64c58a..305b96b26a4e 100644 --- a/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/meteorlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200003", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -63,6 +70,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -72,6 +80,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -81,6 +90,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -90,6 +100,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or Loads (demand or SW prefetch) in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -99,6 +110,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -108,6 +120,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Accounts= for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -135,6 +150,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "2000003", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", "SampleAfterValue": "1000003", @@ -223,6 +248,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -231,6 +257,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -240,6 +267,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -250,6 +278,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -259,6 +288,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -268,6 +298,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -277,6 +308,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -286,6 +318,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -295,6 +328,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -304,6 +338,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or iside in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for iside in PMH every cycle. A PMH page walk is outstanding from page wal= k start till PMH becomes idle again (ready to serve next walk). Includes EP= T-walk intervals. Walks could be counted by edge detecting on this event, = but would count restarted suspended walks.", @@ -313,6 +348,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -322,6 +358,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.DTLB_MISS_AT_RET", "SampleAfterValue": "1000003", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD5EF3BB30 for ; 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Thu, 20 Jun 2024 11:20:10 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:38 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-25-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 24/37] perf vendor events: Add nehalemep counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/nehalemep/cache.json | 320 ++++++++++++++++++ .../arch/x86/nehalemep/counter.json | 7 + .../arch/x86/nehalemep/floating-point.json | 28 ++ .../arch/x86/nehalemep/frontend.json | 3 + .../pmu-events/arch/x86/nehalemep/memory.json | 67 ++++ .../pmu-events/arch/x86/nehalemep/other.json | 18 + .../arch/x86/nehalemep/pipeline.json | 109 ++++++ .../arch/x86/nehalemep/virtual-memory.json | 13 + 8 files changed, 565 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/nehalemep/counter.json diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json b/tools/pe= rf/pmu-events/arch/x86/nehalemep/cache.json index 5113a4e059e4..b90026df2ce7 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "All references to the L1 data cache", + "Counter": "0,1", "EventCode": "0x43", "EventName": "L1D_ALL_REF.ANY", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1 data cacheable reads and writes", + "Counter": "0,1", "EventCode": "0x43", "EventName": "L1D_ALL_REF.CACHEABLE", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1 data cache read in E state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.E_STATE", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1 data cache read in I state (misses)", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.I_STATE", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 data cache reads", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.MESI", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 data cache read in M state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.M_STATE", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "L1 data cache read in S state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.S_STATE", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 data cache load locks in E state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.E_STATE", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 data cache load lock hits", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.HIT", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "L1 data cache load locks in M state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.M_STATE", "SampleAfterValue": "2000000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L1 data cache load locks in S state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.S_STATE", "SampleAfterValue": "2000000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L1D load lock accepted in fill buffer", + "Counter": "0,1", "EventCode": "0x53", "EventName": "L1D_CACHE_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L1 data cache stores in E state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.E_STATE", "SampleAfterValue": "2000000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L1 data cache stores in M state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.M_STATE", "SampleAfterValue": "2000000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L1 data cache stores in S state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.S_STATE", "SampleAfterValue": "2000000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request= ", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -491,6 +561,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -498,6 +569,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -505,6 +577,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -512,6 +585,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -519,6 +593,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -526,6 +601,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -533,6 +609,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -540,6 +617,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -547,6 +625,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -554,6 +633,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -561,6 +641,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -568,6 +649,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -575,6 +657,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -582,6 +665,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -589,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -598,6 +683,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -608,6 +694,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -618,6 +705,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -628,6 +716,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -638,6 +727,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -648,6 +738,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -658,6 +749,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -668,6 +760,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -678,6 +771,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -688,6 +782,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -698,6 +793,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -708,6 +804,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -718,6 +815,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -728,6 +826,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -738,6 +837,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -746,6 +846,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -754,6 +855,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -762,6 +864,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -770,6 +873,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -778,6 +882,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -786,6 +891,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -794,6 +900,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -802,6 +909,7 @@ }, { "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", "PEBS": "1", @@ -810,6 +918,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", "PEBS": "1", @@ -818,6 +927,7 @@ }, { "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", "PEBS": "1", @@ -826,6 +936,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -834,6 +945,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -842,6 +954,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -849,6 +962,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -856,6 +970,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -865,6 +980,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -874,6 +990,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -883,6 +1000,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -892,6 +1010,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -901,6 +1020,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -910,6 +1030,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -919,6 +1040,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -928,6 +1050,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -937,6 +1060,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -946,6 +1070,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -955,6 +1080,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -964,6 +1090,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -973,6 +1100,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -982,6 +1110,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -991,6 +1120,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1000,6 +1130,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1009,6 +1140,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1018,6 +1150,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1027,6 +1160,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1036,6 +1170,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1045,6 +1180,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1054,6 +1190,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1063,6 +1200,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1072,6 +1210,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1081,6 +1220,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1090,6 +1230,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1099,6 +1240,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1108,6 +1250,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1117,6 +1260,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1126,6 +1270,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1135,6 +1280,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1144,6 +1290,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1153,6 +1300,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1162,6 +1310,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1171,6 +1320,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1180,6 +1330,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1189,6 +1340,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1198,6 +1350,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1207,6 +1360,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1216,6 +1370,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1225,6 +1380,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1234,6 +1390,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1243,6 +1400,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1252,6 +1410,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1261,6 +1420,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1270,6 +1430,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1279,6 +1440,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1288,6 +1450,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1297,6 +1460,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1306,6 +1470,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1315,6 +1480,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1324,6 +1490,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1333,6 +1500,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1342,6 +1510,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1351,6 +1520,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1360,6 +1530,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1369,6 +1540,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1378,6 +1550,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1387,6 +1560,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1396,6 +1570,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1405,6 +1580,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1414,6 +1590,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1423,6 +1600,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1432,6 +1610,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1441,6 +1620,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1450,6 +1630,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1459,6 +1640,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1468,6 +1650,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1477,6 +1660,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1486,6 +1670,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1495,6 +1680,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1504,6 +1690,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y location", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1513,6 +1700,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1522,6 +1710,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1531,6 +1720,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1540,6 +1730,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1549,6 +1740,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1558,6 +1750,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1567,6 +1760,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1576,6 +1770,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1585,6 +1780,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1594,6 +1790,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1603,6 +1800,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1612,6 +1810,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1621,6 +1820,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1630,6 +1830,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1639,6 +1840,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1648,6 +1850,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1657,6 +1860,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1666,6 +1870,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1675,6 +1880,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1684,6 +1890,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1693,6 +1900,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1702,6 +1910,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1711,6 +1920,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1720,6 +1930,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1729,6 +1940,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1738,6 +1950,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", @@ -1747,6 +1960,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", @@ -1756,6 +1970,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", @@ -1765,6 +1980,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1774,6 +1990,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1783,6 +2000,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1792,6 +2010,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1801,6 +2020,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1810,6 +2030,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1819,6 +2040,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1828,6 +2050,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1837,6 +2060,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1846,6 +2070,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", @@ -1855,6 +2080,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", @@ -1864,6 +2090,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", @@ -1873,6 +2100,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1882,6 +2110,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1891,6 +2120,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1900,6 +2130,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1909,6 +2140,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1918,6 +2150,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1927,6 +2160,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1936,6 +2170,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1945,6 +2180,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1954,6 +2190,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1963,6 +2200,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1972,6 +2210,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1981,6 +2220,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1990,6 +2230,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1999,6 +2240,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2008,6 +2250,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2017,6 +2260,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2026,6 +2270,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2035,6 +2280,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2044,6 +2290,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2053,6 +2300,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2062,6 +2310,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2071,6 +2320,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2080,6 +2330,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2089,6 +2340,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2098,6 +2350,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2107,6 +2360,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2116,6 +2370,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2125,6 +2380,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote c= ache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2134,6 +2390,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2143,6 +2400,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2152,6 +2410,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2161,6 +2420,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2170,6 +2430,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2179,6 +2440,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2188,6 +2450,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2197,6 +2460,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2206,6 +2470,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2215,6 +2480,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2224,6 +2490,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2233,6 +2500,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2242,6 +2510,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2251,6 +2520,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2260,6 +2530,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2269,6 +2540,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2278,6 +2550,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2287,6 +2560,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2296,6 +2570,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2305,6 +2580,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2314,6 +2590,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2323,6 +2600,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2332,6 +2610,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2341,6 +2620,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2350,6 +2630,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2359,6 +2640,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2368,6 +2650,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2377,6 +2660,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2386,6 +2670,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2395,6 +2680,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2404,6 +2690,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2413,6 +2700,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2422,6 +2710,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2431,6 +2720,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2440,6 +2730,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2449,6 +2740,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2458,6 +2750,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2467,6 +2760,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2476,6 +2770,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2485,6 +2780,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2494,6 +2790,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2503,6 +2800,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2512,6 +2810,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2521,6 +2820,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2530,6 +2830,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2539,6 +2840,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2548,6 +2850,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2557,6 +2860,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2566,6 +2870,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2575,6 +2880,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2584,6 +2890,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2593,6 +2900,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2602,6 +2910,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2611,6 +2920,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2620,6 +2930,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2629,6 +2940,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2638,6 +2950,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2647,6 +2960,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2656,6 +2970,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2665,6 +2980,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2674,6 +2990,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2683,6 +3000,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2690,6 +3008,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2697,6 +3016,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/counter.json b/tools/= perf/pmu-events/arch/x86/nehalemep/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemep/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json b= /tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input = value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transition= s", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json b/tools= /perf/pmu-events/arch/x86/nehalemep/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json b/tools/p= erf/pmu-events/arch/x86/nehalemep/memory.json index f810880a295e..dc732c8baf12 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -118,6 +131,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -163,6 +181,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -172,6 +191,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -181,6 +201,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -190,6 +211,7 @@ }, { "BriefDescription": "Offcore code or data read requests that misse= d the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -199,6 +221,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -208,6 +231,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -217,6 +241,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", @@ -226,6 +251,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -235,6 +261,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -244,6 +271,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -253,6 +281,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -262,6 +291,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -271,6 +301,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -280,6 +311,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -289,6 +321,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -298,6 +331,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -307,6 +341,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -316,6 +351,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -325,6 +361,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -334,6 +371,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -343,6 +381,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -352,6 +391,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -361,6 +401,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -379,6 +421,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -388,6 +431,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -397,6 +441,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", @@ -406,6 +451,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -424,6 +471,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -433,6 +481,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -442,6 +491,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -451,6 +501,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -460,6 +511,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -469,6 +521,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -478,6 +531,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -487,6 +541,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -496,6 +551,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -505,6 +561,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -514,6 +571,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -523,6 +581,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -532,6 +591,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -541,6 +601,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -550,6 +611,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -559,6 +621,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -568,6 +631,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -577,6 +641,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -586,6 +651,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -595,6 +661,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/other.json b/tools/pe= rf/pmu-events/arch/x86/nehalemep/other.json index fb706cb51832..f6887b234b0e 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/other.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "False dependencies due to partial address ali= asing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json b/tools= /perf/pmu-events/arch/x86/nehalemep/pipeline.json index c45f2ffa861e..869c84fa7c60 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediciton Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event= )", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -246,11 +280,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -258,17 +294,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed count= er)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -277,6 +316,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -284,6 +324,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -291,6 +332,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -298,6 +340,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -305,6 +348,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -312,6 +356,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder = 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -319,6 +364,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -326,6 +372,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instru= ction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -333,11 +380,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -346,6 +395,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -354,6 +404,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -364,6 +415,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -374,6 +426,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -382,6 +435,7 @@ }, { "BriefDescription": "Load operations conflicting with software pre= fetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -389,6 +443,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -397,6 +452,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -406,6 +462,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction = queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -420,6 +478,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -427,6 +486,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -434,6 +494,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -441,6 +502,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -448,6 +510,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -455,6 +518,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -462,6 +526,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -469,6 +534,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -476,6 +542,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -483,6 +550,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -490,6 +558,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -497,6 +566,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -504,6 +574,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -511,6 +582,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -518,6 +590,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -525,6 +598,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -533,6 +607,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -572,6 +651,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -579,6 +659,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -587,6 +668,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -597,6 +679,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -606,6 +689,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -615,6 +699,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -626,6 +711,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -637,6 +723,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -647,6 +734,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -656,6 +744,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -663,6 +752,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -670,6 +760,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -679,6 +770,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -687,6 +779,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -695,6 +788,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -703,6 +797,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -711,6 +806,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -718,6 +814,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -725,6 +822,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -733,6 +831,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -743,6 +842,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -751,6 +851,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -758,6 +859,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -767,6 +869,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -776,6 +879,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -784,6 +888,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -810,6 +917,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -820,6 +928,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json index c434cd4ef4f1..e88c0802e679 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemep/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Retired 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Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/nehalemex/cache.json | 315 ++++++++++++++++++ .../arch/x86/nehalemex/counter.json | 7 + .../arch/x86/nehalemex/floating-point.json | 28 ++ .../arch/x86/nehalemex/frontend.json | 3 + .../pmu-events/arch/x86/nehalemex/memory.json | 67 ++++ .../pmu-events/arch/x86/nehalemex/other.json | 18 + .../arch/x86/nehalemex/pipeline.json | 109 ++++++ .../arch/x86/nehalemex/virtual-memory.json | 13 + 8 files changed, 560 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/nehalemex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json b/tools/pe= rf/pmu-events/arch/x86/nehalemex/cache.json index 0042e53fdc78..2c0ea6f8c4e0 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/cache.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "All references to the L1 data cache", + "Counter": "0,1", "EventCode": "0x43", "EventName": "L1D_ALL_REF.ANY", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1 data cacheable reads and writes", + "Counter": "0,1", "EventCode": "0x43", "EventName": "L1D_ALL_REF.CACHEABLE", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1 data cache read in E state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.E_STATE", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1 data cache read in I state (misses)", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.I_STATE", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 data cache reads", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.MESI", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 data cache read in M state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.M_STATE", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "L1 data cache read in S state", + "Counter": "0,1", "EventCode": "0x40", "EventName": "L1D_CACHE_LD.S_STATE", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 data cache load locks in E state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.E_STATE", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 data cache load lock hits", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.HIT", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "L1 data cache load locks in M state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.M_STATE", "SampleAfterValue": "2000000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L1 data cache load locks in S state", + "Counter": "0,1", "EventCode": "0x42", "EventName": "L1D_CACHE_LOCK.S_STATE", "SampleAfterValue": "2000000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L1D load lock accepted in fill buffer", + "Counter": "0,1", "EventCode": "0x53", "EventName": "L1D_CACHE_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L1 data cache stores in E state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.E_STATE", "SampleAfterValue": "2000000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L1 data cache stores in M state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.M_STATE", "SampleAfterValue": "2000000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L1 data cache stores in S state", + "Counter": "0,1", "EventCode": "0x41", "EventName": "L1D_CACHE_ST.S_STATE", "SampleAfterValue": "2000000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request= ", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -491,6 +561,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -498,6 +569,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -505,6 +577,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -512,6 +585,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -519,6 +593,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -526,6 +601,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -533,6 +609,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -540,6 +617,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -547,6 +625,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -554,6 +633,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -561,6 +641,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -568,6 +649,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -575,6 +657,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -582,6 +665,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -589,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -598,6 +683,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -608,6 +694,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -618,6 +705,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -628,6 +716,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -638,6 +727,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -648,6 +738,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -658,6 +749,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -668,6 +760,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -678,6 +771,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -688,6 +782,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -698,6 +793,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -708,6 +804,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -718,6 +815,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -728,6 +826,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -738,6 +837,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -746,6 +846,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -754,6 +855,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -762,6 +864,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -770,6 +873,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -778,6 +882,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -786,6 +891,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -794,6 +900,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -802,6 +909,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -809,6 +917,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -816,6 +925,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -825,6 +935,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -834,6 +945,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -843,6 +955,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -852,6 +965,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -861,6 +975,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -870,6 +985,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -879,6 +995,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -888,6 +1005,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -897,6 +1015,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -906,6 +1025,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -915,6 +1035,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -924,6 +1045,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -933,6 +1055,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -942,6 +1065,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -951,6 +1075,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -960,6 +1085,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -969,6 +1095,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -978,6 +1105,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -987,6 +1115,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -996,6 +1125,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1005,6 +1135,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1014,6 +1145,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1023,6 +1155,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1032,6 +1165,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1041,6 +1175,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1050,6 +1185,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1059,6 +1195,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1068,6 +1205,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1077,6 +1215,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1086,6 +1225,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1095,6 +1235,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1104,6 +1245,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1113,6 +1255,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1122,6 +1265,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1131,6 +1275,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1140,6 +1285,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1149,6 +1295,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1158,6 +1305,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1167,6 +1315,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1176,6 +1325,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1185,6 +1335,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1194,6 +1345,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1203,6 +1355,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1212,6 +1365,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1221,6 +1375,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1230,6 +1385,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1239,6 +1395,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1248,6 +1405,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1257,6 +1415,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1266,6 +1425,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1275,6 +1435,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1284,6 +1445,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1293,6 +1455,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1302,6 +1465,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1311,6 +1475,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1320,6 +1485,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1329,6 +1495,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1338,6 +1505,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1347,6 +1515,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1356,6 +1525,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1365,6 +1535,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1374,6 +1545,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1383,6 +1555,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1392,6 +1565,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1401,6 +1575,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1410,6 +1585,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1419,6 +1595,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1428,6 +1605,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1437,6 +1615,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1446,6 +1625,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1455,6 +1635,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1464,6 +1645,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y location", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1473,6 +1655,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1482,6 +1665,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1491,6 +1675,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1500,6 +1685,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1509,6 +1695,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1518,6 +1705,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1527,6 +1715,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1536,6 +1725,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1545,6 +1735,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1554,6 +1745,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1563,6 +1755,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1572,6 +1765,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1581,6 +1775,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1590,6 +1785,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1599,6 +1795,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1608,6 +1805,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1617,6 +1815,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1626,6 +1825,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1635,6 +1835,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1644,6 +1845,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1653,6 +1855,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1662,6 +1865,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1671,6 +1875,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1680,6 +1885,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1689,6 +1895,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1698,6 +1905,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", @@ -1707,6 +1915,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", @@ -1716,6 +1925,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", @@ -1725,6 +1935,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1734,6 +1945,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1743,6 +1955,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1752,6 +1965,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1761,6 +1975,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1770,6 +1985,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1779,6 +1995,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1788,6 +2005,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1797,6 +2015,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1806,6 +2025,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", @@ -1815,6 +2035,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", @@ -1824,6 +2045,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", @@ -1833,6 +2055,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1842,6 +2065,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1851,6 +2075,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1860,6 +2085,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1869,6 +2095,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1878,6 +2105,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1887,6 +2115,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1896,6 +2125,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1905,6 +2135,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1914,6 +2145,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1923,6 +2155,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1932,6 +2165,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1941,6 +2175,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1950,6 +2185,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1959,6 +2195,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1968,6 +2205,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1977,6 +2215,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1986,6 +2225,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1995,6 +2235,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2004,6 +2245,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2013,6 +2255,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2022,6 +2265,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2031,6 +2275,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2040,6 +2285,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2049,6 +2295,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2058,6 +2305,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2067,6 +2315,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2076,6 +2325,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2085,6 +2335,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote c= ache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2094,6 +2345,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2103,6 +2355,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2112,6 +2365,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2121,6 +2375,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2130,6 +2385,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2139,6 +2395,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2148,6 +2405,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2157,6 +2415,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2166,6 +2425,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2175,6 +2435,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2184,6 +2445,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2193,6 +2455,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2202,6 +2465,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2211,6 +2475,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2220,6 +2485,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2229,6 +2495,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2238,6 +2505,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2247,6 +2515,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2256,6 +2525,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2265,6 +2535,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2274,6 +2545,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2283,6 +2555,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2292,6 +2565,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2301,6 +2575,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2310,6 +2585,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2319,6 +2595,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2328,6 +2605,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2337,6 +2615,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2346,6 +2625,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2355,6 +2635,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2364,6 +2645,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2373,6 +2655,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2382,6 +2665,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2391,6 +2675,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2400,6 +2685,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2409,6 +2695,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2418,6 +2705,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2427,6 +2715,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2436,6 +2725,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2445,6 +2735,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2454,6 +2745,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2463,6 +2755,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2472,6 +2765,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2481,6 +2775,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2490,6 +2785,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2499,6 +2795,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2508,6 +2805,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2517,6 +2815,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2526,6 +2825,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2535,6 +2835,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2544,6 +2845,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2553,6 +2855,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2562,6 +2865,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2571,6 +2875,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2580,6 +2885,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2589,6 +2895,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2598,6 +2905,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2607,6 +2915,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2616,6 +2925,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2625,6 +2935,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2634,6 +2945,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2643,6 +2955,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2650,6 +2963,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2657,6 +2971,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/counter.json b/tools/= perf/pmu-events/arch/x86/nehalemex/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/nehalemex/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json b= /tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input = value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transition= s", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json b/tools= /perf/pmu-events/arch/x86/nehalemex/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json b/tools/p= erf/pmu-events/arch/x86/nehalemex/memory.json index f810880a295e..dc732c8baf12 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -118,6 +131,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -163,6 +181,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -172,6 +191,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -181,6 +201,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -190,6 +211,7 @@ }, { "BriefDescription": "Offcore code or data read requests that misse= d the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -199,6 +221,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -208,6 +231,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -217,6 +241,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", @@ -226,6 +251,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -235,6 +261,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -244,6 +271,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -253,6 +281,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -262,6 +291,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -271,6 +301,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -280,6 +311,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -289,6 +321,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -298,6 +331,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -307,6 +341,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -316,6 +351,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -325,6 +361,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -334,6 +371,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -343,6 +381,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -352,6 +391,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -361,6 +401,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -379,6 +421,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -388,6 +431,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -397,6 +441,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", @@ -406,6 +451,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -424,6 +471,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -433,6 +481,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -442,6 +491,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -451,6 +501,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -460,6 +511,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -469,6 +521,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -478,6 +531,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -487,6 +541,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -496,6 +551,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -505,6 +561,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -514,6 +571,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -523,6 +581,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -532,6 +591,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -541,6 +601,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -550,6 +611,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -559,6 +621,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -568,6 +631,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -577,6 +641,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -586,6 +651,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -595,6 +661,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/other.json b/tools/pe= rf/pmu-events/arch/x86/nehalemex/other.json index fb706cb51832..f6887b234b0e 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/other.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "False dependencies due to partial address ali= asing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json b/tools= /perf/pmu-events/arch/x86/nehalemex/pipeline.json index c45f2ffa861e..869c84fa7c60 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediciton Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event= )", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -246,11 +280,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -258,17 +294,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed count= er)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -277,6 +316,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -284,6 +324,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -291,6 +332,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -298,6 +340,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -305,6 +348,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -312,6 +356,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder = 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -319,6 +364,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -326,6 +372,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instru= ction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -333,11 +380,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -346,6 +395,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -354,6 +404,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -364,6 +415,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -374,6 +426,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -382,6 +435,7 @@ }, { "BriefDescription": "Load operations conflicting with software pre= fetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -389,6 +443,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -397,6 +452,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -406,6 +462,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction = queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -420,6 +478,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -427,6 +486,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -434,6 +494,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -441,6 +502,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -448,6 +510,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -455,6 +518,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -462,6 +526,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -469,6 +534,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -476,6 +542,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -483,6 +550,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -490,6 +558,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -497,6 +566,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -504,6 +574,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -511,6 +582,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -518,6 +590,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -525,6 +598,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -533,6 +607,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -572,6 +651,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -579,6 +659,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -587,6 +668,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -597,6 +679,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -606,6 +689,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -615,6 +699,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -626,6 +711,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -637,6 +723,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -647,6 +734,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -656,6 +744,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -663,6 +752,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -670,6 +760,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -679,6 +770,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -687,6 +779,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -695,6 +788,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -703,6 +797,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -711,6 +806,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -718,6 +814,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -725,6 +822,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -733,6 +831,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -743,6 +842,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -751,6 +851,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -758,6 +859,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -767,6 +869,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -776,6 +879,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -784,6 +888,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -810,6 +917,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -820,6 +928,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json index c434cd4ef4f1..e88c0802e679 100644 --- a/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/nehalemex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -87,6 +99,7 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC", 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00721157ae682-63a8ae565femr8438427b3.0.1718907615564; Thu, 20 Jun 2024 11:20:15 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:40 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-27-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 26/37] perf vendor events: Add/update rocketlake events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.02 to v1.03. Update TMA metrics from v4.7 to v4.8. Bring in the event updates v1.03: https://github.com/intel/perfmon/commit/a7c75ffd56c7056494cd3acc2749336cd63= 63b90 The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ Adds the event SW_PREFETCH_ACCESS.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/rocketlake/cache.json | 109 +++++++ .../arch/x86/rocketlake/counter.json | 17 + .../arch/x86/rocketlake/floating-point.json | 13 + .../arch/x86/rocketlake/frontend.json | 41 ++- .../arch/x86/rocketlake/memory.json | 44 +++ .../arch/x86/rocketlake/metricgroups.json | 13 + .../pmu-events/arch/x86/rocketlake/other.json | 27 ++ .../arch/x86/rocketlake/pipeline.json | 94 ++++++ .../arch/x86/rocketlake/rkl-metrics.json | 308 +++++++++++++----- .../x86/rocketlake/uncore-interconnect.json | 28 +- .../arch/x86/rocketlake/uncore-other.json | 1 + .../arch/x86/rocketlake/virtual-memory.json | 20 ++ 13 files changed, 629 insertions(+), 88 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/rocketlake/counter.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 1040f68fee94..51765cc94a3b 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -24,7 +24,7 @@ GenuineIntel-6-BD,v1.01,lunarlake,core GenuineIntel-6-A[AC],v1.10,meteorlake,core GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core -GenuineIntel-6-A7,v1.02,rocketlake,core +GenuineIntel-6-A7,v1.03,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.20,sapphirerapids,core GenuineIntel-6-AF,v1.02,sierraforest,core diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/cache.json b/tools/p= erf/pmu-events/arch/x86/rocketlake/cache.json index b0f54a6650fe..2e93b7835b41 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -52,6 +58,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", @@ -68,6 +76,7 @@ }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -76,6 +85,7 @@ }, { "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", "EventCode": "0xf2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", @@ -84,6 +94,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -92,6 +103,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -100,6 +112,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -108,6 +121,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts demand requests to L2 cache.", @@ -116,6 +130,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -124,6 +139,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "All requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts all requests that miss L2 cache.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "All L2 requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all L2 requests.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -180,6 +202,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -188,6 +211,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -196,6 +220,7 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", @@ -204,6 +229,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -212,6 +238,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -220,6 +247,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -230,6 +258,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -240,6 +269,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -250,6 +280,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -260,6 +291,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -280,6 +313,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -290,6 +324,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -300,6 +335,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -310,6 +346,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -320,6 +357,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -330,6 +368,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or Bus Lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -350,6 +390,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -360,6 +401,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -370,6 +412,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -380,6 +423,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -390,6 +434,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -400,6 +445,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -410,6 +456,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -420,6 +467,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -429,6 +477,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another cores caches, data forwarding is required as the data is modified= .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -438,6 +487,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop hit i= n another core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -447,6 +497,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -456,6 +507,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was n= ot needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -465,6 +517,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a cacheline in the L3 where a snoop was s= ent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -474,6 +527,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -483,6 +537,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -492,6 +547,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another core, data forwarding is not requir= ed.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -501,6 +557,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -510,6 +567,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -519,6 +577,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -528,6 +587,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -537,6 +597,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another cores caches, data forward= ing is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -546,6 +607,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another core, data forwarding is n= ot required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -555,6 +617,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent but no other cores had the data.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -564,6 +627,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -573,6 +637,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -582,6 +647,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -591,6 +657,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was sent but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -600,6 +667,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that hit a cacheline in the L3 where a= snoop was not needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -609,6 +677,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent or n= ot.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -618,6 +687,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r cores caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -627,6 +697,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop hit in anothe= r core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -636,6 +707,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent but = no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -645,6 +717,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was not neede= d to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -654,6 +727,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that hit a cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -663,6 +737,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -672,6 +747,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another cores= caches, data forwarding is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -681,6 +757,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop hit in another core,= data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -690,6 +767,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent but no othe= r cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -699,6 +777,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was not needed to sa= tisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -708,6 +787,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that hit a cacheline in the L3 where a snoop was sent.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -717,6 +797,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit a cacheline in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L3.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -726,6 +807,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop hit in= another core, data forwarding is not required.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -735,6 +817,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt but no other cores had the data.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -744,6 +827,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was no= t needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -753,6 +837,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that hit a cacheline in the L3 where a snoop was se= nt.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_HIT.SNOOP_SENT", "MSRIndex": "0x1a6,0x1a7", @@ -762,6 +847,7 @@ }, { "BriefDescription": "Counts streaming stores that hit a cacheline = in the L3 where a snoop was sent or not.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_HIT.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -771,6 +857,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -779,6 +866,7 @@ }, { "BriefDescription": "Counts memory transactions sent to the uncore= .", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions sent to the uncor= e including requests initiated by the core, all L3 prefetches, reads result= ing from page walks, and snoop responses.", @@ -787,6 +875,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -795,6 +884,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -803,6 +893,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding data read requests pending. Data read requests include cachea= ble demand reads and L2 prefetches, but do not include RFOs, code reads or = prefetches to the L3. Reads due to page walks resulting from any request t= ype will also be counted. Requests are considered outstanding from the tim= e they miss the core's L2 cache until the transaction completion message is= sent to the requestor.", @@ -811,6 +902,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding data read= request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -820,6 +912,7 @@ }, { "BriefDescription": "Cycles where at least 1 outstanding Demand RF= O request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -829,6 +922,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -837,6 +931,7 @@ }, { "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", @@ -845,6 +940,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -853,14 +949,24 @@ }, { "BriefDescription": "Cycles the queue waiting for offcore response= s is full.", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SQ_FULL", "PublicDescription": "Counts the cycles for which the thread is ac= tive and the queue waiting for responses from the uncore cannot take any mo= re entries.", "SampleAfterValue": "100003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -869,6 +975,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -877,6 +984,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -885,6 +993,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/counter.json b/tools= /perf/pmu-events/arch/x86/rocketlake/counter.json new file mode 100644 index 000000000000..5a350072522a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/rocketlake/counter.json @@ -0,0 +1,17 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "CLOCK", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/floating-point.json = b/tools/perf/pmu-events/arch/x86/rocketlake/floating-point.json index 85c26c889088..61ddce0c8db6 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP= and FM(N)ADD/SUB instructions count twice as they perform multiple calcula= tions per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/frontend.json b/tool= s/perf/pmu-events/arch/x86/rocketlake/frontend.json index 2b539a08d2bf..e7c7d4d4152d 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xab", @@ -27,6 +30,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,6 +75,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -90,6 +99,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -101,6 +111,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -123,6 +135,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -134,6 +147,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -145,6 +159,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -156,6 +171,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -167,6 +183,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -189,6 +207,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -200,6 +219,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -211,6 +231,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -222,6 +243,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", @@ -230,6 +252,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", @@ -238,6 +261,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", @@ -246,6 +270,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.ST= ALLS]", @@ -254,6 +279,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", @@ -262,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IF= TAG_STALL]", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -279,15 +307,17 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the D= SB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the I= DQ.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -296,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -305,6 +336,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -314,6 +346,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -322,6 +355,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -331,6 +365,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -341,6 +376,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -349,6 +385,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", @@ -357,6 +394,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -366,6 +404,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/memory.json b/tools/= perf/pmu-events/arch/x86/rocketlake/memory.json index f84763220549..f73035f44330 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED", "PublicDescription": "Counts the number of times HLE abort was tri= ggered.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an HLE execution = aborted due to unfriendly events (such as interrupts).", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an HLE execution = aborted due to various memory events (e.g., read/write capacity and conflic= ts).", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an HLE execution = aborted due to HLE-unfriendly instructions and certain unfriendly events (s= uch as AD assists etc.).", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Counts the number of times HLE commit succee= ded.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Counts the number of times we entered an HLE= region. Does not count nested transactions.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -85,6 +95,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -121,6 +134,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -133,6 +147,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -145,6 +160,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -157,6 +173,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -169,6 +186,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +196,7 @@ }, { "BriefDescription": "Counts demand data reads that was not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +206,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that was no= t supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +216,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that was not supplied by the L3 cache.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +226,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +236,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +246,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that was not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +256,7 @@ }, { "BriefDescription": "Counts streaming stores that was not supplied= by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +266,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -248,6 +274,7 @@ }, { "BriefDescription": "Cycles where at least one demand data read re= quest known to have missed the L3 cache is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -257,6 +284,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -266,6 +294,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -274,6 +303,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -282,6 +312,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -290,6 +321,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -298,6 +330,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -306,6 +339,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -314,6 +348,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", @@ -322,6 +357,7 @@ }, { "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", @@ -330,6 +366,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -338,6 +375,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -346,6 +384,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", @@ -354,6 +393,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to release/commit but data and address mismatch.", @@ -362,6 +402,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to commit but Lock Buffer not empty.", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to attempting an unsupported alignment from Lock Buffer.", @@ -378,6 +420,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Counts the number of times a TSX Abort was t= riggered due to a non-release/commit store to lock.", @@ -386,6 +429,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Counts the number of times we could not allo= cate Lock Buffer.", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/metricgroups.json b/= tools/perf/pmu-events/arch/x86/rocketlake/metricgroups.json index 5452a1448ded..3a88260194d1 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/other.json b/tools/p= erf/pmu-events/arch/x86/rocketlake/other.json index 4fdc87339555..a96b2a989d3f 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/other.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -70,6 +78,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied t= he request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -79,6 +88,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -88,6 +98,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that DRAM s= upplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -124,6 +138,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and so= ftware prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -133,6 +148,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which br= ing data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -160,6 +178,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +198,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring da= ta to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +208,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +218,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +228,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O an= d un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +238,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +248,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +258,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied th= e request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/pipeline.json b/tool= s/perf/pmu-events/arch/x86/rocketlake/pipeline.json index c7313fd4fdf4..4fdf07c7beb7 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -160,6 +178,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -185,6 +206,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", "SampleAfterValue": "2000003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", @@ -208,6 +232,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -254,6 +284,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -262,6 +293,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "20", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -278,6 +311,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -286,6 +320,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -302,6 +338,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -310,6 +347,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -319,6 +357,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -327,6 +366,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -335,6 +375,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of instructions retired - = an Architectural PerfMon event. Counting continues during hardware interrup= ts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counte= d by a designated fixed counter freeing up programmable counters to count o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -343,6 +384,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -351,6 +393,7 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -359,6 +402,7 @@ }, { "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", @@ -367,6 +411,7 @@ }, { "BriefDescription": "Cycles without actually retired instructions.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc0", "EventName": "INST_RETIRED.STALL_CYCLES", @@ -377,6 +422,7 @@ }, { "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", @@ -386,6 +432,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -396,6 +443,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -404,6 +452,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -412,6 +461,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -420,6 +470,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -428,6 +479,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -436,6 +488,7 @@ }, { "BriefDescription": "False dependencies due to partial compare on = address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies due to partial compare on address.", @@ -444,6 +497,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -452,6 +506,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -461,6 +516,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -470,6 +526,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -478,6 +535,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -488,6 +546,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -496,6 +555,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR to be enabled properly.", @@ -504,6 +564,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.PAUSE_INST", "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", @@ -512,6 +573,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -520,6 +582,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -527,6 +590,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5e", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -535,6 +599,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -546,6 +611,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", @@ -554,6 +620,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -561,6 +628,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -569,6 +637,7 @@ }, { "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UOPS_DECODED.DEC0", "PublicDescription": "Uops exclusively fetched by decoder 0", @@ -577,6 +646,7 @@ }, { "BriefDescription": "Number of uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -585,6 +655,7 @@ }, { "BriefDescription": "Number of uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -593,6 +664,7 @@ }, { "BriefDescription": "Number of uops executed on port 2 and 3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_2_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", @@ -601,6 +673,7 @@ }, { "BriefDescription": "Number of uops executed on port 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", @@ -609,6 +682,7 @@ }, { "BriefDescription": "Number of uops executed on port 5", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -617,6 +691,7 @@ }, { "BriefDescription": "Number of uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -625,6 +700,7 @@ }, { "BriefDescription": "Number of uops executed on port 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", @@ -633,6 +709,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -641,6 +718,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -650,6 +728,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -659,6 +738,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -668,6 +748,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -677,6 +758,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -686,6 +768,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -695,6 +778,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -704,6 +788,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -713,6 +798,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -723,6 +809,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -730,6 +817,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -738,6 +826,7 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -746,6 +835,7 @@ }, { "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -756,6 +846,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to 'Mixing Intel AVX and Intel = SSE Code' section of the Optimization Guide.", @@ -764,6 +855,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -772,6 +864,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -782,6 +875,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "10", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/rkl-metrics.json b/t= ools/perf/pmu-events/arch/x86/rocketlake/rkl-metrics.json index 1dad462e58b1..13474af97786 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/rkl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/rkl-metrics.json @@ -104,7 +104,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -114,7 +114,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MIS= C.CLEARS_COUNT / tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -135,7 +135,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions.", "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES= / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_branch_instructions", "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_oper= ations > 0.6", "ScaleUnit": "100%" @@ -143,7 +143,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -181,7 +181,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(29 * tma_info_system_core_frequency * MEM_LOAD_L3_= HIT_RETIRED.XSNP_HITM + 23.5 * tma_info_system_core_frequency * MEM_LOAD_L3= _HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L= 1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -201,7 +201,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "23.5 * tma_info_system_core_frequency * MEM_LOAD_L3= _HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_= MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -219,7 +219,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -250,13 +250,13 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -265,7 +265,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -274,7 +274,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "32.5 * tma_info_system_core_frequency * OCR.DEMAND_= RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -283,7 +283,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -296,7 +296,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -338,7 +338,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -347,7 +347,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0xfc@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -385,7 +385,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -405,7 +405,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -460,6 +460,27 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, + { + "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", + "MetricExpr": "tma_info_botlnk_l0_core_bound_likely", + "MetricGroup": "Cor;Metric;SMT", + "MetricName": "tma_info_botlnk_core_bound_likely", + "MetricThreshold": "tma_info_botlnk_core_bound_likely > 0.5" + }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", + "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + t= ma_lcp + tma_dsb_switches) + tma_fetch_bandwidth * tma_mite / (tma_mite + t= ma_dsb + tma_lsd))", + "MetricGroup": "DSBmiss;Fed;Scaled_Slots;tma_issueFB", + "MetricName": "tma_info_botlnk_dsb_misses", + "MetricThreshold": "tma_info_botlnk_dsb_misses > 10" + }, + { + "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", + "MetricExpr": "100 * (tma_fetch_latency * tma_icache_misses / (tma= _icache_misses + tma_itlb_misses + tma_branch_resteers + tma_ms_switches + = tma_lcp + tma_dsb_switches))", + "MetricGroup": "Fed;FetchLat;IcMiss;Scaled_Slots;tma_issueFL", + "MetricName": "tma_info_botlnk_ic_misses", + "MetricThreshold": "tma_info_botlnk_ic_misses > 5" + }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricConstraint": "NO_GROUP_EVENTS", @@ -468,6 +489,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd = + tma_mite)))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -475,7 +504,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -486,40 +515,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound= / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store= _bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_= full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -527,23 +550,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -551,8 +574,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store /= (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency= + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_spl= it_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma= _dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)= ) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_store= s + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -560,7 +583,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (t= ma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_d= ata_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores = + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_mach= ine_clears * (1 - tma_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -569,18 +592,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -638,7 +668,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -655,7 +685,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 5 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -721,7 +751,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -816,12 +846,24 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 11", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" + }, + { + "BriefDescription": "\"Bus lock\" per kilo instruction", + "MetricExpr": "tma_info_memory_mix_bus_lock_pki", + "MetricGroup": "Mem;Metric", + "MetricName": "tma_info_memory_bus_lock_pki" + }, + { + "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", + "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", + "MetricGroup": "Fed;MemoryTLB;Metric", + "MetricName": "tma_info_memory_code_stlb_mpki" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -847,6 +889,12 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, + { + "BriefDescription": "Average Parallel L2 cache miss data reads", + "MetricExpr": "tma_info_memory_latency_data_l2_mlp", + "MetricGroup": "Memory_BW;Metric;Offcore", + "MetricName": "tma_info_memory_data_l2_mlp" + }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -854,11 +902,17 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", + "MetricExpr": "tma_info_memory_l1d_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" + }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -872,11 +926,17 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l2_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" + }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", @@ -908,17 +968,35 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_access_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW;Offcore", + "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + }, + { + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, + { + "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", + "MetricExpr": "tma_info_memory_l3_cache_fill_bw", + "MetricGroup": "Core_Metric;Mem;MemoryBW", + "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" + }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -933,7 +1011,7 @@ }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", + "MetricExpr": "tma_info_memory_load_l2_miss_latency", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, @@ -949,12 +1027,36 @@ "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l3_miss_latency" }, + { + "BriefDescription": "Average Latency for L2 cache miss demand Load= s", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", + "MetricGroup": "Clocks_Latency;Memory_Lat;Offcore", + "MetricName": "tma_info_memory_load_l2_miss_latency" + }, + { + "BriefDescription": "Average Parallel L2 cache miss demand Loads", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@O= FFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=3D0x1@", + "MetricGroup": "Memory_BW;Metric;Offcore", + "MetricName": "tma_info_memory_load_l2_mlp" + }, + { + "BriefDescription": "Average Latency for L3 cache miss demand Load= s", + "MetricExpr": "cpu@OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,u= mask\\=3D0x0@ / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", + "MetricGroup": "Clocks_Latency;Memory_Lat;Offcore", + "MetricName": "tma_info_memory_load_l3_miss_latency" + }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", "MetricExpr": "L1D_PEND_MISS.PENDING / (MEM_LOAD_RETIRED.L1_MISS += MEM_LOAD_RETIRED.FB_HIT)", "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, + { + "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", + "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", + "MetricGroup": "Mem;MemoryTLB;Metric", + "MetricName": "tma_info_memory_load_stlb_mpki" + }, { "BriefDescription": "\"Bus lock\" per kilo instruction", "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", @@ -963,7 +1065,7 @@ }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricExpr": "tma_info_memory_uc_load_pki", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -974,6 +1076,19 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, + { + "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", + "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", + "MetricGroup": "Core_Metric;Mem;MemoryTLB", + "MetricName": "tma_info_memory_page_walks_utilization", + "MetricThreshold": "tma_info_memory_page_walks_utilization > 0.5" + }, + { + "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", + "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", + "MetricGroup": "Mem;MemoryTLB;Metric", + "MetricName": "tma_info_memory_store_stlb_mpki" + }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -1000,11 +1115,35 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "", + "BriefDescription": "Un-cacheable retired load per kilo instructio= n", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", + "MetricGroup": "Mem;Metric", + "MetricName": "tma_info_memory_uc_load_pki" + }, + { + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from LSD per c= ycle", + "MetricExpr": "LSD.UOPS / LSD.CYCLES_ACTIVE", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_lsd" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", @@ -1027,13 +1166,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1171,7 +1310,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1180,7 +1319,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1195,11 +1334,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS)= * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_= info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1218,7 +1366,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "9 * tma_info_system_core_frequency * (MEM_LOAD_RETI= RED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)) = / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1230,7 +1378,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1275,7 +1423,7 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { @@ -1290,7 +1438,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1300,7 +1448,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1309,7 +1457,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1346,7 +1494,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1390,7 +1538,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1409,7 +1557,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1417,7 +1565,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1469,7 +1617,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + = tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_AC= TIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks= ", + "MetricExpr": "cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ / t= ma_info_thread_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1497,7 +1645,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -1507,7 +1655,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -1517,7 +1665,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -1554,7 +1702,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1582,7 +1730,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1625,7 +1773,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/rocketlake/uncore-interconnect.json index 8027590f1776..3946d4e01a8c 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, etc.", + "Counter": "1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -8,55 +9,68 @@ "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core. This event is not su= pported on ICL products but is supported on RKL products.", + "BriefDescription": "Each cycle counts number of any coherent requ= ests at memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core. T= his event is not supported on ICL products but is supported on RKL products= .", + "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches. This event is not supported on I= CL products but is supported on RKL products.", + "BriefDescription": "Each cycle counts number of valid coherent Da= ta Read entries. Such entry is defined as valid when it is allocated until = deallocation. Does not include prefetches.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches", + "Counter": "1", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { - "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic. T= his event is not supported on ICL products but is supported on RKL products= .", + "BriefDescription": "Each cycle counts number of all outgoing vali= d entries in ReqTrk. Such entry is defined as valid from its allocation in = ReqTrk until deallocation. Accounts for Coherent and non-coherent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { - "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches. This event is not supported on I= CL products but is supported on RKL products.", + "BriefDescription": "Each cycle counts number of valid coherent Da= ta Read entries. Such entry is defined as valid when it is allocated until = deallocation. Does not include prefetches.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Total number of all outgoing entries allocate= d. Accounts for Coherent and non-coherent traffic.", + "Counter": "1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -64,9 +78,11 @@ "Unit": "ARB" }, { - "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches. This event is not supported on ICL products but is= supported on RKL products.", + "BriefDescription": "Counts number of all coherent Data Read entri= es. Does not include prefetches.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/uncore-other.json b/= tools/perf/pmu-events/arch/x86/rocketlake/uncore-other.json index c6596ba09195..cc8110ac020c 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "UNC_CLOCK.SOCKET", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/rocketlake/virtual-memory.json index b28f62ce1f39..3ff51040f84f 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -116,6 +130,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87B0B1B581A for ; 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Thu, 20 Jun 2024 11:20:18 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:41 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-28-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 27/37] perf vendor events: Update sandybridge metrics add event counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. The TMA 4.8 information was updated in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/sandybridge/cache.json | 173 ++++++++++++++++++ .../arch/x86/sandybridge/counter.json | 17 ++ .../arch/x86/sandybridge/floating-point.json | 15 ++ .../arch/x86/sandybridge/frontend.json | 32 ++++ .../arch/x86/sandybridge/memory.json | 37 ++++ .../arch/x86/sandybridge/metricgroups.json | 11 ++ .../arch/x86/sandybridge/other.json | 6 + .../arch/x86/sandybridge/pipeline.json | 128 +++++++++++++ .../arch/x86/sandybridge/snb-metrics.json | 24 +-- .../arch/x86/sandybridge/uncore-cache.json | 25 +++ .../x86/sandybridge/uncore-interconnect.json | 9 + .../arch/x86/sandybridge/virtual-memory.json | 16 ++ 12 files changed, 481 insertions(+), 12 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sandybridge/counter.json diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json b/tools/= perf/pmu-events/arch/x86/sandybridge/cache.json index 4e5572ee7dfe..b5b1e160eba1 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Allocated L1D data cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALLOCATED_IN_M", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cache lines in M state evicted out of L1D due= to Snoop HitM or dirty line replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.ALL_M_REPLACEMENT", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D data cache lines in M state evicted due t= o replacement.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.EVICTION", "SampleAfterValue": "2000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D data line replacements.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "This event counts L1D data line replacements= . Replacements occur when a new line is brought into the cache, causing ev= iction of a line loaded earlier.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles when dispatched loads are cancelled du= e to L1D bank conflicts with other load ports.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xBF", "EventName": "L1D_BLOCKS.BANK_CONFLICT_CYCLES", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles a demand request was blocked due to Fi= ll Buffers unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", @@ -46,6 +52,7 @@ }, { "BriefDescription": "L1D miss outstanding duration in cycles.", + "Counter": "2", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -62,6 +70,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "2", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.ALL", "SampleAfterValue": "200003", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -84,6 +95,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Not rejected writebacks from L1D to L2 cache = lines in S state.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.HIT_S", "SampleAfterValue": "200003", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Count the number of modified Lines evicted fr= om L1 and missed L2. (Non-rejected WBs from the DCU.).", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L2_L1D_WB_RQSTS.MISS", "SampleAfterValue": "200003", @@ -105,6 +119,7 @@ }, { "BriefDescription": "L2 cache lines filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "This event counts the number of L2 cache lin= es brought into the L2 cache. Lines are filled into the L2 cache when ther= e was an L2 miss.", @@ -113,6 +128,7 @@ }, { "BriefDescription": "L2 cache lines in E state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E", "SampleAfterValue": "100003", @@ -120,6 +136,7 @@ }, { "BriefDescription": "L2 cache lines in I state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.I", "SampleAfterValue": "100003", @@ -127,6 +144,7 @@ }, { "BriefDescription": "L2 cache lines in S state filling L2.", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S", "SampleAfterValue": "100003", @@ -134,6 +152,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100003", @@ -141,6 +160,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by demand.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100003", @@ -148,6 +168,7 @@ }, { "BriefDescription": "Dirty L2 cache lines filling the L2.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DIRTY_ALL", "SampleAfterValue": "100003", @@ -155,6 +176,7 @@ }, { "BriefDescription": "Clean L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_CLEAN", "SampleAfterValue": "100003", @@ -162,6 +184,7 @@ }, { "BriefDescription": "Dirty L2 cache lines evicted by L2 prefetch.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PF_DIRTY", "SampleAfterValue": "100003", @@ -169,6 +192,7 @@ }, { "BriefDescription": "L2 code requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "SampleAfterValue": "200003", @@ -176,6 +200,7 @@ }, { "BriefDescription": "Demand Data Read requests.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -183,6 +208,7 @@ }, { "BriefDescription": "Requests from L2 hardware prefetchers.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "SampleAfterValue": "200003", @@ -190,6 +216,7 @@ }, { "BriefDescription": "RFO requests to L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "SampleAfterValue": "200003", @@ -197,6 +224,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "SampleAfterValue": "200003", @@ -204,6 +232,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "SampleAfterValue": "200003", @@ -211,6 +240,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "SampleAfterValue": "200003", @@ -218,6 +248,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "SampleAfterValue": "200003", @@ -225,6 +256,7 @@ }, { "BriefDescription": "Requests from the L2 hardware prefetchers tha= t miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "SampleAfterValue": "200003", @@ -232,6 +264,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200003", @@ -239,6 +272,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200003", @@ -246,6 +280,7 @@ }, { "BriefDescription": "RFOs that access cache lines in any state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.ALL", "SampleAfterValue": "200003", @@ -253,6 +288,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in E state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_E", "SampleAfterValue": "200003", @@ -260,6 +296,7 @@ }, { "BriefDescription": "RFOs that hit cache lines in M state.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.HIT_M", "SampleAfterValue": "200003", @@ -267,6 +304,7 @@ }, { "BriefDescription": "RFOs that miss cache lines.", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_STORE_LOCK_RQSTS.MISS", "SampleAfterValue": "200003", @@ -274,6 +312,7 @@ }, { "BriefDescription": "L2 or LLC HW prefetches that access L2 cache.= ", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_PF", "SampleAfterValue": "200003", @@ -281,6 +320,7 @@ }, { "BriefDescription": "Transactions accessing L2 pipe.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.ALL_REQUESTS", "SampleAfterValue": "200003", @@ -288,6 +328,7 @@ }, { "BriefDescription": "L2 cache accesses when fetching instructions.= ", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.CODE_RD", "SampleAfterValue": "200003", @@ -295,6 +336,7 @@ }, { "BriefDescription": "Demand Data Read requests that access L2 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.DEMAND_DATA_RD", "SampleAfterValue": "200003", @@ -302,6 +344,7 @@ }, { "BriefDescription": "L1D writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L1D_WB", "SampleAfterValue": "200003", @@ -309,6 +352,7 @@ }, { "BriefDescription": "L2 fill requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_FILL", "SampleAfterValue": "200003", @@ -316,6 +360,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "SampleAfterValue": "200003", @@ -323,6 +368,7 @@ }, { "BriefDescription": "RFO requests that access L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.RFO", "SampleAfterValue": "200003", @@ -330,6 +376,7 @@ }, { "BriefDescription": "Cycles when L1D is locked.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "SampleAfterValue": "2000003", @@ -337,6 +384,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100003", @@ -344,6 +392,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to LLC.", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "100003", @@ -351,6 +400,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT", "PEBS": "1", @@ -360,6 +410,7 @@ }, { "BriefDescription": "Retired load uops which data sources were Hit= M responses from shared LLC. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM", "PEBS": "1", @@ -369,6 +420,7 @@ }, { "BriefDescription": "Retired load uops which data sources were LLC= hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEB= S).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_MISS", "PEBS": "1", @@ -377,6 +429,7 @@ }, { "BriefDescription": "Retired load uops which data sources were hit= s in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE", "PEBS": "1", @@ -385,6 +438,7 @@ }, { "BriefDescription": "Retired load uops with unknown information as= data source in cache serviced the load. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "MEM_LOAD_UOPS_MISC_RETIRED.LLC_MISS", "PEBS": "1", @@ -394,6 +448,7 @@ }, { "BriefDescription": "Retired load uops which data sources were loa= d uops missed L1 but hit FB due to preceding miss to the same cache line wi= th data not ready. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "PEBS": "1", @@ -402,6 +457,7 @@ }, { "BriefDescription": "Retired load uops with L1 cache hits as data = sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "PEBS": "1", @@ -410,6 +466,7 @@ }, { "BriefDescription": "Retired load uops with L2 cache hits as data = sources. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "PEBS": "1", @@ -418,6 +475,7 @@ }, { "BriefDescription": "Retired load uops which data sources were dat= a hits in LLC without snoops required. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "MEM_LOAD_UOPS_RETIRED.LLC_HIT", "PEBS": "1", @@ -427,6 +485,7 @@ }, { "BriefDescription": "All retired load uops. (Precise Event - PEBS)= .", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PEBS": "1", @@ -436,6 +495,7 @@ }, { "BriefDescription": "All retired store uops. (Precise Event - PEBS= ).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PEBS": "1", @@ -445,6 +505,7 @@ }, { "BriefDescription": "Retired load uops with locked access. (Precis= e Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", "PEBS": "1", @@ -453,6 +514,7 @@ }, { "BriefDescription": "Retired load uops that split across a cacheli= ne boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "PEBS": "1", @@ -462,6 +524,7 @@ }, { "BriefDescription": "Retired store uops that split across a cachel= ine boundary. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", "PEBS": "1", @@ -471,6 +534,7 @@ }, { "BriefDescription": "Retired load uops that miss the STLB. (Precis= e Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "PEBS": "1", @@ -479,6 +543,7 @@ }, { "BriefDescription": "Retired store uops that miss the STLB. (Preci= se Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "PEBS": "1", @@ -487,6 +552,7 @@ }, { "BriefDescription": "Demand and prefetch data reads.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "SampleAfterValue": "100003", @@ -494,6 +560,7 @@ }, { "BriefDescription": "Cacheable and noncacheable code read requests= .", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "SampleAfterValue": "100003", @@ -501,6 +568,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -508,6 +576,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "SampleAfterValue": "100003", @@ -515,6 +584,7 @@ }, { "BriefDescription": "Cases when offcore requests buffer cannot tak= e more entries for core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "SampleAfterValue": "2000003", @@ -522,6 +592,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "SampleAfterValue": "2000003", @@ -529,6 +600,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -537,6 +609,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -545,6 +618,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -553,6 +627,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -560,6 +635,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_C6", @@ -568,6 +644,7 @@ }, { "BriefDescription": "Offcore outstanding RFO store transactions in= SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "SampleAfterValue": "2000003", @@ -575,6 +652,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -584,6 +662,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -593,6 +672,7 @@ }, { "BriefDescription": "Counts demand & prefetch code reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -602,6 +682,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -611,6 +692,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -620,6 +702,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -629,6 +712,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops to sibling cores hit in either E/S state and the = line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -638,6 +722,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.NO_SNOOP_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -647,6 +732,7 @@ }, { "BriefDescription": "Counts demand & prefetch data reads that hit = in the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -656,6 +742,7 @@ }, { "BriefDescription": "Counts all prefetch code reads that hit in th= e LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -665,6 +752,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -674,6 +762,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -683,6 +772,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -692,6 +782,7 @@ }, { "BriefDescription": "Counts prefetch code reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -701,6 +792,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -710,6 +802,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoop to one of the sibling cores hits the line in M state and th= e line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -719,6 +812,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops to sibling cores hit in either E/S state and the line is n= ot forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -728,6 +822,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and sibling core snoops are not needed as either the core-valid bit is no= t set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -737,6 +832,7 @@ }, { "BriefDescription": "Counts prefetch data reads that hit in the LL= C and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -746,6 +842,7 @@ }, { "BriefDescription": "Counts all prefetch RFOs that hit in the LLC.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -755,6 +852,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoop to one of the sibling cores hits the line in M state and the line= is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -764,6 +862,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops to sibling cores hit in either E/S state and the line is not for= warded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -773,6 +872,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = sibling core snoops are not needed as either the core-valid bit is not set = or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -782,6 +882,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the LLC and = the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -791,6 +892,7 @@ }, { "BriefDescription": "Counts all data/code/rfo references (demand &= prefetch) .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -800,6 +902,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -809,6 +912,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoop to one of the sibling cores hits the li= ne in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -818,6 +922,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops to sibling cores hit in either E/S sta= te and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -827,6 +932,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and sibling core snoops are not needed as either the = core-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -836,6 +942,7 @@ }, { "BriefDescription": "Counts data/code/rfo reads (demand & prefetch= ) that hit in the LLC and the snoops sent to sibling cores return clean res= ponse.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -845,6 +952,7 @@ }, { "BriefDescription": "Counts all demand & prefetch prefetch RFOs .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -854,6 +962,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -863,6 +972,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -872,6 +982,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops to sibling cores hit in either E/S state and the line i= s not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -881,6 +992,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -890,6 +1002,7 @@ }, { "BriefDescription": "Counts demand & prefetch RFOs that hit in the= LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -899,6 +1012,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -908,6 +1022,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_INTO_CORE and RESPONSE =3D A= NY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -917,6 +1032,7 @@ }, { "BriefDescription": "Counts all demand code reads.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -926,6 +1042,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -935,6 +1052,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -944,6 +1062,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -953,6 +1072,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -962,6 +1082,7 @@ }, { "BriefDescription": "Counts demand code reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -971,6 +1092,7 @@ }, { "BriefDescription": "Counts all demand data reads .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -980,6 +1102,7 @@ }, { "BriefDescription": "Counts all demand data reads that hit in the = LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -989,6 +1112,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoop to one of the sibling cores hits the line in M state and the = line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -998,6 +1122,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops to sibling cores hit in either E/S state and the line is not= forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1007,6 +1132,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and sibling core snoops are not needed as either the core-valid bit is not = set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1016,6 +1142,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the LLC = and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1025,6 +1152,7 @@ }, { "BriefDescription": "Counts all demand rfo's .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1034,6 +1162,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1043,6 +1172,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1052,6 +1182,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops to sibling cores hit in either E/S state and the lin= e is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1061,6 +1192,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1070,6 +1202,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that hit in = the LLC and the snoops sent to sibling cores return clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1079,6 +1212,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_M and SNOOP =3D HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_M.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1088,6 +1222,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses. It also includes L2 hints sen= t to LLC to keep a line from being evicted out of the core caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1097,6 +1232,7 @@ }, { "BriefDescription": "Counts L2 hints sent to LLC to keep a line fr= om being evicted out of the core caches.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LRU_HINTS", "MSRIndex": "0x1a6,0x1a7", @@ -1106,6 +1242,7 @@ }, { "BriefDescription": "Counts miscellaneous accesses that include po= rt i/o, MMIO and uncacheable memory accesses.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.PORTIO_MMIO_UC", "MSRIndex": "0x1a6,0x1a7", @@ -1115,6 +1252,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_RESPO= NSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1124,6 +1262,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1133,6 +1272,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -1142,6 +1282,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1151,6 +1292,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1160,6 +1302,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) code = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1169,6 +1312,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) d= ata reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1178,6 +1322,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -1187,6 +1332,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1196,6 +1342,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -1205,6 +1352,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the LLC and the snoops sent to sibling cores return clean= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1214,6 +1362,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1223,6 +1372,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoop to one of the sibling cores hits the line= in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1232,6 +1382,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops to sibling cores hit in either E/S state= and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1241,6 +1392,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and sibling core snoops are not needed as either the co= re-valid bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1250,6 +1402,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) RFOs = that hit in the LLC and the snoops sent to sibling cores return clean respo= nse.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1259,6 +1412,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1268,6 +1422,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -1277,6 +1432,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1286,6 +1442,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1295,6 +1452,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= code reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1304,6 +1462,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1313,6 +1472,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoop to one of the sibling cores h= its the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -1322,6 +1482,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops to sibling cores hit in eith= er E/S state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1331,6 +1492,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and sibling core snoops are not needed as e= ither the core-valid bit is not set or the shared line is present in multip= le cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.NO_SNOOP_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1340,6 +1502,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= data reads that hit in the LLC and the snoops sent to sibling cores return= clean response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1349,6 +1512,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the LLC.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1358,6 +1522,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoop to one of the sibling cores hits th= e line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1367,6 +1532,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops to sibling cores hit in either E/S= state and the line is not forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1376,6 +1542,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and sibling core snoops are not needed as either = the core-valid bit is not set or the shared line is present in multiple cor= es.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1385,6 +1552,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to LLC only)= RFOs that hit in the LLC and the snoops sent to sibling cores return clean= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1394,6 +1562,7 @@ }, { "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D A= NY_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1403,6 +1572,7 @@ }, { "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D AN= Y_RESPONSE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1412,6 +1582,7 @@ }, { "BriefDescription": "Counts requests where the address of an atomi= c lock instruction spans a cache line boundary or the lock instruction is e= xecuted on uncacheable address.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.SPLIT_LOCK_UC_LOCK.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1421,6 +1592,7 @@ }, { "BriefDescription": "Counts non-temporal stores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1430,6 +1602,7 @@ }, { "BriefDescription": "Split locks in SQ.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/counter.json b/tool= s/perf/pmu-events/arch/x86/sandybridge/counter.json new file mode 100644 index 000000000000..35bb154900d7 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sandybridge/counter.json @@ -0,0 +1,17 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "ARB", + "CountersNumFixed": "1", + "CountersNumGeneric": "2" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json= b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json index 79e8f403c426..8b570829e2e0 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles with any input/output SSE or FP assist= .", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to input values= .", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_INPUT", "SampleAfterValue": "100003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of SIMD FP assists due to Output value= s.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.SIMD_OUTPUT", "SampleAfterValue": "100003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Number of X87 assists due to input value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_INPUT", "SampleAfterValue": "100003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Number of X87 assists due to output value.", + "Counter": "0,1,2,3", "EventCode": "0xCA", "EventName": "FP_ASSIST.X87_OUTPUT", "SampleAfterValue": "100003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked double-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE", "SampleAfterValue": "2000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational pa= cked single-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE", "SampleAfterValue": "2000003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar double-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE", "SampleAfterValue": "2000003", @@ -58,6 +66,7 @@ }, { "BriefDescription": "Number of SSE* or AVX-128 FP Computational sc= alar single-precision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE", "SampleAfterValue": "2000003", @@ -65,6 +74,7 @@ }, { "BriefDescription": "Number of FP Computational Uops Executed this= cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIV= s, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish= an FADD used in the middle of a transcendental flow from a s.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000003", @@ -72,6 +82,7 @@ }, { "BriefDescription": "Number of GSSE memory assist for stores. GSSE= microcode assist is being invoked whenever the hardware is unable to prope= rly handle GSSE-256b operations.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_STORE", "SampleAfterValue": "100003", @@ -79,6 +90,7 @@ }, { "BriefDescription": "Number of transitions from AVX-256 to legacy = SSE when penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.AVX_TO_SSE", "SampleAfterValue": "100003", @@ -86,6 +98,7 @@ }, { "BriefDescription": "Number of transitions from SSE to AVX-256 whe= n penalty applicable.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.SSE_TO_AVX", "SampleAfterValue": "100003", @@ -93,6 +106,7 @@ }, { "BriefDescription": "Number of AVX-256 Computational FP double pre= cision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_DOUBLE", "SampleAfterValue": "2000003", @@ -100,6 +114,7 @@ }, { "BriefDescription": "Number of GSSE-256 Computational FP single pr= ecision uops issued this cycle.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "SIMD_FP_256.PACKED_SINGLE", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/frontend.json index 700716b42f1a..e95d1005e22f 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "This event counts the cycles attributed to a= switch from the Decoded Stream Buffer (DSB), which holds decoded instructi= ons, to the legacy decode pipeline. It excludes cycles when the back-end c= annot accept new micro-ops. The penalty for these switches is potentially= several cycles of instruction starvation, where no micro-ops are delivered= to the back-end.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cases of cancelling valid Decode Stream Buffe= r (DSB) fill not because of exceeding way limit.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.ALL_CANCEL", "SampleAfterValue": "2000003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Cycles when Decode Stream Buffer (DSB) fill e= ncounter more than 3 Decode Stream Buffer (DSB) lines.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.EXCEED_DSB_LINES", "SampleAfterValue": "2000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Cases of cancelling valid DSB fill not becaus= e of exceeding way limit.", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "DSB_FILL.OTHER_CANCEL", "SampleAfterValue": "2000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Number of Instruction Cache, Streaming Buffer= and Victim Cache Reads. both cacheable and noncacheable, including UC fetc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "SampleAfterValue": "2000003", @@ -51,6 +58,7 @@ }, { "BriefDescription": "Instruction cache, streaming buffer and victi= m cache misses.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts the number of instruction = cache, streaming buffer and victim cache misses. Counting includes unchache= able accesses.", @@ -59,6 +67,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 Uops.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -75,6 +85,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -83,6 +94,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -99,6 +112,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "SampleAfterValue": "2000003", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.EMPTY", "SampleAfterValue": "2000003", @@ -113,6 +128,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_ALL_UOPS", "SampleAfterValue": "2000003", @@ -120,6 +136,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -128,6 +145,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "SampleAfterValue": "2000003", @@ -135,6 +153,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -144,6 +163,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -152,6 +172,7 @@ }, { "BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) = initiated by Decode Stream Buffer (DSB) while Microcode Sequencer (MS) is b= usy.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -161,6 +182,7 @@ }, { "BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) = that are being delivered to Instruction Decode Queue (IDQ) while Microcode = Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_UOPS", "SampleAfterValue": "2000003", @@ -168,6 +190,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "SampleAfterValue": "2000003", @@ -175,6 +198,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -184,6 +208,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy.", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "SampleAfterValue": "2000003", @@ -191,6 +216,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled .", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "This event counts the number of uops not del= ivered to the back-end per cycle, per thread, when the back-end was not sta= lled. In the ideal case 4 uops can be delivered each cycle. The event cou= nts the undelivered uops - so if 3 were delivered in one cycle, the counter= would be incremented by 1 for that cycle (4 - 3). If the back-end is stall= ed, the count for this event is not incremented even when uops were not del= ivered, because the back-end would not have been able to accept them. This= event is used in determining the front-end bound category of the top-down = pipeline slots characterization.", @@ -199,6 +225,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -207,6 +234,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -216,6 +244,7 @@ }, { "BriefDescription": "Cycles when 1 or more uops were delivered to = the by the front end.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_GE_1_UOP_DELIV.CORE", @@ -225,6 +254,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -233,6 +263,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -241,6 +272,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json b/tools= /perf/pmu-events/arch/x86/sandybridge/memory.json index 0a6fc0136f4a..72b79b606c40 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of memory order= ing Machine Clears detected. Memory Ordering Machine Clears can result from= memory disambiguation, external snoops, or cross SMT-HW-thread snoop (stor= es) hitting load buffers. Machine clears can have a significant performanc= e impact if they are happening frequently.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads with latency value being above 128.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Loads with latency value being above 16.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Loads with latency value being above 256.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", @@ -39,6 +43,7 @@ }, { "BriefDescription": "Loads with latency value being above 32.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", @@ -49,6 +54,7 @@ }, { "BriefDescription": "Loads with latency value being above 4 .", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", @@ -59,6 +65,7 @@ }, { "BriefDescription": "Loads with latency value being above 512.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", @@ -69,6 +76,7 @@ }, { "BriefDescription": "Loads with latency value being above 64.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Loads with latency value being above 8.", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", @@ -89,6 +98,7 @@ }, { "BriefDescription": "Sample stores and collect precise store opera= tion via PEBS record. PMC3 only. (Precise Event - PEBS).", + "Counter": "3", "EventCode": "0xCD", "EventName": "MEM_TRANS_RETIRED.PRECISE_STORE", "PEBS": "2", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Speculative cache line split load uops dispat= ched to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.LOADS", "SampleAfterValue": "2000003", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative cache line split STA uops dispatc= hed to L1 cache.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "MISALIGN_MEM_REF.STORES", "SampleAfterValue": "2000003", @@ -111,6 +123,7 @@ }, { "BriefDescription": "Counts all demand & prefetch code reads that = miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -120,6 +133,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -129,6 +143,7 @@ }, { "BriefDescription": "Counts all prefetch code reads that miss the = LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -138,6 +153,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts all prefetch RFOs that miss the LLC a= nd the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -156,6 +173,7 @@ }, { "BriefDescription": "Counts all data/code/rfo reads (demand & pref= etch) that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -165,6 +183,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -174,6 +193,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= MISS_LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -184,6 +204,7 @@ }, { "BriefDescription": "Counts LLC replacements.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -194,6 +215,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN_SOCKET and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D ANY_LLC_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN_SOCKET.LLC_MISS_LOCAL.ANY_L= LC_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -203,6 +225,7 @@ }, { "BriefDescription": "Counts demand code reads that miss the LLC an= d the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -212,6 +235,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the LLC an= d the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -221,6 +245,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -230,6 +255,7 @@ }, { "BriefDescription": "Counts demand data writes (RFOs) that miss th= e LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -239,6 +265,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_M= ISS_LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -248,6 +275,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_MISS_= LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -257,6 +285,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) c= ode reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -266,6 +295,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -275,6 +305,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -284,6 +315,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) code reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -293,6 +325,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -302,6 +335,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the LLC and the data returned from dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -311,6 +345,7 @@ }, { "BriefDescription": "REQUEST =3D PF_LLC_DATA_RD and RESPONSE =3D L= LC_MISS_LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_DATA_RD.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -320,6 +355,7 @@ }, { "BriefDescription": "REQUEST =3D PF_LLC_IFETCH and RESPONSE =3D LL= C_MISS_LOCAL and SNOOP =3D DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L_IFETCH.LLC_MISS_LOCAL.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -329,6 +365,7 @@ }, { "BriefDescription": "Number of any page walk that had a miss in LL= C. Does not necessary cause a SUSPEND.", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "PAGE_WALKS.LLC_MISS", "SampleAfterValue": "100003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json b= /tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json index a2c27794c0d8..7dc7eb0d3dd3 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/metricgroups.json @@ -5,7 +5,18 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", "DSB": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/= perf/pmu-events/arch/x86/sandybridge/other.json index 9f96121baef8..42692fa24b6c 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ri= ng 0.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Number of intervals between processor halts w= hile thread is in ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings = 1, 2, or 3.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Hardware Prefetch requests that miss the L1D = cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers= . A request is being counted each time it access the cache & miss it, inclu= ding if a block is applicable or if hit the Fill Buffer for .", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Valid instructions written to IQ per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or= split lock.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json b/too= ls/perf/pmu-events/arch/x86/sandybridge/pipeline.json index ecaf94ccc9c7..f2198bab5586 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event counts executed load operations wi= th all the following traits: 1. addressing of the format [base + offset], 2= . the offset is between 1 and 2047, 3. the address specified in the base re= gister is in one page and the address [base+offset] is in an.", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "AGU_BYPASS_CANCEL.COUNT", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide operations executed.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Cycles when divider is busy executing divide = operations.", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.FPU_DIV_ACTIVE", "SampleAfterValue": "2000003", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Speculative and retired branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Speculative and retired macro-conditional bra= nches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Speculative and retired macro-unconditional b= ranches excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_JMP", "SampleAfterValue": "200003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Speculative and retired direct near calls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Speculative and retired indirect branches exc= luding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Speculative and retired indirect return branc= hes.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ALL_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Not taken macro-conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branches.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Taken speculative and retired macro-condition= al branch instructions excluding calls and indirects.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_JUMP", "SampleAfterValue": "200003", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Taken speculative and retired direct near cal= ls.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect calls.= ", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Taken speculative and retired indirect branch= es with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN_INDIRECT_NEAR_RETURN", "SampleAfterValue": "200003", @@ -116,12 +132,14 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "SampleAfterValue": "400009" }, { "BriefDescription": "All (macro) branch instructions retired. (Pre= cise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. (Pre= cise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -138,6 +157,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "SampleAfterValue": "100007", @@ -145,6 +165,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -153,6 +174,7 @@ }, { "BriefDescription": "Direct and indirect macro near call instructi= ons retired (captured in ring 3). (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL_R3", "PEBS": "1", @@ -161,6 +183,7 @@ }, { "BriefDescription": "Return instructions retired. (Precise Event -= PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -169,6 +192,7 @@ }, { "BriefDescription": "Taken branch instructions retired. (Precise E= vent - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -177,6 +201,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", "SampleAfterValue": "400009", @@ -184,6 +209,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "SampleAfterValue": "200003", @@ -191,6 +217,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_CONDITIONAL", "SampleAfterValue": "200003", @@ -198,6 +225,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted direct n= ear calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -205,6 +233,7 @@ }, { "BriefDescription": "Mispredicted indirect branches excluding call= s and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -212,6 +241,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -220,6 +250,7 @@ }, { "BriefDescription": "Not taken speculative and retired mispredicte= d macro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NONTAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -227,6 +258,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted ma= cro conditional branches.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_CONDITIONAL", "SampleAfterValue": "200003", @@ -234,6 +266,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted di= rect near calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_DIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -241,6 +274,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches excluding calls and returns.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_JUMP_NON_CALL_RET", "SampleAfterValue": "200003", @@ -248,6 +282,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct calls.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_INDIRECT_NEAR_CALL", "SampleAfterValue": "200003", @@ -255,6 +290,7 @@ }, { "BriefDescription": "Taken speculative and retired mispredicted in= direct branches with return mnemonic.", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN_RETURN_NEAR", "SampleAfterValue": "200003", @@ -262,12 +298,14 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "SampleAfterValue": "400009" }, { "BriefDescription": "Mispredicted macro branch instructions retire= d. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -276,6 +314,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -284,6 +323,7 @@ }, { "BriefDescription": "Direct and indirect mispredicted near call in= structions retired. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -292,6 +332,7 @@ }, { "BriefDescription": "Mispredicted not taken branch instructions re= tired.(Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NOT_TAKEN", "PEBS": "1", @@ -300,6 +341,7 @@ }, { "BriefDescription": "Mispredicted taken branch instructions retire= d. (Precise Event - PEBS).", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN", "PEBS": "1", @@ -308,6 +350,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -315,6 +358,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "2000003", @@ -323,6 +367,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -330,6 +375,7 @@ }, { "BriefDescription": "Count XClk pulses when this thread is unhalte= d and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "2000003", @@ -337,6 +383,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "This event counts the number of reference cy= cles when the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction or the MWAIT instruction. This event = is not affected by core frequency changes (for example, P states, TM2 trans= itions) but has the same incrementing frequency as the time stamp counter. = This event can approximate elapsed time while the core was not in a halt st= ate. This event has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK eve= nt. It is counted on a dedicated fixed counter, leaving the four (eight whe= n Hyperthreading is disabled) programmable counters available for other eve= nts.", "SampleAfterValue": "2000003", @@ -344,6 +391,7 @@ }, { "BriefDescription": "Reference cycles when the thread is unhalted = (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "2000003", @@ -352,6 +400,7 @@ { "AnyThread": "1", "BriefDescription": "Reference cycles when the at least one thread= on the physical core is unhalted (counts at 100 MHz rate).", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "2000003", @@ -359,6 +408,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "This event counts the number of core cycles = while the thread is not in a halt state. The thread enters the halt state w= hen it is running the HLT instruction. This event is a component in many ke= y event ratios. The core frequency may change from time to time due to tran= sitions associated with Enhanced Intel SpeedStep Technology or TM2. For thi= s reason this event may have a changing ratio with regards to time. When th= e core frequency is constant, this event can approximate elapsed time while= the core was not in the halt state. It is counted on a dedicated fixed cou= nter, leaving the four (eight when Hyperthreading is disabled) programmable= counters available for other events.", "SampleAfterValue": "2000003", @@ -367,12 +417,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003" @@ -380,12 +432,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread, increment by 1. Note this is in DCU and connected to Umask = 1. Miss Pending demand load should be deduced by OR-ing increment bits of D= CACHE_MISS_PEND.PENDING.", + "Counter": "2", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_PENDING", @@ -394,6 +448,7 @@ }, { "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load this thread (i.e. Non-completed valid SQ entry allocated for demand = load and waiting for Uncore), increment by 1. Note this is in MLC and conne= cted to Umask 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_PENDING", @@ -402,6 +457,7 @@ }, { "BriefDescription": "Each cycle there was no dispatch for this thr= ead, increment by 1. Note this is connect to Umask 2. No dispatch can be de= duced from the UOPS_EXECUTED event.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_NO_DISPATCH", @@ -410,6 +466,7 @@ }, { "BriefDescription": "Each cycle there was a miss-pending demand lo= ad this thread and no uops dispatched, increment by 1. Note this is in DCU = and connected to Umask 1 and 2. Miss Pending demand load should be deduced = by OR-ing increment bits of DCACHE_MISS_PEND.PENDING.", + "Counter": "2", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_PENDING", @@ -418,6 +475,7 @@ }, { "BriefDescription": "Each cycle there was a MLC-miss pending deman= d load and no uops dispatched on this thread (i.e. Non-completed valid SQ e= ntry allocated for demand load and waiting for Uncore), increment by 1. Not= e this is in MLC and connected to Umask 0 and 2.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_PENDING", @@ -426,6 +484,7 @@ }, { "BriefDescription": "Stall cycles because IQ is full.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000003", @@ -433,6 +492,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000003", @@ -440,6 +500,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= retired from execution. For instructions that consist of multiple micro-op= s, this event counts the retirement of the last micro-op of the instruction= . Counting continues during hardware interrupts, traps, and inside interrup= t handlers.", "SampleAfterValue": "2000003", @@ -447,12 +508,14 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event.", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Instructions retired. (Precise Event - PEBS).= ", + "Counter": "1", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "2", @@ -461,6 +524,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) e= xternal stall is sent to Instruction Decode Queue (IDQ) for the thread.", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RAT_STALL_CYCLES", "SampleAfterValue": "2000003", @@ -468,6 +532,7 @@ }, { "BriefDescription": "Number of cycles waiting for the checkpoints = in Resource Allocation Table (RAT) to be recovered after Nuke due to all ot= her cases except JEClear (e.g. whenever a ucode assist is needed like SSE e= xception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", @@ -477,6 +542,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", @@ -485,6 +551,7 @@ }, { "BriefDescription": "Number of occurrences waiting for the checkpo= ints in Resource Allocation Table (RAT) to be recovered after Nuke due to a= ll other cases except JEClear (e.g. whenever a ucode assist is needed like = SSE exception, memory disambiguation, etc...).", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -494,6 +561,7 @@ }, { "BriefDescription": "Number of cases where any load ends up with a= valid block-code written to the load buffer (including blocks due to Memor= y Order Buffer (MOB), Data Cache Unit (DCU), TLB, but load has no DCU miss)= .", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL_BLOCK", "SampleAfterValue": "100003", @@ -501,6 +569,7 @@ }, { "BriefDescription": "Loads delayed due to SB blocks, preceding sto= re operations with known addresses but unknown data.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "SampleAfterValue": "100003", @@ -508,6 +577,7 @@ }, { "BriefDescription": "This event counts the number of times that sp= lit load operations are temporarily blocked because all resources for handl= ing the split accesses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "SampleAfterValue": "100003", @@ -515,6 +585,7 @@ }, { "BriefDescription": "Cases when loads get true Block-on-Store bloc= king code preventing store forwarding.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "This event counts loads that followed a stor= e to the same address, where the data could not be forwarded inside the pip= eline from the store to the load. The most common reason why store forward= ing would be blocked is when a load's address range overlaps with a precedi= ng smaller uncompleted store. See the table of not supported store forward= s in the Intel(R) 64 and IA-32 Architectures Optimization Reference Manual.= The penalty for blocked store forwarding is that the load must wait for t= he store to complete before it can be issued.", @@ -523,6 +594,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Aliasing occurs when a load is issued after = a store and their memory addresses are offset by 4K. This event counts the= number of loads that aliased with a preceding store, resulting in an exten= ded address check in the pipeline. The enhanced address check typically ha= s a performance penalty of 5 cycles.", @@ -531,6 +603,7 @@ }, { "BriefDescription": "This event counts the number of times that lo= ad operations are temporarily blocked because of older stores, with address= es that are not yet known. A load operation may incur more than one block o= f this type.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ALL_STA_BLOCK", "SampleAfterValue": "100003", @@ -538,6 +611,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for hardware prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.HW_PF", "SampleAfterValue": "100003", @@ -545,6 +619,7 @@ }, { "BriefDescription": "Not software-prefetch load dispatches that hi= t FB allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "SampleAfterValue": "100003", @@ -552,6 +627,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -560,6 +636,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -568,6 +645,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "SampleAfterValue": "2000003", @@ -575,6 +653,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -584,6 +663,7 @@ }, { "BriefDescription": "This event counts the number of executed Inte= l AVX masked load operations that refer to an illegal address range with th= e mask bits set to 0.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MASKMOV", "PublicDescription": "Maskmov false fault - counts number of time = ucode passes through Maskmov flow due to instruction's mask being 0 while t= he flow was completed without raising a fault.", @@ -592,6 +672,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event is incremented when self-modifyin= g code (SMC) is detected, which causes a machine clear. Machine clears can= have a significant performance impact if they are happening frequently.", @@ -600,6 +681,7 @@ }, { "BriefDescription": "Retired instructions experiencing ITLB misses= .", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ITLB_MISS_RETIRED", "SampleAfterValue": "100003", @@ -607,6 +689,7 @@ }, { "BriefDescription": "Increments the number of flags-merge uops in = flight each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP", "SampleAfterValue": "2000003", @@ -614,6 +697,7 @@ }, { "BriefDescription": "Performance sensitive flags-merging uops adde= d by Sandy Bridge u-arch.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.FLAGS_MERGE_UOP_CYCLES", @@ -623,6 +707,7 @@ }, { "BriefDescription": "Multiply packed/scalar single precision uops = allocated.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.MUL_SINGLE_UOP", "SampleAfterValue": "2000003", @@ -630,6 +715,7 @@ }, { "BriefDescription": "Cycles with at least one slow LEA uop being a= llocated.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SLOW_LEA_WINDOW", "PublicDescription": "This event counts the number of cycles with = at least one slow LEA uop being allocated. A uop is generally considered as= slow LEA if it has three sources (for example, two sources and immediate) = regardless of whether it is a result of LEA instruction or not. Examples of= the slow LEA uop are or uops with base, index, and offset source operands = using base and index reqisters, where base is EBR/RBP/R13, using RIP relati= ve or 16-bit addressing modes. See the Intel(R) 64 and IA-32 Architectures = Optimization Reference Manual for more details about slow LEA instructions.= ", @@ -638,6 +724,7 @@ }, { "BriefDescription": "Resource-related stall cycles.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000003", @@ -645,6 +732,7 @@ }, { "BriefDescription": "Counts the cycles of stall due to lack of loa= d buffers.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LB", "SampleAfterValue": "2000003", @@ -652,6 +740,7 @@ }, { "BriefDescription": "Resource stalls due to load or store buffers = all being in use.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LB_SB", "SampleAfterValue": "2000003", @@ -659,6 +748,7 @@ }, { "BriefDescription": "Resource stalls due to memory buffers or Rese= rvation Station (RS) being fully utilized.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MEM_RS", "SampleAfterValue": "2000003", @@ -666,6 +756,7 @@ }, { "BriefDescription": "Resource stalls due to Rob being full, FCSW, = MXCSR and OTHER.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OOO_RSRC", "SampleAfterValue": "2000003", @@ -673,6 +764,7 @@ }, { "BriefDescription": "Cycles stalled due to re-order buffer full.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB", "SampleAfterValue": "2000003", @@ -680,6 +772,7 @@ }, { "BriefDescription": "Cycles stalled due to no eligible RS entry av= ailable.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS", "SampleAfterValue": "2000003", @@ -687,6 +780,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "SampleAfterValue": "2000003", @@ -694,6 +788,7 @@ }, { "BriefDescription": "Cycles with either free list is empty.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.ALL_FL_EMPTY", "SampleAfterValue": "2000003", @@ -701,6 +796,7 @@ }, { "BriefDescription": "Resource stalls2 control structures full for = physical registers.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.ALL_PRF_CONTROL", "SampleAfterValue": "2000003", @@ -708,6 +804,7 @@ }, { "BriefDescription": "Cycles when Allocator is stalled if BOB is fu= ll and new branch needs it.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.BOB_FULL", "SampleAfterValue": "2000003", @@ -715,6 +812,7 @@ }, { "BriefDescription": "Resource stalls out of order resources full.", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "RESOURCE_STALLS2.OOO_RSRC", "SampleAfterValue": "2000003", @@ -722,6 +820,7 @@ }, { "BriefDescription": "Count cases of saving new LBR.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "SampleAfterValue": "2000003", @@ -729,6 +828,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "SampleAfterValue": "2000003", @@ -736,6 +836,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -746,6 +847,7 @@ }, { "BriefDescription": "Uops dispatched from any thread.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_DISPATCHED.CORE", "SampleAfterValue": "2000003", @@ -753,6 +855,7 @@ }, { "BriefDescription": "Uops dispatched per thread.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_DISPATCHED.THREAD", "SampleAfterValue": "2000003", @@ -760,6 +863,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "SampleAfterValue": "2000003", @@ -768,6 +872,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 0.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0_CORE", "SampleAfterValue": "2000003", @@ -775,6 +880,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "SampleAfterValue": "2000003", @@ -783,6 +889,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 1.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1_CORE", "SampleAfterValue": "2000003", @@ -790,6 +897,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "SampleAfterValue": "2000003", @@ -798,6 +906,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 2.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2_CORE", "SampleAfterValue": "2000003", @@ -805,6 +914,7 @@ }, { "BriefDescription": "Cycles per thread when load or STA uops are d= ispatched to port 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "SampleAfterValue": "2000003", @@ -813,6 +923,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when load or STA uops are dis= patched to port 3.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3_CORE", "SampleAfterValue": "2000003", @@ -820,6 +931,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "SampleAfterValue": "2000003", @@ -828,6 +940,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 4.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4_CORE", "SampleAfterValue": "2000003", @@ -835,6 +948,7 @@ }, { "BriefDescription": "Cycles per thread when uops are dispatched to= port 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "SampleAfterValue": "2000003", @@ -843,6 +957,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles per core when uops are dispatched to p= ort 5.", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5_CORE", "SampleAfterValue": "2000003", @@ -850,6 +965,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -858,6 +974,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -866,6 +983,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -874,6 +992,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -882,6 +1001,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", "Invert": "1", @@ -890,6 +1010,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS).", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "This event counts the number of Uops issued = by the front-end of the pipeilne to the back-end.", @@ -899,6 +1020,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for all threads.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -908,6 +1030,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -917,6 +1040,7 @@ }, { "BriefDescription": "Actually retired uops. (Precise Event - PEBS)= .", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -926,6 +1050,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.CORE_STALL_CYCLES", @@ -935,6 +1060,7 @@ }, { "BriefDescription": "Retirement slots used. (Precise Event - PEBS)= .", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -944,6 +1070,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -953,6 +1080,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "10", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json b/= tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json index ce836ebda542..ff2e515c744a 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/snb-metrics.json @@ -73,7 +73,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "1 - (tma_frontend_bound + tma_bad_speculation + tma= _retiring)", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -94,7 +94,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -124,7 +124,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.FPU_DIV_ACTIVE / tma_info_core_core_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_UOPS", @@ -152,7 +152,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "(7 * DTLB_LOAD_MISSES.STLB_HIT + DTLB_LOAD_MISSES.W= ALK_DURATION) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_UOPS_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store", @@ -226,7 +226,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -296,13 +296,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -399,7 +399,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "(12 * ITLB_MISSES.STLB_HIT + ITLB_MISSES.WALK_DURAT= ION) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: ITLB_M= ISSES.WALK_COMPLETED", @@ -438,7 +438,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -448,7 +448,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D6@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_info_system_dram_bw_use", @@ -457,7 +457,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: ", @@ -505,7 +505,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json b= /tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json index be9a3ed1a940..8379dae91be4 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_ES", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_I", "PerPkg": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_M", "PerPkg": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "L3 Lookup external snoop request that access = cache and found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.EXTSNP_MESI", "PerPkg": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_M", "PerPkg": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in I-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_I", "PerPkg": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state.", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -129,6 +145,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EVICTION", "PerPkg": "1", @@ -137,6 +154,7 @@ }, { "BriefDescription": "An external snoop hits a modified line in som= e processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_EXTERNAL", "PerPkg": "1", @@ -145,6 +163,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", @@ -153,6 +172,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which hits a non-modified line in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EVICTION", "PerPkg": "1", @@ -161,6 +181,7 @@ }, { "BriefDescription": "An external snoop hits a non-modified line in= some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_EXTERNAL", "PerPkg": "1", @@ -169,6 +190,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", @@ -177,6 +199,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", @@ -185,6 +208,7 @@ }, { "BriefDescription": "An external snoop misses in some processor co= re.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EXTERNAL", "PerPkg": "1", @@ -193,6 +217,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect= .json b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json index c3252c094a9c..ba340e858ed4 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles weighted by number of requests pending= in Coherency Tracker.", + "Counter": "0", "EventCode": "0x83", "EventName": "UNC_ARB_COH_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of requests allocated in Coherency Tra= cker.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts cycles weighted by the number of reque= sts waiting for data returning from the memory controller. Accounts for coh= erent and non-coherent requests initiated by IA cores, processor graphic un= its, or LLC.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with at least half of the requests out= standing are waiting for data return from memory controller. Account for co= herent and non-coherent requests initiated by IA Cores, Processor Graphics = Unit, or LLC.", + "Counter": "0,1", "CounterMask": "10", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_OVER_HALF_FULL", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0,1", "CounterMask": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts the number of coherent and in-coherent= requests initiated by IA cores, processor graphic units, or LLC.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of LLC evictions allocated.= ", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.EVICTIONS", "PerPkg": "1", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Counts the number of allocated write entries,= include full, partial, and LLC evictions.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", @@ -67,6 +75,7 @@ }, { "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les.", + "Counter": "Fixed", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json= b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json index fa08d355b97e..e0f6eb95455d 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "This event counts load operations that miss = the first DTLB level but hit the second and do not cause any page walks. Th= e penalty in this case is approximately 7 cycles.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Load misses at all DTLB levels that cause com= pleted page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss= handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB leve= l but hit the second and do not cause page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -45,6 +51,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause co= mpleted page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -52,6 +59,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "SampleAfterValue": "2000003", @@ -59,6 +67,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk. = The Extended Page Directory cache is used by Virtual Machine operating sys= tems while the guest operating systems use the standard TLB caches.", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -66,6 +75,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "SampleAfterValue": "100007", @@ -73,6 +83,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "SampleAfterValue": "100003", @@ -80,6 +91,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but= hit the second and do not cause any page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -87,6 +99,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause complete= d page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "100003", @@ -94,6 +107,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event count cycles when Page Miss Handl= er (PMH) is servicing page walks caused by ITLB misses.", @@ -102,6 +116,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries.", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "SampleAfterValue": "100007", @@ -109,6 +124,7 @@ }, { "BriefDescription": "STLB flush attempts.", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "SampleAfterValue": "100007", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yw1-f201.google.com (mail-yw1-f201.google.com [209.85.128.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 658071BB6A1 for ; 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Thu, 20 Jun 2024 11:20:20 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:42 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-29-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 28/37] perf vendor events: Add/update sapphirerapids events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.20 to v1.23. Update TMA metrics from v4.7 to v4.8. Bring in the event updates v1.23: https://github.com/intel/perfmon/commit/6ace93281c0f573b90d3f8f624486ad59dd= e1c93 v1.22: https://github.com/intel/perfmon/commit/356eba05c07c4d54ed5b92c1164ce00fab5= 45636 The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ New events are: EXE_ACTIVITY.2_3_PORTS_UTIL, ICACHE_DATA.STALL_PERIODS, L2_TRANS.L2_WB, MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024, OFFCORE_REQUESTS.DEMAND_CODE_RD, OFFCORE_REQUESTS.DEMAND_RFO, OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD, OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD, RS.EMPTY_RESOURCE, SW_PREFETCH_ACCESS.ANY, UOPS_ISSUED.CYCLES. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/sapphirerapids/cache.json | 161 +- .../arch/x86/sapphirerapids/counter.json | 82 + .../x86/sapphirerapids/floating-point.json | 28 + .../arch/x86/sapphirerapids/frontend.json | 50 + .../arch/x86/sapphirerapids/memory.json | 50 + .../arch/x86/sapphirerapids/metricgroups.json | 13 + .../arch/x86/sapphirerapids/other.json | 48 + .../arch/x86/sapphirerapids/pipeline.json | 133 ++ .../arch/x86/sapphirerapids/spr-metrics.json | 411 ++--- .../arch/x86/sapphirerapids/uncore-cache.json | 1244 ++++++++++++++ .../arch/x86/sapphirerapids/uncore-cxl.json | 110 ++ .../sapphirerapids/uncore-interconnect.json | 1427 +++++++++++++++++ .../arch/x86/sapphirerapids/uncore-io.json | 679 ++++++++ .../x86/sapphirerapids/uncore-memory.json | 742 +++++++++ .../arch/x86/sapphirerapids/uncore-power.json | 49 + .../x86/sapphirerapids/virtual-memory.json | 20 + 17 files changed, 5001 insertions(+), 248 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sapphirerapids/counter.j= son diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 51765cc94a3b..fb83c9a1bc5d 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -26,7 +26,7 @@ GenuineIntel-6-1[AEF],v4,nehalemep,core GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-6-A7,v1.03,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core -GenuineIntel-6-8F,v1.20,sapphirerapids,core +GenuineIntel-6-8F,v1.23,sapphirerapids,core GenuineIntel-6-AF,v1.02,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json b/too= ls/perf/pmu-events/arch/x86/sapphirerapids/cache.json index b0447aad0dfc..eec7bf6ebd53 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.HWPF_MISS", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -34,6 +38,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L1D_PEND_MISS.L2_STALLS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALLS", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -67,6 +75,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -74,14 +83,17 @@ "UMask": "0x1f" }, { - "BriefDescription": "L2_LINES_OUT.NON_SILENT", + "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.NON_SILENT", + "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Cache lines that have been L2 hardware prefet= ched but not used by demand accesses", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_LINES_OUT.USELESS_HWPF", "PublicDescription": "Counts the number of cache lines that have b= een prefetched by the L2 hardware prefetcher but not used by demand access = when evicted from the L2 cache", @@ -98,6 +111,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_RQSTS.REFERENCES]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_RQSTS.REFERENCES]", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_RQSTS.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_RQSTS.MISS]", @@ -114,6 +129,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -122,6 +138,7 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", @@ -130,6 +147,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Counts demand requests that miss L2 cache.", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Counts demand requests to L2 cache.", @@ -146,6 +165,7 @@ }, { "BriefDescription": "L2_RQSTS.ALL_HWPF", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_HWPF", "SampleAfterValue": "200003", @@ -153,6 +173,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -161,6 +182,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -169,6 +191,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -177,6 +200,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -185,6 +209,7 @@ }, { "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", @@ -193,6 +218,7 @@ }, { "BriefDescription": "L2_RQSTS.HWPF_MISS", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.HWPF_MISS", "SampleAfterValue": "200003", @@ -200,6 +226,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache. [Th= is event is alias to L2_REQUEST.MISS]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses. [This event is alias to L2_REQUEST.MISS]", @@ -208,6 +235,7 @@ }, { "BriefDescription": "All accesses to L2 cache [This event is alias= to L2_REQUEST.ALL]", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses. [This event is alias to L2_REQUEST.ALL]", @@ -216,6 +244,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -224,6 +253,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -232,6 +262,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -240,14 +271,25 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", "SampleAfterValue": "200003", "UMask": "0x28" }, + { + "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", + "EventCode": "0x23", + "EventName": "L2_TRANS.L2_WB", + "PublicDescription": "Counts L2 writebacks that access L2 cache.", + "SampleAfterValue": "200003", + "UMask": "0x40" + }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -256,6 +298,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that refer= to L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts core-originated cacheable requests to= the L3 cache (Longest Latency cache). Requests include data and code reads= , Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches = to the L1 and L2. It does not include hardware prefetches to the L3, and m= ay not count other types of requests to the L3.", @@ -264,6 +307,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -274,6 +318,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -284,6 +329,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -294,6 +340,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -304,6 +351,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -314,6 +362,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -324,6 +373,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -334,6 +384,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -344,6 +395,7 @@ }, { "BriefDescription": "Completed demand load uops that miss the L1 d= -cache.", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY", "PublicDescription": "Number of completed demand load requests tha= t missed the L1 data cache including shadow misses (FB hits, merge to an on= going L1D miss)", @@ -352,6 +404,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -362,6 +415,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -372,6 +426,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -382,6 +437,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -392,6 +448,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -402,6 +459,7 @@ }, { "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -411,6 +469,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -421,6 +480,7 @@ }, { "BriefDescription": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -430,6 +490,7 @@ }, { "BriefDescription": "Retired load instructions with remote Intel(R= ) Optane(TM) DC persistent memory as the data source where the data request= missed all caches.", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM", "PEBS": "1", @@ -439,6 +500,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -449,6 +511,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -459,6 +522,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -469,6 +533,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -479,6 +544,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -489,6 +555,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -499,6 +566,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -509,6 +577,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -519,6 +588,7 @@ }, { "BriefDescription": "Retired load instructions with local Intel(R)= Optane(TM) DC persistent memory as the data source where the data request = missed all caches.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM", @@ -529,6 +599,7 @@ }, { "BriefDescription": "MEM_STORE_RETIRED.L2_HIT", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "MEM_STORE_RETIRED.L2_HIT", "SampleAfterValue": "200003", @@ -536,6 +607,7 @@ }, { "BriefDescription": "Retired memory uops for any access", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe5", "EventName": "MEM_UOP_RETIRED.ANY", "PublicDescription": "Number of retired micro-operations (uops) fo= r load or store memory accesses", @@ -544,6 +616,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit in the L3 or were snooped from another co= re's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -553,6 +626,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that resulted in a snoop hit a modified line in an= other core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -562,6 +636,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that hit a modified line in a distant L3 Cache or = were snooped from a distant core's L1/L2 caches on this socket when the sys= tem is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -571,6 +646,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that either hit a non-modified line in a distant L= 3 Cache or were snooped from a distant core's L1/L2 caches on this socket w= hen the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -580,6 +656,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 o= r were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -589,6 +666,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit a modified line in another core's caches which forwarded the data.= ", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -598,6 +676,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop that hit in another core, which did not forward the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -607,6 +686,7 @@ }, { "BriefDescription": "Counts demand data reads that resulted in a s= noop hit in another core's caches which forwarded the unmodified data to th= e requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -616,6 +696,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit a modified line in another c= ore's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -625,6 +706,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y a cache on a remote socket where a snoop hit in another core's caches whi= ch forwarded the unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -634,6 +716,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a modified = line in a distant L3 Cache or were snooped from a distant core's L1/L2 cach= es on this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -643,6 +726,7 @@ }, { "BriefDescription": "Counts demand data reads that either hit a no= n-modified line in a distant L3 Cache or were snooped from a distant core's= L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) m= ode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -652,6 +736,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit in= the L3 or were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -661,6 +746,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that result= ed in a snoop hit a modified line in another core's caches which forwarded = the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -670,6 +756,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = modified line in a distant L3 Cache or were snooped from a distant core's L= 1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mod= e.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -679,6 +766,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that either= hit a non-modified line in a distant L3 Cache or were snooped from a dista= nt core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA c= luster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -688,6 +776,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t hit in the L3 or were snooped from another core's caches on the same sock= et.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -697,6 +786,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit in the L3 or were snooped from another core's caches on the sa= me socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -706,6 +796,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit a modified line in another core's caches w= hich forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -715,6 +806,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop that hit in another core, which did not forwar= d the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -724,6 +816,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that resulted in a snoop hit in another core's caches which forwarded t= he unmodified data to the requesting core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -733,6 +826,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop was sent= and data was returned (Modified or Not Modified).", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -742,6 +836,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit a mo= dified line in another core's caches which forwarded the data.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -751,6 +846,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by a cache on a remote socket where a snoop hit in a= nother core's caches which forwarded the unmodified data to the requesting = core.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -760,6 +856,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that hit a modified line in a distant L3 Cache or were snooped from a d= istant core's L1/L2 caches on this socket when the system is in SNC (sub-NU= MA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM", "MSRIndex": "0x1a6,0x1a7", @@ -769,6 +866,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that either hit a non-modified line in a distant L3 Cache or were snoop= ed from a distant core's L1/L2 caches on this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -778,6 +876,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO), hard= ware prefetch RFOs (which bring data to L2), and software prefetches for ex= clusive ownership (PREFETCHW) that hit to a (M)odified cacheline in the L3 = or snoop filter.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.RFO_TO_CORE.L3_HIT_M", "MSRIndex": "0x1a6,0x1a7", @@ -787,6 +886,7 @@ }, { "BriefDescription": "Counts streaming stores that hit in the L3 or= were snooped from another core's caches on the same socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -796,6 +896,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "SampleAfterValue": "100003", @@ -803,22 +904,43 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", "SampleAfterValue": "100003", "UMask": "0x8" }, + { + "BriefDescription": "Cacheable and noncacheable code read requests= ", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", + "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", + "SampleAfterValue": "100003", + "UMask": "0x2" + }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", + "EventCode": "0x21", + "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", + "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", + "SampleAfterValue": "100003", + "UMask": "0x4" + }, { "BriefDescription": "This event is deprecated. Refer to new event = OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", @@ -827,14 +949,26 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA= _RD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", "SampleAfterValue": "1000003", "UMask": "0x8" }, + { + "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, { "BriefDescription": "Cycles where at least 1 outstanding demand da= ta read request is pending.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -843,6 +977,7 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMA= ND_RFO", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -851,13 +986,24 @@ }, { "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD", "SampleAfterValue": "1000003", "UMask": "0x8" }, + { + "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", + "EventCode": "0x20", + "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", + "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, { "BriefDescription": "For every cycle, increments by the number of = outstanding demand data read requests pending.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= outstanding demand data read requests pending. Requests are considered o= utstanding from the time they miss the core's L2 cache until the transactio= n completion message is sent to the requestor.", @@ -866,14 +1012,24 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", "SampleAfterValue": "100003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x40", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -882,6 +1038,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -890,6 +1047,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -898,6 +1056,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/counter.json b/t= ools/perf/pmu-events/arch/x86/sapphirerapids/counter.json new file mode 100644 index 000000000000..088d5954747c --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/counter.json @@ -0,0 +1,82 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M3UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CXLCM", + "CountersNumFixed": "0", + "CountersNumGeneric": "8" + }, + { + "Unit": "CXLDP", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "MCHBM", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2HBM", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "MDF", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.j= son b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json index 1bdefaf96287..bc475e163227 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.FPDIV_ACTIVE", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -17,6 +19,7 @@ }, { "BriefDescription": "ASSISTS.SSE_AVX_MIX", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.SSE_AVX_MIX", "SampleAfterValue": "1000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0 [This event is ali= as to FP_ARITH_DISPATCHED.V0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_0", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1 [This event is ali= as to FP_ARITH_DISPATCHED.V1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_1", "SampleAfterValue": "2000003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5 [This event is ali= as to FP_ARITH_DISPATCHED.V2]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.PORT_5", "SampleAfterValue": "2000003", @@ -45,6 +51,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V0 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_0]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V0", "SampleAfterValue": "2000003", @@ -52,6 +59,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V1 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_1]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V1", "SampleAfterValue": "2000003", @@ -59,6 +67,7 @@ }, { "BriefDescription": "FP_ARITH_DISPATCHED.V2 [This event is alias t= o FP_ARITH_DISPATCHED.PORT_5]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb3", "EventName": "FP_ARITH_DISPATCHED.V2", "SampleAfterValue": "2000003", @@ -66,6 +75,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -82,6 +93,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -106,6 +120,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -114,6 +129,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -122,6 +138,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -130,6 +147,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -146,6 +165,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -154,6 +174,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "PublicDescription": "Number of any Vector retired FP arithmetic i= nstructions. The DAZ and FTZ flags in the MXCSR register need to be set wh= en using these events.", @@ -162,6 +183,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.128B_PACKED_HALF", "SampleAfterValue": "100003", @@ -169,6 +191,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.256B_PACKED_HALF", "SampleAfterValue": "100003", @@ -176,6 +199,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.512B_PACKED_HALF", "SampleAfterValue": "100003", @@ -183,6 +207,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF", "SampleAfterValue": "100003", @@ -190,6 +215,7 @@ }, { "BriefDescription": "Number of all Scalar Half-Precision FP arithm= etic instructions(1) retired - regular and complex.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.SCALAR", "PublicDescription": "FP_ARITH_INST_RETIRED2.SCALAR", @@ -198,6 +224,7 @@ }, { "BriefDescription": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.SCALAR_HALF", "SampleAfterValue": "100003", @@ -205,6 +232,7 @@ }, { "BriefDescription": "Number of all Vector (also called packed) Hal= f-Precision FP arithmetic instructions(1) retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcf", "EventName": "FP_ARITH_INST_RETIRED2.VECTOR", "PublicDescription": "FP_ARITH_INST_RETIRED2.VECTOR", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json b/= tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json index 93d99318a623..f6e3e40a3b20 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clears due to Unknown Branches.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "BACLEARS.ANY", "PublicDescription": "Number of times the front-end is resteered w= hen it finds a branch instruction in a fetch line. This is called Unknown B= ranch which occurs for the first time a branch instruction is fetched or wh= en the branch is not tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles the Microcode Sequencer is busy.", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.MS_BUSY", "SampleAfterValue": "500009", @@ -24,6 +27,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -87,6 +96,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -98,6 +108,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -109,6 +120,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -120,6 +132,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -131,6 +144,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -142,6 +156,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -153,6 +168,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -164,6 +180,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -175,6 +192,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -186,6 +204,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -197,6 +216,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -208,6 +228,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.MS_FLOWS", "MSRIndex": "0x3F7", @@ -218,6 +239,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -229,6 +251,7 @@ }, { "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH", "MSRIndex": "0x3F7", @@ -239,14 +262,26 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The decode pipeline works at a 32= Byte granularity.", "SampleAfterValue": "500009", "UMask": "0x4" }, + { + "BriefDescription": "ICACHE_DATA.STALL_PERIODS", + "Counter": "0,1,2,3", + "CounterMask": "1", + "EdgeDetect": "1", + "EventCode": "0x80", + "EventName": "ICACHE_DATA.STALL_PERIODS", + "SampleAfterValue": "500009", + "UMask": "0x4" + }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss.", @@ -255,6 +290,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -264,6 +300,7 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -273,6 +310,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -281,6 +319,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -290,6 +329,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -299,6 +339,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -307,6 +348,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -316,6 +358,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -326,6 +369,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS).", @@ -334,6 +378,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE= ]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_UOPS_NOT_DELIVERED.CORE]", @@ -342,6 +387,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE", @@ -351,6 +397,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_BUBBLES.CYCLES_FE_WAS_OK", @@ -361,6 +408,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled [This event is alias to IDQ_BUBBLES.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle. [This event is alias to IDQ_BUBBLES.CORE]", @@ -369,6 +417,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled [This event is alias to IDQ_= BUBBLES.CYCLES_0_UOPS_DELIV.CORE]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -378,6 +427,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled [This event is alias t= o IDQ_BUBBLES.CYCLES_FE_WAS_OK]", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json b/to= ols/perf/pmu-events/arch/x86/sapphirerapids/memory.json index 5420f529f491..2ea19539291b 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.CYCLES_L1D_MISS", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L1D_MISS", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L2_MISS", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand c= acheable load request is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "9", "EventCode": "0x47", "EventName": "MEMORY_ACTIVITY.STALLS_L3_MISS", @@ -49,8 +55,22 @@ "SampleAfterValue": "1000003", "UMask": "0x9" }, + { + "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 1024 cycles.", + "Counter": "1,2,3,4,5,6,7", + "Data_LA": "1", + "EventCode": "0xcd", + "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_1024", + "MSRIndex": "0x3F6", + "MSRValue": "0x400", + "PEBS": "2", + "PublicDescription": "Counts randomly selected loads when the late= ncy from first dispatch to completion is greater than 1024 cycles. Reporte= d latency may be longer than just the memory latency.", + "SampleAfterValue": "53", + "UMask": "0x1" + }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -63,6 +83,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -75,6 +96,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -87,6 +109,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -99,6 +122,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -111,6 +135,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -123,6 +148,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -135,6 +161,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -147,6 +174,7 @@ }, { "BriefDescription": "Retired memory store access operations. A PDi= st event for PEBS Store Latency Facility.", + "Counter": "0", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.STORE_SAMPLE", @@ -157,6 +185,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the local socket's L1, L= 2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -166,6 +195,7 @@ }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -175,6 +205,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were n= ot supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -184,6 +215,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t missed the local socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -193,6 +225,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -202,6 +235,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -211,6 +245,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and t= he cacheline is homed locally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -220,6 +255,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that missed the L3 Cache and were supplied by the local socket (DRAM or= PMM), whether or not in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts PM= M or DRAM accesses that are controlled by the close or distant SNC Cluster.= It does not count misses to the L3 which go to Local CXL Type 2 Memory or= Local Non DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL_SOCKET", "MSRIndex": "0x1a6,0x1a7", @@ -229,6 +265,7 @@ }, { "BriefDescription": "Counts streaming stores that missed the local= socket's L1, L2, and L3 caches.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -238,6 +275,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the local socket's L1, L2, or L3 caches and the cacheline is homed loc= ally.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -247,6 +285,7 @@ }, { "BriefDescription": "Counts demand data read requests that miss th= e L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "100003", @@ -254,6 +293,7 @@ }, { "BriefDescription": "For every cycle, increments by the number of = demand data read requests pending that are known to have missed the L3 cach= e.", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "For every cycle, increments by the number of= demand data read requests pending that are known to have missed the L3 cac= he. Note that this does not capture all elapsed cycles while requests are = outstanding - only cycles from when the requests were known by the requesti= ng core to have missed the L3 cache.", @@ -262,6 +302,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "1", @@ -271,6 +312,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -279,6 +321,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -287,6 +330,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -295,6 +339,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -303,6 +348,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -311,6 +357,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -319,6 +366,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -327,6 +375,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -335,6 +384,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/metricgroups.jso= n b/tools/perf/pmu-events/arch/x86/sapphirerapids/metricgroups.json index 81e5ca1c3078..e1de6c2675c4 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/metricgroups.json @@ -5,8 +5,21 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "C0Wait": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json b/too= ls/perf/pmu-events/arch/x86/sapphirerapids/other.json index 442ef3807a9d..05d8f14956ee 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ASSISTS.PAGE_FAULT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.PAGE_FAULT", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the cycles where the AMX (Advance Matr= ix Extension) unit is busy performing an operation.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb7", "EventName": "EXE.AMX_BUSY", "SampleAfterValue": "2000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM attached to this socket= , unless in Sub NUMA Cluster(SNC) Mode. In SNC Mode counts only those DRAM= accesses that are controlled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM on a distant memory con= troller of this socket when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_CODE_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mode. In S= NC Mode counts only those DRAM accesses that are controlled by the close SN= C Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to this socket, whether or not in Sub NUMA Cluster(SNC) Mode= . In SNC Mode counts PMM accesses that are controlled by the close or dist= ant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_SOCKET_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.PMM", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -105,6 +117,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.REMOTE_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -114,6 +127,7 @@ }, { "BriefDescription": "Counts demand data reads that were supplied b= y DRAM on a distant memory controller of this socket when the system is in = SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_DATA_RD.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that have a= ny type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -132,6 +147,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -141,6 +157,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM attached to this socket, unless in Sub NUMA Cluster(SNC) Mo= de. In SNC Mode counts only those DRAM accesses that are controlled by the= close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that were s= upplied by DRAM on a distant memory controller of this socket when the syst= em is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.DEMAND_RFO.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -159,6 +177,7 @@ }, { "BriefDescription": "Counts data load hardware prefetch requests t= o the L1 data cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L1D.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -168,6 +187,7 @@ }, { "BriefDescription": "Counts hardware prefetches (which bring data = to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L2.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -186,6 +207,7 @@ }, { "BriefDescription": "Counts hardware prefetches to the L3 only tha= t were not supplied by the local socket's L1, L2, or L3 caches and the cach= eline was homed in a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.HWPF_L3.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -195,6 +217,7 @@ }, { "BriefDescription": "Counts writebacks of modified cachelines and = streaming stores that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.MODIFIED_WRITE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +227,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -213,6 +237,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -222,6 +247,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, unless in Sub NUMA = Cluster(SNC) Mode. In SNC Mode counts only those DRAM accesses that are co= ntrolled by the close SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -231,6 +257,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to this socket, whether or not in S= ub NUMA Cluster(SNC) Mode. In SNC Mode counts DRAM accesses that are contr= olled by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -240,6 +267,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to this socket, whether or not in Su= b NUMA Cluster(SNC) Mode. In SNC Mode counts PMM accesses that are control= led by the close or distant SNC Cluster.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.LOCAL_SOCKET_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -249,6 +277,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were not supplied by the local socket's L1, L2, or L3 caches and w= ere supplied by a remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE", "MSRIndex": "0x1a6,0x1a7", @@ -258,6 +287,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -267,6 +297,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM or PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_MEMORY", "MSRIndex": "0x1a6,0x1a7", @@ -276,6 +307,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by PMM attached to another socket.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.REMOTE_PMM", "MSRIndex": "0x1a6,0x1a7", @@ -285,6 +317,7 @@ }, { "BriefDescription": "Counts all (cacheable) data read, code read a= nd RFO requests including demands and prefetches to the core caches (L1 or = L2) that were supplied by DRAM on a distant memory controller of this socke= t when the system is in SNC (sub-NUMA cluster) mode.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.READS_TO_CORE.SNC_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -294,6 +327,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -303,6 +337,7 @@ }, { "BriefDescription": "Counts Demand RFOs, ItoM's, PREFECTHW's, Hard= ware RFO Prefetches to the L1/L2 and Streaming stores that likely resulted = in a store to Memory (DRAM or PMM)", + "Counter": "0,1,2,3", "EventCode": "0x2A,0x2B", "EventName": "OCR.WRITE_ESTIMATE.MEMORY", "MSRIndex": "0x1a6,0x1a7", @@ -312,6 +347,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa5", "EventName": "RS.EMPTY", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -320,6 +356,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xa5", @@ -329,8 +366,17 @@ "SampleAfterValue": "100003", "UMask": "0x7" }, + { + "BriefDescription": "Cycles when Reservation Station (RS) is empty= due to a resource in the back-end", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa5", + "EventName": "RS.EMPTY_RESOURCE", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY_COUNT", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EdgeDetect": "1", @@ -342,6 +388,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = RS.EMPTY", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xa5", "EventName": "RS_EMPTY.CYCLES", @@ -350,6 +397,7 @@ }, { "BriefDescription": "Cycles the uncore cannot take further request= s", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x2d", "EventName": "XQ.FULL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json b/= tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json index e2086bedeca8..5d5811f26151 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.DIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.DIV_ACTIVE", @@ -19,6 +21,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.FPDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -28,6 +31,7 @@ }, { "BriefDescription": "This event counts the cycles the integer divi= der is busy.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb0", "EventName": "ARITH.IDIV_ACTIVE", @@ -36,6 +40,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = ARITH.IDIV_ACTIVE", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb0", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware. Examples include AD (page Access Dirt= y), FP and AVX related assists.", @@ -53,6 +59,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -70,6 +78,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -79,6 +88,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -88,6 +98,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -141,6 +157,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -159,6 +177,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -168,6 +187,7 @@ }, { "BriefDescription": "Miss-predicted near indirect branch instructi= ons retired (excluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -186,6 +207,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -195,6 +217,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -204,6 +227,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 li= ght-weight slower wakeup time but more power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C01", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 light-weight slower wakeup time but more power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -212,6 +236,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.2 li= ght-weight faster wakeup time but less power saving optimized state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C02", "PublicDescription": "Counts core clocks when the thread is in the= C0.2 light-weight faster wakeup time but less power saving optimized state= . This state can be entered via the TPAUSE or UMWAIT instructions.", @@ -220,6 +245,7 @@ }, { "BriefDescription": "Core clocks when the thread is in the C0.1 or= C0.2 or running a PAUSE in C0 ACPI state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.C0_WAIT", "PublicDescription": "Counts core clocks when the thread is in the= C0.1 or C0.2 power saving optimized states (TPAUSE or UMWAIT instructions)= or running the PAUSE instruction.", @@ -228,6 +254,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -236,6 +263,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -244,6 +272,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.PAUSE", "SampleAfterValue": "2000003", @@ -251,6 +280,7 @@ }, { "BriefDescription": "CPU_CLK_UNHALTED.PAUSE_INST", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xec", @@ -260,6 +290,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -268,6 +299,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the eight programmable counte= rs available for other events. Note: On all current platforms this event st= ops counting during 'throttling (TM)' states duty off periods the processor= is 'halted'. The counter update is done at a lower clock rate then the co= re clock the overflow status bit for this counter may appear 'sticky'. Aft= er the counter has overflowed and software clears the overflow status bit a= nd resets the counter to less than MAX. The reset value to the counter is n= ot clocked immediately so the overflow status bit will flip 'high (1)' and = generate another PMI (if enabled) after which the reset value gets clocked = into the counter. Therefore, software will get the interrupt, read the over= flow status bit '1 for bit 34 while the counter value is less than MAX. Sof= tware should ignore this case.", "SampleAfterValue": "2000003", @@ -275,6 +307,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. It is = counted on a dedicated fixed counter, leaving the four (eight when Hyperthr= eading is disabled) programmable counters available for other events. Note:= On all current platforms this event stops counting during 'throttling (TM)= ' states duty off periods the processor is 'halted'. The counter update is= done at a lower clock rate then the core clock the overflow status bit for= this counter may appear 'sticky'. After the counter has overflowed and so= ftware clears the overflow status bit and resets the counter to less than M= AX. The reset value to the counter is not clocked immediately so the overfl= ow status bit will flip 'high (1)' and generate another PMI (if enabled) af= ter which the reset value gets clocked into the counter. Therefore, softwar= e will get the interrupt, read the overflow status bit '1 for bit 34 while = the counter value is less than MAX. Software should ignore this case.", @@ -283,6 +316,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -290,6 +324,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -297,6 +332,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -305,6 +341,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -313,6 +350,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -321,6 +359,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -329,6 +368,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -337,6 +377,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -345,14 +386,24 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", "SampleAfterValue": "2000003", "UMask": "0x2" }, + { + "BriefDescription": "Cycles total of 2 or 3 uops are executed on a= ll ports and Reservation Station (RS) was not empty.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xa6", + "EventName": "EXE_ACTIVITY.2_3_PORTS_UTIL", + "SampleAfterValue": "2000003", + "UMask": "0xc" + }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -361,6 +412,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -369,6 +421,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -377,6 +430,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", @@ -385,6 +439,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -394,6 +449,7 @@ }, { "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", @@ -402,6 +458,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -410,6 +467,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -418,6 +476,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -426,6 +485,7 @@ }, { "BriefDescription": "INST_RETIRED.MACRO_FUSED", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -434,6 +494,7 @@ }, { "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Precise instruction retired with PEBS precise= -distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = precise distribution of samples across instructions retired. It utilizes th= e Precise Distribution of Instructions Retired (PDIR++) feature to fix bias= in how retired instructions get sampled. Use on Fixed Counter 0.", @@ -451,6 +513,7 @@ }, { "BriefDescription": "Iterations of Repeat string retired instructi= ons.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.REP_ITERATION", "PEBS": "1", @@ -460,6 +523,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xad", @@ -470,6 +534,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -478,6 +543,7 @@ }, { "BriefDescription": "INT_MISC.MBA_STALLS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.MBA_STALLS", "SampleAfterValue": "1000003", @@ -485,6 +551,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -493,6 +560,7 @@ }, { "BriefDescription": "Bubble cycles of BAClear (Unknown Branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UNKNOWN_BRANCH_CYCLES", "MSRIndex": "0x3F7", @@ -502,6 +570,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xad", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -510,6 +579,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.128BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.128BIT", "SampleAfterValue": "1000003", @@ -517,6 +587,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.256BIT", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.256BIT", "SampleAfterValue": "1000003", @@ -524,6 +595,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 128-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_128", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 128-bit vector instructions.", @@ -532,6 +604,7 @@ }, { "BriefDescription": "integer ADD, SUB, SAD 256-bit vector instruct= ions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.ADD_256", "PublicDescription": "Number of retired integer ADD/SUB (regular o= r horizontal), SAD 256-bit vector instructions.", @@ -540,6 +613,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.MUL_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.MUL_256", "SampleAfterValue": "1000003", @@ -547,6 +621,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.SHUFFLES", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.SHUFFLES", "SampleAfterValue": "1000003", @@ -554,6 +629,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_128", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_128", "SampleAfterValue": "1000003", @@ -561,6 +637,7 @@ }, { "BriefDescription": "INT_VEC_RETIRED.VNNI_256", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe7", "EventName": "INT_VEC_RETIRED.VNNI_256", "SampleAfterValue": "1000003", @@ -568,6 +645,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", @@ -576,6 +654,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -584,6 +663,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -592,6 +672,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -600,6 +681,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", @@ -609,6 +691,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "6", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -618,6 +701,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -626,6 +710,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -636,6 +721,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -644,6 +730,7 @@ }, { "BriefDescription": "LFENCE instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe0", "EventName": "MISC2_RETIRED.LFENCE", "PublicDescription": "number of LFENCE retired instructions", @@ -652,6 +739,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -660,6 +748,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -668,6 +757,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -675,6 +765,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Number of slots in TMA method where no micro= -operations were being issued from front-end to back-end of the machine due= to lack of back-end resources.", @@ -683,6 +774,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= s.", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BAD_SPEC_SLOTS", "PublicDescription": "Number of slots of TMA method that were wast= ed due to incorrect speculation. It covers all types of control-flow or dat= a-related mis-speculations.", @@ -691,6 +783,7 @@ }, { "BriefDescription": "TMA slots wasted due to incorrect speculation= by branch mispredictions", + "Counter": "0", "EventCode": "0xa4", "EventName": "TOPDOWN.BR_MISPREDICT_SLOTS", "PublicDescription": "Number of TMA slots that were wasted due to = incorrect speculation by (any type of) branch mispredictions. This event es= timates number of speculative operations that were issued but not retired a= s well as the out-of-order engine recovery past a branch misprediction.", @@ -699,6 +792,7 @@ }, { "BriefDescription": "TOPDOWN.MEMORY_BOUND_SLOTS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.MEMORY_BOUND_SLOTS", "SampleAfterValue": "10000003", @@ -706,6 +800,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -713,6 +808,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -721,6 +817,7 @@ }, { "BriefDescription": "UOPS_DECODED.DEC0_UOPS", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UOPS_DECODED.DEC0_UOPS", "SampleAfterValue": "1000003", @@ -728,6 +825,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Number of uops dispatch to execution port 0= .", @@ -736,6 +834,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Number of uops dispatch to execution port 1= .", @@ -744,6 +843,7 @@ }, { "BriefDescription": "Uops executed on ports 2, 3 and 10", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_2_3_10", "PublicDescription": "Number of uops dispatch to execution ports 2= , 3 and 10", @@ -752,6 +852,7 @@ }, { "BriefDescription": "Uops executed on ports 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Number of uops dispatch to execution ports 4= and 9", @@ -760,6 +861,7 @@ }, { "BriefDescription": "Uops executed on ports 5 and 11", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_5_11", "PublicDescription": "Number of uops dispatch to execution ports 5= and 11", @@ -768,6 +870,7 @@ }, { "BriefDescription": "Uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Number of uops dispatch to execution port 6= .", @@ -776,6 +879,7 @@ }, { "BriefDescription": "Uops executed on ports 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb2", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Number of uops dispatch to execution ports = 7 and 8.", @@ -784,6 +888,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -801,6 +907,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -810,6 +917,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -819,6 +927,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -828,6 +937,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -837,6 +947,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -846,6 +957,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -855,6 +967,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -864,6 +977,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.STALLS", @@ -874,6 +988,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_EXECUTED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xb1", @@ -884,6 +999,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -891,6 +1007,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -899,14 +1016,25 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xae", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", "SampleAfterValue": "2000003", "UMask": "0x1" }, + { + "BriefDescription": "UOPS_ISSUED.CYCLES", + "Counter": "0,1,2,3,4,5,6,7", + "CounterMask": "1", + "EventCode": "0xae", + "EventName": "UOPS_ISSUED.CYCLES", + "SampleAfterValue": "2000003", + "UMask": "0x1" + }, { "BriefDescription": "Cycles with retired uop(s).", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.CYCLES", @@ -916,6 +1044,7 @@ }, { "BriefDescription": "Retired uops except the last uop of each inst= ruction.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.HEAVY", "PublicDescription": "Counts the number of retired micro-operation= s (uops) except the last uop of each instruction. An instruction that is de= coded into less than two uops does not contribute to the count.", @@ -924,6 +1053,7 @@ }, { "BriefDescription": "UOPS_RETIRED.MS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "MSRIndex": "0x3F7", @@ -933,6 +1063,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -941,6 +1072,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALLS", @@ -951,6 +1083,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UOPS_RETIRED.STALLS", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "Deprecated": "1", "EventCode": "0xc2", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json= b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json index f8c0eac8b828..2b3b013ccb06 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/spr-metrics.json @@ -47,7 +47,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -72,18 +72,54 @@ "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", "ScaleUnit": "1per_instr" }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic controller (IIO) of IO reads that are initiated by end device controlle= rs that are requesting memory from the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e= 6 / duration_time", + "MetricName": "iio_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic controller (IIO) of IO writes that are initiated by end device controll= ers that are writing memory to the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1= e6 / duration_time", + "MetricName": "iio_bandwidth_write", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / durati= on_time", "MetricName": "io_bandwidth_read", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the local CPU socket.= ", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / = duration_time", + "MetricName": "io_bandwidth_read_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from a remote CPU socket.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 /= duration_time", + "MetricName": "io_bandwidth_read_remote", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.= IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time", "MetricName": "io_bandwidth_write", "ScaleUnit": "1MB/s" }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the local CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_IN= SERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to a remote CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_I= NSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_remote", + "ScaleUnit": "1MB/s" + }, { "BriefDescription": "Percentage of inbound full cacheline writes i= nitiated by end device controllers that miss the L3 cache.", "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM / UNC_CHA_TOR_INSE= RTS.IO_ITOM", @@ -334,7 +370,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the Advanced Matrix eXtensions (AMX) execution engine was busy with tile = (arithmetic) operations", "MetricExpr": "EXE.AMX_BUSY / tma_info_core_core_clks", - "MetricGroup": "Compute;HPC;Server;TopdownL3;tma_L3_group;tma_core= _bound_group", + "MetricGroup": "BvCB;Compute;HPC;Server;TopdownL3;tma_L3_group;tma= _core_bound_group", "MetricName": "tma_amx_busy", "MetricThreshold": "tma_amx_busy > 0.5 & (tma_core_bound > 0.1 & t= ma_backend_bound > 0.2)", "ScaleUnit": "100%" @@ -342,7 +378,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "78 * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -360,7 +396,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_inf= o_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -382,7 +418,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "DefaultMetricgroupName": "TopdownL2", "MetricExpr": "topdown\\-br\\-mispredict / (topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tm= a_info_thread_slots", - "MetricGroup": "BadSpec;BrMispredicts;Default;TmaL2;TopdownL2;tma_= L2_group;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;Default;TmaL2;TopdownL2= ;tma_L2_group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2;Default", @@ -434,8 +470,8 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", - "MetricExpr": "(76 * tma_info_system_core_frequency * (MEM_LOAD_L3= _HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND= _DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))= ) + 75.5 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MI= SS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_in= fo_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricExpr": "(76.6 * tma_info_system_core_frequency * (MEM_LOAD_= L3_HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMA= ND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD= ))) + 74.6 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_= MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_= info_thread_clks", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related m= etrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote= _cache", @@ -454,8 +490,8 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", - "MetricExpr": "75.5 * tma_info_system_core_frequency * (MEM_LOAD_L= 3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEM= AND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR= .DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT= / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricExpr": "74.6 * tma_info_system_core_frequency * (MEM_LOAD_L= 3_HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEM= AND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR= .DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT= / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -473,7 +509,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIV_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -503,13 +539,13 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - MEMOR= Y_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -518,7 +554,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -526,8 +562,8 @@ }, { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", - "MetricExpr": "80 * tma_info_system_core_frequency * OCR.DEMAND_RF= O.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricExpr": "81 * tma_info_system_core_frequency * OCR.DEMAND_RF= O.L3_HIT.SNOOP_HITM / tma_info_thread_clks", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -536,7 +572,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -550,7 +586,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2;Default", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -602,7 +638,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,uma= sk\\=3D0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR) / (tma_retiring * tma_info_th= read_slots)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_INST_RETIR= ED2.VECTOR) / (tma_retiring * tma_info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -640,7 +676,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -650,7 +686,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.MACRO_FUSED / (= tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", @@ -670,7 +706,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -724,24 +760,6 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(100 * (1 - max(0, topdown\\-be\\-bound / (topdown\= \-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-b= ound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown\\-bad\\-spe= c + topdown\\-retiring + topdown\\-be\\-bound)) / (((cpu@EXE_ACTIVITY.3_POR= TS_UTIL\\,umask\\=3D0x80@ + cpu@RS.EMPTY\\,umask\\=3D0x1@) / CPU_CLK_UNHALT= ED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / C= PU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UT= IL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + to= pdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\\,= umask\\=3D0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIV_ACTIVE < CYCLE_ACTI= VITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIVITY.1_PORTS_= UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + = topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_PORTS_UTIL\= \,umask\\=3D0xc@) / CPU_CLK_UNHALTED.THREAD) if max(0, topdown\\-be\\-bound= / (topdown\\-fe\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topd= own\\-be\\-bound) - topdown\\-mem\\-bound / (topdown\\-fe\\-bound + topdown= \\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound)) < (((cpu@EXE_AC= TIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + cpu@RS.EMPTY\\,umask\\=3D0x1@) / CP= U_CLK_UNHALTED.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_O= N_LOADS) / CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVIT= Y.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-bad= \\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2_P= ORTS_UTIL\\,umask\\=3D0xc@)) / CPU_CLK_UNHALTED.THREAD if ARITH.DIV_ACTIVE = < CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS else (EXE_ACTIV= ITY.1_PORTS_UTIL + topdown\\-retiring / (topdown\\-fe\\-bound + topdown\\-b= ad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) * cpu@EXE_ACTIVITY.2= _PORTS_UTIL\\,umask\\=3D0xc@) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_inf= o_system_smt_2t_utilization > 0.5 else 0) + 0 * slots", - "MetricGroup": "Cor;SMT", - "MetricName": "tma_info_botlnk_core_bound_likely" - }, - { - "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (100 * ((topdown\\-fetch\\-lat / (topdown\\-f= e\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-boun= d) - INT_MISC.UOP_DROPPING / slots) * (DSB2MITE_SWITCHES.PENALTY_CYCLES / C= PU_CLK_UNHALTED.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + I= CACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES= / CPU_CLK_UNHALTED.THREAD + INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHAL= TED.THREAD) + min(3 * cpu@UOPS_RETIRED.MS\\,cmask\\=3D0x1\\,edge\\=3D0x1@ /= (UOPS_RETIRED.SLOTS / UOPS_ISSUED.ANY) / CPU_CLK_UNHALTED.THREAD, 1) + DEC= ODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_= CLK_UNHALTED.THREAD) + max(0, topdown\\-fe\\-bound / (topdown\\-fe\\-bound = + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_M= ISC.UOP_DROPPING / slots - (topdown\\-fetch\\-lat / (topdown\\-fe\\-bound += topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MI= SC.UOP_DROPPING / slots)) * ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (= CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2) = / ((IDQ.MITE_CYCLES_ANY - IDQ.MITE_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUT= ED if #SMT_on else CPU_CLK_UNHALTED.THREAD) / 2 + (IDQ.DSB_CYCLES_ANY - IDQ= .DSB_CYCLES_OK) / (CPU_CLK_UNHALTED.DISTRIBUTED if #SMT_on else CPU_CLK_UNH= ALTED.THREAD) / 2)))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "tma_info_botlnk_dsb_misses" - }, - { - "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", - "MetricExpr": "100 * (100 * ((topdown\\-fetch\\-lat / (topdown\\-f= e\\-bound + topdown\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-boun= d) - INT_MISC.UOP_DROPPING / slots) * (ICACHE_DATA.STALLS / CPU_CLK_UNHALTE= D.THREAD) / (ICACHE_DATA.STALLS / CPU_CLK_UNHALTED.THREAD + ICACHE_TAG.STAL= LS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCLES / CPU_CLK_UNH= ALTED.THREAD + INT_MISC.UNKNOWN_BRANCH_CYCLES / CPU_CLK_UNHALTED.THREAD) + = min(3 * cpu@UOPS_RETIRED.MS\\,cmask\\=3D0x1\\,edge\\=3D0x1@ / (UOPS_RETIRED= .SLOTS / UOPS_ISSUED.ANY) / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_= CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.T= HREAD)))", - "MetricGroup": "Fed;FetchLat;IcMiss", - "MetricName": "tma_info_botlnk_ic_misses" - }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricExpr": "(100 * (1 - tma_core_bound / tma_ports_utilization = if tma_core_bound < tma_ports_utilization else 1) if tma_info_system_smt_2t= _utilization > 0.5 else 0)", @@ -749,13 +767,21 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricExpr": "100 * (tma_fetch_latency * tma_dsb_switches / (tma_= branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_misses + = tma_lcp + tma_ms_switches) + tma_fetch_bandwidth * tma_mite / (tma_dsb + tm= a_mite))", "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -765,39 +791,33 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads = + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)= ) + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma= _l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_sq_full= / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + tma_sq= _full)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tma_l1_bound= + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_f= b_full / (tma_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_laten= cy + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound)) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) = + tma_memory_bound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l= 2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_l3_hit_la= tency / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full)) + tma_memory_bound * tma_l2_bound / (tma_dram_bound + tma_l1_b= ound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound) + tma= _memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_= bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tma_store_laten= cy / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_lat= ency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound / (tma_dra= m_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_= store_bound)) * (tma_l1_hit_latency / (tma_dtlb_load + tma_fb_full + tma_l1= _hit_latency + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -805,30 +825,30 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_amx_busy= + tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_c= ore_bound * tma_amx_busy / (tma_amx_busy + tma_divider + tma_ports_utilizat= ion + tma_serializing_operation) + tma_core_bound * (tma_ports_utilization = / (tma_amx_busy + tma_divider + tma_ports_utilization + tma_serializing_ope= ration)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_utili= zed_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - (1 - I= NST_RETIRED.REP_ITERATION / cpu@UOPS_RETIRED.MS\\,cmask\\=3D1@) * (tma_fetc= h_latency * (tma_ms_switches + tma_branch_resteers * (tma_clears_resteers += tma_mispredicts_resteers * tma_other_mispredicts / tma_branch_mispredicts)= / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_branches))= / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + tma_itlb_m= isses + tma_lcp + tma_ms_switches))) - tma_info_bottleneck_big_code", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * ((1 - INST_RETIRED.REP_ITERATION / cpu@UOPS_R= ETIRED.MS\\,cmask\\=3D1@) * (tma_fetch_latency * (tma_ms_switches + tma_bra= nch_resteers * (tma_clears_resteers + tma_mispredicts_resteers * tma_other_= mispredicts / tma_branch_mispredicts) / (tma_clears_resteers + tma_mispredi= cts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma_dsb_swit= ches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)) + = 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_mispredic= ts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes / tma_ot= her_nukes + tma_core_bound * (tma_serializing_operation + cpu@RS.EMPTY\\,um= ask\\=3D1@ / tma_info_thread_clks * tma_ports_utilized_0) / (tma_amx_busy += tma_divider + tma_ports_utilization + tma_serializing_operation) + tma_mic= rocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) * = (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" }, { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_fw= d_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_bo= und + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma_store_bound)) * (tm= a_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma= _store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_pmm_bound + tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_= dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split= _loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_d= ram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tm= a_store_bound)) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + t= ma_split_stores + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -836,7 +856,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_pmm_bound + tma= _store_bound) * (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) *= tma_remote_cache / (tma_local_mem + tma_remote_cache + tma_remote_mem) + t= ma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound = + tma_pmm_bound + tma_store_bound) * (tma_contested_accesses + tma_data_sha= ring) / (tma_contested_accesses + tma_data_sharing + tma_l3_hit_latency + t= ma_sq_full) + tma_store_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bou= nd + tma_l3_bound + tma_pmm_bound + tma_store_bound) * tma_false_sharing / = (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency = + tma_streaming_stores - tma_store_latency)) + tma_machine_clears * (1 - tm= a_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -844,18 +864,25 @@ { "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -907,7 +934,7 @@ }, { "BriefDescription": "Floating Point Operations Per Cycle", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_R= ETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARIT= H_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / t= ma_info_core_core_clks", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_= INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 = * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS)= + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.51= 2B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / tma_inf= o_core_core_clks", "MetricGroup": "Flops;Ret", "MetricName": "tma_info_core_flopc" }, @@ -930,7 +957,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 6 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -997,7 +1024,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED2.SCALAR + (cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUB= LE\\,umask\\=3D0xfc@ + FP_ARITH_INST_RETIRED2.VECTOR))", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED2.SCALAR + (FP_ARITH_INST_RETIRED.VECTOR + FP_ARITH_IN= ST_RETIRED2.VECTOR))", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -1067,7 +1094,7 @@ }, { "BriefDescription": "Instructions per Floating Point (FP) Operatio= n (lower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_= FLOPS + 8 * FP_ARITH_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B= _PACKED_SINGLE)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED= _DOUBLE + FP_ARITH_INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_R= ETIRED.4_FLOPS + 8 * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_IN= ST_RETIRED.8_FLOPS) + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_AR= ITH_INST_RETIRED.512B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PAC= KED_HALF)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_ipflop", "MetricThreshold": "tma_info_inst_mix_ipflop < 10" @@ -1100,24 +1127,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 13", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" - }, - { - "BriefDescription": "\"Bus lock\" per kilo instruction", - "MetricExpr": "tma_info_memory_mix_bus_lock_pki", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_bus_lock_pki" - }, - { - "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", - "MetricGroup": "Fed;MemoryTLB", - "MetricName": "tma_info_memory_code_stlb_mpki" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -1155,12 +1170,6 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, - { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -1168,17 +1177,11 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -1192,29 +1195,11 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, - { - "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" - }, - { - "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_silent_pki" - }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", @@ -1246,29 +1231,23 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duratio= n_time * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -1283,7 +1262,7 @@ }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", + "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, @@ -1293,29 +1272,11 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_load_l2_mlp" }, - { - "BriefDescription": "Average Latency for L3 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l3_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l3_miss_latency" - }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / cpu@O= FFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD\\,cmask\\=3D0x1@", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L3 cache miss demand Load= s", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD= / OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l3_miss_latency" + "MetricName": "tma_info_memory_latency_load_l3_miss_latency" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -1323,12 +1284,6 @@ "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, - { - "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_load_stlb_mpki" - }, { "BriefDescription": "\"Bus lock\" per kilo instruction", "MetricExpr": "1e3 * SQ_MISC.BUS_LOCK / INST_RETIRED.ANY", @@ -1355,7 +1310,7 @@ }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "tma_info_memory_uc_load_pki", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -1366,51 +1321,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Off-core accesses per kilo instruction for mo= dified write requests", - "MetricExpr": "1e3 * OCR.MODIFIED_WRITE.ANY_RESPONSE / INST_RETIRE= D.ANY", - "MetricGroup": "Offcore", - "MetricName": "tma_info_memory_offcore_mwrite_any_pki" - }, - { - "BriefDescription": "Off-core accesses per kilo instruction for re= ads-to-core requests (speculative; including in-core HW prefetches)", - "MetricExpr": "1e3 * OCR.READS_TO_CORE.ANY_RESPONSE / INST_RETIRED= .ANY", - "MetricGroup": "CacheHits;Offcore", - "MetricName": "tma_info_memory_offcore_read_any_pki" - }, - { - "BriefDescription": "L3 cache misses per kilo instruction for read= s-to-core requests (speculative; including in-core HW prefetches)", - "MetricExpr": "1e3 * OCR.READS_TO_CORE.L3_MISS / INST_RETIRED.ANY", - "MetricGroup": "Offcore", - "MetricName": "tma_info_memory_offcore_read_l3m_pki" - }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "(ITLB_MISSES.WALK_PENDING + DTLB_LOAD_MISSES.WALK_P= ENDING + DTLB_STORE_MISSES.WALK_PENDING) / (4 * (CPU_CLK_UNHALTED.DISTRIBUT= ED if #SMT_on else CPU_CLK_UNHALTED.THREAD))", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, - { - "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) cover= ing for memory attached to local- and remote-socket", - "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / (duration_time = * 1e3 / 1e3)", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "tma_info_memory_r2c_dram_bw", - "PublicDescription": "Average DRAM BW for Reads-to-Core (R2C) cove= ring for memory attached to local- and remote-socket. See R2C_Offcore_BW." - }, - { - "BriefDescription": "Average L3-cache miss BW for Reads-to-Core (R= 2C)", - "MetricExpr": "64 * OCR.READS_TO_CORE.L3_MISS / 1e9 / (duration_ti= me * 1e3 / 1e3)", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "tma_info_memory_r2c_l3m_bw", - "PublicDescription": "Average L3-cache miss BW for Reads-to-Core (= R2C). This covering going to DRAM or other memory off-chip memory tears. Se= e R2C_Offcore_BW." - }, - { - "BriefDescription": "Average Off-core access BW for Reads-to-Core = (R2C)", - "MetricExpr": "64 * OCR.READS_TO_CORE.ANY_RESPONSE / 1e9 / (durati= on_time * 1e3 / 1e3)", - "MetricGroup": "HPC;Mem;MemoryBW;SoC", - "MetricName": "tma_info_memory_r2c_offcore_bw", - "PublicDescription": "Average Off-core access BW for Reads-to-Core= (R2C). R2C account for demand or prefetch load/RFO/code access that fill d= ata into the Core caches." - }, { "BriefDescription": "Average DRAM BW for Reads-to-Core (R2C) cover= ing for memory attached to local- and remote-socket", "MetricExpr": "64 * OCR.READS_TO_CORE.DRAM / 1e9 / duration_time", @@ -1432,12 +1342,6 @@ "MetricName": "tma_info_memory_soc_r2c_offcore_bw", "PublicDescription": "Average Off-core access BW for Reads-to-Core= (R2C). R2C account for demand or prefetch load/RFO/code access that fill d= ata into the Core caches." }, - { - "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_store_stlb_mpki" - }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -1464,17 +1368,23 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_uc_load_pki" - }, - { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", @@ -1511,13 +1421,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1530,7 +1440,7 @@ }, { "BriefDescription": "Giga Floating Point Operations Per Second", - "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + 2 * FP_ARITH_INST_R= ETIRED.128B_PACKED_DOUBLE + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 * FP_ARIT= H_INST_RETIRED.8_FLOPS + 16 * FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE) / 1= e9 / duration_time", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED2.SCALAR_HALF + 2 * (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_= INST_RETIRED2.COMPLEX_SCALAR_HALF) + 4 * FP_ARITH_INST_RETIRED.4_FLOPS + 8 = * (FP_ARITH_INST_RETIRED2.128B_PACKED_HALF + FP_ARITH_INST_RETIRED.8_FLOPS)= + 16 * (FP_ARITH_INST_RETIRED2.256B_PACKED_HALF + FP_ARITH_INST_RETIRED.51= 2B_PACKED_SINGLE) + 32 * FP_ARITH_INST_RETIRED2.512B_PACKED_HALF) / 1e9 / d= uration_time", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_system_gflops", "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width" @@ -1685,7 +1595,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1721,7 +1631,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1736,10 +1646,19 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - MEMORY_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricExpr": "(MEMORY_ACTIVITY.STALLS_L1D_MISS - MEMORY_ACTIVITY.= STALLS_L2_MISS) / tma_info_thread_clks", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1756,8 +1675,8 @@ }, { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", - "MetricExpr": "33 * tma_info_system_core_frequency * (MEM_LOAD_RET= IRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2))= / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricExpr": "32.6 * tma_info_system_core_frequency * (MEM_LOAD_R= ETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2= )) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1769,7 +1688,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1810,11 +1729,11 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from local memory", - "MetricExpr": "71 * tma_info_system_core_frequency * MEM_LOAD_L3_M= ISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1= _MISS / 2) / tma_info_thread_clks", + "MetricExpr": "72 * tma_info_system_core_frequency * MEM_LOAD_L3_M= ISS_RETIRED.LOCAL_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1= _MISS / 2) / tma_info_thread_clks", "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", "MetricName": "tma_local_mem", "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 &= (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)= ))", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM_PS", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM", "ScaleUnit": "100%" }, { @@ -1823,14 +1742,14 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "DefaultMetricgroupName": "TopdownL2", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;Default;MachineClears;TmaL2;TopdownL2;tma_= L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;Default;MachineClears;TmaL2;TopdownL2= ;tma_L2_group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2;Default", @@ -1848,7 +1767,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1857,7 +1776,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1903,7 +1822,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "tma_branch_mispredicts / tma_bad_speculation * INT_= MISC.CLEAR_RESTEER_CYCLES / tma_info_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1939,7 +1858,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - INST_RETIRED.MACRO_FUSED) / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", @@ -1948,7 +1867,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1966,7 +1885,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1974,7 +1893,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -2035,7 +1954,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + = cpu@RS.EMPTY\\,umask\\=3D1@) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALL= S_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_thread_clks", + "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + max(cpu@RS.EMPTY\= \,umask\\=3D1@ - RESOURCE_STALLS.SCOREBOARD, 0)) / tma_info_thread_clks * (= CYCLE_ACTIVITY.STALLS_TOTAL - EXE_ACTIVITY.BOUND_ON_LOADS) / tma_info_threa= d_clks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -2065,7 +1984,7 @@ "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -2073,7 +1992,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote cache in other socket= s including synchronizations issues", - "MetricExpr": "(135.5 * tma_info_system_core_frequency * MEM_LOAD_= L3_MISS_RETIRED.REMOTE_HITM + 135.5 * tma_info_system_core_frequency * MEM_= LOAD_L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_= RETIRED.L1_MISS / 2) / tma_info_thread_clks", + "MetricExpr": "(133 * tma_info_system_core_frequency * MEM_LOAD_L3= _MISS_RETIRED.REMOTE_HITM + 133 * tma_info_system_core_frequency * MEM_LOAD= _L3_MISS_RETIRED.REMOTE_FWD) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETI= RED.L1_MISS / 2) / tma_info_thread_clks", "MetricGroup": "Offcore;Server;Snoop;TopdownL5;tma_L5_group;tma_is= sueSyncxn;tma_mem_latency_group", "MetricName": "tma_remote_cache", "MetricThreshold": "tma_remote_cache > 0.05 & (tma_mem_latency > 0= .1 & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > = 0.2)))", @@ -2082,7 +2001,7 @@ }, { "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling loads from remote memory", - "MetricExpr": "149 * tma_info_system_core_frequency * MEM_LOAD_L3_= MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.= L1_MISS / 2) / tma_info_thread_clks", + "MetricExpr": "153 * tma_info_system_core_frequency * MEM_LOAD_L3_= MISS_RETIRED.REMOTE_DRAM * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.= L1_MISS / 2) / tma_info_thread_clks", "MetricGroup": "Server;Snoop;TopdownL5;tma_L5_group;tma_mem_latenc= y_group", "MetricName": "tma_remote_mem", "MetricThreshold": "tma_remote_mem > 0.1 & (tma_mem_latency > 0.1 = & (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2= )))", @@ -2093,7 +2012,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -2103,7 +2022,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks += tma_c02_wait", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -2149,7 +2068,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(XQ.FULL_CYCLES + L1D_PEND_MISS.L2_STALLS) / tma_in= fo_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -2176,7 +2095,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(MEM_STORE_RETIRED.L2_HIT * 10 * (1 - MEM_INST_RETI= RED.LOCK_LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE= _REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -2219,7 +2138,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "INT_MISC.UNKNOWN_BRANCH_CYCLES / tma_info_thread_cl= ks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: FRONTEND_RETIRED.UNKNOWN_BRANCH", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.jso= n b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json index 25a2b9695135..a38db3e253f2 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cache.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", "UMask": "0x2", @@ -10,8 +12,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", "UMask": "0x4", @@ -19,8 +23,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", "UMask": "0x1", @@ -28,6 +34,7 @@ }, { "BriefDescription": "CHA Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", @@ -36,6 +43,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", @@ -43,8 +51,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0xf2", @@ -52,8 +62,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", "UMask": "0xf1", @@ -61,8 +73,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", @@ -70,8 +84,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", "UMask": "0x41", @@ -79,8 +95,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", @@ -88,8 +106,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", "UMask": "0x81", @@ -97,8 +117,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x22", @@ -106,8 +128,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x21", @@ -115,8 +139,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Snoop Tar= gets from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Snoop Ta= rgets from Remote : Counts the number of transactions that trigger a config= urable number of cross snoops. Cores are snooped if the transaction looks = up the cache and determines that it is necessary based on the operation typ= e and what CoreValid bits are set. For example, if 2 CV bits are set on a = data read, the cores must have the data in S state so it is not necessary t= o snoop them. However, if only 1 CV bit is set the core my have modified t= he data. If the transaction was an RFO, it would need to invalidate the li= nes. This event can be filtered based on who triggered the initial snoop(s= ).", "UMask": "0x12", @@ -124,8 +150,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Snoop Targe= t from Remote", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.REMOTE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Snoop Targ= et from Remote : Counts the number of transactions that trigger a configura= ble number of cross snoops. Cores are snooped if the transaction looks up = the cache and determines that it is necessary based on the operation type a= nd what CoreValid bits are set. For example, if 2 CV bits are set on a dat= a read, the cores must have the data in S state so it is not necessary to s= noop them. However, if only 1 CV bit is set the core my have modified the = data. If the transaction was an RFO, it would need to invalidate the lines= . This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x11", @@ -133,96 +161,120 @@ }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6e", "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6d", "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts transactions that looked into the mul= ti-socket cacheline Directory state, and therefore did not send a snoop bec= ause the Directory indicated it was not needed.", "UMask": "0x2", @@ -230,8 +282,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts transactions that looked into the mu= lti-socket cacheline Directory state, and sent one or more snoops, because = the Directory indicated it was needed.", "UMask": "0x1", @@ -239,6 +293,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", @@ -248,6 +303,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", @@ -257,8 +313,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -266,8 +324,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -275,8 +335,10 @@ }, { "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts read requests from a remote socket wh= ich hit in the HitME cache (used to cache the multi-socket Directory state)= to a line in the E(Exclusive) state. This includes the following read opc= odes (RdCode, RdData, RdDataMigratory, RdCur, RdInv*, Inv*).", "UMask": "0x1", @@ -284,80 +346,100 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : Shared= hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : op is = WbMtoE", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache : op is = WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d : op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : No S= F/LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : op i= s RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache : SF/L= LC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Deallocate HitME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a local request : Received RspFwdI= * for a local request, but converted HitME$ to SF entry", "UMask": "0x1", @@ -365,16 +447,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Allocate/Update to HitM= e Cache : op is RspIFwd or RspIFwdWb for a remote request : Updated HitME$ = on RspFwdI* or local HitM/E received for a remote request", "UMask": "0x2", @@ -382,14 +468,17 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache : Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -399,8 +488,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", "UMask": "0x2", @@ -408,6 +499,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -417,8 +509,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", "UMask": "0x4", @@ -426,8 +520,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", "UMask": "0x2", @@ -435,8 +531,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", "UMask": "0x8", @@ -444,8 +542,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1fffff", @@ -453,8 +553,10 @@ }, { "BriefDescription": "Cache Lookups : All transactions from Remote = Agents", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All transactions from Remote= Agents : Counts the number of times the LLC was accessed - this includes c= ode, data, prefetches and hints coming from L2. This has numerous filters = available. Note the non-standard filtering equation. This event will coun= t requests that lookup the cache multiple times with multiple increments. = One must ALWAYS select a state or states (in the umask field) to match. Ot= herwise, the event will count nothing.", "UMask": "0x17e0ff", @@ -462,16 +564,20 @@ }, { "BriefDescription": "Cache Lookups : All Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Any local or remote transaction to the LLC, including pref= etch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1bd0ff", @@ -479,24 +585,30 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Local non-prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local non-prefetch requests = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Any local transaction to the LLC, not inclu= ding prefetch", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1bc1ff", @@ -504,8 +616,10 @@ }, { "BriefDescription": "Cache Lookups : Data Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1fc1ff", @@ -513,16 +627,20 @@ }, { "BriefDescription": "Cache Lookups : Data Read Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Request : Counts t= he number of times the LLC was accessed - this includes code, data, prefetc= hes and hints coming from L2. This has numerous filters available. Note t= he non-standard filtering equation. This event will count requests that lo= okup the cache multiple times with multiple increments. One must ALWAYS se= t umask bit 0 and select a state or states to match. Otherwise, the event = will count nothing. : Read transactions.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Demand Data Reads, Core and L= LC prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Demand Data Reads, Core and = LLC prefetches : Counts the number of times the LLC was accessed - this inc= ludes code, data, prefetches and hints coming from L2. This has numerous f= ilters available. Note the non-standard filtering equation. This event wi= ll count requests that lookup the cache multiple times with multiple increm= ents. One must ALWAYS select a state or states (in the umask field) to mat= ch. Otherwise, the event will count nothing.", "UMask": "0x841ff", @@ -530,8 +648,10 @@ }, { "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1fc101", @@ -539,8 +659,10 @@ }, { "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Exclusive State", "UMask": "0x20", @@ -548,8 +670,10 @@ }, { "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Forward State", "UMask": "0x80", @@ -557,8 +681,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a44ff", @@ -566,16 +692,20 @@ }, { "BriefDescription": "Cache Lookups : Flush", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Miss", "UMask": "0x1", @@ -583,16 +713,20 @@ }, { "BriefDescription": "Cache Lookups : Local LLC prefetch requests (= from LLC)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LLCPREF_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local LLC prefetch requests = (from LLC) : Counts the number of times the LLC was accessed - this include= s code, data, prefetches and hints coming from L2. This has numerous filte= rs available. Note the non-standard filtering equation. This event will c= ount requests that lookup the cache multiple times with multiple increments= . One must ALWAYS set umask bit 0 and select a state or states to match. = Otherwise, the event will count nothing. : Any local LLC prefetch to the LL= C", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed locally", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS set umask bit 0 and select a state or states to match. Otherwise, t= he event will count nothing. : Transaction whose address resides in the loc= al MC.", "UMask": "0xbdfff", @@ -600,8 +734,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x19d0ff", @@ -609,8 +745,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x19c1ff", @@ -618,8 +756,10 @@ }, { "BriefDescription": "Cache Lookups : Demand CRd Requests that come= from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1850ff", @@ -627,8 +767,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Demand Data R= eads that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1841ff", @@ -636,8 +778,10 @@ }, { "BriefDescription": "Cache Lookups : Demand RFO Requests that come= from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1848ff", @@ -645,16 +789,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed locally", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS set umask bit 0 and select a state or states to match. Otherwise, t= he event will count nothing. : Transaction whose address resides in the loc= al MC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests = that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1844ff", @@ -662,8 +810,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Prefetch requ= ests to the LLC that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x189dff", @@ -671,8 +821,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Pre= fetches that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x199dff", @@ -680,8 +832,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Prefetches that come from= the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1910ff", @@ -689,8 +843,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Pre= fetches that come from the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1981ff", @@ -698,8 +854,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Prefetches that come from= the local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1908ff", @@ -707,8 +865,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests that come from t= he local socket (usually the core)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x19c8ff", @@ -716,8 +876,10 @@ }, { "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Modified State", "UMask": "0x40", @@ -725,8 +887,10 @@ }, { "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x1fe001", @@ -734,24 +898,30 @@ }, { "BriefDescription": "Cache Lookups : Write Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Remote non-snoop requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.PREF_OR_DMND_REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote non-snoop requests : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS set umask bit 0 and select a state or states to match. Otherwise, th= e event will count nothing. : Remote non-snoop transactions to the LLC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Transactions homed remotely", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "UMask": "0x15dfff", @@ -759,8 +929,10 @@ }, { "BriefDescription": "Cache Lookups : CRd Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote CRd transactions to the LLC. This include= s CRd prefetch.", "UMask": "0x1a10ff", @@ -768,8 +940,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uests that come from a Remote socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1a01ff", @@ -777,16 +951,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed remotely", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Flush or Invalidate requests = that come from a Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a04ff", @@ -794,8 +972,10 @@ }, { "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache that come from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "UMask": "0x1a02ff", @@ -803,8 +983,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests that come from a= Remote socket.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1a08ff", @@ -812,16 +994,20 @@ }, { "BriefDescription": "Cache Lookups : Remote snoop requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote snoop requests : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : Remote snoop transactions to the LLC.", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Snoop Request= s from a Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1c19ff", @@ -829,8 +1015,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1bc8ff", @@ -838,16 +1026,20 @@ }, { "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing. : Local or remo= te RFO transactions to the LLC. This includes RFO prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Locally HOMed RFOs - Demand a= nd Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x9c8ff", @@ -855,8 +1047,10 @@ }, { "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS set umask bi= t 0 and select a state or states to match. Otherwise, the event will count= nothing. : Hit Shared State", "UMask": "0x10", @@ -864,8 +1058,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit Exclusive State", "UMask": "0x4", @@ -873,8 +1069,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit HitMe State", "UMask": "0x8", @@ -882,8 +1080,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S set umask bit 0 and select a state or states to match. Otherwise, the ev= ent will count nothing. : SF Hit Shared State", "UMask": "0x2", @@ -891,8 +1091,10 @@ }, { "BriefDescription": "Cache Lookups : Writes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing. : Requests that= install or change a line in the LLC. Examples: Writebacks from Core L2= 's and UPI. Prefetches into the LLC.", "UMask": "0x842ff", @@ -900,8 +1102,10 @@ }, { "BriefDescription": "Cache Lookups : Remote Writes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS select a state or states (in the umask= field) to match. Otherwise, the event will count nothing.", "UMask": "0x17c2ff", @@ -909,8 +1113,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x2", @@ -918,8 +1124,10 @@ }, { "BriefDescription": "Lines Victimized : IA traffic", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : IA traffic : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "UMask": "0x20", @@ -927,8 +1135,10 @@ }, { "BriefDescription": "Lines Victimized : IO traffic", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : IO traffic : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "UMask": "0x10", @@ -936,8 +1146,10 @@ }, { "BriefDescription": "All LLC lines in E state that are victimized = on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x12", @@ -945,8 +1157,10 @@ }, { "BriefDescription": "All LLC lines in F or S state that are victim= ized on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_FS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1c", @@ -954,8 +1168,10 @@ }, { "BriefDescription": "All LLC lines in M state that are victimized = on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x11", @@ -963,8 +1179,10 @@ }, { "BriefDescription": "All LLC lines in any state that are victimize= d on a fill from an IO device", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO_MESF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1f", @@ -972,8 +1190,10 @@ }, { "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x200f", @@ -981,8 +1201,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2002", @@ -990,8 +1212,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2001", @@ -999,16 +1223,20 @@ }, { "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x2004", @@ -1016,8 +1244,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x1", @@ -1025,8 +1255,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x800f", @@ -1034,8 +1266,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8002", @@ -1043,8 +1277,10 @@ }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8001", @@ -1052,16 +1288,20 @@ }, { "BriefDescription": "Lines Victimized : Remote Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote Only : Counts the = number of lines that were victimized on a fill. This can be filtered by th= e state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Counts the number of line= s that were victimized on a fill. This can be filtered by the state that t= he line was in.", "UMask": "0x8004", @@ -1069,8 +1309,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x4", @@ -1078,8 +1320,10 @@ }, { "BriefDescription": "All LLC lines in E state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2", @@ -1087,8 +1331,10 @@ }, { "BriefDescription": "All LLC lines in M state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x1", @@ -1096,8 +1342,10 @@ }, { "BriefDescription": "All LLC lines in S state that are victimized = on a fill", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x4", @@ -1105,8 +1353,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", "UMask": "0x20", @@ -1114,8 +1364,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", "UMask": "0x10", @@ -1123,8 +1375,10 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x8", @@ -1132,8 +1386,10 @@ }, { "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", "UMask": "0x1", @@ -1141,8 +1397,10 @@ }, { "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", @@ -1150,8 +1408,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local InvItoE : Count = of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be b= roadcast. Does not count all the snoops generated by OSB.", "UMask": "0x1", @@ -1159,8 +1419,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Local Rd : Count of OS= B snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadc= ast. Does not count all the snoops generated by OSB.", "UMask": "0x2", @@ -1168,8 +1430,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Off", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Off : Count of OSB sno= op broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. = Does not count all the snoops generated by OSB.", "UMask": "0x20", @@ -1177,8 +1441,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd : Count of O= SB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broad= cast. Does not count all the snoops generated by OSB.", "UMask": "0x4", @@ -1186,8 +1452,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd InvItoE", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READINVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : Remote Rd InvItoE : Co= unt of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to = be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x8", @@ -1195,8 +1463,10 @@ }, { "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadca= st : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB sno= ops to be broadcast. Does not count all the snoops generated by OSB.", "UMask": "0x10", @@ -1204,32 +1474,40 @@ }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_CHA_PMM_MEMMODE_NM_INVITOX.SETCONFLICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near Memory set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Near Memory evictions due to another read to= the same Near Memory set in the LLC.", "UMask": "0x2", @@ -1237,8 +1515,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near memory set conflict in SF/LLC", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.SF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Near Memory evictions due to another read to= the same Near Memory set in the SF", "UMask": "0x1", @@ -1246,8 +1526,10 @@ }, { "BriefDescription": "Memory Mode related events; Counts the number= of times CHA saw a Near Memory set conflict in TOR", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS.TOR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Reject in the CHA due to a pending read t= o the same Near Memory set in the TOR.", "UMask": "0x4", @@ -1255,88 +1537,110 @@ }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.IODC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_CHA_PMM_MEMMODE_NM_SETCONFLICTS2.MEMWRNI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.DDR4_FAST_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.REJ_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOWTORQ_SKIP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.SLOW_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_IRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Counter": "0,1,2,3", "EventCode": "0x66", "EventName": "UNC_CHA_PMM_QOS.THROTTLE_PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_FAST_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": count # of FAST TOR Request inserted to ha= _tor_req_fifo", "UMask": "0x2", @@ -1344,16 +1648,20 @@ }, { "BriefDescription": "Number of SLOW TOR Request inserted to ha_pmm= _tor_req_fifo", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_CHA_PMM_QOS_OCCUPANCY.DDR_SLOW_FIFO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", "UMask": "0x1", @@ -1361,8 +1669,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", "UMask": "0x2", @@ -1370,8 +1680,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", "UMask": "0x4", @@ -1379,8 +1691,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", "UMask": "0x8", @@ -1388,8 +1702,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", @@ -1397,8 +1713,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", @@ -1406,8 +1724,10 @@ }, { "BriefDescription": "Requests for exclusive ownership of a cache l= ine without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", "UMask": "0x30", @@ -1415,6 +1735,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -1424,6 +1745,7 @@ }, { "BriefDescription": "Remote requests for exclusive ownership of a = cache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -1433,6 +1755,7 @@ }, { "BriefDescription": "Read requests made into the CHA", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -1442,6 +1765,7 @@ }, { "BriefDescription": "Read requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -1451,6 +1775,7 @@ }, { "BriefDescription": "Read requests from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -1460,6 +1785,7 @@ }, { "BriefDescription": "Write requests made into the CHA", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -1469,6 +1795,7 @@ }, { "BriefDescription": "Write Requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -1478,6 +1805,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes Remote", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -1487,8 +1815,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IPQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x4", @@ -1496,8 +1826,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", @@ -1505,8 +1837,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", "UMask": "0x2", @@ -1514,8 +1848,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", @@ -1523,8 +1859,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", @@ -1532,8 +1870,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : RRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x40", @@ -1541,8 +1881,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : WBQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x80", @@ -1550,8 +1892,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1559,8 +1903,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1568,8 +1914,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -1577,8 +1925,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1586,8 +1936,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1595,8 +1947,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1604,8 +1958,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1613,8 +1969,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -1622,16 +1980,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IPQ0 Reject counter was true", "UMask": "0x1", @@ -1639,16 +2001,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -1656,16 +2022,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -1673,8 +2043,10 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IPQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -1682,16 +2054,20 @@ }, { "BriefDescription": "IPQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1699,8 +2075,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1708,8 +2086,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -1717,8 +2097,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1726,8 +2108,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1735,8 +2119,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1744,8 +2130,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1753,8 +2141,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -1762,16 +2152,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", "UMask": "0x1", @@ -1779,16 +2173,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -1796,24 +2194,30 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -1821,16 +2225,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1838,8 +2246,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1847,8 +2257,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -1856,8 +2268,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1865,8 +2279,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1874,8 +2290,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1883,8 +2301,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1892,8 +2312,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -1901,8 +2323,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -1910,8 +2334,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -1919,8 +2345,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -1928,8 +2356,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -1937,8 +2367,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -1946,8 +2378,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -1955,8 +2389,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -1964,8 +2400,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -1973,8 +2411,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -1982,8 +2422,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -1991,8 +2433,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2000,8 +2444,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2009,8 +2455,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IPQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x4", @@ -2018,8 +2466,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : RRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : RRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x40", @@ -2027,8 +2477,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : WBQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : WBQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x80", @@ -2036,8 +2488,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", "UMask": "0x1", @@ -2045,8 +2499,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", "UMask": "0x2", @@ -2054,8 +2510,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", "UMask": "0x40", @@ -2063,8 +2521,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2072,8 +2532,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2081,8 +2543,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", "UMask": "0x4", @@ -2090,8 +2554,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", "UMask": "0x8", @@ -2099,8 +2565,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", "UMask": "0x80", @@ -2108,8 +2576,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", "UMask": "0x40", @@ -2117,8 +2587,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", "UMask": "0x1", @@ -2126,8 +2598,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", "UMask": "0x2", @@ -2135,8 +2609,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", "UMask": "0x20", @@ -2144,8 +2620,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", "UMask": "0x4", @@ -2153,8 +2631,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", "UMask": "0x80", @@ -2162,8 +2642,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", "UMask": "0x8", @@ -2171,8 +2653,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", "UMask": "0x10", @@ -2180,8 +2664,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2189,8 +2675,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2198,8 +2686,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2207,8 +2697,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2216,8 +2708,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2225,8 +2719,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2234,8 +2730,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2243,8 +2741,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -2252,16 +2752,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", "UMask": "0x1", @@ -2269,16 +2773,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2286,16 +2794,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -2303,8 +2815,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2312,16 +2826,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2329,8 +2847,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2338,8 +2858,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", @@ -2347,8 +2869,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2356,8 +2880,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2365,8 +2891,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2374,8 +2902,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2383,8 +2913,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", "UMask": "0x80", @@ -2392,8 +2924,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x40", @@ -2401,8 +2935,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -2410,8 +2946,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x2", @@ -2419,8 +2957,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2428,8 +2968,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x4", @@ -2437,8 +2979,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2446,8 +2990,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2455,8 +3001,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x10", @@ -2464,8 +3012,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2473,8 +3023,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2482,8 +3034,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -2491,8 +3045,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2500,8 +3056,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2509,8 +3067,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2518,8 +3078,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the RRQ (Remote Response Queue) had = to retry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2527,8 +3089,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the RRQ (Remote Response Queue= ) had to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -2536,8 +3100,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the RRQ (Remote Response Queue) had t= o retry.", "UMask": "0x40", @@ -2545,8 +3111,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the RRQ (Remote Response Queue) had to retry= . : Any condition listed in the RRQ0 Reject counter was true", "UMask": "0x1", @@ -2554,8 +3122,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2563,8 +3133,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2572,8 +3144,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the RRQ (Remote Response Queue) had to= retry.", "UMask": "0x4", @@ -2581,8 +3155,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the RRQ (Remote Response Queue) had= to retry. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2590,8 +3166,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the RRQ (Remote Response Queue) had to = retry. : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2599,8 +3177,10 @@ }, { "BriefDescription": "RRQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RRQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the RRQ (Remote Response Queue) had to ret= ry.", "UMask": "0x10", @@ -2608,8 +3188,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD REQ on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2617,8 +3199,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : AD RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2626,8 +3210,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI AK Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject AK ring message", "UMask": "0x40", @@ -2635,8 +3221,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCB on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2644,8 +3232,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL NCS on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2653,8 +3243,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL RSP on VN0 : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2662,8 +3254,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : BL WB on VN0 : Number = of times a transaction flowing through the WBQ (Writeback Queue) had to ret= ry. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2671,8 +3265,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 0 : Non UPI IV Request : N= umber of times a transaction flowing through the WBQ (Writeback Queue) had = to retry. : Can't inject IV ring message", "UMask": "0x80", @@ -2680,8 +3276,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Allow Snoop : Number o= f times a transaction flowing through the WBQ (Writeback Queue) had to retr= y.", "UMask": "0x40", @@ -2689,8 +3287,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : ANY0 : Number of times= a transaction flowing through the WBQ (Writeback Queue) had to retry. : An= y condition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -2698,8 +3298,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : HA : Number of times a= transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2707,8 +3309,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC OR SF Way : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2716,8 +3320,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : LLC Victim : Number of= times a transaction flowing through the WBQ (Writeback Queue) had to retry= .", "UMask": "0x4", @@ -2725,8 +3331,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : PhyAddr Match : Number= of times a transaction flowing through the WBQ (Writeback Queue) had to re= try. : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -2734,8 +3342,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : SF Victim : Number of = times a transaction flowing through the WBQ (Writeback Queue) had to retry.= : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2743,8 +3353,10 @@ }, { "BriefDescription": "WBQ Rejects - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WBQ Rejects - Set 1 : Victim : Number of tim= es a transaction flowing through the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2752,8 +3364,10 @@ }, { "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", "UMask": "0x1", @@ -2761,8 +3375,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoop for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoop for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= broadcast snoops issued by the HA. This filter includes only requests comi= ng from local sockets.", "UMask": "0x10", @@ -2770,8 +3386,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Remote Req= uests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Remote Re= quests : Counts the number of snoops issued by the HA. : Counts the number = of broadcast snoops issued by the HA.This filter includes only requests com= ing from remote sockets.", "UMask": "0x20", @@ -2779,8 +3397,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA. This filter includes only requests comin= g from local sockets.", "UMask": "0x40", @@ -2788,8 +3408,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Remote Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Remote Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f directed snoops issued by the HA. This filter includes only requests comi= ng from remote sockets.", "UMask": "0x80", @@ -2797,8 +3419,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast or directed Snoops se= nt for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast or directed Snoops s= ent for Local Requests : Counts the number of snoops issued by the HA. : Co= unts the number of broadcast or directed snoops issued by the HA per reques= t. This filter includes only requests coming from the local socket.", "UMask": "0x4", @@ -2806,8 +3430,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast or directed Snoops se= nt for Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast or directed Snoops s= ent for Remote Requests : Counts the number of snoops issued by the HA. : C= ounts the number of broadcast or directed snoops issued by the HA per reque= st. This filter includes only requests coming from the remote socket.", "UMask": "0x8", @@ -2815,8 +3441,10 @@ }, { "BriefDescription": "Snoop Responses Received : RSPCNFLCT*", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RSPCNFLCT* : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for snoops responses of RspC= onflict. This is returned when a snoop finds an existing outstanding trans= action in a remote caching agent when it CAMs that caching agent. This tri= ggers conflict resolution hardware. This covers both RspCnflct and RspCnfl= ctWbI.", "UMask": "0x40", @@ -2824,8 +3452,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RspFwd : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspFwd t= o a CA request. This snoop response is only possible for RdCur when a snoo= p HITM/E in a remote caching agent and it directly forwards data to a reque= stor without changing the requestor's cache line state.", "UMask": "0x80", @@ -2833,8 +3463,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*Fwd*WB", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*Fwd*WB : Coun= ts the total number of RspI snoop responses received. Whenever a snoops ar= e issued, one or more snoop responses will be returned depending on the top= ology of the system. In systems larger than 2s, when multiple snoops are = returned this will count all the snoops that are received. For example, if= 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of th= ese sub-events would increment by 1. : Filters for a snoop response of Rsp*= Fwd*WB. This snoop response is only used in 4s systems. It is used when a= snoop HITM's in a remote caching agent and it directly forwards data to a = requestor, and simultaneously returns data to the home to be written back t= o memory.", "UMask": "0x20", @@ -2842,8 +3474,10 @@ }, { "BriefDescription": "RspI Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspI Snoop Response was received which indicates the remote cache does n= ot have the data, or when the remote cache silently evicts data (such as wh= en an RFO: the Read for Ownership issued before a write hits non-modified d= ata).", "UMask": "0x1", @@ -2851,8 +3485,10 @@ }, { "BriefDescription": "RspIFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspIFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data and the requesting agent is able to acquire the dat= a in E (Exclusive) or M (modified) states. This is commonly returned with = RFO (the Read for Ownership issued before a write) transactions. The snoop= could have either been to a cacheline in the M,E,F (Modified, Exclusive or= Forward) states.", "UMask": "0x4", @@ -2860,8 +3496,10 @@ }, { "BriefDescription": "RspS Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a transaction with the opcode ty= pe RspS Snoop Response was received which indicates when a remote cache has= data but is not forwarding it. It is a way to let the requesting socket k= now that it cannot allocate the data in E state. No data is sent with S Rs= pS.", "UMask": "0x2", @@ -2869,8 +3507,10 @@ }, { "BriefDescription": "RspSFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a a transaction with the opcode = type RspSFwd Snoop Response was received which indicates a remote caching a= gent forwarded the data but held on to its current copy. This is common fo= r data and code reads that hit in a remote socket in E (Exclusive) or F (Fo= rward) state.", "UMask": "0x8", @@ -2878,8 +3518,10 @@ }, { "BriefDescription": "Snoop Responses Received : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_CHA_SNOOP_RESP.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : Rsp*WB : Counts t= he total number of RspI snoop responses received. Whenever a snoops are is= sued, one or more snoop responses will be returned depending on the topolog= y of the system. In systems larger than 2s, when multiple snoops are retu= rned this will count all the snoops that are received. For example, if 3 s= noops were issued and returned RspI, RspS, and RspSFwd; then each of these = sub-events would increment by 1. : Filters for a snoop response of RspIWB o= r RspSWB. This is returned when a non-RFO request hits in M state. Data a= nd Code Reads can return either RspIWB or RspSWB depending on how the syste= m has been configured. InvItoE transactions will also return RspIWB becaus= e they must acquire ownership.", "UMask": "0x10", @@ -2887,8 +3529,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", "UMask": "0x40", @@ -2896,8 +3540,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", "UMask": "0x80", @@ -2905,8 +3551,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", "UMask": "0x20", @@ -2914,8 +3562,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", "UMask": "0x1", @@ -2923,8 +3573,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -2932,8 +3584,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", "UMask": "0x2", @@ -2941,8 +3595,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its current copy. This is com= mon for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", @@ -2950,8 +3606,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", "UMask": "0x10", @@ -2959,56 +3617,70 @@ }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "Counter": "0,1,2,3", "EventCode": "0x6b", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0xc001ffff", @@ -3016,16 +3688,20 @@ }, { "BriefDescription": "TOR Inserts : DDR Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DDR Access : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. : TOR allocation occurred as a result of SF/= LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -3033,14 +3709,17 @@ }, { "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; All from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -3050,6 +3729,7 @@ }, { "BriefDescription": "TOR Inserts;CLFlush from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -3059,8 +3739,10 @@ }, { "BriefDescription": "TOR Inserts;CLFlushOpt from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; C= LFlushOpt events that are initiated from the Core", "UMask": "0xc8d7ff01", @@ -3068,6 +3750,7 @@ }, { "BriefDescription": "TOR Inserts; CRd from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -3077,8 +3760,10 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", "UMask": "0xc88fff01", @@ -3086,6 +3771,7 @@ }, { "BriefDescription": "TOR Inserts; DRd from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD", "PerPkg": "1", @@ -3095,8 +3781,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -3104,8 +3792,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t misses in the snoop filter", "UMask": "0xc827ff01", @@ -3113,8 +3803,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that misses in the snoop filter", "UMask": "0xc8a7ff01", @@ -3122,6 +3814,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_PREF", "PerPkg": "1", @@ -3131,6 +3824,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -3140,6 +3834,7 @@ }, { "BriefDescription": "TOR Inserts; CRd hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -3149,6 +3844,7 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -3158,16 +3854,20 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018101", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008101", @@ -3175,6 +3875,7 @@ }, { "BriefDescription": "TOR Inserts; DRd hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", "PerPkg": "1", @@ -3184,8 +3885,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837fd01", @@ -3193,8 +3896,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t hits in the snoop filter", "UMask": "0xc827fd01", @@ -3202,8 +3907,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that hits in the snoop filter", "UMask": "0xc8a7fd01", @@ -3211,6 +3918,7 @@ }, { "BriefDescription": "TOR Inserts; DRd Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_PREF", "PerPkg": "1", @@ -3220,8 +3928,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that H= it LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -3229,8 +3939,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA that hits in the snoop filter", "UMask": "0xcccffd01", @@ -3238,8 +3950,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefData hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch data = read from local IA that hits in the snoop filter", "UMask": "0xccd7fd01", @@ -3247,6 +3961,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -3256,6 +3971,7 @@ }, { "BriefDescription": "TOR Inserts; RFO hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -3265,6 +3981,7 @@ }, { "BriefDescription": "TOR Inserts; RFO Pref hits from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -3274,8 +3991,10 @@ }, { "BriefDescription": "TOR Inserts;ItoM from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; I= toM events that are initiated from the Core", "UMask": "0xcc47ff01", @@ -3283,8 +4002,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears issued by iA Cor= es", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -3292,8 +4013,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA.", "UMask": "0xcccfff01", @@ -3301,6 +4024,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefData from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", "PerPkg": "1", @@ -3310,6 +4034,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", "PerPkg": "1", @@ -3319,6 +4044,7 @@ }, { "BriefDescription": "TOR Inserts; misses from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -3328,6 +4054,7 @@ }, { "BriefDescription": "TOR Inserts for CRd misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -3337,16 +4064,20 @@ }, { "BriefDescription": "CRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c80b8201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80efe01", @@ -3354,6 +4085,7 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -3363,8 +4095,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88efe01", @@ -3372,8 +4106,10 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88f7e01", @@ -3381,8 +4117,10 @@ }, { "BriefDescription": "TOR Inserts : CRd issued by iA Cores that Mis= sed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80f7e01", @@ -3390,16 +4128,20 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008201", @@ -3407,6 +4149,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", "PerPkg": "1", @@ -3416,16 +4159,20 @@ }, { "BriefDescription": "DRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8138201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc837fe01", @@ -3433,16 +4180,20 @@ }, { "BriefDescription": "DRds issued from an IA core which miss the L3= and target memory in a CXL type 2 memory expander card.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8178201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8168201", @@ -3450,6 +4201,7 @@ }, { "BriefDescription": "TOR Inserts for DRds issued by IA Cores targe= ting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -3459,6 +4211,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA targ= eting local memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -3468,6 +4221,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", @@ -3477,6 +4231,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL_PMM", "PerPkg": "1", @@ -3486,8 +4241,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt from local IA tha= t misses in the snoop filter", "UMask": "0xc827fe01", @@ -3495,8 +4252,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_L= OCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8268201", @@ -3504,8 +4263,10 @@ }, { "BriefDescription": "TOR Inserts; DRd Opt Pref misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Data read opt prefetch from loc= al IA that misses in the snoop filter", "UMask": "0xc8a7fe01", @@ -3513,8 +4274,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_= ACC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_CXL_ACC_LOC= AL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8a68201", @@ -3522,6 +4285,7 @@ }, { "BriefDescription": "TOR Inserts for DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -3531,6 +4295,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF", "PerPkg": "1", @@ -3540,16 +4305,20 @@ }, { "BriefDescription": "L2 data prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8978201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8968201", @@ -3557,8 +4326,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8978601", @@ -3566,6 +4337,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= targeting local memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL", "PerPkg": "1", @@ -3575,8 +4347,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8968601", @@ -3584,8 +4358,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8968a01", @@ -3593,8 +4369,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8978a01", @@ -3602,6 +4380,7 @@ }, { "BriefDescription": "TOR Inserts for DRd Pref misses from local IA= targeting remote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE", "PerPkg": "1", @@ -3611,8 +4390,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8970601", @@ -3620,8 +4401,10 @@ }, { "BriefDescription": "TOR Inserts : DRd_Prefs issued by iA Cores ta= rgeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8970a01", @@ -3629,6 +4412,7 @@ }, { "BriefDescription": "TOR Inserts for DRd misses from local IA targ= eting remote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -3638,6 +4422,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", @@ -3647,6 +4432,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores targeti= ng PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE_PMM", "PerPkg": "1", @@ -3656,8 +4442,10 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by iA Cores that M= issed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -3665,8 +4453,10 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefCode misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Last level cache prefetch code = read from local IA that misses in the snoop filter", "UMask": "0xcccffe01", @@ -3674,14 +4464,17 @@ }, { "BriefDescription": "LLC Prefetch Code transactions issued from an= IA core which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10cccf8201", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; LLCPrefData misses from local IA= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -3691,16 +4484,20 @@ }, { "BriefDescription": "LLC data prefetches issued from an IA core wh= ich miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccd78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_A= CC_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC_LOCA= L", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccd68201", @@ -3708,6 +4505,7 @@ }, { "BriefDescription": "TOR Inserts; LLCPrefRFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -3717,16 +4515,20 @@ }, { "BriefDescription": "L2 RFO prefetches issued from an IA core whic= h miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8878201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_AC= C_LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8868201", @@ -3734,8 +4536,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8668601", @@ -3743,8 +4547,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8668a01", @@ -3752,8 +4558,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86e8601", @@ -3761,8 +4569,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed locally", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86e8a01", @@ -3770,8 +4580,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8670601", @@ -3779,8 +4591,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8670a01", @@ -3788,8 +4602,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f0601", @@ -3797,8 +4613,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC - HOMed remotely", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f0a01", @@ -3806,6 +4624,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -3815,24 +4634,30 @@ }, { "BriefDescription": "RFO and L2 RFO prefetches issued from an IA c= ore which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFOMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8038201", "Unit": "CHA" }, { "BriefDescription": "RFOs issued from an IA core which miss the L3= and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8078201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL= ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8068201", @@ -3840,6 +4665,7 @@ }, { "BriefDescription": "TOR Inserts RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -3849,6 +4675,7 @@ }, { "BriefDescription": "TOR Inserts; RFO pref misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -3858,16 +4685,20 @@ }, { "BriefDescription": "LLC RFO prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccc78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_= LOCAL", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccc68201", @@ -3875,6 +4706,7 @@ }, { "BriefDescription": "TOR Inserts; RFO prefetch misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -3884,6 +4716,7 @@ }, { "BriefDescription": "TOR Inserts; RFO prefetch misses from local I= A", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -3893,6 +4726,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -3902,8 +4736,10 @@ }, { "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -3911,8 +4747,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -3920,8 +4758,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -3929,8 +4769,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678601", @@ -3938,8 +4780,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLFs issued by iA Cores targe= ting PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8678a01", @@ -3947,8 +4791,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing DDR that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8601", @@ -3956,8 +4802,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores target= ing PMM that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86f8a01", @@ -3965,8 +4813,10 @@ }, { "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -3974,6 +4824,7 @@ }, { "BriefDescription": "TOR Inserts; RFO from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -3983,6 +4834,7 @@ }, { "BriefDescription": "TOR Inserts; RFO pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -3992,6 +4844,7 @@ }, { "BriefDescription": "TOR Inserts;SpecItoM from Local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", "PerPkg": "1", @@ -4001,8 +4854,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc3fff01", @@ -4010,8 +4865,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc37ff01", @@ -4019,8 +4876,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc2fff01", @@ -4028,8 +4887,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -4037,8 +4898,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc67ff01", @@ -4046,8 +4909,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -4055,8 +4920,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -4064,6 +4931,7 @@ }, { "BriefDescription": "TOR Inserts; All from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", @@ -4073,6 +4941,7 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", "PerPkg": "1", @@ -4082,6 +4951,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -4091,6 +4961,7 @@ }, { "BriefDescription": "TOR Inserts; ItoM hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -4100,6 +4971,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -4109,6 +4981,7 @@ }, { "BriefDescription": "TOR Inserts; RdCur and FsRdCur hits from loca= l IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -4118,6 +4991,7 @@ }, { "BriefDescription": "TOR Inserts; RFO hits from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", "PerPkg": "1", @@ -4127,6 +5001,7 @@ }, { "BriefDescription": "TOR Inserts for ItoM from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -4136,6 +5011,7 @@ }, { "BriefDescription": "TOR Inserts for ItoMCacheNears from IO device= s.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -4145,6 +5021,7 @@ }, { "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", "PerPkg": "1", @@ -4154,6 +5031,7 @@ }, { "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", "PerPkg": "1", @@ -4163,6 +5041,7 @@ }, { "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", "PerPkg": "1", @@ -4172,6 +5051,7 @@ }, { "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", "PerPkg": "1", @@ -4181,6 +5061,7 @@ }, { "BriefDescription": "TOR Inserts; Misses from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -4190,6 +5071,7 @@ }, { "BriefDescription": "TOR Inserts : ItoM, indicating a full cacheli= ne write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -4199,6 +5081,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -4208,6 +5091,7 @@ }, { "BriefDescription": "TOR Inserts; RdCur and FsRdCur requests from = local IO that miss LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -4217,6 +5101,7 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", "PerPkg": "1", @@ -4226,6 +5111,7 @@ }, { "BriefDescription": "TOR Inserts for RdCur from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -4235,6 +5121,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", "PerPkg": "1", @@ -4244,6 +5131,7 @@ }, { "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", "PerPkg": "1", @@ -4253,6 +5141,7 @@ }, { "BriefDescription": "TOR Inserts; RFO from local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", "PerPkg": "1", @@ -4262,6 +5151,7 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", "PerPkg": "1", @@ -4271,8 +5161,10 @@ }, { "BriefDescription": "TOR Inserts : IPQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IPQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x8", @@ -4280,8 +5172,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. : From an iA Core", "UMask": "0x1", @@ -4289,8 +5183,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "UMask": "0x10", @@ -4298,24 +5194,30 @@ }, { "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. : All locally initiated requests", "UMask": "0xc000ff05", @@ -4323,8 +5225,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. : All locally initiated requests from iA Co= res", "UMask": "0xc000ff01", @@ -4332,8 +5236,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. : All locally generated IO traffic", "UMask": "0xc000ff04", @@ -4341,80 +5247,100 @@ }, { "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMIO Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMIO Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PMM Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PM Access : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. : From a PCIe Device", "UMask": "0x4", @@ -4422,8 +5348,10 @@ }, { "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent.", "UMask": "0x20", @@ -4431,16 +5359,20 @@ }, { "BriefDescription": "TOR Inserts : Just Remote Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Remote Targets : Counts t= he number of entries successfully inserted into the TOR that match qualific= ations specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Remote : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. : All remote requests (e.g. snoops, writeback= s) that came from remote sockets", "UMask": "0xc001ffc8", @@ -4448,8 +5380,10 @@ }, { "BriefDescription": "TOR Inserts : All Snoops from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All Snoops from Remote : Count= s the number of entries successfully inserted into the TOR that match quali= fications specified by the subevent. : All snoops to this LLC that came fro= m remote sockets", "UMask": "0xc001ff08", @@ -4457,8 +5391,10 @@ }, { "BriefDescription": "TOR Inserts : RRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RRQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x40", @@ -4466,8 +5402,10 @@ }, { "BriefDescription": "TOR Inserts; All Snoops from Remote", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.SNPS_FROM_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent. Al= l snoops to this LLC that came from remote sockets.", "UMask": "0xc001ff08", @@ -4475,8 +5413,10 @@ }, { "BriefDescription": "TOR Inserts : WBQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WBQ : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent.", "UMask": "0x80", @@ -4484,8 +5424,10 @@ }, { "BriefDescription": "TOR Occupancy : All", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0xc001ffff", @@ -4493,16 +5435,20 @@ }, { "BriefDescription": "TOR Occupancy : DDR Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DDR Access : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. T : TOR allocation occurre= d as a result of SF/LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -4510,14 +5456,17 @@ }, { "BriefDescription": "TOR Occupancy : Just Hits", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; All from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4527,6 +5476,7 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", @@ -4536,8 +5486,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4545,6 +5497,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -4554,8 +5507,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4563,6 +5518,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD", "PerPkg": "1", @@ -4572,8 +5528,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -4583,8 +5541,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat misses in the snoop filter", "UMask": "0xc827ff01", @@ -4592,8 +5552,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that misses in the snoop filter", "UMask": "0xc8a7ff01", @@ -4601,6 +5563,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_PREF", "PerPkg": "1", @@ -4610,6 +5573,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4619,6 +5583,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "PerPkg": "1", @@ -4628,6 +5593,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -4637,16 +5603,20 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018101", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008101", @@ -4654,6 +5624,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "PerPkg": "1", @@ -4663,8 +5634,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -4674,8 +5647,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat hits in the snoop filter", "UMask": "0xc827fd01", @@ -4683,8 +5658,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref hits from local I= A", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that hits in the snoop filter", "UMask": "0xc8a7fd01", @@ -4692,6 +5669,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_PREF", "PerPkg": "1", @@ -4701,8 +5679,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Hit LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Hit LLC : For each cycle, this event accumulates the number of valid entr= ies in the TOR that match qualifications specified by the subevent. Doe= s not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fd01", @@ -4710,8 +5690,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode hits from local IA= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch cod= e read from local IA that hits in the snoop filter", "UMask": "0xcccffd01", @@ -4719,8 +5701,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefData hits from local IA= ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch dat= a read from local IA that hits in the snoop filter", "UMask": "0xccd7fd01", @@ -4728,6 +5712,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -4737,6 +5722,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "PerPkg": "1", @@ -4746,6 +5732,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO Pref hits from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -4755,8 +5742,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc47ff01", @@ -4764,8 +5753,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears issued by iA C= ores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears issued by iA = Cores : For each cycle, this event accumulates the number of valid entries = in the TOR that match qualifications specified by the subevent. Does no= t include addressless requests such as locks and interrupts.", "UMask": "0xcd47ff01", @@ -4773,8 +5764,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch dat= a read from local IA.", "UMask": "0xcccfff01", @@ -4782,6 +5775,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefData from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", "PerPkg": "1", @@ -4791,6 +5785,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", "PerPkg": "1", @@ -4800,6 +5795,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -4809,6 +5805,7 @@ }, { "BriefDescription": "TOR Occupancy; CRd misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -4818,16 +5815,20 @@ }, { "BriefDescription": "TOR Occupancy for CRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c80b8201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed locally : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc80efe01", @@ -4835,8 +5836,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88ffe01", @@ -4844,8 +5847,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed locally : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc88efe01", @@ -4853,8 +5858,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC - HOMed remotely : For each cycle, this event accumula= tes the number of valid entries in the TOR that match qualifications specif= ied by the subevent. Does not include addressless requests such as lock= s and interrupts.", "UMask": "0xc88f7e01", @@ -4862,8 +5869,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd issued by iA Cores that M= issed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd issued by iA Cores that = Missed the LLC - HOMed remotely : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc80f7e01", @@ -4871,16 +5880,20 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c0018201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c0008201", @@ -4888,6 +5901,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "PerPkg": "1", @@ -4897,16 +5911,20 @@ }, { "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8138201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -4916,16 +5934,20 @@ }, { "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= memory expander card.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8178201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8168201", @@ -4933,6 +5955,7 @@ }, { "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_DDR", "PerPkg": "1", @@ -4942,6 +5965,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA ta= rgeting local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL", "PerPkg": "1", @@ -4951,6 +5975,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_DDR", "PerPkg": "1", @@ -4960,6 +5985,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL_PMM", "PerPkg": "1", @@ -4969,8 +5995,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt from local IA t= hat misses in the snoop filter", "UMask": "0xc827fe01", @@ -4978,8 +6006,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC= _LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8268201", @@ -4987,8 +6017,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Opt Pref misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read opt prefetch from l= ocal IA that misses in the snoop filter", "UMask": "0xc8a7fe01", @@ -4996,8 +6028,10 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CX= L_ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF_CXL_ACC_L= OCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8a68201", @@ -5005,6 +6039,7 @@ }, { "BriefDescription": "TOR Occupancy for DRds issued by iA Cores tar= geting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PMM", "PerPkg": "1", @@ -5014,6 +6049,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF", "PerPkg": "1", @@ -5023,16 +6059,20 @@ }, { "BriefDescription": "TOR Occupancy for L2 data prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8978201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_AC= C_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8968201", @@ -5040,8 +6080,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978601", @@ -5049,8 +6091,10 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc896fe01", @@ -5058,8 +6102,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968601", @@ -5067,8 +6113,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_LOCAL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed locally : For each cycle, th= is event accumulates the number of valid entries in the TOR that match qual= ifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc8968a01", @@ -5076,8 +6124,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC : For each cycle, this event accumul= ates the number of valid entries in the TOR that match qualifications speci= fied by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "UMask": "0xc8978a01", @@ -5085,6 +6135,7 @@ }, { "BriefDescription": "TOR Occupancy; DRd Pref misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE", "PerPkg": "1", @@ -5094,8 +6145,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting DDR Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970601", @@ -5103,8 +6156,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores = targeting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_REMOTE_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Prefs issued by iA Cores= targeting PMM Mem that Missed the LLC - HOMed remotely : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts.", "UMask": "0xc8970a01", @@ -5112,6 +6167,7 @@ }, { "BriefDescription": "TOR Occupancy for DRd misses from local IA ta= rgeting remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE", "PerPkg": "1", @@ -5121,6 +6177,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting DDR Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_DDR", "PerPkg": "1", @@ -5130,6 +6187,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores targe= ting PMM Mem that Missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE_PMM", "PerPkg": "1", @@ -5139,8 +6197,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by iA Cores that= Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by iA Cores tha= t Missed LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc47fe01", @@ -5148,8 +6208,10 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefCode misses from local = IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Last level cache prefetch cod= e read from local IA that misses in the snoop filter", "UMask": "0xcccffe01", @@ -5157,14 +6219,17 @@ }, { "BriefDescription": "TOR Occupancy for LLC Prefetch Code transacti= ons issued from an IA core which miss the L3 and target memory in a CXL typ= e 2 accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10cccf8201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; LLCPrefData misses from local = IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -5174,16 +6239,20 @@ }, { "BriefDescription": "TOR Occupancy for LLC data prefetches issued = from an IA core which miss the L3 and target memory in a CXL type 2 acceler= ator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccd78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL= _ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC_LO= CAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccd68201", @@ -5191,6 +6260,7 @@ }, { "BriefDescription": "TOR Occupancy; LLCPrefRFO misses from local I= A", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -5200,16 +6270,20 @@ }, { "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued fr= om an IA core which miss the L3 and target memory in a CXL type 2 accelerat= or.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8878201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_= ACC_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC_LOC= AL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8868201", @@ -5217,8 +6291,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668601", @@ -5226,8 +6302,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed locally : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc8668a01", @@ -5235,8 +6313,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8601", @@ -5244,8 +6324,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally : For each cycle, this event= accumulates the number of valid entries in the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests suc= h as locks and interrupts.", "UMask": "0xc86e8a01", @@ -5253,8 +6335,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670601", @@ -5262,8 +6346,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed remotely : For each cycle, this eve= nt accumulates the number of valid entries in the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests s= uch as locks and interrupts.", "UMask": "0xc8670a01", @@ -5271,8 +6357,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0601", @@ -5280,8 +6368,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely : For each cycle, this even= t accumulates the number of valid entries in the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "UMask": "0xc86f0a01", @@ -5289,6 +6379,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -5298,24 +6389,30 @@ }, { "BriefDescription": "TOR Occupancy for RFO and L2 RFO prefetches i= ssued from an IA core which miss the L3 and target memory in a CXL type 2 a= ccelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFOMORPH_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8038201", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for RFOs issued from an IA core= which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c8078201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOC= AL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC_LOCAL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10c8068201", @@ -5323,6 +6420,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -5332,6 +6430,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -5341,16 +6440,20 @@ }, { "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10ccc78201", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_AC= C_LOCAL", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC_LOCAL= ", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10ccc68201", @@ -5358,6 +6461,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -5367,6 +6471,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch misses from local= IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -5376,6 +6481,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -5385,8 +6491,10 @@ }, { "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -5394,8 +6502,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -5403,8 +6513,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -5412,8 +6524,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting DDR that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678601", @@ -5421,8 +6535,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLFs issued by iA Cores tar= geting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC : For each cycle, this event accumulates th= e number of valid entries in the TOR that match qualifications specified by= the subevent. Does not include addressless requests such as locks and = interrupts.", "UMask": "0xc8678a01", @@ -5430,8 +6546,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting DDR that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting DDR that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8601", @@ -5439,8 +6557,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores targ= eting PMM that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC : For each cycle, this event accumulates the= number of valid entries in the TOR that match qualifications specified by = the subevent. Does not include addressless requests such as locks and i= nterrupts.", "UMask": "0xc86f8a01", @@ -5448,8 +6568,10 @@ }, { "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -5457,6 +6579,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -5466,6 +6589,7 @@ }, { "BriefDescription": "TOR Occupancy; RFO prefetch from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", "PerPkg": "1", @@ -5475,6 +6599,7 @@ }, { "BriefDescription": "TOR Occupancy : SpecItoMs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", "PerPkg": "1", @@ -5484,8 +6609,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -5493,8 +6620,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -5502,8 +6631,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -5511,6 +6642,7 @@ }, { "BriefDescription": "TOR Occupancy; All from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", @@ -5520,8 +6652,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -5529,6 +6663,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", @@ -5538,6 +6673,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", "PerPkg": "1", @@ -5547,6 +6683,7 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -5556,6 +6693,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur hits from lo= cal IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -5565,8 +6703,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO hits from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -5574,6 +6714,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", "PerPkg": "1", @@ -5583,8 +6724,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -5594,6 +6737,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", @@ -5603,6 +6747,7 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", "PerPkg": "1", @@ -5612,6 +6757,7 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -5621,8 +6767,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC and targets loca= l memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcd42fe04", @@ -5630,8 +6778,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC and targets remo= te memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcd437e04", @@ -5639,8 +6789,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO and = targets local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcc42fe04", @@ -5648,8 +6800,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM misses from local IO and = targets remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xcc437e04", @@ -5657,6 +6811,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -5666,8 +6821,10 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO and targets local memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc8f2fe04", @@ -5675,8 +6832,10 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur misses from = local IO and targets remote memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "UMask": "0xc8f37e04", @@ -5684,8 +6843,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -5693,6 +6854,7 @@ }, { "BriefDescription": "TOR Occupancy; RdCur and FsRdCur from local I= O", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -5702,8 +6864,10 @@ }, { "BriefDescription": "TOR Occupancy; ItoM from local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -5711,8 +6875,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -5720,8 +6886,10 @@ }, { "BriefDescription": "TOR Occupancy : IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IPQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x8", @@ -5729,8 +6897,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. T : From an iA Core", "UMask": "0x1", @@ -5738,8 +6908,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "UMask": "0x10", @@ -5747,24 +6919,30 @@ }, { "BriefDescription": "TOR Occupancy : Just ISOC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Local Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. T : All locally in= itiated requests", "UMask": "0xc000ff05", @@ -5772,8 +6950,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. T : All locally initiated= requests from iA Cores", "UMask": "0xc000ff01", @@ -5781,8 +6961,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. T : All locally generated= IO traffic", "UMask": "0xc000ff04", @@ -5790,80 +6972,100 @@ }, { "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Misses", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMCFG Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMIO Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMIO Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NonCoherent", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NotNearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PMM Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PMM Access : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. T : From a PCIe Device", "UMask": "0x4", @@ -5871,8 +7073,10 @@ }, { "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. T", "UMask": "0x20", @@ -5880,16 +7084,20 @@ }, { "BriefDescription": "TOR Occupancy : Just Remote Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REMOTE_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Remote Targets : For ea= ch cycle, this event accumulates the number of valid entries in the TOR tha= t match qualifications specified by the subevent. T", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Remote : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. T : All remote requests (e.= g. snoops, writebacks) that came from remote sockets", "UMask": "0xc001ffc8", @@ -5897,8 +7105,10 @@ }, { "BriefDescription": "TOR Occupancy : All Snoops from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All Snoops from Remote : For= each cycle, this event accumulates the number of valid entries in the TOR = that match qualifications specified by the subevent. T : All snoops to th= is LLC that came from remote sockets", "UMask": "0xc001ff08", @@ -5906,8 +7116,10 @@ }, { "BriefDescription": "TOR Occupancy : RRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RRQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x40", @@ -5915,8 +7127,10 @@ }, { "BriefDescription": "TOR Occupancy; All Snoops from Remote", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.SNPS_FROM_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. All snoops to this LLC that came from remote sockets.", "UMask": "0xc001ff08", @@ -5924,8 +7138,10 @@ }, { "BriefDescription": "TOR Occupancy : WBQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WBQ : For each cycle, this e= vent accumulates the number of valid entries in the TOR that match qualific= ations specified by the subevent. T", "UMask": "0x80", @@ -5933,8 +7149,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", "UMask": "0x1", @@ -5942,8 +7160,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", "UMask": "0x2", @@ -5951,8 +7171,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", "UMask": "0x1", @@ -5960,8 +7182,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", "UMask": "0x2", @@ -5969,8 +7193,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", "UMask": "0x4", @@ -5978,8 +7204,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", "UMask": "0x8", @@ -5987,8 +7215,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", "UMask": "0x10", @@ -5996,8 +7226,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x5a", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", "UMask": "0x20", @@ -6005,8 +7237,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x8", @@ -6014,8 +7248,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x4", @@ -6023,8 +7259,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x80", @@ -6032,8 +7270,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x40", @@ -6041,8 +7281,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", "UMask": "0x1", @@ -6050,8 +7292,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", "UMask": "0x10", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json = b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json index f3e84fd88de3..ff81f3a6426a 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-cxl.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of lfclk ticks", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x01", "EventName": "UNC_CXLCM_CLOCKTICKS", "PerPkg": "1", @@ -9,390 +10,487 @@ }, { "BriefDescription": "Number of Allocation to Mem Rxx AGF 0", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req AGF0", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_REQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.CACHE_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req AGF 1", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data AGF", + "Counter": "4,5,6,7", "EventCode": "0x43", "EventName": "UNC_CXLCM_RxC_AGF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with AK set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.AK_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with BE set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.BE_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of control flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.CTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Headerless flits received= ", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.NO_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of protocol flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.PROT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with SZ set", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.SZ_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of flits received", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.VALID", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of valid messages in the fli= t", + "Counter": "4,5,6,7", "EventCode": "0x4b", "EventName": "UNC_CXLCM_RxC_FLITS.VALID_MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of CRC errors detected", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Init flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.INIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of LLCRD flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Retry flits sent", + "Counter": "4,5,6,7", "EventCode": "0x40", "EventName": "UNC_CXLCM_RxC_MISC.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles the Packing Buffer is Full", + "Counter": "4,5,6,7", "EventCode": "0x52", "EventName": "UNC_CXLCM_RxC_PACK_BUF_FULL.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data Packing bu= ffer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp Packing buf= fer", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Rxx Packing buffe= r", + "Counter": "4,5,6,7", "EventCode": "0x41", "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Data = Packing buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Req P= acking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Cache Rsp P= acking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.CACHE_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Mem Data Pa= cking buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of cycles of Not Empty for Mem Rxx Pac= king buffer", + "Counter": "4,5,6,7", "EventCode": "0x42", "EventName": "UNC_CXLCM_RxC_PACK_BUF_NE.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with AK set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.AK_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with BE set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.BE_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of control flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.CTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Headerless flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.NO_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of protocol flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.PROT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of Flits with SZ set", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.SZ_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Count the number of flits packed", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_CXLCM_TxC_FLITS.VALID", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Data Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp1 Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_REQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Rsp0 Packing bu= ffer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Cache Req Packing buf= fer", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.CACHE_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLCM" }, { "BriefDescription": "Number of Allocation to Mem Rxx Packing buffe= r", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLCM_TxC_PACK_BUF_INSERTS.MEM_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLCM" }, { "BriefDescription": "Counts the number of uclk ticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CXLDP_CLOCKTICKS", "PerPkg": "1", @@ -401,48 +499,60 @@ }, { "BriefDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to M2S Req AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Data AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Req AGF", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Rsp AGF 0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CXLDP" }, { "BriefDescription": "Number of Allocation to U2C Rsp AGF 1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.U2C_RSP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CXLDP" diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconn= ect.json b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnec= t.json index 22bb490e9666..8b1ae9540066 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", "EventCode": "0x0f", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total IRP occupancy of inbound read and writ= e requests to coherent memory. This is effectively the sum of read occupan= cy and write occupancy.", "UMask": "0x4", @@ -10,6 +12,7 @@ }, { "BriefDescription": "IRP Clockticks", + "Counter": "0,1", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -18,6 +21,7 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", @@ -25,6 +29,7 @@ }, { "BriefDescription": "FAF - request insert from TC.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -32,6 +37,7 @@ }, { "BriefDescription": "FAF occupancy", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -39,6 +45,7 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", @@ -46,14 +53,17 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.EVICTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", @@ -62,78 +72,97 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -143,8 +172,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", @@ -152,8 +183,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", "UMask": "0x40", @@ -161,8 +194,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", "UMask": "0x4", @@ -170,8 +205,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", @@ -179,8 +216,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", @@ -188,8 +227,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", @@ -197,8 +238,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -206,8 +249,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -215,8 +260,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -224,6 +271,7 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", @@ -233,8 +281,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -242,62 +292,77 @@ }, { "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -307,132 +372,167 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0x0b", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x05", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x08", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x06", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x09", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x07", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x04", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x0a", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", "EventCode": "0x1c", "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0AD1 both. Stalls on both AD0 and AD1 will count = as 2", "Unit": "IRP" }, { "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1a", "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1b", "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1d", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0d", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0e", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0x0c", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Request Queue Occupancy : Accumulat= es the number of outstanding outbound requests from the IRP to the switch (= towards the devices). This can be used in conjunction with the allocations= event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "M2M Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", @@ -441,6 +541,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", @@ -448,16 +549,20 @@ }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled : Non Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when direct to core mode, which bypas= ses the CHA, was disabled : Non Cisgress : Counts the number of time non ci= sgress D2C was not honoured by egress due to directory state constraints", "UMask": "0x2", @@ -465,39 +570,49 @@ }, { "BriefDescription": "Counts the time when FM didn't do d2c for fil= l reads (cross tile case)", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : 2LM Hit?", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE.PMM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_DIRECT2UPITXN_OVERRIDE.PMM_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a direct to UPI transaction = was overridden. : Counts the number of times D2K wasn't honored even though= the incoming request had d2k set", "UMask": "0x1", @@ -505,24 +620,30 @@ }, { "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgres= s D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Cisgre= ss D2U Ignored : Counts cisgress d2K that was not honored due to directory = constraints", "UMask": "0x4", @@ -530,8 +651,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Egress= Ignored D2U : Counts the number of time D2K was not honoured by egress due= to directory state constraints", "UMask": "0x1", @@ -539,8 +662,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cis= gress D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles when Direct2UPI was Disabled : Non Ci= sgress D2U Ignored : Counts non cisgress d2K that was not honored due to di= rectory constraints", "UMask": "0x2", @@ -548,8 +673,10 @@ }, { "BriefDescription": "Messages sent direct to the Intel UPI", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times egress did D2K (D= irect to KTI)", "UMask": "0x7", @@ -557,86 +684,107 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -646,6 +794,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -655,6 +804,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -664,6 +814,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -673,86 +824,107 @@ }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x320", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -761,8 +933,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from A to I to non persistent memory (DRAM or= HBM)", "UMask": "0x120", @@ -770,8 +944,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from A to I to non persistent memory (DRAM or HBM)", "UMask": "0x220", @@ -779,8 +955,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from A to S to non persistent memory (DRAM or= HBM)", "UMask": "0x140", @@ -788,8 +966,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from A to S to non persistent memory (DRAM or HBM)", "UMask": "0x240", @@ -797,8 +977,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts any 1lm or 2lm hit data return that w= ould result in directory update to non persistent memory (DRAM or HBM)", "UMask": "0x101", @@ -806,24 +988,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from I to A to non persistent memory (DRAM or= HBM)", "UMask": "0x104", @@ -831,8 +1019,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from I to A to non persistent memory (DRAM or HBM)", "UMask": "0x204", @@ -840,8 +1030,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from I to S to non persistent memory (DRAM or= HBM)", "UMask": "0x102", @@ -849,8 +1041,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would re= sult in directory update from I to S to non persistent memory (DRAM or HBM)= ", "UMask": "0x202", @@ -858,8 +1052,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts any 2lm miss data return that would r= esult in directory update to non persistent memory (DRAM or HBM)", "UMask": "0x201", @@ -867,24 +1063,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from S to A to non persistent memory (DRAM or= HBM)", "UMask": "0x110", @@ -892,8 +1094,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from S to A to non persistent memory (DRAM or HBM)", "UMask": "0x210", @@ -901,8 +1105,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 1lm or 2lm hit data returns that wou= ld result in directory update from S to I to non persistent memory (DRAM or= HBM)", "UMask": "0x108", @@ -910,8 +1116,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts 2lm miss data returns that would res= ult in directory update from S to I to non persistent memory (DRAM or HBM)", "UMask": "0x208", @@ -919,8 +1127,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x80000004", @@ -928,8 +1138,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x80000001", @@ -937,40 +1149,50 @@ }, { "BriefDescription": "Count when Starve Glocab counter is at 7", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_IGR_STARVE_WINNER.MASK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0.TO_NMCache", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -979,24 +1201,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1005,24 +1233,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH0_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1031,24 +1265,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x208", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1.TO_NMCache", + "Experimental": "1", "PerPkg": "1", "UMask": "0x210", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1057,24 +1297,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1083,24 +1329,30 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x210", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x208", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.CH1_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1109,62 +1361,77 @@ }, { "BriefDescription": "UNC_M2M_IMC_READS.FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x301", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_NM1LM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_NM1LM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_NMCACHE", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_NMCACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_READS.TO_PMM", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_IMC_READS.TO_PMM", "PerPkg": "1", @@ -1173,23 +1440,29 @@ }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1810", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1198,15 +1471,19 @@ }, { "BriefDescription": "From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1215,30 +1492,38 @@ }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1247,32 +1532,40 @@ }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x840", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x820", "Unit": "M2M" }, { "BriefDescription": "PMM - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH0_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1282,15 +1575,19 @@ }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1299,15 +1596,19 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1316,30 +1617,38 @@ }, { "BriefDescription": "ISOCH Full Line - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1004", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1348,32 +1657,40 @@ }, { "BriefDescription": "ISOCH Partial - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1008", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1040", "Unit": "M2M" }, { "BriefDescription": "DDR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1020", "Unit": "M2M" }, { "BriefDescription": "PMM - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.CH1_TO_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1383,75 +1700,94 @@ }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1801", "Unit": "M2M" }, { "BriefDescription": "ISOCH Full Line - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1804", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1802", "Unit": "M2M" }, { "BriefDescription": "ISOCH Partial - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1808", "Unit": "M2M" }, { "BriefDescription": "DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1840", "Unit": "M2M" }, { "BriefDescription": "DDR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1820", "Unit": "M2M" }, { "BriefDescription": "PMM - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_IMC_WRITES.TO_PMM", "PerPkg": "1", @@ -1460,143 +1796,179 @@ }, { "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2M" }, { "BriefDescription": ": UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": ": XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", "UMask": "0x5", @@ -1604,108 +1976,135 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCE= PT", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.PMM_MEMMODE_ACCEPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2M_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Clean NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_CLEAN", "PerPkg": "1", @@ -1715,6 +2114,7 @@ }, { "BriefDescription": "Dirty NearMem Read Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_RD_HIT_DIRTY", "PerPkg": "1", @@ -1724,8 +2124,10 @@ }, { "BriefDescription": "Tag Hit : Clean NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_CLEAN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit indicates when a request sent to the= iMC hit in Near Memory. : Counts clean underfill hits due to a partial wri= te", "UMask": "0x4", @@ -1733,8 +2135,10 @@ }, { "BriefDescription": "Tag Hit : Dirty NearMem Underfill Hit", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TAG_HIT.NM_UFILL_HIT_DIRTY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tag Hit indicates when a request sent to the= iMC hit in Near Memory. : Counts dirty underfill read hits due to a partia= l write", "UMask": "0x8", @@ -1742,230 +2146,288 @@ }, { "BriefDescription": "UNC_M2M_TAG_MISS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2M_TAG_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CBox AD Credits Empty : Requests", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Requests : No credit= s available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x4", @@ -1973,8 +2435,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Snoops", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Snoops : No credits = available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x8", @@ -1982,8 +2446,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : VNA Messages", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : VNA Messages : No cr= edits available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x1", @@ -1991,8 +2457,10 @@ }, { "BriefDescription": "CBox AD Credits Empty : Writebacks", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CBox AD Credits Empty : Writebacks : No cred= its available to send to Cbox on the AD Ring (covers higher CBoxes)", "UMask": "0x2", @@ -2000,6 +2468,7 @@ }, { "BriefDescription": "M3UPI Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M3UPI_CLOCKTICKS", "PerPkg": "1", @@ -2008,31 +2477,39 @@ }, { "BriefDescription": "M3UPI CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "D2C Sent", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_M3UPI_D2C_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2C Sent : Count cases BL sends direct to co= re", "Unit": "M3UPI" }, { "BriefDescription": "D2U Sent", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_M3UPI_D2U_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2U Sent : Cases where SMI3 sends D2U comman= d", "Unit": "M3UPI" }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -2040,8 +2517,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -2049,8 +2528,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO0 and IIO1 share the= same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO0 and IIO1 share th= e same ring destination. (1 VN0 credit only) : No vn0 and vna credits avail= able to send to M2", "UMask": "0x1", @@ -2058,8 +2539,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO2", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO2 : No vn0 and vna = credits available to send to M2", "UMask": "0x2", @@ -2067,8 +2550,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO3", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO3 : No vn0 and vna = credits available to send to M2", "UMask": "0x4", @@ -2076,8 +2561,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO4", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO4 : No vn0 and vna = credits available to send to M2", "UMask": "0x8", @@ -2085,8 +2572,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x10", @@ -2094,8 +2583,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : All IIO targets for NCS= are in single mask. ORs them together", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : All IIO targets for NC= S are in single mask. ORs them together : No vn0 and vna credits available = to send to M2", "UMask": "0x40", @@ -2103,8 +2594,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : Selected M2p BL NCS cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : Selected M2p BL NCS cr= edits : No vn0 and vna credits available to send to M2", "UMask": "0x80", @@ -2112,8 +2605,10 @@ }, { "BriefDescription": "M2 BL Credits Empty : IIO5", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.UBOX_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2 BL Credits Empty : IIO5 : No vn0 and vna = credits available to send to M2", "UMask": "0x20", @@ -2121,8 +2616,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x1", @@ -2130,8 +2627,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 1 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x2", @@ -2139,8 +2638,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AD - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AD - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x4", @@ -2148,8 +2649,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x10", @@ -2157,8 +2660,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : AK - Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : AK - Slot 2 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x20", @@ -2166,8 +2671,10 @@ }, { "BriefDescription": "Multi Slot Flit Received : BL - Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3e", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi Slot Flit Received : BL - Slot 0 : Mul= ti slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks = for AK allocations)", "UMask": "0x8", @@ -2175,8 +2682,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : REQ on AD : VN0 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -2184,8 +2693,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on AD : VN0 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -2193,8 +2704,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : SNP on AD : VN0 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -2202,8 +2715,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCB on BL : VN0 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -2211,8 +2726,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : NCS on BL : VN0 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -2220,8 +2737,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : RSP on BL : VN0 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -2229,8 +2748,10 @@ }, { "BriefDescription": "Lost Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x4b", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN0 : WB on BL : VN0 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -2238,8 +2759,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : REQ on AD : VN1 message r= equested but lost arbitration : Home (REQ) messages on AD. REQ is generall= y used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -2247,8 +2770,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on AD : VN1 message r= equested but lost arbitration : Response (RSP) messages on AD. RSP packets= are used to transmit a variety of protocol flits including grants and comp= letions (CMP).", "UMask": "0x4", @@ -2256,8 +2781,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : SNP on AD : VN1 message r= equested but lost arbitration : Snoops (SNP) messages on AD. SNP is used f= or outgoing snoops.", "UMask": "0x2", @@ -2265,8 +2792,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCB on BL : VN1 message r= equested but lost arbitration : Non-Coherent Broadcast (NCB) messages on BL= . NCB is generally used to transmit data without coherency. For example, = non-coherent read data returns.", "UMask": "0x20", @@ -2274,8 +2803,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : NCS on BL : VN1 message r= equested but lost arbitration : Non-Coherent Standard (NCS) messages on BL.= ", "UMask": "0x40", @@ -2283,8 +2814,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : RSP on BL : VN1 message r= equested but lost arbitration : Response (RSP) messages on BL. RSP packets = are used to transmit a variety of protocol flits including grants and compl= etions (CMP).", "UMask": "0x8", @@ -2292,8 +2825,10 @@ }, { "BriefDescription": "Lost Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lost Arb for VN1 : WB on BL : VN1 message re= quested but lost arbitration : Data Response (WB) messages on BL. WB is ge= nerally used to transmit data with coherency. For example, remote reads an= d writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -2301,8 +2836,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN0 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x10", @@ -2310,8 +2847,10 @@ }, { "BriefDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : AD, BL Parallel Win VN1 = : AD and BL messages won arbitration concurrently / in parallel", "UMask": "0x20", @@ -2319,8 +2858,10 @@ }, { "BriefDescription": "Arb Miscellaneous : Max Parallel Win", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ALL_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : Max Parallel Win : VN0 a= nd VN1 arbitration sub-pipelines both produced AD and BL winners (maximum p= ossible parallel winners)", "UMask": "0x80", @@ -2328,8 +2869,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN0 : Arbitration stage made no progress on pending ad vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x1", @@ -2337,8 +2880,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending AD= VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending A= D VN1 : Arbitration stage made no progress on pending ad vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x2", @@ -2346,8 +2891,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN0", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN0 : Arbitration stage made no progress on pending bl vn0 messages becau= se slotting stage cannot accept new message", "UMask": "0x4", @@ -2355,8 +2902,10 @@ }, { "BriefDescription": "Arb Miscellaneous : No Progress on Pending BL= VN1", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : No Progress on Pending B= L VN1 : Arbitration stage made no progress on pending bl vn1 messages becau= se slotting stage cannot accept new message", "UMask": "0x8", @@ -2364,8 +2913,10 @@ }, { "BriefDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_M3UPI_RxC_ARB_MISC.VN01_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arb Miscellaneous : VN0, VN1 Parallel Win : = VN0 and VN1 arbitration sub-pipelines had parallel winners (at least one AD= or BL on each side)", "UMask": "0x40", @@ -2373,8 +2924,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : REQ on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -2382,8 +2935,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2391,8 +2946,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : SNP on AD : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2400,8 +2957,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCB on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -2409,8 +2968,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : NCS on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2418,8 +2979,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : RSP on BL : VN0 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2427,8 +2990,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN0 : WB on BL : VN0 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -2436,8 +3001,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : REQ on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Home (REQ) messages on AD. REQ is generally used to send requests,= request responses, and snoop responses.", "UMask": "0x1", @@ -2445,8 +3012,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on AD. RSP packets are used to transmit a = variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2454,8 +3023,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : SNP on AD : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2463,8 +3034,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCB on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used= to transmit data without coherency. For example, non-coherent read data r= eturns.", "UMask": "0x20", @@ -2472,8 +3045,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : NCS on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2481,8 +3056,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : RSP on BL : VN1 = message is blocked from requesting arbitration due to lack of remote UPI cr= edits : Response (RSP) messages on BL. RSP packets are used to transmit a v= ariety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2490,8 +3067,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRD_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No Credits to Arb for VN1 : WB on BL : VN1 m= essage is blocked from requesting arbitration due to lack of remote UPI cre= dits : Data Response (WB) messages on BL. WB is generally used to transmit= data with coherency. For example, remote reads and writes, or cache to ca= che transfers will transmit their data using WB.", "UMask": "0x10", @@ -2499,8 +3078,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : REQ on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : REQ on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -2508,8 +3089,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2517,8 +3100,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : SNP on AD", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : SNP on AD : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2526,8 +3111,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCB on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCB on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -2535,8 +3122,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : NCS on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : NCS on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2544,8 +3133,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : RSP on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : RSP on BL : VN0 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2553,8 +3144,10 @@ }, { "BriefDescription": "Can't Arb for VN0 : WB on BL", + "Counter": "0", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN0 : WB on BL : VN0 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -2562,8 +3155,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : REQ on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : REQ on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Home (REQ) messages on AD. REQ is generally used to send requests, req= uest responses, and snoop responses.", "UMask": "0x1", @@ -2571,8 +3166,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on AD. RSP packets are used to transmit a vari= ety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -2580,8 +3177,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : SNP on AD", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : SNP on AD : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2589,8 +3188,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCB on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCB on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to = transmit data without coherency. For example, non-coherent read data retur= ns.", "UMask": "0x20", @@ -2598,8 +3199,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : NCS on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : NCS on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2607,8 +3210,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : RSP on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : RSP on BL : VN1 message = was not able to request arbitration while some other message won arbitratio= n : Response (RSP) messages on BL. RSP packets are used to transmit a varie= ty of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -2616,8 +3221,10 @@ }, { "BriefDescription": "Can't Arb for VN1 : WB on BL", + "Counter": "0", "EventCode": "0x4a", "EventName": "UNC_M3UPI_RxC_ARB_NOREQ_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Can't Arb for VN1 : WB on BL : VN1 message w= as not able to request arbitration while some other message won arbitration= : Data Response (WB) messages on BL. WB is generally used to transmit dat= a with coherency. For example, remote reads and writes, or cache to cache = transfers will transmit their data using WB.", "UMask": "0x10", @@ -2625,8 +3232,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL A= rb", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on BL = Arb : Number of times message is bypassed around the Ingress Queue : AD is = taking bypass to slot 0 of independent flit while bl message is in arbitrat= ion", "UMask": "0x2", @@ -2634,8 +3243,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idle= ", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD to Slot 0 on Idl= e : Number of times message is bypassed around the Ingress Queue : AD is ta= king bypass to slot 0 of independent flit while pipeline is idle", "UMask": "0x1", @@ -2643,8 +3254,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 1", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 1 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 1 while merging with bl message in same flit", "UMask": "0x4", @@ -2652,8 +3265,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses : AD + BL to Slot 2", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress Queue Bypasses : AD + BL to Slot 2 := Number of times message is bypassed around the Ingress Queue : AD is takin= g bypass to flit slot 2 while merging with bl message in same flit", "UMask": "0x8", @@ -2661,8 +3276,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any In BGF FIFO= ", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any In BGF FIF= O : Indication that at least one packet (flit) is in the bgf (fifo only)", "UMask": "0x1", @@ -2670,8 +3287,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : Any in BGF Path= ", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : Any in BGF Pat= h : Indication that at least one packet (flit) is in the bgf path (i.e. pip= e to fifo)", "UMask": "0x2", @@ -2679,8 +3298,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT1_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 1", "UMask": "0x10", @@ -2688,8 +3309,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.LT2_FOR_D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : d2k credit cou= nt is less than 2", "UMask": "0x20", @@ -2697,8 +3320,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events : No D2K For Arb", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN0_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : No D2K For Arb= : VN0 BL RSP message was blocked from arbitration request due to lack of D= 2K CMP credit", "UMask": "0x4", @@ -2706,8 +3331,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events", + "Counter": "0", "EventCode": "0x5f", "EventName": "UNC_M3UPI_RxC_CRD_MISC.VN1_NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous Credit Events : VN1 BL RSP mes= sage was blocked from arbitration request due to lack of D2K CMP credits", "UMask": "0x8", @@ -2715,8 +3342,10 @@ }, { "BriefDescription": "Credit Occupancy : Credits Consumed", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.CONSUMED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Credits Consumed : number= of remote vna credits consumed per cycle", "UMask": "0x80", @@ -2724,8 +3353,10 @@ }, { "BriefDescription": "Credit Occupancy : D2K Credits", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : D2K Credits : D2K complet= ion fifo credit occupancy (credits in use), accumulated across all cycles", "UMask": "0x10", @@ -2733,8 +3364,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF FIFO", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF FIFO : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in fifo", "UMask": "0x2", @@ -2742,8 +3375,10 @@ }, { "BriefDescription": "Credit Occupancy : Packets in BGF Path", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Packets in BGF Path : Occ= upancy of m3upi ingress -> upi link layer bgf; packets (flits) in path (i.e= . pipe to fifo or fifo)", "UMask": "0x4", @@ -2751,8 +3386,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in completion fifo only", "UMask": "0x40", @@ -2760,8 +3397,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : count of bl messages in p= ump-1-pending state, in marker table and in fifo", "UMask": "0x20", @@ -2769,8 +3408,10 @@ }, { "BriefDescription": "Credit Occupancy : Transmit Credits", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : Transmit Credits : Link l= ayer transmit queue credit occupancy (credits in use), accumulated across a= ll cycles", "UMask": "0x8", @@ -2778,8 +3419,10 @@ }, { "BriefDescription": "Credit Occupancy : VNA In Use", + "Counter": "0", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Credit Occupancy : VNA In Use : Remote UPI V= NA credit occupancy (number of credits in use), accumulated across all cycl= es", "UMask": "0x1", @@ -2787,8 +3430,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : REQ on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : REQ on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Home (REQ) me= ssages on AD. REQ is generally used to send requests, request responses, a= nd snoop responses.", "UMask": "0x1", @@ -2796,8 +3441,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on AD. RSP packets are used to transmit a variety of protocol f= lits including grants and completions (CMP).", "UMask": "0x4", @@ -2805,8 +3452,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : SNP on AD", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : SNP on AD : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Snoops (SNP) = messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -2814,8 +3463,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCB on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCB on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Broadcast (NCB) messages on BL. NCB is generally used to transmit data wit= hout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -2823,8 +3474,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : NCS on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : NCS on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Non-Coherent = Standard (NCS) messages on BL.", "UMask": "0x40", @@ -2832,8 +3485,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : RSP on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : RSP on BL : Counts the number of cycles when the UPI Ingress is not e= mpty. This tracks one of the three rings that are used by the UPI agent. = This can be used in conjunction with the UPI Ingress Occupancy Accumulator = event in order to calculate average queue occupancy. Multiple ingress buff= ers can be tracked at a given time using multiple counters. : Response (RSP= ) messages on BL. RSP packets are used to transmit a variety of protocol fl= its including grants and completions (CMP).", "UMask": "0x8", @@ -2841,8 +3496,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty : WB on BL", + "Counter": "0", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Em= pty : WB on BL : Counts the number of cycles when the UPI Ingress is not em= pty. This tracks one of the three rings that are used by the UPI agent. T= his can be used in conjunction with the UPI Ingress Occupancy Accumulator e= vent in order to calculate average queue occupancy. Multiple ingress buffe= rs can be tracked at a given time using multiple counters. : Data Response = (WB) messages on BL. WB is generally used to transmit data with coherency.= For example, remote reads and writes, or cache to cache transfers will tr= ansmit their data using WB.", "UMask": "0x10", @@ -2850,8 +3507,10 @@ }, { "BriefDescription": "Data Flit Not Sent : All", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : All : Data flit is read= y for transmission but could not be sent : data flit is ready for transmiss= ion but could not be sent for any reason, e.g. low credits, low tsv, stall = injection", "UMask": "0x1", @@ -2859,8 +3518,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No BGF Credits", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_BGF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No BGF Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x8", @@ -2868,8 +3529,10 @@ }, { "BriefDescription": "Data Flit Not Sent : No TxQ Credits", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.NO_TXQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : No TxQ Credits : Data f= lit is ready for transmission but could not be sent", "UMask": "0x10", @@ -2877,8 +3540,10 @@ }, { "BriefDescription": "Data Flit Not Sent : TSV High", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : TSV High : Data flit is= ready for transmission but could not be sent : data flit is ready for tran= smission but was not sent while tsv high", "UMask": "0x2", @@ -2886,8 +3551,10 @@ }, { "BriefDescription": "Data Flit Not Sent : Cycle valid for Flit", + "Counter": "0", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_DATA_FLITS_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data Flit Not Sent : Cycle valid for Flit : = Data flit is ready for transmission but could not be sent : data flit is re= ady for transmission but was not sent while cycle is valid for flit transmi= ssion", "UMask": "0x4", @@ -2895,8 +3562,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 0", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 0 : generating bl data flit sequence; waiting for data pump 0", "UMask": "0x1", @@ -2904,8 +3573,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at capacity (pending table plus completion fifo at limit)", "UMask": "0x10", @@ -2913,8 +3584,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is tracking at least one message", "UMask": "0x8", @@ -2922,8 +3595,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding completion fifo is full", "UMask": "0x40", @@ -2931,8 +3606,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : pump-1-pe= nding logic is at or near capacity, such that pump-0-only bl messages are g= etting stalled in slotting stage", "UMask": "0x20", @@ -2940,8 +3617,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : a bl mess= age finished but is in limbo and moved to pump-1-pending logic", "UMask": "0x4", @@ -2949,8 +3628,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence : Wait on Pu= mp 1", + "Counter": "0", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Generating BL Data Flit Sequence : Wait on P= ump 1 : generating bl data flit sequence; waiting for data pump 1", "UMask": "0x2", @@ -2958,8 +3639,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_HOLDOFF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request naturally serviced during h= old-off period", "UMask": "0x4", @@ -2967,8 +3650,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_IN_SERVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request forcibly serviced during se= rvice window", "UMask": "0x8", @@ -2976,8 +3661,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_RECEIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request received from link layer wh= ile idle (with no slot 2 request active immediately prior)", "UMask": "0x1", @@ -2985,8 +3672,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Counter": "0", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_MISC.S2REQ_WITHDRAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": slot 2 request withdrawn during hold-off p= eriod or service window", "UMask": "0x2", @@ -2994,16 +3683,20 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : All", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit : Needs = Data Flit", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Needs= Data Flit : BL message requires data flit sequence", "UMask": "0x2", @@ -3011,8 +3704,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 0", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 0 : Waiting for header pump 0", "UMask": "0x4", @@ -3020,8 +3715,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 : Header pump 1 is not required for flit", "UMask": "0x10", @@ -3029,8 +3726,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Bubble", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Bubble : Header pump 1 is not required for flit but flit tra= nsmission delayed", "UMask": "0x20", @@ -3038,8 +3737,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Don't = Need Pump 1 - Not Avail", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Don't= Need Pump 1 - Not Avail : Header pump 1 is not required for flit and not a= vailable", "UMask": "0x40", @@ -3047,8 +3748,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit : Wait o= n Pump 1", + "Counter": "0", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Slotting BL Message Into Header Flit : Wait = on Pump 1 : Waiting for header pump 1", "UMask": "0x8", @@ -3056,8 +3759,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate : Events re= lated to Header Flit Generation - Set 1 : Header flit slotting control stat= e machine is in any accumulate state; multi-message flit may be assembled o= ver multiple cycles", "UMask": "0x1", @@ -3065,8 +3770,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Ready", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Ready : Eve= nts related to Header Flit Generation - Set 1 : header flit slotting contro= l state machine is in accum_ready state; flit is ready to send but transmis= sion is blocked; more messages may be slotted into flit", "UMask": "0x2", @@ -3074,8 +3781,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Accumulate Wasted", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Accumulate Wasted : Ev= ents related to Header Flit Generation - Set 1 : Flit is being assembled ov= er multiple cycles, but no additional message is being slotted into flit in= current cycle; accumulate cycle is wasted", "UMask": "0x4", @@ -3083,8 +3792,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Blocked : = Events related to Header Flit Generation - Set 1 : Header flit slotting ent= ered run-ahead state; new header flit is started while transmission of prio= r, fully assembled flit is blocked", "UMask": "0x8", @@ -3092,8 +3803,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: message was slotted only after= run-ahead was over; run-ahead mode definitely wasted", "UMask": "0x80", @@ -3101,8 +3814,10 @@ }, { "BriefDescription": "Flit Gen - Header 1 : Run-Ahead - Message", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG1_DURING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Run-Ahead - Message : = Events related to Header Flit Generation - Set 1 : run-ahead mode: one mess= age slotted during run-ahead", "UMask": "0x10", @@ -3110,8 +3825,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_AFTER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: second message slotted immedia= tely after run-ahead; potential run-ahead success", "UMask": "0x20", @@ -3119,8 +3836,10 @@ }, { "BriefDescription": "Flit Gen - Header 1", + "Counter": "0", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG2_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 1 : Events related to Head= er Flit Generation - Set 1 : run-ahead mode: two (or three) message flit se= nt immediately after run-ahead; complete run-ahead success", "UMask": "0x40", @@ -3128,8 +3847,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Ok", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Ok : Events r= elated to Header Flit Generation - Set 2 : new header flit construction may= proceed in parallel with data flit sequence", "UMask": "0x4", @@ -3137,8 +3858,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Flit Finished", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Flit Finished= : Events related to Header Flit Generation - Set 2 : header flit finished = assembly in parallel with data flit sequence", "UMask": "0x10", @@ -3146,8 +3869,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Parallel Message", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.PAR_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Parallel Message : Eve= nts related to Header Flit Generation - Set 2 : message is slotted into hea= der flit in parallel with data flit sequence", "UMask": "0x8", @@ -3155,8 +3880,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall : = Events related to Header Flit Generation - Set 2 : Rate-matching stall inje= cted", "UMask": "0x1", @@ -3164,8 +3891,10 @@ }, { "BriefDescription": "Flit Gen - Header 2 : Rate-matching Stall - N= o Message", + "Counter": "0", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Flit Gen - Header 2 : Rate-matching Stall - = No Message : Events related to Header Flit Generation - Set 2 : Rate matchi= ng stall injected, but no additional message slotted during stall cycle", "UMask": "0x2", @@ -3173,8 +3902,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message : One message= in flit; VNA or non-VNA flit", "UMask": "0x1", @@ -3182,8 +3913,10 @@ }, { "BriefDescription": "Sent Header Flit : One Message in non-VNA", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.1_MSG_VNX", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : One Message in non-VNA : = One message in flit; non-VNA flit", "UMask": "0x8", @@ -3191,8 +3924,10 @@ }, { "BriefDescription": "Sent Header Flit : Two Messages", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.2_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Two Messages : Two messag= es in flit; VNA flit", "UMask": "0x2", @@ -3200,8 +3935,10 @@ }, { "BriefDescription": "Sent Header Flit : Three Messages", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.3_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Sent Header Flit : Three Messages : Three me= ssages in flit; VNA flit", "UMask": "0x4", @@ -3209,32 +3946,40 @@ }, { "BriefDescription": "Sent Header Flit : One Slot Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : Two Slots Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit : All Slots Taken", + "Counter": "0", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_HDR_FLITS_SENT.SLOTS_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "Header Not Sent : All", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : All : header flit is ready= for transmission but could not be sent : header flit is ready for transmis= sion but could not be sent for any reason, e.g. no credits, low tsv, stall = injection", "UMask": "0x1", @@ -3242,8 +3987,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits : header fl= it is ready for transmission but could not be sent : No BGF credits availab= le", "UMask": "0x8", @@ -3251,8 +3998,10 @@ }, { "BriefDescription": "Header Not Sent : No BGF Credits + No Extra M= essage Slotted", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No BGF Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No BGF credits available; no additional message slotted into flit", "UMask": "0x20", @@ -3260,8 +4009,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits : header fl= it is ready for transmission but could not be sent : No TxQ credits availab= le", "UMask": "0x10", @@ -3269,8 +4020,10 @@ }, { "BriefDescription": "Header Not Sent : No TxQ Credits + No Extra M= essage Slotted", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : No TxQ Credits + No Extra = Message Slotted : header flit is ready for transmission but could not be se= nt : No TxQ credits available; no additional message slotted into flit", "UMask": "0x40", @@ -3278,8 +4031,10 @@ }, { "BriefDescription": "Header Not Sent : TSV High", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.TSV_HI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : TSV High : header flit is = ready for transmission but could not be sent : header flit is ready for tra= nsmission but was not sent while tsv high", "UMask": "0x2", @@ -3287,8 +4042,10 @@ }, { "BriefDescription": "Header Not Sent : Cycle valid for Flit", + "Counter": "0", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_HDR_FLIT_NOT_SENT.VALID_FOR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header Not Sent : Cycle valid for Flit : hea= der flit is ready for transmission but could not be sent : header flit is r= eady for transmission but was not sent while cycle is valid for flit transm= ission", "UMask": "0x4", @@ -3296,8 +4053,10 @@ }, { "BriefDescription": "Message Held : Can't Slot AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot AD : some AD messa= ge could not be slotted (logical OR of all AD events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x10", @@ -3305,8 +4064,10 @@ }, { "BriefDescription": "Message Held : Can't Slot BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Can't Slot BL : some BL messa= ge could not be slotted (logical OR of all BL events under INGR_SLOT_CANT_M= C_VN{0,1})", "UMask": "0x20", @@ -3314,8 +4075,10 @@ }, { "BriefDescription": "Message Held : Parallel Attempt", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Attempt : ad and bl = messages attempted to slot into the same flit in parallel", "UMask": "0x4", @@ -3323,8 +4086,10 @@ }, { "BriefDescription": "Message Held : Parallel Success", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : Parallel Success : ad and bl = messages were actually slotted into the same flit in parallel", "UMask": "0x8", @@ -3332,8 +4097,10 @@ }, { "BriefDescription": "Message Held : VN0", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN0 : vn0 message(s) that cou= ldn't be slotted into last vn0 flit are held in slotting stage while proces= sing vn1 flit", "UMask": "0x1", @@ -3341,8 +4108,10 @@ }, { "BriefDescription": "Message Held : VN1", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Held : VN1 : vn1 message(s) that cou= ldn't be slotted into last vn1 flit are held in slotting stage while proces= sing vn0 flit", "UMask": "0x2", @@ -3350,8 +4119,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -3359,8 +4130,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -3368,8 +4141,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -3377,8 +4152,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -3386,8 +4163,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -3395,8 +4174,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -3404,8 +4185,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4e", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -3413,8 +4196,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : REQ on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Home (REQ) messages on AD. REQ is generally used to send re= quests, request responses, and snoop responses.", "UMask": "0x1", @@ -3422,8 +4207,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on AD. RSP packets are used to tran= smit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -3431,8 +4218,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : SNP on AD= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Snoops (SNP) messages on AD. SNP is used for outgoing snoop= s.", "UMask": "0x2", @@ -3440,8 +4229,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCB on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Broadcast (NCB) messages on BL. NCB is general= ly used to transmit data without coherency. For example, non-coherent read= data returns.", "UMask": "0x20", @@ -3449,8 +4240,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : NCS on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -3458,8 +4251,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : RSP on BL= : Count cases where Ingress has packets to send but did not have time to p= ack into flit before sending to Agent so slot was left NULL which could hav= e been used. : Response (RSP) messages on BL. RSP packets are used to trans= mit a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -3467,8 +4262,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit : WB on BL", + "Counter": "0,1,2", "EventCode": "0x4f", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message can't slot into flit : WB on BL = : Count cases where Ingress has packets to send but did not have time to pa= ck into flit before sending to Agent so slot was left NULL which could have= been used. : Data Response (WB) messages on BL. WB is generally used to t= ransmit data with coherency. For example, remote reads and writes, or cach= e to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -3476,8 +4273,10 @@ }, { "BriefDescription": "Remote VNA Credits : Any In Use", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Any In Use : At least o= ne remote vna credit is in use", "UMask": "0x20", @@ -3485,8 +4284,10 @@ }, { "BriefDescription": "Remote VNA Credits : Corrected", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Corrected : Number of r= emote vna credits corrected (local return) per cycle", "UMask": "0x1", @@ -3494,8 +4295,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 1", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 1 : Remote vna = credit level is less than 1 (i.e. no vna credits available)", "UMask": "0x2", @@ -3503,8 +4306,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 10", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 10 : remote vna= credit level is less than 10; parallel vn0/vn1 arb not possible", "UMask": "0x10", @@ -3512,8 +4317,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 4", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 4 : Remote vna = credit level is less than 4; bl (or ad requiring 4 vna) cannot arb on vna", "UMask": "0x4", @@ -3521,8 +4328,10 @@ }, { "BriefDescription": "Remote VNA Credits : Level < 5", + "Counter": "0", "EventCode": "0x5a", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote VNA Credits : Level < 5 : Remote vna = credit level is less than 5; parallel ad/bl arb on vna not possible", "UMask": "0x8", @@ -3530,8 +4339,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_ADBL_ALLOC_L5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 5 an= d allocation to ad or bl messages was required", "UMask": "0x2", @@ -3539,8 +4350,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT1= 0", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.REQ_VN01_ALLOC_LT10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credit count was less than 10 a= nd allocation to vn0 or vn1 was required", "UMask": "0x1", @@ -3548,8 +4361,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x10", @@ -3557,8 +4372,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn0, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x20", @@ -3566,8 +4383,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN0_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn0, not to vn1", "UMask": "0x4", @@ -3575,8 +4394,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to ad messages, not to bl", "UMask": "0x40", @@ -3584,8 +4405,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_JUST_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": on vn1, remote vna credits were allocated = only to bl messages, not to ad", "UMask": "0x80", @@ -3593,8 +4416,10 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Counter": "0", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_VNA_CRD_MISC.VN1_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": remote vna credits were allocated only to = vn1, not to vn0", "UMask": "0x8", @@ -3602,8 +4427,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -3611,8 +4438,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -3620,8 +4449,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x2", @@ -3629,8 +4460,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN0 WB Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN0 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x8", @@ -3638,8 +4471,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 REQ Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -3647,8 +4482,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 RSP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -3656,8 +4493,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 SNP Messages : AD ar= b but no win; arb request asserted but not won", "UMask": "0x20", @@ -3665,8 +4504,10 @@ }, { "BriefDescription": "Failed ARB for AD : VN1 WB Messages", + "Counter": "0", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for AD : VN1 WB Messages : AD arb= but no win; arb request asserted but not won", "UMask": "0x80", @@ -3674,8 +4515,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3684,8 +4527,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x1", @@ -3693,8 +4538,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x2", @@ -3702,8 +4549,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x4", @@ -3711,8 +4560,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD FlowQ Bypass : Counts cases when the AD f= lowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 ha= ving the highest priority and S2 the least)", "UMask": "0x8", @@ -3720,8 +4571,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x1", @@ -3729,8 +4582,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x4", @@ -3738,8 +4593,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x2", @@ -3747,8 +4604,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x8", @@ -3756,8 +4615,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x10", @@ -3765,8 +4626,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x40", @@ -3774,8 +4637,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the AD Egress queue is Not Empty", "UMask": "0x20", @@ -3783,8 +4648,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the AD Egress queue is Not Empty", "UMask": "0x80", @@ -3792,8 +4659,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -3801,8 +4670,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -3810,8 +4681,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -3819,8 +4692,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -3828,8 +4703,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 REQ Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -3837,8 +4714,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -3846,8 +4725,10 @@ }, { "BriefDescription": "AD Flow Q Inserts : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Flow Q Inserts : VN1 SNP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -3855,78 +4736,98 @@ }, { "BriefDescription": "AD Flow Q Occupancy : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x1c", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Occupancy", + "Counter": "0", "EventCode": "0x1e", "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Failed ARB for BL : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x4", @@ -3934,8 +4835,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 NCS Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x8", @@ -3943,8 +4846,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x1", @@ -3952,8 +4857,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN0 WB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN0 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x2", @@ -3961,8 +4868,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCS Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCS Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x40", @@ -3970,8 +4879,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 NCB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 NCB Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x80", @@ -3979,8 +4890,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 RSP Messages : BL ar= b but no win; arb request asserted but not won", "UMask": "0x10", @@ -3988,8 +4901,10 @@ }, { "BriefDescription": "Failed ARB for BL : VN1 WB Messages", + "Counter": "0", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Failed ARB for BL : VN1 WB Messages : BL arb= but no win; arb request asserted but not won", "UMask": "0x20", @@ -3997,8 +4912,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x1", @@ -4006,8 +4923,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x4", @@ -4015,8 +4934,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x2", @@ -4024,8 +4945,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN0 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x8", @@ -4033,8 +4956,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 REQ Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x10", @@ -4042,8 +4967,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 RSP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x40", @@ -4051,8 +4978,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 SNP Messages : Num= ber of cycles the BL Egress queue is Not Empty", "UMask": "0x20", @@ -4060,8 +4989,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Not Empty : VN1 WB Messages : Numb= er of cycles the BL Egress queue is Not Empty", "UMask": "0x80", @@ -4069,8 +5000,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x1", @@ -4078,8 +5011,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x2", @@ -4087,8 +5022,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x8", @@ -4096,8 +5033,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN0 NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN0 NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x4", @@ -4105,8 +5044,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 RSP Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x10", @@ -4114,8 +5055,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1 WB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1 WB Messages : Counts= the number of allocations into the QPI FlowQ. This can be used in conjunct= ion with the QPI FlowQ Occupancy Accumulator event in order to calculate av= erage queue latency. Only a single FlowQ queue can be tracked at any given= time. It is not possible to filter based on direction or polarity.", "UMask": "0x20", @@ -4123,8 +5066,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCB Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCB Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x80", @@ -4132,8 +5077,10 @@ }, { "BriefDescription": "BL Flow Q Inserts : VN1_NCS Messages", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Flow Q Inserts : VN1_NCS Messages : Count= s the number of allocations into the QPI FlowQ. This can be used in conjunc= tion with the QPI FlowQ Occupancy Accumulator event in order to calculate a= verage queue latency. Only a single FlowQ queue can be tracked at any give= n time. It is not possible to filter based on direction or polarity.", "UMask": "0x40", @@ -4141,120 +5088,150 @@ }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCS Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1d", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 WB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN0_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1 WB Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_THROUGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy : VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1f", "EventName": "UNC_M3UPI_TxC_BL_WB_FLQ_OCCUPANCY.VN1_WRPULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x2", @@ -4262,8 +5239,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x8", @@ -4271,8 +5250,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN0 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN0 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x4", @@ -4280,8 +5261,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 REQ Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 REQ Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x10", @@ -4289,8 +5272,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 RSP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 RSP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x40", @@ -4298,8 +5283,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VN1 SNP Messages", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VN1 SNP Messages : N= o credits available to send to UPIs on the AD Ring", "UMask": "0x20", @@ -4307,8 +5294,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty : VNA", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 AD Credits Empty : VNA : No credits ava= ilable to send to UPIs on the AD Ring", "UMask": "0x1", @@ -4316,8 +5305,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 RSP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x4", @@ -4325,8 +5316,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 REQ Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x2", @@ -4334,8 +5327,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN0 SNP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN0 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x8", @@ -4343,8 +5338,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 RSP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 RSP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x20", @@ -4352,8 +5349,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 REQ Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 REQ Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x10", @@ -4361,8 +5360,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VN1 SNP Messages", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VN1 SNP Messages : N= o credits available to send to UPI on the BL Ring (diff between non-SMI and= SMI mode)", "UMask": "0x40", @@ -4370,8 +5371,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty : VNA", + "Counter": "0", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "UPI0 BL Credits Empty : VNA : No credits ava= ilable to send to UPI on the BL Ring (diff between non-SMI and SMI mode)", "UMask": "0x1", @@ -4379,16 +5382,20 @@ }, { "BriefDescription": "FlowQ Generated Prefetch", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "FlowQ Generated Prefetch : Count cases where= FlowQ causes spawn of Prefetch to iMC/SMI3 target", "Unit": "M3UPI" }, { "BriefDescription": "VN0 Credit Used : WB on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : WB on BL : Number of times= a VN0 credit was used on the DRS message channel. In order for a request = to be transferred across UPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN0.= VNA is a shared pool used to achieve high performance. The VN0 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN0 if= they fail. This counts the number of times a VN0 credit was used. Note t= hat a single VN0 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN0 will only count a single credit ev= en though it may use multiple buffers. : Data Response (WB) messages on BL.= WB is generally used to transmit data with coherency. For example, remot= e reads and writes, or cache to cache transfers will transmit their data us= ing WB.", "UMask": "0x10", @@ -4396,8 +5403,10 @@ }, { "BriefDescription": "VN0 Credit Used : NCB on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : NCB on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -4405,8 +5414,10 @@ }, { "BriefDescription": "VN0 Credit Used : REQ on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : REQ on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4414,8 +5425,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -4423,8 +5436,10 @@ }, { "BriefDescription": "VN0 Credit Used : SNP on AD", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : SNP on AD : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -4432,8 +5447,10 @@ }, { "BriefDescription": "VN0 Credit Used : RSP on BL", + "Counter": "0", "EventCode": "0x5b", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Used : RSP on BL : Number of time= s a VN0 credit was used on the DRS message channel. In order for a request= to be transferred across UPI, it must be guaranteed to have a flit buffer = on the remote socket to sink into. There are two credit pools, VNA and VN0= . VNA is a shared pool used to achieve high performance. The VN0 pool has= reserved entries for each message class and is used to prevent deadlock. = Requests first attempt to acquire a VNA credit, and then fall back to VN0 i= f they fail. This counts the number of times a VN0 credit was used. Note = that a single VN0 credit holds access to potentially multiple flit buffers.= For example, a transfer that uses VNA could use 9 flit buffers and in tha= t case uses 9 credits. A transfer on VN0 will only count a single credit e= ven though it may use multiple buffers. : Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -4441,8 +5458,10 @@ }, { "BriefDescription": "VN0 No Credits : WB on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : WB on BL : Number of Cycles= there were no VN0 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -4450,8 +5469,10 @@ }, { "BriefDescription": "VN0 No Credits : NCB on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : NCB on BL : Number of Cycle= s there were no VN0 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -4459,8 +5480,10 @@ }, { "BriefDescription": "VN0 No Credits : REQ on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : REQ on AD : Number of Cycle= s there were no VN0 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4468,8 +5491,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on AD : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -4477,8 +5502,10 @@ }, { "BriefDescription": "VN0 No Credits : SNP on AD", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : SNP on AD : Number of Cycle= s there were no VN0 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -4486,8 +5513,10 @@ }, { "BriefDescription": "VN0 No Credits : RSP on BL", + "Counter": "0", "EventCode": "0x5d", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 No Credits : RSP on BL : Number of Cycle= s there were no VN0 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -4495,8 +5524,10 @@ }, { "BriefDescription": "VN1 Credit Used : WB on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : WB on BL : Number of times= a VN1 credit was used on the WB message channel. In order for a request t= o be transferred across QPI, it must be guaranteed to have a flit buffer on= the remote socket to sink into. There are two credit pools, VNA and VN1. = VNA is a shared pool used to achieve high performance. The VN1 pool has r= eserved entries for each message class and is used to prevent deadlock. Re= quests first attempt to acquire a VNA credit, and then fall back to VN1 if = they fail. This counts the number of times a VN1 credit was used. Note th= at a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that = case uses 9 credits. A transfer on VN1 will only count a single credit eve= n though it may use multiple buffers. : Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote= reads and writes, or cache to cache transfers will transmit their data usi= ng WB.", "UMask": "0x10", @@ -4504,8 +5535,10 @@ }, { "BriefDescription": "VN1 Credit Used : NCB on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : NCB on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Non-Coherent Broadcast (NCB) messa= ges on BL. NCB is generally used to transmit data without coherency. For = example, non-coherent read data returns.", "UMask": "0x20", @@ -4513,8 +5546,10 @@ }, { "BriefDescription": "VN1 Credit Used : REQ on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : REQ on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Home (REQ) messages on AD. REQ is= generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4522,8 +5557,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on AD. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x4", @@ -4531,8 +5568,10 @@ }, { "BriefDescription": "VN1 Credit Used : SNP on AD", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : SNP on AD : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Snoops (SNP) messages on AD. SNP = is used for outgoing snoops.", "UMask": "0x2", @@ -4540,8 +5579,10 @@ }, { "BriefDescription": "VN1 Credit Used : RSP on BL", + "Counter": "0", "EventCode": "0x5c", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Used : RSP on BL : Number of time= s a VN1 credit was used on the WB message channel. In order for a request = to be transferred across QPI, it must be guaranteed to have a flit buffer o= n the remote socket to sink into. There are two credit pools, VNA and VN1.= VNA is a shared pool used to achieve high performance. The VN1 pool has = reserved entries for each message class and is used to prevent deadlock. R= equests first attempt to acquire a VNA credit, and then fall back to VN1 if= they fail. This counts the number of times a VN1 credit was used. Note t= hat a single VN1 credit holds access to potentially multiple flit buffers. = For example, a transfer that uses VNA could use 9 flit buffers and in that= case uses 9 credits. A transfer on VN1 will only count a single credit ev= en though it may use multiple buffers. : Response (RSP) messages on BL. RSP= packets are used to transmit a variety of protocol flits including grants = and completions (CMP).", "UMask": "0x8", @@ -4549,8 +5590,10 @@ }, { "BriefDescription": "VN1 No Credits : WB on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : WB on BL : Number of Cycles= there were no VN1 Credits : Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -4558,8 +5601,10 @@ }, { "BriefDescription": "VN1 No Credits : NCB on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : NCB on BL : Number of Cycle= s there were no VN1 Credits : Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, no= n-coherent read data returns.", "UMask": "0x20", @@ -4567,8 +5612,10 @@ }, { "BriefDescription": "VN1 No Credits : REQ on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : REQ on AD : Number of Cycle= s there were no VN1 Credits : Home (REQ) messages on AD. REQ is generally = used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -4576,8 +5623,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on AD : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on AD. RSP packets a= re used to transmit a variety of protocol flits including grants and comple= tions (CMP).", "UMask": "0x4", @@ -4585,8 +5634,10 @@ }, { "BriefDescription": "VN1 No Credits : SNP on AD", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : SNP on AD : Number of Cycle= s there were no VN1 Credits : Snoops (SNP) messages on AD. SNP is used for= outgoing snoops.", "UMask": "0x2", @@ -4594,8 +5645,10 @@ }, { "BriefDescription": "VN1 No Credits : RSP on BL", + "Counter": "0", "EventCode": "0x5e", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 No Credits : RSP on BL : Number of Cycle= s there were no VN1 Credits : Response (RSP) messages on BL. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x8", @@ -4603,168 +5656,210 @@ }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x82", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_EQ_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_GT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LO= CALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.BOTHNONZERO_RT_LT_LOCALDEST= _VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc0", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_EQ_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_GT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7e", "EventName": "UNC_M3UPI_WB_OCC_COMPARE.RT_LT_LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCALDEST_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.LOCAL_AND_RT_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.ROUTETHRU_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Counter": "0", "EventCode": "0x7d", "EventName": "UNC_M3UPI_WB_PENDING.WAITING4PULL_VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARB", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message is making arbitration= request", "UMask": "0x4", @@ -4772,8 +5867,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.ARRIVED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message arrived in ingress pi= peline", "UMask": "0x1", @@ -4781,8 +5878,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.BYPASS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message took bypass path", "UMask": "0x2", @@ -4790,8 +5889,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.FLITTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was slotted into flit= (non bypass)", "UMask": "0x10", @@ -4799,8 +5900,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message lost arbitration", "UMask": "0x8", @@ -4808,8 +5911,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_OLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t became too old", "UMask": "0x20", @@ -4817,8 +5922,10 @@ }, { "BriefDescription": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Counter": "0", "EventCode": "0x61", "EventName": "UNC_M3UPI_XPT_PFTCH.LOST_QFULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": xpt prefetch message was dropped because i= t was overwritten by new message while prefetch queue was full", "UMask": "0x40", @@ -4826,8 +5933,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AD Bounceable)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD Bounceable : Number of allocations into t= he CRS Egress", "UMask": "0x1", @@ -4835,8 +5944,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AD credited)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD credited : Number of allocations into the= CRS Egress", "UMask": "0x2", @@ -4844,8 +5955,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AK)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AK : Number of allocations into the CRS Egre= ss", "UMask": "0x10", @@ -4853,8 +5966,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (AKC)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AKC : Number of allocations into the CRS Egr= ess", "UMask": "0x40", @@ -4862,8 +5977,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (BL Bounceable)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL Bounceable : Number of allocations into t= he CRS Egress", "UMask": "0x4", @@ -4871,8 +5988,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (BL credited)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL credited : Number of allocations into the= CRS Egress", "UMask": "0x8", @@ -4880,8 +5999,10 @@ }, { "BriefDescription": "Number of allocations into the CRS Egress us= ed to queue up requests destined to the mesh (IV)", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_MDF_CRS_TxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IV : Number of allocations into the CRS Egre= ss", "UMask": "0x20", @@ -4889,8 +6010,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AD)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x1", @@ -4898,8 +6021,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AK)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AK : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x4", @@ -4907,8 +6032,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (AKC)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AKC : Number of cycles incoming messages fro= m the vertical ring that are bounced at the SBO", "UMask": "0x10", @@ -4916,8 +6043,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (BL)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x2", @@ -4925,8 +6054,10 @@ }, { "BriefDescription": "Number of cycles incoming messages from the v= ertical ring that are bounced at the SBO Ingress (V-EMIB) (IV)", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_MDF_CRS_TxR_V_BOUNCES.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IV : Number of cycles incoming messages from= the vertical ring that are bounced at the SBO", "UMask": "0x8", @@ -4934,8 +6065,10 @@ }, { "BriefDescription": "Counts the number of cycles when the distress= signals are asserted based on SBO Ingress threshold", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_MDF_FAST_ASSERTED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD bnc : Counts the number of cycles when th= e distress signals are asserted based on SBO Ingress threshold", "UMask": "0x1", @@ -4943,8 +6076,10 @@ }, { "BriefDescription": "Counts the number of cycles when the distress= signals are asserted based on SBO Ingress threshold", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_MDF_FAST_ASSERTED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL bnc : Counts the number of cycles when th= e distress signals are asserted based on SBO Ingress threshold", "UMask": "0x2", @@ -4952,6 +6087,7 @@ }, { "BriefDescription": "UPI Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -4960,8 +6096,10 @@ }, { "BriefDescription": "Direct packet attempts : D2C", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2C : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x1", @@ -4969,8 +6107,10 @@ }, { "BriefDescription": "Direct packet attempts : D2K", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Direct packet attempts : D2K : Counts the nu= mber of DRS packets that we attempted to do direct2core/direct2UPI on. The= re are 4 mutually exclusive filters. Filter [0] can be used to get success= ful spawns, while [1:3] provide the different failure cases. Note that thi= s does not count packets that are not candidates for Direct2Core. The only= candidates for Direct2Core are DRS packets destined for Cbos.", "UMask": "0x2", @@ -4978,70 +6118,87 @@ }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Cycles in L1", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", @@ -5050,246 +6207,308 @@ }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_UPI_POWER_L1_NACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req Nack : Counts the number of times a l= ink sends/receives a LinkReqNAck. When the UPI links would like to change = power state, the Tx side initiates a request to the Rx side requesting to c= hange states. This requests can either be accepted or denied. If the Rx s= ide replies with an Ack, the power mode will change. If it replies with NA= ck, no change will take place. This can be filtered based on Rx and Tx. A= n Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx origi= nally requested the power change). A Tx LinkReqNAck refers to sending this= command (meaning the peer agent's Tx originally requested the power change= and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "L1 Req (same as L1 Ack).", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_UPI_POWER_L1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "L1 Req (same as L1 Ack). : Counts the number= of times a link sends/receives a LinkReqAck. When the UPI links would lik= e to change power state, the Tx side initiates a request to the Rx side req= uesting to change states. This requests can either be accepted or denied. = If the Rx side replies with an Ack, the power mode will change. If it rep= lies with NAck, no change will take place. This can be filtered based on R= x and Tx. An Rx LinkReqAck refers to receiving an Ack (meaning this agent'= s Tx originally requested the power change). A Tx LinkReqAck refers to sen= ding this command (meaning the peer agent's Tx originally requested the pow= er change and this agent accepted it).", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles s= pent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lane= s, decreasing our bandwidth in order to save power. It increases snoop and= data transfer latencies and decreases overall bandwidth. This mode can be= very useful in NUMA optimized workloads that largely only utilize UPI for = snoops and their responses. Use edge detect to count the number of instanc= es when the UPI link entered L0p. Link power states are per link and per d= irection, so for example the Tx direction could be in one state while Rx wa= s in another.", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.DATA", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.NULL", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_UPI_RxL_ANY_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass : Matches on Receive path of a UPI port. Match based on UMa= sk specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opcod= e (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr Ena= ble R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Enabl= e Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even un= der specific opcode match_en cases. Note: If Message Class is disabled, we = expect opcode to also be disabled.", "UMask": "0xe", @@ -5297,8 +6516,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Bypass, Match Opcode : Matches on Receive path of a UPI port. Matc= h based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class E= nable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S= : Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single = Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL, = LLCRD) even under specific opcode match_en cases. Note: If Message Class is= disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -5306,8 +6527,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard : Matches on Receive path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xf", @@ -5315,8 +6538,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Receive path of a UPI Port : Non-= Coherent Standard, Match Opcode : Matches on Receive path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -5324,8 +6549,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 0 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x1", @@ -5333,8 +6560,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 1 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x2", @@ -5342,8 +6571,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Bypassed : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Bypassed : Slot 2 : Counts t= he number of times that an incoming flit was able to bypass the flit buffer= and pass directly across the BGF and into the Egress. This is a latency o= ptimization, and should generally be the common case. If this value is les= s than the number of flits transferred, it implies that there was queueing = getting onto the ring, and thus the transactions saw higher latency.", "UMask": "0x4", @@ -5351,40 +6582,50 @@ }, { "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", "EventCode": "0x0b", "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CRC Errors Detected : Number of CRC errors d= etected in the UPI Agent. Each UPI flit incorporates 8 bits of CRC for err= or detection. This counts the number of flits where the CRC was able to de= tect an error. After an error has been detected, the UPI agent will send a= request to the transmitting socket to resend the flit (as well as any flit= s that came after it).", "Unit": "UPI" }, { "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "LLR Requests Sent : Number of LLR Requests w= ere transmitted. This should generally be <=3D the number of CRC errors de= tected. If multiple errors are detected before the Rx side receives a LLC_= REQ_ACK from the Tx side, there is no need to send more LLR_REQ_NACKs..", "Unit": "UPI" }, { "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 Credit Consumed : Counts the number of t= imes that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x3a", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 Credit Consumed : Counts the number of t= imes that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit fo= r the Rx Buffer). This includes packets that went through the RxQ and thos= e that were bypasssed.", "Unit": "UPI" }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -5393,6 +6634,7 @@ }, { "BriefDescription": "Valid Flits Received : All Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -5402,6 +6644,7 @@ }, { "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -5410,8 +6653,10 @@ }, { "BriefDescription": "Valid Flits Received : Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Data : Shows legal fl= it time (hides impact of L0p and L0c). : Count Data Flits (which consume al= l slots), but how much to count is based on Slot0-2 mask, so count can be 0= -3 depending on which slots are enabled for counting..", "UMask": "0x8", @@ -5419,8 +6664,10 @@ }, { "BriefDescription": "Valid Flits Received : Idle", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Idle : Shows legal fl= it time (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5428,8 +6675,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCRD Not Empty : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables counting of LLC= RD (with non-zero payload). This only applies to slot 2 since LLCRD is only= allowed in slot 2", "UMask": "0x10", @@ -5437,8 +6686,10 @@ }, { "BriefDescription": "Valid Flits Received : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : LLCTRL : Shows legal = flit time (hides impact of L0p and L0c). : Equivalent to an idle packet. E= nables counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -5446,6 +6697,7 @@ }, { "BriefDescription": "Valid Flits Received : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -5455,8 +6707,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Emp= ty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot NULL or LLCRD Em= pty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all= zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dua= l slot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -5464,8 +6718,10 @@ }, { "BriefDescription": "Valid Flits Received : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Protocol Header : Sho= ws legal flit time (hides impact of L0p and L0c). : Enables count of protoc= ol headers in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -5473,8 +6729,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 0 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits d= etermine types of headers to count.", "UMask": "0x1", @@ -5482,8 +6740,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 1 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits d= etermine types of headers to count.", "UMask": "0x2", @@ -5491,8 +6751,10 @@ }, { "BriefDescription": "Valid Flits Received : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Slot 2 : Shows legal = flit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits d= etermine types of headers to count.", "UMask": "0x4", @@ -5500,8 +6762,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 0 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x1", @@ -5509,8 +6773,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 1 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x2", @@ -5518,8 +6784,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Flit Buffer Allocations : Slot 2 : Numbe= r of allocations into the UPI Rx Flit Buffer. Generally, when data is tran= smitted across UPI, it will bypass the RxQ and pass directly to the ring in= terface. If things back up getting transmitted onto the ring, however, it = may need to allocate into this buffer, thus increasing the latency. This e= vent can be used in conjunction with the Flit Buffer Occupancy event in ord= er to calculate the average flit buffer lifetime.", "UMask": "0x4", @@ -5527,8 +6795,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 0 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x1", @@ -5536,8 +6806,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 1 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x2", @@ -5545,8 +6817,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RxQ Occupancy - All Packets : Slot 2 : Accum= ulates the number of elements in the UPI RxQ in each cycle. Generally, whe= n data is transmitted across UPI, it will bypass the RxQ and pass directly = to the ring interface. If things back up getting transmitted onto the ring= , however, it may need to allocate into this buffer, thus increasing the la= tency. This event can be used in conjunction with the Flit Buffer Not Empt= y event to calculate average occupancy, or with the Flit Buffer Allocations= event to track average lifetime.", "UMask": "0x4", @@ -5554,214 +6828,268 @@ }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0p", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0p : Number of UPI qfclk cycles s= pent in L0p power mode. L0p is a mode where we disable 1/2 of the UPI lane= s, decreasing our bandwidth in order to save power. It increases snoop and= data transfer latencies and decreases overall bandwidth. This mode can be= very useful in NUMA optimized workloads that largely only utilize UPI for = snoops and their responses. Use edge detect to count the number of instanc= es when the UPI link entered L0p. Link power states are per link and per d= irection, so for example the Tx direction could be in one state while Rx wa= s in another.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles in L0 : Number of UPI qfclk cycles sp= ent in L0 power mode in the Link Layer. L0 is the default mode which provi= des the highest performance with the most power. Use edge detect to count = the number of instances that the link entered L0. Link power states are pe= r link and per direction, so for example the Tx direction could be in one s= tate while Rx was in another. The phy layer sometimes leaves L0 for train= ing, which will not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.DATA", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.NULL", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_UPI_TxL_ANY_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass : Matches on Transmit path of a UPI port. Match based on U= Mask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: Opc= ode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr E= nable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr Ena= ble Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) even = under specific opcode match_en cases. Note: If Message Class is disabled, w= e expect opcode to also be disabled.", "UMask": "0xe", @@ -5769,8 +7097,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Bypass, Match Opcode : Matches on Transmit path of a UPI port. Ma= tch based on UMask specific bits: Z: Message Class (3-bit) Y: Message Class= Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable= S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Singl= e Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NULL= , LLCRD) even under specific opcode match_en cases. Note: If Message Class = is disabled, we expect opcode to also be disabled.", "UMask": "0x10e", @@ -5778,8 +7108,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard : Matches on Transmit path of a UPI port. Match based on= UMask specific bits: Z: Message Class (3-bit) Y: Message Class Enable W: O= pcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enable S: Data Hdr= Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Single Slot Hdr E= nable Link Layer control types are excluded (LL CTRL, slot NULL, LLCRD) eve= n under specific opcode match_en cases. Note: If Message Class is disabled,= we expect opcode to also be disabled.", "UMask": "0xf", @@ -5787,8 +7119,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Matches on Transmit path of a UPI Port : Non= -Coherent Standard, Match Opcode : Matches on Transmit path of a UPI port. = Match based on UMask specific bits: Z: Message Class (3-bit) Y: Message Cla= ss Enable W: Opcode (4-bit) V: Opcode Enable U: Local Enable T: Remote Enab= le S: Data Hdr Enable R: Non-Data Hdr Enable Q: Dual Slot Hdr Enable P: Sin= gle Slot Hdr Enable Link Layer control types are excluded (LL CTRL, slot NU= LL, LLCRD) even under specific opcode match_en cases. Note: If Message Clas= s is disabled, we expect opcode to also be disabled.", "UMask": "0x10f", @@ -5796,14 +7130,17 @@ }, { "BriefDescription": "Tx Flit Buffer Bypassed", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Bypassed : Counts the number = of times that an incoming flit was able to bypass the Tx flit buffer and pa= ss directly out the UPI Link. Generally, when data is transmitted across UP= I, it will bypass the TxQ and pass directly to the link. However, the TxQ = will be used with L0p and when LLR occurs, increasing latency to transfer o= ut to the link.", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : All Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -5813,8 +7150,10 @@ }, { "BriefDescription": "Valid Flits Sent : All LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All Data : Shows legal fl= it time (hides impact of L0p and L0c).", "UMask": "0x17", @@ -5822,8 +7161,10 @@ }, { "BriefDescription": "Valid Flits Sent : All LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All LLCTRL : Shows legal = flit time (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5831,6 +7172,7 @@ }, { "BriefDescription": "All Null Flits", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -5839,8 +7181,10 @@ }, { "BriefDescription": "Valid Flits Sent : All Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : All ProtDDR : Shows legal= flit time (hides impact of L0p and L0c).", "UMask": "0x87", @@ -5848,8 +7192,10 @@ }, { "BriefDescription": "Valid Flits Sent : Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Data : Shows legal flit t= ime (hides impact of L0p and L0c). : Count Data Flits (which consume all sl= ots), but how much to count is based on Slot0-2 mask, so count can be 0-3 d= epending on which slots are enabled for counting..", "UMask": "0x8", @@ -5857,8 +7203,10 @@ }, { "BriefDescription": "Valid Flits Sent : Idle", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Idle : Shows legal flit t= ime (hides impact of L0p and L0c).", "UMask": "0x47", @@ -5866,8 +7214,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCRD Not Empty : Shows l= egal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (= with non-zero payload). This only applies to slot 2 since LLCRD is only all= owed in slot 2", "UMask": "0x10", @@ -5875,8 +7225,10 @@ }, { "BriefDescription": "Valid Flits Sent : LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : LLCTRL : Shows legal flit= time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enabl= es counting of slot 0 LLCTRL messages.", "UMask": "0x40", @@ -5884,6 +7236,7 @@ }, { "BriefDescription": "Valid Flits Sent : All Non Data", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -5893,8 +7246,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty = : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zer= os is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual sl= ot. This can apply to slot 0,1, or 2.", "UMask": "0x20", @@ -5902,8 +7257,10 @@ }, { "BriefDescription": "Valid Flits Sent : Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Protocol Header : Shows l= egal flit time (hides impact of L0p and L0c). : Enables count of protocol h= eaders in slot 0,1,2 (depending on slot uMask bits)", "UMask": "0x80", @@ -5911,8 +7268,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 0 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits deter= mine types of headers to count.", "UMask": "0x1", @@ -5920,8 +7279,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 1 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits deter= mine types of headers to count.", "UMask": "0x2", @@ -5929,8 +7290,10 @@ }, { "BriefDescription": "Valid Flits Sent : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Sent : Slot 2 : Shows legal flit= time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits deter= mine types of headers to count.", "UMask": "0x4", @@ -5938,47 +7301,59 @@ }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Allocations : Number of alloc= ations into the UPI Tx Flit Buffer. Generally, when data is transmitted ac= ross UPI, it will bypass the TxQ and pass directly to the link. However, t= he TxQ will be used with L0p and when LLR occurs, increasing latency to tra= nsfer out to the link. This event can be used in conjunction with the Flit= Buffer Occupancy event in order to calculate the average flit buffer lifet= ime.", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Tx Flit Buffer Occupancy : Accumulates the n= umber of flits in the TxQ. Generally, when data is transmitted across UPI,= it will bypass the TxQ and pass directly to the link. However, the TxQ wi= ll be used with L0p and when LLR occurs, increasing latency to transfer out= to the link. This can be used with the cycles not empty event to track ave= rage occupancy, or the allocations event to track average lifetime in the T= xQ.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VNA Credits Pending Return - Occupancy : Num= ber of VNA credits in the Rx side that are waitng to be returned back acros= s the link.", "Unit": "UPI" }, { "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", @@ -5986,8 +7361,10 @@ }, { "BriefDescription": "Message Received : IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", "UMask": "0x4", @@ -5995,8 +7372,10 @@ }, { "BriefDescription": "Message Received : MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", "UMask": "0x2", @@ -6004,8 +7383,10 @@ }, { "BriefDescription": "Message Received : VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", "UMask": "0x1", @@ -6013,152 +7394,190 @@ }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Counter": "0", "EventCode": "0x4d", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_UPI_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0", "EventCode": "0x4e", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0", "EventCode": "0x4f", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0", "EventCode": "0x4f", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", "UMask": "0x1", @@ -6166,32 +7585,40 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0", "EventCode": "0x4c", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json b= /tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json index 03596db87710..91013ced74aa 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-io.json @@ -1,134 +1,167 @@ [ { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x23", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x25", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x26", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x27", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "9", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x30", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "10", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "11", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x32", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "12", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x33", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "13", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x34", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "14", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x35", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "15", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x36", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "16", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_OUT.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "iio_free_running" }, { "BriefDescription": "IIO Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -138,6 +171,7 @@ }, { "BriefDescription": "Free running counter that increments for IIO = clocktick", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", @@ -146,8 +180,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xff", @@ -157,8 +193,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -168,8 +206,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -179,8 +219,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -190,8 +232,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -201,8 +245,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -212,8 +258,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -223,8 +271,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -234,8 +284,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -245,8 +297,10 @@ }, { "BriefDescription": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "UMask": "0xff", @@ -254,8 +308,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 0", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -265,8 +321,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 1", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -276,8 +334,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 2", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -287,8 +347,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 3", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -298,8 +360,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 4", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -309,8 +373,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 5", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -320,8 +386,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 6", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -331,8 +399,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy : Part 7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0000", @@ -342,8 +412,10 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0-7", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -352,6 +424,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -363,6 +436,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -374,6 +448,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -385,6 +460,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -396,6 +472,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -407,6 +484,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -418,6 +496,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -429,6 +508,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Cards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -440,8 +520,10 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0-7 = by the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -450,8 +532,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0100", @@ -461,8 +545,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0200", @@ -472,6 +558,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -483,6 +570,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -494,6 +582,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -505,6 +594,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -516,6 +606,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -527,6 +618,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -538,6 +630,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -549,6 +642,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -560,8 +654,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -571,8 +667,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -582,8 +680,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -593,8 +693,10 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -604,8 +706,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -615,8 +719,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -626,8 +732,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -637,8 +745,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -648,8 +758,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -659,8 +771,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -670,8 +784,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -681,8 +797,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -692,8 +810,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -703,8 +823,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -714,8 +836,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -725,8 +849,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -736,8 +862,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xff", @@ -747,6 +875,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -758,6 +887,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -769,6 +899,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -780,6 +911,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -791,6 +923,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -802,6 +935,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -813,6 +947,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -824,6 +959,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -835,8 +971,10 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part0-7 = to Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -845,6 +983,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part0 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -856,6 +995,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part1 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -867,6 +1007,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part2 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -878,6 +1019,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by IIO Part3 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -889,6 +1031,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -900,6 +1043,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -911,6 +1055,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -922,6 +1067,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -933,8 +1079,10 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part0-7 = to Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00ff", @@ -943,6 +1091,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part0 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -954,6 +1103,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part1 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -965,6 +1115,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part2 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -976,6 +1127,7 @@ }, { "BriefDescription": "Write request of 4 bytes made by IIO Part3 to= Memory", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -987,6 +1139,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -998,6 +1151,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1009,6 +1163,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1020,6 +1175,7 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to D= RAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1031,8 +1187,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -1042,8 +1200,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -1053,8 +1213,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -1064,8 +1226,10 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -1075,8 +1239,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -1086,8 +1252,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -1097,8 +1265,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -1108,8 +1278,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -1119,8 +1291,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1130,8 +1304,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1141,8 +1317,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1152,8 +1330,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1163,8 +1343,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1174,8 +1356,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1185,8 +1369,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1196,8 +1382,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1207,8 +1395,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1218,8 +1408,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1229,8 +1421,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1240,8 +1434,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1251,8 +1447,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", @@ -1261,8 +1459,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", @@ -1271,8 +1471,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", @@ -1281,8 +1483,10 @@ }, { "BriefDescription": ": Context cache hits", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", @@ -1291,8 +1495,10 @@ }, { "BriefDescription": ": Context cache lookups", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", @@ -1301,8 +1507,10 @@ }, { "BriefDescription": ": IOTLB lookups first", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", @@ -1311,8 +1519,10 @@ }, { "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "Counter": "0", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "IOTLB Fills (same as IOTLB miss) : When a tr= ansaction misses IOTLB, it does a page walk to look up memory and bring in = the relevant page translation. Counts when this page translation is written= to IOTLB.", @@ -1321,8 +1531,10 @@ }, { "BriefDescription": ": IOMMU memory access", + "Counter": "0", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", "UMask": "0xc0", @@ -1330,8 +1542,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -1339,8 +1553,10 @@ }, { "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", "UMask": "0x10", @@ -1348,8 +1564,10 @@ }, { "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", "UMask": "0x2", @@ -1357,8 +1575,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -1366,8 +1586,10 @@ }, { "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", "UMask": "0x20", @@ -1375,8 +1597,10 @@ }, { "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", "UMask": "0x1", @@ -1384,8 +1608,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -1393,8 +1619,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x10", @@ -1402,8 +1630,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -1411,8 +1641,10 @@ }, { "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.PWT_OCCUPANCY_MSB", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", @@ -1421,8 +1653,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", @@ -1431,8 +1665,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", @@ -1441,8 +1677,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", @@ -1451,8 +1689,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", @@ -1461,8 +1701,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", @@ -1471,8 +1713,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", @@ -1481,8 +1725,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", @@ -1491,8 +1737,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", @@ -1501,8 +1749,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", @@ -1511,8 +1761,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", @@ -1521,8 +1773,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", @@ -1531,8 +1785,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", @@ -1541,6 +1797,7 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", @@ -1552,8 +1809,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1562,8 +1821,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1572,8 +1833,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1582,8 +1845,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1592,8 +1857,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1602,8 +1869,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1612,8 +1881,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1622,8 +1893,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1632,8 +1905,10 @@ }, { "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", @@ -1641,8 +1916,10 @@ }, { "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1652,8 +1929,10 @@ }, { "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1663,8 +1942,10 @@ }, { "BriefDescription": "PWT occupancy. Does not include 9th bit of o= ccupancy (will undercount if PWT is greater than 255 per cycle).", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x0000", "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", @@ -1673,8 +1954,10 @@ }, { "BriefDescription": "Request Ownership : PCIe Request complete", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1684,8 +1967,10 @@ }, { "BriefDescription": "Request Ownership : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1695,8 +1980,10 @@ }, { "BriefDescription": "Request Ownership : Issuing final read or wri= te of line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1706,8 +1993,10 @@ }, { "BriefDescription": "Request Ownership : Passing data to be writte= n", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1717,8 +2006,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Passing data= to be written", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1728,8 +2019,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Issuing fina= l read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1738,8 +2031,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Request Owne= rship", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1749,8 +2044,10 @@ }, { "BriefDescription": "Processing response from IOMMU : Writing line= ", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1760,8 +2057,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1771,8 +2070,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1782,8 +2083,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1793,8 +2096,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x00FF", @@ -1804,6 +2109,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1815,6 +2121,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1826,6 +2133,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1837,6 +2145,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1848,6 +2157,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1859,6 +2169,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1870,6 +2181,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1881,6 +2193,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1892,6 +2205,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1903,6 +2217,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1914,6 +2229,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1925,6 +2241,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1936,6 +2253,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1947,6 +2265,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1958,6 +2277,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1969,6 +2289,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1980,8 +2301,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -1991,8 +2314,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -2002,8 +2327,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -2013,8 +2340,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -2024,8 +2353,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -2035,8 +2366,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -2046,8 +2379,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -2057,8 +2392,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -2068,6 +2405,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -2079,6 +2417,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -2090,6 +2429,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -2101,6 +2441,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -2112,6 +2453,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -2123,6 +2465,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -2134,6 +2477,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -2145,6 +2489,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -2156,6 +2501,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -2167,6 +2513,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -2178,6 +2525,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -2189,6 +2537,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -2200,6 +2549,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -2211,6 +2561,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -2222,6 +2573,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -2233,6 +2585,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -2244,6 +2597,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -2255,6 +2609,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -2266,6 +2621,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -2277,6 +2633,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -2288,6 +2645,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -2299,6 +2657,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -2310,6 +2669,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -2321,6 +2681,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -2332,8 +2693,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0001", @@ -2343,8 +2706,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0002", @@ -2354,8 +2719,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0004", @@ -2365,8 +2732,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0008", @@ -2376,8 +2745,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0010", @@ -2387,8 +2758,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0020", @@ -2398,8 +2771,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0040", @@ -2409,8 +2784,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0080", @@ -2420,6 +2797,7 @@ }, { "BriefDescription": "M2P Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", @@ -2428,6 +2806,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", @@ -2435,8 +2814,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -2444,8 +2825,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -2453,8 +2836,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x1", @@ -2462,8 +2847,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x2", @@ -2471,8 +2858,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x4", @@ -2480,8 +2869,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x8", @@ -2489,8 +2880,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", @@ -2498,8 +2891,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", @@ -2507,8 +2902,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", "UMask": "0x8", @@ -2516,8 +2913,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", "UMask": "0x10", @@ -2525,8 +2924,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", "UMask": "0x20", @@ -2534,8 +2935,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x1", @@ -2543,8 +2946,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x2", @@ -2552,8 +2957,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x4", @@ -2561,8 +2968,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x8", @@ -2570,8 +2979,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", "UMask": "0x10", @@ -2579,8 +2990,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", "UMask": "0x20", @@ -2588,896 +3001,1120 @@ }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 0 : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - DRS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Dedicated P2P Credit Taken - 1 : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2P_REMOTE_DED_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI0 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI1 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Dedicated Credits Returned : UPI2 = - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2P_REMOTE_P2P_DED_RETURNED.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI0 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 0 : UPI1 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - D= RS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CB", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Taken - 1 : UPI2 - N= CS", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_TAKEN_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 0 : UPI= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_0.UPI1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - DRS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_DRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Remote Shared P2P Credit - 1 : UPI= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_WAIT_1.UPI2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x80", @@ -3485,8 +4122,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x1", @@ -3494,8 +4133,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x2", @@ -3503,8 +4144,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x4", @@ -3512,8 +4155,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x20", @@ -3521,8 +4166,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x40", @@ -3530,8 +4177,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x8", @@ -3539,8 +4188,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x10", @@ -3548,8 +4199,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x80", @@ -3557,8 +4210,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x1", @@ -3566,8 +4221,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x2", @@ -3575,8 +4232,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x4", @@ -3584,8 +4243,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x20", @@ -3593,8 +4254,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x40", @@ -3602,8 +4265,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x8", @@ -3611,8 +4276,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.UPI_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x10", @@ -3620,24 +4287,30 @@ }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PMM", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3647,8 +4320,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.PMM_BLOCK_1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3658,8 +4333,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3669,8 +4346,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.PMM_DISTRESS_1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.js= on b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json index 3ff9e9b722c8..aa06088dd26f 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2HBM_CLOCKTICKS", "PerPkg": "1", @@ -8,6 +9,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2HBM_CMS_CLOCKTICKS", "PerPkg": "1", @@ -15,16 +17,20 @@ }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled : Non Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_DIRSTATE.NON_CISGRES= S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of time non cisgress D2C w= as not honoured by egress due to directory state constraints", "UMask": "0x2", @@ -32,47 +38,59 @@ }, { "BriefDescription": "Counts the time when FM didn't do d2c for fil= l reads (cross tile case)", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2HBM_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden : Cisgress", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2HBM_DIRECT2CORE_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Number of reads in which direct to Intel UPI = transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_CREDITS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when direct to Intel UPI was disabled", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2HBM" }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Cisgres= s D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.CISGRESS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -82,8 +100,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -93,8 +113,10 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Non Cis= gress D2U Ignored", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2HBM_DIRECT2UPI_NOT_TAKEN_DIRSTATE.NON_CISGRESS= ", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -104,86 +126,107 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Number of times a direct to UPI transaction w= as overridden.", + "Counter": "0,1,2,3", "EventCode": "0x1c", "EventName": "UNC_M2HBM_DIRECT2UPI_TXN_OVERRIDE.CISGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1d", "EventName": "UNC_M2HBM_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -193,6 +236,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -202,6 +246,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -211,6 +256,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2HBM_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -220,86 +266,107 @@ }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1e", "EventName": "UNC_M2HBM_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x320", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -308,8 +375,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -319,8 +388,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_I_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -330,8 +401,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -341,8 +414,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.A_TO_S_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -352,8 +427,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -363,24 +440,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -390,8 +473,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_A_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -401,8 +486,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -412,8 +499,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.I_TO_S_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -423,8 +512,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -434,24 +525,30 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "M2HBM" }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -461,8 +558,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_A_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -472,8 +571,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_HIT_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -483,8 +584,10 @@ }, { "BriefDescription": "Multi-socket cacheline Directory Updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2HBM_DIRECTORY_UPDATE.S_TO_I_MISS_NON_PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -494,64 +597,80 @@ }, { "BriefDescription": "Count distress signalled on AkAd cmp message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on any packet type", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on Bl Cmp message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.BL_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on NM fill write mes= sage", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.CROSSTILE_NMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2Cha message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2CHA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2c message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Count distress signalled on D2k message", + "Counter": "0,1,2,3", "EventCode": "0x67", "EventName": "UNC_M2HBM_DISTRESS.D2UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x80000004", @@ -559,8 +678,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2HBM_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x80000001", @@ -568,8 +689,10 @@ }, { "BriefDescription": "Count when Starve Glocab counter is at 7", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2HBM_IGR_STARVE_WINNER.MASK7", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -578,32 +701,40 @@ }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x304", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -612,24 +743,30 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH0_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -638,24 +775,30 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x201", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_ALL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -664,24 +807,30 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.CH1_NORMAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -690,64 +839,80 @@ }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x340", "Unit": "M2HBM" }, { "BriefDescription": "Critical Priority - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x302", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_READS.NORMAL", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2HBM_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x301", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1810", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x810", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x801", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x802", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -756,15 +921,19 @@ }, { "BriefDescription": "From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -773,16 +942,20 @@ }, { "BriefDescription": "ISOCH Full Line - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -790,8 +963,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -799,8 +974,10 @@ }, { "BriefDescription": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -809,40 +986,50 @@ }, { "BriefDescription": "ISOCH Partial - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1010", "Unit": "M2HBM" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1001", "Unit": "M2HBM" }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1002", "Unit": "M2HBM" }, { "BriefDescription": "All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_ALL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -851,15 +1038,19 @@ }, { "BriefDescription": "From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Full Line Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -868,16 +1059,20 @@ }, { "BriefDescription": "ISOCH Full Line - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1004", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -885,8 +1080,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -894,8 +1091,10 @@ }, { "BriefDescription": "Partial Non-ISOCH - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -904,39 +1103,49 @@ }, { "BriefDescription": "ISOCH Partial - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1008", "Unit": "M2HBM" }, { "BriefDescription": "From TGR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1801", "Unit": "M2HBM" }, { "BriefDescription": "ISOCH Full Line - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1804", "Unit": "M2HBM" }, { "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.NI", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -944,8 +1153,10 @@ }, { "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.NI_MISS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -953,159 +1164,199 @@ }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1802", "Unit": "M2HBM" }, { "BriefDescription": "ISOCH Partial - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2HBM_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1808", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x5c", "EventName": "UNC_M2HBM_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": "Data Prefetches Dropped", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2HBM" }, { "BriefDescription": ": UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": ": XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.RD_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_MERGED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2HBM" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x5e", "EventName": "UNC_M2HBM_PREFCAM_DEMAND_NO_MERGE.WR_SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.UPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2HBM_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Prefetch CAM Inserts : XPT -All Channels", "UMask": "0x5", @@ -1113,80 +1364,100 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2HBM_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "All Channels", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5f", "EventName": "UNC_M2HBM_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2HBM_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2HBM_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1194,8 +1465,10 @@ }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2HBM_RxC_AD.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1204,23 +1477,29 @@ }, { "BriefDescription": "AD Ingress (from CMS) : AD Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2HBM_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2HBM_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2HBM_RxC_BL.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1230,8 +1509,10 @@ }, { "BriefDescription": "BL Ingress (from CMS) : BL Ingress (from CMS)= Allocations", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2HBM_RxC_BL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts anytime a BL packet is added to Ingre= ss", "UMask": "0x1", @@ -1239,61 +1520,77 @@ }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M2HBM_RxC_BL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "UNC_M2HBM_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_M2HBM_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2HBM_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2HBM_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Alloc= ations", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2HBM_TxC_AD.INSERTS", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1303,8 +1600,10 @@ }, { "BriefDescription": "AD Egress (to CMS) : AD Egress (to CMS) Alloc= ations", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2HBM_TxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts anytime a AD packet is added to Egres= s", "UMask": "0x1", @@ -1312,15 +1611,19 @@ }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "UNC_M2HBM_TxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) : Inserts - CMS0 - Near Si= de", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS0", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1330,8 +1633,10 @@ }, { "BriefDescription": "BL Egress (to CMS) : Inserts - CMS1 - Far Sid= e", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UNC_M2HBM_TxC_BL.INSERTS_CMS1", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -1341,160 +1646,200 @@ }, { "BriefDescription": "BL Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "BL Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2HBM_TxC_BL_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2HBM_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2HBM_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : = Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Regular : = Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2HBM_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : = Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "M2M and iMC WPQ Cycles w/Credits - Special : = Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2HBM_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2HBM_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4d", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "UNC_M2HBM_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2HBM" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2HBM_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2HBM" }, { "BriefDescription": "Activate due to read, write, underfill, or by= pass", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0xff", @@ -1502,8 +1847,10 @@ }, { "BriefDescription": "Activate due to read", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x11", @@ -1511,8 +1858,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Read in = PCH0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x1", @@ -1520,8 +1869,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Read in = PCH1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x10", @@ -1529,8 +1880,10 @@ }, { "BriefDescription": "HBM Activate Count : Underfill Read transacti= on on Page Empty or Page Miss", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x44", @@ -1538,8 +1891,10 @@ }, { "BriefDescription": "HBM Activate Count", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x4", @@ -1547,8 +1902,10 @@ }, { "BriefDescription": "HBM Activate Count", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x40", @@ -1556,8 +1913,10 @@ }, { "BriefDescription": "Activate due to write", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x22", @@ -1565,8 +1924,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Write in= PCH0", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x2", @@ -1574,8 +1935,10 @@ }, { "BriefDescription": "HBM Activate Count : Activate due to Write in= PCH1", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_MCHBM_ACT_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Activate commands s= ent on this channel. Activate commands are issued to open up a page on the= HBM devices so that it can be read or written to with a CAS. One can calc= ulate the number of Page Misses by subtracting the number of Page Miss prec= harges from the number of Activates.", "UMask": "0x20", @@ -1583,16 +1946,20 @@ }, { "BriefDescription": "All CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xff", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HBM RD_CAS and WR_CAS Commands", "UMask": "0x40", @@ -1600,8 +1967,10 @@ }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HBM RD_CAS and WR_CAS Commands", "UMask": "0x80", @@ -1609,134 +1978,167 @@ }, { "BriefDescription": "Read CAS commands issued (regular and underfi= ll)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xcf", "Unit": "MCHBM" }, { "BriefDescription": "Regular read CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "MCHBM" }, { "BriefDescription": "Underfill read CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "MCHBM" }, { "BriefDescription": "Regular read CAS commands issued (does not in= clude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "MCHBM" }, { "BriefDescription": "Underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf0", "Unit": "MCHBM" }, { "BriefDescription": "HBM RD_CAS and WR_CAS Commands. : HBM WR_CAS = commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS commands with precharge", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_MCHBM_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "MCHBM" }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "MCHBM" }, { "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "MCHBM" }, { "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pse= udochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "MCHBM" }, { "BriefDescription": "Underfill Read CAS Command in Interleaved Mod= e (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "MCHBM" }, { "BriefDescription": "Underfill Read CAS Command in Regular Mode (6= 4B) in Pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "MCHBM" }, { "BriefDescription": "Write CAS Command in Regular Mode (64B) in Ps= eudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_MCHBM_CAS_ISSUED_REQ_LEN.WR_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "MCHBM" }, { "BriefDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_MCHBM_CLOCKTICKS", "PerPkg": "1", @@ -1745,8 +2147,10 @@ }, { "BriefDescription": "HBM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PREALL.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "UMask": "0x1", @@ -1754,8 +2158,10 @@ }, { "BriefDescription": "HBM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PREALL.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "UMask": "0x2", @@ -1763,8 +2169,10 @@ }, { "BriefDescription": "All Precharge Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_MCHBM_HBM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Precharge All Commands: Counts the number of= times that the precharge all command was sent.", "UMask": "0x3", @@ -1772,15 +2180,19 @@ }, { "BriefDescription": "IMC Clockticks at HCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_MCHBM_HCLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "All precharge events", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0xff", @@ -1788,8 +2200,10 @@ }, { "BriefDescription": "Precharge from MC page table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x88", @@ -1797,8 +2211,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharges from Pag= e Table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Equivalent to PAGE_EMPTY", "UMask": "0x8", @@ -1806,8 +2222,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.PGT_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x80", @@ -1815,8 +2233,10 @@ }, { "BriefDescription": "Precharge due to read on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x11", @@ -1824,8 +2244,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharge due to re= ad", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Precharge from read bank scheduler", "UMask": "0x1", @@ -1833,8 +2255,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x10", @@ -1842,8 +2266,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x44", @@ -1851,8 +2277,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x4", @@ -1860,8 +2288,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x40", @@ -1869,8 +2299,10 @@ }, { "BriefDescription": "Precharge due to write on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x22", @@ -1878,8 +2310,10 @@ }, { "BriefDescription": "HBM Precharge commands. : Precharge due to wr= ite", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel. : Precharge from write bank scheduler", "UMask": "0x2", @@ -1887,8 +2321,10 @@ }, { "BriefDescription": "HBM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_MCHBM_PRE_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of HBM Precharge commands = sent on this channel.", "UMask": "0x20", @@ -1896,46 +2332,58 @@ }, { "BriefDescription": "Counts the number of cycles where the read bu= ffer has greater than UMASK elements. NOTE: Umask must be set to the maxim= um number of elements in the queue (24 entries for SPR).", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_MCHBM_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "Counts the number of inserts into the read bu= ffer.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "MCHBM" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "MCHBM" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_MCHBM_RDB_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "MCHBM" }, { "BriefDescription": "Counts the number of elements in the read buf= fer per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_MCHBM_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "MCHBM" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Allocations: Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", "UMask": "0x1", @@ -1943,8 +2391,10 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_MCHBM_RPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Allocations: Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", "UMask": "0x2", @@ -1952,24 +2402,30 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Occupancy: Accumulates th= e occupancies of the Read Pending Queue each cycle. This can then be used = to calculate both the average occupancy (in conjunction with the number of = cycles not empty) and the average latency (in conjunction with the number o= f allocations). The RPQ is used to schedule reads out to the memory contro= ller and to track the requests. Requests allocate into the RPQ soon after = they enter the memory controller, and need credits for an entry in this buf= fer before being sent from the HA to the iMC. They deallocate after the CAS= command has been issued to memory.", "Unit": "MCHBM" }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_MCHBM_RPQ_OCCUPANCY_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Occupancy: Accumulates th= e occupancies of the Read Pending Queue each cycle. This can then be used = to calculate both the average occupancy (in conjunction with the number of = cycles not empty) and the average latency (in conjunction with the number o= f allocations). The RPQ is used to schedule reads out to the memory contro= ller and to track the requests. Requests allocate into the RPQ soon after = they enter the memory controller, and need credits for an entry in this buf= fer before being sent from the HA to the iMC. They deallocate after the CAS= command has been issued to memory.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Allocations: Counts the = number of allocations into the Write Pending Queue. This can then be used = to calculate the average queuing latency (in conjunction with the WPQ occup= ancy count). The WPQ is used to schedule write out to the memory controlle= r and to track the writes. Requests allocate into the WPQ soon after they = enter the memory controller, and need credits for an entry in this buffer b= efore being sent from the CHA to the iMC. They deallocate after being issu= ed. Write requests themselves are able to complete (from the perspective o= f the rest of the system) as soon they have posted to the iMC.", "UMask": "0x1", @@ -1977,8 +2433,10 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_MCHBM_WPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Allocations: Counts the = number of allocations into the Write Pending Queue. This can then be used = to calculate the average queuing latency (in conjunction with the WPQ occup= ancy count). The WPQ is used to schedule write out to the memory controlle= r and to track the writes. Requests allocate into the WPQ soon after they = enter the memory controller, and need credits for an entry in this buffer b= efore being sent from the CHA to the iMC. They deallocate after being issu= ed. Write requests themselves are able to complete (from the perspective o= f the rest of the system) as soon they have posted to the iMC.", "UMask": "0x2", @@ -1986,24 +2444,30 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Occupancy: Accumulates t= he occupancies of the Write Pending Queue each cycle. This can then be use= d to calculate both the average queue occupancy (in conjunction with the nu= mber of cycles not empty) and the average latency (in conjunction with the = number of allocations). The WPQ is used to schedule write out to the memor= y controller and to track the writes. Requests allocate into the WPQ soon = after they enter the memory controller, and need credits for an entry in th= is buffer before being sent from the HA to the iMC. They deallocate after = being issued to memory. Write requests themselves are able to complete (fr= om the perspective of the rest of the system) as soon they have posted to t= he iMC. This is not to be confused with actually performing the write. Th= erefore, the average latency for this queue is actually not useful for deco= nstruction intermediate write latencies. So, we provide filtering based on= if the request has posted or not. By using the not posted filter, we can = track how long writes spent in the iMC before completions were sent to the = HA. The posted filter, on the other hand, provides information about how m= uch queueing is actually happening in the iMC for writes before they are ac= tually issued to memory. High average occupancies will generally coincide = with high write major mode counts.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_MCHBM_WPQ_OCCUPANCY_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Occupancy: Accumulates t= he occupancies of the Write Pending Queue each cycle. This can then be use= d to calculate both the average queue occupancy (in conjunction with the nu= mber of cycles not empty) and the average latency (in conjunction with the = number of allocations). The WPQ is used to schedule write out to the memor= y controller and to track the writes. Requests allocate into the WPQ soon = after they enter the memory controller, and need credits for an entry in th= is buffer before being sent from the HA to the iMC. They deallocate after = being issued to memory. Write requests themselves are able to complete (fr= om the perspective of the rest of the system) as soon they have posted to t= he iMC. This is not to be confused with actually performing the write. Th= erefore, the average latency for this queue is actually not useful for deco= nstruction intermediate write latencies. So, we provide filtering based on= if the request has posted or not. By using the not posted filter, we can = track how long writes spent in the iMC before completions were sent to the = HA. The posted filter, on the other hand, provides information about how m= uch queueing is actually happening in the iMC for writes before they are ac= tually issued to memory. High average occupancies will generally coincide = with high write major mode counts.", "Unit": "MCHBM" }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2012,8 +2476,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -2021,8 +2487,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_MCHBM_WPQ_READ_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -2030,8 +2498,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2040,8 +2510,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -2049,8 +2521,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_MCHBM_WPQ_WRITE_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match: Counts the nu= mber of times a request hits in the WPQ (write-pending queue). The iMC all= ows writes and reads to pass up other writes to different addresses. Befor= e a read or a write is issued, it will first CAM the WPQ to see if there is= a write pending to that address. When reads hit, they are able to directl= y pull their data from the WPQ instead of going to memory. Writes that hit= will overwrite the existing data. Partial writes that hit will not need t= o do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -2058,6 +2532,7 @@ }, { "BriefDescription": "Activate due to read, write, underfill, or by= pass", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -2067,6 +2542,7 @@ }, { "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -2076,8 +2552,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Ch= annel 0 : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x40", @@ -2085,8 +2563,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Pseudo Ch= annel 1 : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x80", @@ -2094,6 +2574,7 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -2103,8 +2584,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xc2", @@ -2112,8 +2595,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xc8", @@ -2121,8 +2606,10 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/out auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the t= otal number or DRAM Read CAS commands issued on this channel. This include= s both regular RD CAS commands as well as those with implicit Precharge. = We do not filter based on major mode, as RD_CAS is not issued during WMM (w= ith the exception of underfills).", "UMask": "0xc1", @@ -2130,8 +2617,10 @@ }, { "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : Underfill= Read Issued : DRAM RD_CAS and WR_CAS Commands", "UMask": "0xc4", @@ -2139,6 +2628,7 @@ }, { "BriefDescription": "All DRAM write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -2148,8 +2638,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0xd0", @@ -2157,8 +2649,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0xe0", @@ -2166,70 +2660,87 @@ }, { "BriefDescription": "Pseudo Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Pseudo Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Read CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc8", "Unit": "iMC" }, { "BriefDescription": "Read CAS Command in Regular Mode (64B) in Pse= udochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc1", "Unit": "iMC" }, { "BriefDescription": "Underfill Read CAS Command in Interleaved Mod= e (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "iMC" }, { "BriefDescription": "Underfill Read CAS Command in Regular Mode (6= 4B) in Pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.RD_UFILL_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc2", "Unit": "iMC" }, { "BriefDescription": "Write CAS Command in Interleaved Mode (32B)", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_32B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "iMC" }, { "BriefDescription": "Write CAS Command in Regular Mode (64B) in Ps= eudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_ISSUED_REQ_LEN.WR_64B", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc4", "Unit": "iMC" }, { "BriefDescription": "IMC Clockticks at DCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -2239,8 +2750,10 @@ }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "UMask": "0x3", @@ -2248,6 +2761,7 @@ }, { "BriefDescription": "IMC Clockticks at HCLK frequency", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", @@ -2256,30 +2770,37 @@ }, { "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.TOTAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M_PCLS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "PMM Read Pending Queue inserts", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M_PMM_RPQ_INSERTS", "PerPkg": "1", @@ -2288,6 +2809,7 @@ }, { "BriefDescription": "PMM Read Pending Queue occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH0", "PerPkg": "1", @@ -2297,6 +2819,7 @@ }, { "BriefDescription": "PMM Read Pending Queue occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.ALL_SCH1", "PerPkg": "1", @@ -2306,8 +2829,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x10", @@ -2315,8 +2840,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.GNT_WAIT_SCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM Read Pending Queue Occupancy : Accumulat= es the per cycle occupancy of the PMM Read Pending Queue.", "UMask": "0x20", @@ -2324,8 +2851,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the per cycle occupancy of the P= MM Read Pending Queue.", "UMask": "0x4", @@ -2333,8 +2862,10 @@ }, { "BriefDescription": "PMM Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M_PMM_RPQ_OCCUPANCY.NO_GNT_SCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the per cycle occupancy of the P= MM Read Pending Queue.", "UMask": "0x8", @@ -2342,13 +2873,16 @@ }, { "BriefDescription": "PMM (for IXP) Write Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M_PMM_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "PMM Write Pending Queue inserts", + "Counter": "0,1,2,3", "EventCode": "0xe7", "EventName": "UNC_M_PMM_WPQ_INSERTS", "PerPkg": "1", @@ -2357,6 +2891,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL", "PerPkg": "1", @@ -2366,6 +2901,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH0", "PerPkg": "1", @@ -2375,6 +2911,7 @@ }, { "BriefDescription": "PMM Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.ALL_SCH1", "PerPkg": "1", @@ -2384,8 +2921,10 @@ }, { "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.CAS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy = : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP= DIMM.", "UMask": "0xc", @@ -2393,8 +2932,10 @@ }, { "BriefDescription": "PMM (for IXP) Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M_PMM_WPQ_OCCUPANCY.PWR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PMM (for IXP) Write Pending Queue Occupancy = : Accumulates the per cycle occupancy of the Write Pending Queue to the IXP= DIMM.", "UMask": "0x30", @@ -2402,16 +2943,20 @@ }, { "BriefDescription": "Channel PPD Cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Channel PPD Cycles : Number of cycles when a= ll the ranks in the channel are in PPD mode. If IBT=3Doff is enabled, then= this can be used to count those cycles. If it is not enabled, then this c= an count the number of cycles when that could have been taken advantage of.= ", "Unit": "iMC" }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x1", @@ -2419,8 +2964,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x2", @@ -2428,8 +2975,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x4", @@ -2437,8 +2986,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x8", @@ -2446,8 +2997,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -2455,8 +3008,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -2464,14 +3019,17 @@ }, { "BriefDescription": "Clock-Enabled Self-Refresh", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Clock-Enabled Self-Refresh : Counts the numb= er of cycles when the iMC is in self-refresh and the iMC still has a clock.= This happens in some package C-states. For example, the PCU may ask the = iMC to enter self-refresh even though some of the cores are still processin= g. One use of this is for Monroe technology. Self-refresh is required dur= ing package C3 and C6, but there is no clock in the iMC at this time, so it= is not possible to count these cases.", "Unit": "iMC" }, { "BriefDescription": "Precharge due to read, write, underfill, or P= GT.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -2481,6 +3039,7 @@ }, { "BriefDescription": "DRAM Precharge commands", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -2490,8 +3049,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharges from Pa= ge Table", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharges from P= age Table : Counts the number of DRAM Precharge commands sent on this chann= el. : Equivalent to PAGE_EMPTY", "UMask": "0x8", @@ -2499,8 +3060,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x80", @@ -2508,6 +3071,7 @@ }, { "BriefDescription": "Precharge due to read on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -2517,8 +3081,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to r= ead", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = read : Counts the number of DRAM Precharge commands sent on this channel. := Precharge from read bank scheduler", "UMask": "0x1", @@ -2526,8 +3092,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x10", @@ -2535,8 +3103,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x44", @@ -2544,8 +3114,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x4", @@ -2553,8 +3125,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x40", @@ -2562,6 +3136,7 @@ }, { "BriefDescription": "Precharge due to write on page miss", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -2571,8 +3146,10 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to w= rite", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = write : Counts the number of DRAM Precharge commands sent on this channel. = : Precharge from write bank scheduler", "UMask": "0x2", @@ -2580,8 +3157,10 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Counts the number= of DRAM Precharge commands sent on this channel.", "UMask": "0x20", @@ -2589,21 +3168,26 @@ }, { "BriefDescription": "Counts the number of cycles where the read bu= ffer has greater than UMASK elements. This includes reads to both DDR and = PMEM. NOTE: Umask must be set to the maximum number of elements in the que= ue (24 entries for SPR).", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Counts the number of inserts into the read bu= ffer destined for DDR. Does not count reads destined for PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.PCH0", "PerPkg": "1", @@ -2612,6 +3196,7 @@ }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.PCH1", "PerPkg": "1", @@ -2620,45 +3205,56 @@ }, { "BriefDescription": "Counts the number of cycles where there's at = least one element in the read buffer. This includes reads to both DDR and = PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Counts the number of cycles where there's at = least one element in the read buffer. This includes reads to both DDR and = PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NOT_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "Counts the number of elements in the read buf= fer, including reads to both DDR and PMEM.", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", @@ -2668,6 +3264,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", @@ -2677,6 +3274,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -2685,6 +3283,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -2693,294 +3292,368 @@ }, { "BriefDescription": "Scoreboard accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Write Rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.FM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM read completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NM_RD_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : FM write completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.NM_WR_CMPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Accepts", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.RD_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : Read Rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.RD_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard rejects", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM read completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.WR_ACCEPTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Accesses : NM write completions", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M_SB_ACCESSES.WR_REJECTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Alloc", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.ALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Dealloc", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_TGR_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.FM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": ": Valid", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NM_RD_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read Starved", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.NM_WR_STARVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Reject", + "Counter": "0,1,2,3", "EventCode": "0xd9", "EventName": "UNC_M_SB_CANARY.VLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M_SB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Cycles Not-Empty", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M_SB_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Reads", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Inserts : Writes", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M_SB_INSERTS.WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Block region writes", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.BLOCK_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Persistent Mem writes", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.PMM_WRS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Occupancy : Reads", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M_SB_OCCUPANCY.RDS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Inserts : PMM", + "Counter": "0,1,2,3", "EventCode": "0xda", "EventName": "UNC_M_SB_PREF_INSERTS.PMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : DDR4", + "Counter": "0,1,2,3", "EventCode": "0xdb", "EventName": "UNC_M_SB_PREF_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Scoreboard Prefetch Occupancy : Persistent Me= m", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UNC_M_SB_PREF_OCCUPANCY.PMM", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -2989,230 +3662,287 @@ }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.CANARY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.DDR_EARLY_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : FM r= equests rejected due to full address conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.FM_ADDR_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : NM r= equests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.NM_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Number of Scoreboard Requests Rejected : Patr= ol requests rejected due to set conflict", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M_SB_REJECT.PATROL_SET_CNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M_SB_STRV_ALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write - Set", + "Counter": "0,1,2,3", "EventCode": "0xde", "EventName": "UNC_M_SB_STRV_DEALLOC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read - Clear", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": ": Far Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.FM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Read", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NM_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": ": Near Mem Write", + "Counter": "0,1,2,3", "EventCode": "0xd8", "EventName": "UNC_M_SB_STRV_OCC.NM_WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.DDR4_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.DDR4_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.NEW", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.NEW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.OCC", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.OCC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM0_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM0_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM1_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM1_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.PMM2_CMP", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.PMM2_CMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_HIT", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.RD_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "UNC_M_SB_TAGGED.RD_MISS", + "Counter": "0,1,2,3", "EventCode": "0xdd", "EventName": "UNC_M_SB_TAGGED.RD_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "2LM Tag check hit in near memory cache (DDR4)= ", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.HIT", "PerPkg": "1", @@ -3221,6 +3951,7 @@ }, { "BriefDescription": "2LM Tag check miss, no data at this line", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.MISS_CLEAN", "PerPkg": "1", @@ -3229,6 +3960,7 @@ }, { "BriefDescription": "2LM Tag check miss, existing data may be evic= ted to PMM", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.MISS_DIRTY", "PerPkg": "1", @@ -3237,6 +3969,7 @@ }, { "BriefDescription": "2LM Tag check hit due to memory read", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.NM_RD_HIT", "PerPkg": "1", @@ -3245,6 +3978,7 @@ }, { "BriefDescription": "2LM Tag check hit due to memory write", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M_TAGCHK.NM_WR_HIT", "PerPkg": "1", @@ -3253,6 +3987,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", @@ -3262,6 +3997,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", @@ -3271,6 +4007,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -3279,6 +4016,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -3287,8 +4025,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", @@ -3297,8 +4037,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", + "Experimental": "1", "FCMask": "0x00000000", "PerPkg": "1", "PortMask": "0x00000000", diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.jso= n b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json index 8948e85074f0..9482ddaea4d1 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCU PCLK Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", @@ -9,187 +10,235 @@ }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2f", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2a", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2b", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2d", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C0", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C0 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C3", + "Counter": "0,1,2,3", "EventCode": "0x36", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C3 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C6", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_P_POWER_STATE_OCCUPANCY_CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C6 : This is an occupancy= event that tracks the number of cores that are in the chosen C-State. It = can be used by itself to get the average number of cores in that C-state wi= th thresholding to generate histograms, or with other PCU events and occupa= ncy triggering to capture other details.", "Unit": "PCU" }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0x0a", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" diff --git a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.j= son b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json index a1e3b8d2ebe7..609a9549cbf3 100644 --- a/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sapphirerapids/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. 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charset="utf-8" Update events from v1.02 to v1.04. Add TMA metrics v4.8. Bring in the event updates v1.04: https://github.com/intel/perfmon/commit/0a9546cdf63c8b07f5c33ebf6fe49e6ebec= 89f86 v1.03: https://github.com/intel/perfmon/commit/c7dd26ce67ca4477d40fb4b55b6baa0584b= 3e5d6 The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ New events are: FP_INST_RETIRED.128B_DP, FP_INST_RETIRED.128B_SP, FP_INST_RETIRED.256B_DP, FP_INST_RETIRED.32B_SP, FP_INST_RETIRED.64B_DP, OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM, OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD, OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM, OCR.STREAMING_WR.ANY_RESPONSE, UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL, UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE, UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL, UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE, UNC_CHA_TOR_INSERTS.IO_MISS, UNC_CHA_TOR_INSERTS.IO_MISS_ITOM, UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR, UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL, UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE, UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA, UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../arch/x86/sierraforest/cache.json | 97 +- .../arch/x86/sierraforest/counter.json | 77 ++ .../arch/x86/sierraforest/floating-point.json | 54 +- .../arch/x86/sierraforest/frontend.json | 5 +- .../arch/x86/sierraforest/memory.json | 13 +- .../arch/x86/sierraforest/metricgroups.json | 23 + .../arch/x86/sierraforest/other.json | 15 +- .../arch/x86/sierraforest/pipeline.json | 97 +- .../arch/x86/sierraforest/srf-metrics.json | 927 ++++++++++++++++++ .../arch/x86/sierraforest/uncore-cache.json | 549 ++++++++++- .../arch/x86/sierraforest/uncore-cxl.json | 21 + .../x86/sierraforest/uncore-interconnect.json | 267 +++++ .../arch/x86/sierraforest/uncore-io.json | 267 +++++ .../arch/x86/sierraforest/uncore-memory.json | 66 ++ .../arch/x86/sierraforest/uncore-power.json | 1 + .../arch/x86/sierraforest/virtual-memory.json | 17 + 17 files changed, 2405 insertions(+), 93 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/counter.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/metricgroup= s.json create mode 100644 tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics= .json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index fb83c9a1bc5d..30a3966d02b7 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -27,7 +27,7 @@ GenuineIntel-6-2E,v4,nehalemex,core GenuineIntel-6-A7,v1.03,rocketlake,core GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.23,sapphirerapids,core -GenuineIntel-6-AF,v1.02,sierraforest,core +GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core GenuineIntel-6-55-[01234],v1.33,skylakex,core diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json b/tools= /perf/pmu-events/arch/x86/sierraforest/cache.json index f937ba0e50e1..04802e254e51 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/cache.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/cache.json @@ -1,22 +1,25 @@ [ { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", - "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= core has access to an L3 cache, the LLC is the L3 cache, otherwise it is t= he L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", - "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", + "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = core has access to an L3 cache, the LLC is the L3 cache, otherwise it is th= e L2 cache. Counts on a per core basis.", "SampleAfterValue": "200003", "UMask": "0x4f" }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an instruction cache or TLB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.ALL", "SampleAfterValue": "1000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -32,6 +36,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_HIT", "SampleAfterValue": "1000003", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an icache or itlb miss which missed all the caches.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x35", "EventName": "MEM_BOUND_STALLS_IFETCH.LLC_MISS", "SampleAfterValue": "1000003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to an L1 demand load miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.ALL", "SampleAfterValue": "1000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT", "PublicDescription": "Counts the number of cycles a core is stalle= d due to a demand load which hit in the L2 cache.", @@ -61,6 +69,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which hit in the LLC.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_HIT", "SampleAfterValue": "1000003", @@ -68,6 +77,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles when the= core is stalled due to a demand load miss which missed all the local cache= s.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS", "SampleAfterValue": "1000003", @@ -75,62 +85,63 @@ }, { "BriefDescription": "Counts the number of load ops retired that mi= ss the L3 cache and hit in DRAM", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd3", "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of load ops retired that hi= t the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L1 data cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x40" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of load ops retired that mi= ss in the L2 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of load ops retired that hi= t in the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x1c" }, { "BriefDescription": "Counts the number of loads that hit in a writ= e combining buffer (WCB), excluding the first load that caused the WCB to a= llocate.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x20" }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked for any of the following reasons: load buffer, store buffer or RSV fu= ll.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ALL", "SampleAfterValue": "20003", @@ -138,6 +149,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a load buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF", "SampleAfterValue": "20003", @@ -145,6 +157,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to an RSV full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.RSV", "SampleAfterValue": "20003", @@ -152,6 +165,7 @@ }, { "BriefDescription": "Counts the number of cycles that uops are blo= cked due to a store buffer full condition.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x04", "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF", "SampleAfterValue": "20003", @@ -159,179 +173,210 @@ }, { "BriefDescription": "Counts the number of load ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x81" }, { "BriefDescription": "Counts the number of store ops retired.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x82" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_1024", "MSRIndex": "0x3F6", "MSRValue": "0x400", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128", "MSRIndex": "0x3F6", "MSRValue": "0x80", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16", "MSRIndex": "0x3F6", "MSRValue": "0x10", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_2048", "MSRIndex": "0x3F6", "MSRValue": "0x800", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256", "MSRIndex": "0x3F6", "MSRValue": "0x100", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32", "MSRIndex": "0x3F6", "MSRValue": "0x20", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4", "MSRIndex": "0x3F6", "MSRValue": "0x4", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512", "MSRIndex": "0x3F6", "MSRValue": "0x200", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64", "MSRIndex": "0x3F6", "MSRValue": "0x40", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of tagged load uops retired= that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD = - Only counts with PEBS enabled.", + "Counter": "0,1", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8", "MSRIndex": "0x3F6", "MSRValue": "0x8", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x5" }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x21" }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x43" }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x41" }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x42" }, { "BriefDescription": "Counts the number of stores uops retired sam= e as MEM_UOPS_RETIRED.ALL_STORES", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY", - "PEBS": "2", "SampleAfterValue": "1000003", "UMask": "0x6" }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand data reads that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x8003C0001", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10003C0002", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to an icache miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/counter.json b/too= ls/perf/pmu-events/arch/x86/sierraforest/counter.json new file mode 100644 index 000000000000..e57e3bf98b2a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/counter.json @@ -0,0 +1,77 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "8" + }, + { + "Unit": "B2CMI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IMC", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "B2HOT", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "B2UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "B2CXL", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "CHACMS", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "MDF", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + }, + { + "Unit": "CXLCM", + "CountersNumFixed": "0", + "CountersNumGeneric": 8 + }, + { + "Unit": "CXLDP", + "CountersNumFixed": "0", + "CountersNumGeneric": 4 + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/floating-point.jso= n b/tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json index 00c9a8ae0f53..5266eed969be 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the f= loating point dividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.FPDIV_ACTIVE", @@ -9,48 +10,89 @@ }, { "BriefDescription": "Counts the number of all types of floating po= int operations per uop with all default weighting", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x3" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP64]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.DP", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 32 bit single precision results [This event is alias to FP_F= LOPS_RETIRED.SP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP32", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of floating point operation= s that produce 64 bit double precision results [This event is alias to FP_F= LOPS_RETIRED.DP]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.FP64", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "This event is deprecated. [This event is alia= s to FP_FLOPS_RETIRED.FP32]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc8", "EventName": "FP_FLOPS_RETIRED.SP", - "PEBS": "1", + "SampleAfterValue": "1000003", + "UMask": "0x2" + }, + { + "BriefDescription": "Counts the total number of floating point re= tired instructions.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x8" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 128 bit single precision floating point. This may b= e SSE or AVX.128 operations.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.128B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x4" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a packed 256 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.256B_DP", + "SampleAfterValue": "1000003", + "UMask": "0x20" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 32bit single precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.32B_SP", + "SampleAfterValue": "1000003", + "UMask": "0x1" + }, + { + "BriefDescription": "Counts the number of retired instructions who= se sources are a scalar 64 bit double precision floating point.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xc7", + "EventName": "FP_INST_RETIRED.64B_DP", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -59,9 +101,9 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and sse, including x87 sqrt).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x8" } diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json b/to= ols/perf/pmu-events/arch/x86/sierraforest/frontend.json index 356d36aecc81..7cdf611efb23 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,14 +10,15 @@ }, { "BriefDescription": "Counts the number of instructions retired tha= t were tagged because empty issue slots were seen before the uop due to ITL= B miss", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x10" }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "SampleAfterValue": "200003", @@ -24,6 +26,7 @@ }, { "BriefDescription": "Counts every time the code stream enters into= a new cache line by walking sequential from the previous line or being red= irected by a jump and the instruction cache registers bytes are not present= . -", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "SampleAfterValue": "200003", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/memory.json b/tool= s/perf/pmu-events/arch/x86/sierraforest/memory.json index e0ce2decc805..22d23077618e 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/memory.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to any number of reasons, incl= uding an L1 miss, WCB full, pagewalk, store address block or store data blo= ck, on a load that retires.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ANY_AT_RET", "SampleAfterValue": "1000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer is stalled due to a core bound stall includin= g a store address match, a DTLB miss or a page walk that detains the load f= rom retiring.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_BOUND_AT_RET", "SampleAfterValue": "1000003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DL1 = miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.L1_MISS_AT_RET", "SampleAfterValue": "1000003", @@ -22,6 +25,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to other = block cases.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.OTHER_AT_RET", "PublicDescription": "Counts the number of cycles that the head (o= ldest load) of the load buffer and retirement are both stalled due to other= block cases such as pipeline conflicts, fences, etc.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a page= walk.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.PGWALK_AT_RET", "SampleAfterValue": "1000003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a stor= e address match.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.ST_ADDR_AT_RET", "SampleAfterValue": "1000003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -51,22 +58,23 @@ }, { "BriefDescription": "Counts misaligned loads that are 4K page spli= ts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x2" }, { "BriefDescription": "Counts misaligned stores that are 4K page spl= its.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x4" }, { "BriefDescription": "Counts demand data reads that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/metricgroups.json = b/tools/perf/pmu-events/arch/x86/sierraforest/metricgroups.json new file mode 100644 index 000000000000..40984c23a6c9 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/metricgroups.json @@ -0,0 +1,23 @@ +{ + "Flops": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Ifetch": "Grouping from Top-down Microarchitecture Analysis Metrics s= preadsheet", + "Load_Store_Miss": "Grouping from Top-down Microarchitecture Analysis = Metrics spreadsheet", + "Mem_Exec": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "Power": "Grouping from Top-down Microarchitecture Analysis Metrics sp= readsheet", + "Summary": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", + "TopdownL1": "Metrics for top-down breakdown at level 1", + "TopdownL2": "Metrics for top-down breakdown at level 2", + "TopdownL3": "Metrics for top-down breakdown at level 3", + "load_store_bound": "Grouping from Top-down Microarchitecture Analysis= Metrics spreadsheet", + "tma_L1_group": "Metrics for top-down breakdown at level 1", + "tma_L2_group": "Metrics for top-down breakdown at level 2", + "tma_L3_group": "Metrics for top-down breakdown at level 3", + "tma_backend_bound_group": "Metrics contributing to tma_backend_bound = category", + "tma_bad_speculation_group": "Metrics contributing to tma_bad_speculat= ion category", + "tma_core_bound_group": "Metrics contributing to tma_core_bound catego= ry", + "tma_frontend_bound_group": "Metrics contributing to tma_frontend_boun= d category", + "tma_ifetch_bandwidth_group": "Metrics contributing to tma_ifetch_band= width category", + "tma_ifetch_latency_group": "Metrics contributing to tma_ifetch_latenc= y category", + "tma_machine_clears_group": "Metrics contributing to tma_machine_clear= s category", + "tma_resource_bound_group": "Metrics contributing to tma_resource_boun= d category" +} diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/other.json b/tools= /perf/pmu-events/arch/x86/sierraforest/other.json index 70a9da7e97df..28f9a4c3ea84 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/other.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/other.json @@ -1,15 +1,16 @@ [ { "BriefDescription": "This event is deprecated. [This event is alia= s to MISC_RETIRED.LBR_INSERTS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xe4", "EventName": "LBR_INSERTS.ANY", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts demand data reads that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -19,6 +20,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -26,8 +28,19 @@ "SampleAfterValue": "100003", "UMask": "0x1" }, + { + "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3,4,5,6,7", + "EventCode": "0xB7", + "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", + "MSRIndex": "0x1a6,0x1a7", + "MSRValue": "0x10800", + "SampleAfterValue": "100003", + "UMask": "0x1" + }, { "BriefDescription": "Counts the number of issue slots in a UMWAIT = or TPAUSE instruction where no uop issues due to the instruction putting th= e CPU into the C0.1 activity state.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x75", "EventName": "SERIALIZATION.C01_MS_SCB", "SampleAfterValue": "200003", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json b/to= ols/perf/pmu-events/arch/x86/sierraforest/pipeline.json index 90292dc03d33..b67c0c89054d 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles when any of the d= ividers are active.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xcd", "EventName": "ARITH.DIV_ACTIVE", @@ -9,153 +10,157 @@ }, { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of instructions in w= hich the instruction pointer (IP) of the processor is resteered due to a br= anch instruction and the branch instruction successfully retires. All bran= ch type instructions are accounted for.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xbf" }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "This event is deprecated. Refer to new event = BR_INST_RETIRED.INDIRECT_CALL", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf9" }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", - "PEBS": "1", "PublicDescription": "Counts the total number of mispredicted bran= ch instructions retired. All branch type instructions are accounted for. = Prediction of the branch target address enables the processor to begin exec= uting instructions before the non-speculative execution path is known. The = branch prediction unit (BPU) predicts the target address based on the instr= uction pointer (IP) of the branch and on the execution path through which e= xecution reached this IP. A branch misprediction occurs when the predict= ion is wrong, and results in discarding all instructions executed in the sp= eculative path and re-fetching from the correct path.", "SampleAfterValue": "200003" }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x7e" }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfe" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xeb" }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xfb" }, { "BriefDescription": "Counts the number of mispredicted near taken = branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0x80" }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", - "PEBS": "1", "SampleAfterValue": "200003", "UMask": "0xf7" }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.THREAD_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "SampleAfterValue": "2000003", "UMask": "0x3" }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -164,18 +169,21 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es [This event is alias to CPU_CLK_UNHALTED.CORE_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000003" }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "SampleAfterValue": "2000003", @@ -183,37 +191,38 @@ }, { "BriefDescription": "Counts the number of instructions retired", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", - "PEBS": "1", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.ADDRESS_ALIAS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x4" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x2" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -221,6 +230,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -228,6 +238,7 @@ }, { "BriefDescription": "Counts the number of machine clears that flus= h the pipeline and restart the machine with the use of microcode due to SMC= , MEMORY_ORDERING, FP_ASSISTS, PAGE_FAULT, DISAMBIGUATION, and FPC_VIRTUAL_= TRAP.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SLOW", "SampleAfterValue": "20003", @@ -235,6 +246,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -242,14 +254,15 @@ }, { "BriefDescription": "Counts the number of Last Branch Record (LBR)= entries. Requires LBRs to be enabled and configured in IA32_LBR_CTL. [This= event is alias to LBR_INSERTS.ANY]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xe4", "EventName": "MISC_RETIRED.LBR_INSERTS", - "PEBS": "1", "SampleAfterValue": "1000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL_P]", @@ -257,6 +270,7 @@ }, { "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend because allocation is stalled due to a mispredict= ed jump or a machine clear. [This event is alias to TOPDOWN_BAD_SPECULATION= .ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window, including = relevant microcode flows, and while uops are not yet available in the instr= uction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC.= Also includes the issue slots that were consumed by the backend but were t= hrown away because they were younger than the mispredict or machine clear. = [This event is alias to TOPDOWN_BAD_SPECULATION.ALL]", @@ -264,6 +278,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Fast Nukes such as Memory Ord= ering Machine clears and MRN nukes", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -271,6 +286,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -278,6 +294,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to Branch Mispredict", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -285,6 +302,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to a machine clear (nuke).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.NUKE", "SampleAfterValue": "1000003", @@ -292,12 +310,14 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL_P]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to due to certain allocation rest= rictions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -305,12 +325,14 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to backend stalls [This event is alias to TOPDOWN_BE_BOUND.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL_P", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stall (sche= duler not being able to accept another uop). This could be caused by RSV f= ull or load/store buffer block.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -318,6 +340,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC and FPC RAT stalls - which= can be due to the FIQ and IEC reservation station stall (integer, FP and S= IMD scheduler not being able to accept another uop. )", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -325,6 +348,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to mrbl stall. A 'marble' refers= to a physical register file entry, also known as the physical destination = (PDST).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -332,6 +356,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to ROB full", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -339,6 +364,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to iq/jeu scoreboards or ms scb", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -346,18 +372,21 @@ }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL_= P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of retirement slots not con= sumed due to front end stalls [This event is alias to TOPDOWN_FE_BOUND.ALL]= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL_P", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BAClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "SampleAfterValue": "1000003", @@ -365,6 +394,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTClear", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "SampleAfterValue": "1000003", @@ -372,6 +402,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ms", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -379,6 +410,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -386,6 +418,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to frontend bandwidth restricti= ons due to decode, predecode, cisc, and other limitations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH", "SampleAfterValue": "1000003", @@ -393,6 +426,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to latency related stalls inclu= ding BACLEARs, BTCLEARs, ITLB misses, and ICache misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY", "SampleAfterValue": "1000003", @@ -400,6 +434,7 @@ }, { "BriefDescription": "This event is deprecated. [This event is alia= s to TOPDOWN_FE_BOUND.ITLB_MISS]", + "Counter": "0,1,2,3,4,5,6,7", "Deprecated": "1", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", @@ -408,6 +443,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to itlb miss [This event is ali= as to TOPDOWN_FE_BOUND.ITLB]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB_MISS", "SampleAfterValue": "1000003", @@ -415,6 +451,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend that do not categorize into any oth= er common frontend stall", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -422,27 +459,29 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to predecode wrong", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", "UMask": "0x4" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L_P]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL_P]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL", - "PEBS": "1", "SampleAfterValue": "1000003" }, { - "BriefDescription": "Counts the number of consumed retirement slot= s. Similar to UOPS_RETIRED.ALL [This event is alias to TOPDOWN_RETIRING.AL= L]", + "BriefDescription": "Counts the number of consumed retirement slot= s. [This event is alias to TOPDOWN_RETIRING.ALL]", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x72", "EventName": "TOPDOWN_RETIRING.ALL_P", - "PEBS": "1", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -450,32 +489,32 @@ }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", - "PEBS": "1", "SampleAfterValue": "2000003" }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x10" }, { "BriefDescription": "Counts the number of uops that are from the c= omplex flows issued by the micro-sequencer (MS). This includes uops from f= lows due to complex instructions, faults, assists, and inserted flows.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x1" }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in ms flows", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", - "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" } diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics.json b= /tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics.json new file mode 100644 index 000000000000..b881b1958f11 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/sierraforest/srf-metrics.json @@ -0,0 +1,927 @@ +[ + { + "BriefDescription": "C1 residency percent per core", + "MetricExpr": "cstate_core@c1\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C1_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per core", + "MetricExpr": "cstate_core@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Core_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per module", + "MetricExpr": "cstate_module@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Module_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "C6 residency percent per package", + "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", + "MetricGroup": "Power", + "MetricName": "C6_Pkg_Residency", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles per instruction retired; indicating ho= w much time each executed instruction took; in units of cycles.", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / INST_RETIRED.ANY", + "MetricName": "cpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "CPU operating frequency (in GHz)", + "MetricExpr": "CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC = * #SYSTEM_TSC_FREQ / 1e9", + "MetricName": "cpu_operating_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", + "MetricExpr": "tma_info_system_cpu_utilization", + "MetricName": "cpu_utilization", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte page sizes) caused by demand data loads to the total number of c= ompleted instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRE= D.ANY", + "MetricName": "dtlb_2nd_level_2mb_large_page_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte page sizes) caused by demand data loads to the total number of = completed instructions. This implies it missed in the Data Translation Look= aside Buffer (DTLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data loads to the total number of complete= d instructions", + "MetricExpr": "DTLB_LOAD_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "dtlb_2nd_level_load_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data loads to the total number of complet= ed instructions. This implies it missed in the DTLB and further levels of T= LB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by demand data stores to the total number of complet= ed instructions", + "MetricExpr": "DTLB_STORE_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", + "MetricName": "dtlb_2nd_level_store_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by demand data stores to the total number of comple= ted instructions. This implies it missed in the DTLB and further levels of = TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic contoller (IIO) of IO reads that are initiated by end device controller= s that are requesting memory from the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS * 4 / 1e= 6 / duration_time", + "MetricName": "iio_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth observed by the integrated I/O traf= fic controller (IIO) of IO writes that are initiated by end device controll= ers that are writing memory to the CPU.", + "MetricExpr": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS * 4 / 1= e6 / duration_time", + "MetricName": "iio_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the CPU.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR * 64 / 1e6 / durati= on_time", + "MetricName": "io_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from the local CPU socket.= ", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL * 64 / 1e6 / = duration_time", + "MetricName": "io_bandwidth_read_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO reads that are initiated by e= nd device controllers that are requesting memory from a remote CPU socket.", + "MetricExpr": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE * 64 / 1e6 /= duration_time", + "MetricName": "io_bandwidth_read_remote", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the CPU.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM + UNC_CHA_TOR_INSERTS.= IO_ITOMCACHENEAR) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to the local CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL + UNC_CHA_TOR_IN= SERTS.IO_ITOMCACHENEAR_LOCAL) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_local", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth of IO writes that are initiated by = end device controllers that are writing memory to a remote CPU socket.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE + UNC_CHA_TOR_I= NSERTS.IO_ITOMCACHENEAR_REMOTE) * 64 / 1e6 / duration_time", + "MetricName": "io_bandwidth_write_remote", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total n= umber of completed instructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED_2M_4M / INST_RETIRED.ANY= ", + "MetricName": "itlb_2nd_level_large_page_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= 2 megabyte and 4 megabyte page sizes) caused by a code fetch to the total = number of completed instructions. This implies it missed in the Instruction= Translation Lookaside Buffer (ITLB) and further levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed page walks (for = all page sizes) caused by a code fetch to the total number of completed ins= tructions", + "MetricExpr": "ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY", + "MetricName": "itlb_2nd_level_mpi", + "PublicDescription": "Ratio of number of completed page walks (for= all page sizes) caused by a code fetch to the total number of completed in= structions. This implies it missed in the ITLB (Instruction TLB) and furthe= r levels of TLB.", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= in L1 instruction cache (includes prefetches) to the total number of compl= eted instructions", + "MetricExpr": "ICACHE.MISSES / INST_RETIRED.ANY", + "MetricName": "l1_i_code_read_misses_with_prefetches_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of demand load requests hitti= ng in L1 data cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L1_HIT / INST_RETIRED.ANY", + "MetricName": "l1d_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed demand load requ= ests hitting in L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_HIT / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_hits_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of completed data read reques= t missing L2 cache to the total number of completed instructions", + "MetricExpr": "MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY", + "MetricName": "l2_demand_data_read_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of requests missing L2 cache = (includes code+data+rfo w/ prefetches) to the total number of completed ins= tructions", + "MetricExpr": "LONGEST_LAT_CACHE.REFERENCE / INST_RETIRED.ANY", + "MetricName": "l2_mpi", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_CRD + UNC_CHA_TOR_INSE= RTS.IA_MISS_CRD_PREF) / INST_RETIRED.ANY", + "MetricName": "llc_code_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT + UNC_CHA_TOR_= INSERTS.IA_MISS_DRD_OPT_PREF + UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA) / I= NST_RETIRED.ANY", + "MetricName": "llc_data_read_mpi_demand_plus_prefetch", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Average latency of a last level cache (LLC) d= emand data read miss (read memory access) in nano seconds", + "MetricExpr": "1e9 * (UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT / UNC_= CHA_TOR_INSERTS.IA_MISS_DRD_OPT) / (UNC_CHA_CLOCKTICKS / (source_count(UNC_= CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT) * #num_packages)) * duration_time", + "MetricName": "llc_demand_data_read_miss_latency", + "ScaleUnit": "1ns" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_LOCAL * 64 / 1e6 / duration_= time", + "MetricName": "llc_miss_local_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to local memory.", + "MetricExpr": "UNC_CHA_REQUESTS.WRITES_LOCAL * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_local_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of read requests that miss= the last level cache (LLC) and go to remote memory.", + "MetricExpr": "UNC_CHA_REQUESTS.READS_REMOTE * 64 / 1e6 / duration= _time", + "MetricName": "llc_miss_remote_memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Bandwidth (MB/sec) of write requests that mis= s the last level cache (LLC) and go to remote memory.", + "MetricExpr": "UNC_CHA_REQUESTS.WRITES_REMOTE * 64 / 1e6 / duratio= n_time", + "MetricName": "llc_miss_remote_memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Load operations retired per instruction", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_LOADS / INST_RETIRED.ANY", + "MetricName": "loads_retired_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "DDR memory read bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD)= * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_read", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.RD + UNC_M_CAS_COUNT_SCH1.RD = + UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR) * 64 / 1e6 / duration_= time", + "MetricName": "memory_bandwidth_total", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "DDR memory write bandwidth (MB/sec)", + "MetricExpr": "(UNC_M_CAS_COUNT_SCH0.WR + UNC_M_CAS_COUNT_SCH1.WR)= * 64 / 1e6 / duration_time", + "MetricName": "memory_bandwidth_write", + "ScaleUnit": "1MB/s" + }, + { + "BriefDescription": "Memory read that miss the last level cache (L= LC) addressed to local DRAM as a percentage of total memory read accesses, = does not include LLC prefetches.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL + UNC_CH= A_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL) / (UNC_CHA_TOR_INSERTS.IA_MISS_DR= D_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TOR_= INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_R= EMOTE)", + "MetricName": "numa_reads_addressed_to_local_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Memory reads that miss the last level cache (= LLC) addressed to remote DRAM as a percentage of total memory read accesses= , does not include LLC prefetches.", + "MetricExpr": "(UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_C= HA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE) / (UNC_CHA_TOR_INSERTS.IA_MISS_= DRD_OPT_LOCAL + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL + UNC_CHA_TO= R_INSERTS.IA_MISS_DRD_OPT_REMOTE + UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF= _REMOTE)", + "MetricName": "numa_reads_addressed_to_remote_dram", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of cycles spent in System Manageme= nt Interrupts.", + "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0= else 0)", + "MetricGroup": "smi", + "MetricName": "smi_cycles", + "MetricThreshold": "smi_cycles > 0.1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Number of SMI interrupts.", + "MetricExpr": "msr@smi@", + "MetricGroup": "smi", + "MetricName": "smi_num", + "ScaleUnit": "1SMI#" + }, + { + "BriefDescription": "Store operations retired per instruction", + "MetricExpr": "MEM_UOPS_RETIRED.ALL_STORES / INST_RETIRED.ANY", + "MetricName": "stores_retired_per_instr", + "ScaleUnit": "1per_instr" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to certain allocation restrictions", + "MetricExpr": "tma_core_bound", + "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricName": "tma_allocation_restriction", + "MetricThreshold": "tma_allocation_restriction > 0.1 & (tma_core_b= ound > 0.1 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend due to backend stalls", + "MetricExpr": "TOPDOWN_BE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_backend_bound", + "MetricThreshold": "tma_backend_bound > 0.1", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend due to backend stalls. Note that uops must= be available for consumption in order for this event to count. If a uop is= not available (IQ is empty), this event will not count", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.ALL_P / (6 * CPU_CLK_UNHALT= ED.CORE)", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_bad_speculation", + "MetricThreshold": "tma_bad_speculation > 0.15", + "MetricgroupNoGroup": "TopdownL1", + "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ). Also includes the issue slots that were consumed by the ba= ckend but were thrown away because they were younger than the mispredict or= machine clear.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BACLEARS, which occurs when the Branch T= arget Buffer (BTB) prediction or lack thereof, was corrected by a later bra= nch predictor in the frontend", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_DETECT / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_branch_detect", + "MetricThreshold": "tma_branch_detect > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "PublicDescription": "Counts the number of issue slots that were n= ot delivered by the frontend due to BACLEARS, which occurs when the Branch = Target Buffer (BTB) prediction or lack thereof, was corrected by a later br= anch predictor in the frontend. Includes BACLEARS due to all branch types i= ncluding conditional and unconditional jumps, returns, and indirect branche= s.", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to branch mispredicts", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MISPREDICT / (6 * CPU_CLK_U= NHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_branch_mispredicts", + "MetricThreshold": "tma_branch_mispredicts > 0.05 & tma_bad_specul= ation > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to BTCLEARS, which occurs when the Branch T= arget Buffer (BTB) predicts a taken branch.", + "MetricExpr": "TOPDOWN_FE_BOUND.BRANCH_RESTEER / (6 * CPU_CLK_UNHA= LTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_branch_resteer", + "MetricThreshold": "tma_branch_resteer > 0.05 & (tma_ifetch_latenc= y > 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to the microcode sequencer (MS).", + "MetricExpr": "TOPDOWN_FE_BOUND.CISC / (6 * CPU_CLK_UNHALTED.CORE)= ", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_cisc", + "MetricThreshold": "tma_cisc > 0.05 & (tma_ifetch_bandwidth > 0.1 = & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles due to backend bo= und stalls that are bounded by core restrictions and not attributed to an o= utstanding load or stores, or resource limitation", + "MetricExpr": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS / (6 * CPU_CLK_= UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_core_bound", + "MetricThreshold": "tma_core_bound > 0.1 & tma_backend_bound > 0.1= ", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to decode stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.DECODE / (6 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_decode", + "MetricThreshold": "tma_decode > 0.05 & (tma_ifetch_bandwidth > 0.= 1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that does not require the = use of microcode, classified as a fast nuke, due to memory ordering, memory= disambiguation and memory renaming", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.FASTNUKE / (6 * CPU_CLK_UNH= ALTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_fast_nuke", + "MetricThreshold": "tma_fast_nuke > 0.05 & (tma_machine_clears > 0= .05 & tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to frontend stalls.", + "MetricExpr": "TOPDOWN_FE_BOUND.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_frontend_bound", + "MetricThreshold": "tma_frontend_bound > 0.2", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to instruction cache misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ICACHE / (6 * CPU_CLK_UNHALTED.COR= E)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_icache_misses", + "MetricThreshold": "tma_icache_misses > 0.05 & (tma_ifetch_latency= > 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend bandwidth restrictions due to d= ecode, predecode, cisc, and other limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_BANDWIDTH / (6 * CPU_CLK_= UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_ifetch_bandwidth", + "MetricThreshold": "tma_ifetch_bandwidth > 0.1 & tma_frontend_boun= d > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to frontend latency restrictions due to ica= che misses, itlb misses, branch detection, and resteer limitations.", + "MetricExpr": "TOPDOWN_FE_BOUND.FRONTEND_LATENCY / (6 * CPU_CLK_UN= HALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_frontend_bound_group", + "MetricName": "tma_ifetch_latency", + "MetricThreshold": "tma_ifetch_latency > 0.15 & tma_frontend_bound= > 0.2", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Floating Point (FP) Operatio= n", + "MetricExpr": "INST_RETIRED.ANY / FP_FLOPS_RETIRED.ALL", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipflop" + }, + { + "BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bi= t instruction", + "MetricExpr": "INST_RETIRED.ANY / (FP_INST_RETIRED.128B_DP + FP_IN= ST_RETIRED.128B_SP)", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_avx128" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Double-= Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.64B_DP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_dp" + }, + { + "BriefDescription": "Instructions per FP Arithmetic Scalar Single-= Precision instruction", + "MetricExpr": "INST_RETIRED.ANY / FP_INST_RETIRED.32B_SP", + "MetricGroup": "Flops", + "MetricName": "tma_info_arith_inst_mix_ipfparith_scalar_sp" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "MetricName": "tma_info_bottleneck_%_dtlb_miss_bound_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "MetricGroup": "Ifetch", + "MetricName": "tma_info_bottleneck_%_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "tma_info_bottleneck_load_miss_bound_cycles", + "MetricGroup": "Load_Store_Miss", + "MetricName": "tma_info_bottleneck_%_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "tma_info_bottleneck_mem_exec_bound_cycles", + "MetricGroup": "Mem_Exec", + "MetricName": "tma_info_bottleneck_%_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to a first level data TLB miss", + "MetricExpr": "100 * (LD_HEAD.DTLB_MISS_AT_RET + LD_HEAD.PGWALK_AT= _RET) / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Cycles", + "MetricName": "tma_info_bottleneck_dtlb_miss_bound_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation and retire= ment is stalled by the Frontend Cluster due to an Ifetch Miss, either Icach= e or ITLB Miss", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.ALL / CPU_CLK_UNHALTE= D.CORE", + "MetricGroup": "Cycles;Ifetch", + "MetricName": "tma_info_bottleneck_ifetch_miss_bound_cycles", + "PublicDescription": "Percentage of time that allocation and retir= ement is stalled by the Frontend Cluster due to an Ifetch Miss, either Icac= he or ITLB Miss. See Info.Ifetch_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= due to an L1 miss", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.ALL / CPU_CLK_UNHALTED.= CORE", + "MetricGroup": "Cycles;Load_Store_Miss", + "MetricName": "tma_info_bottleneck_load_miss_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d due to an L1 miss. See Info.Load_Miss_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that retirement is stalled= by the Memory Cluster due to a pipeline stall", + "MetricExpr": "100 * LD_HEAD.ANY_AT_RET / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Cycles;Mem_Exec", + "MetricName": "tma_info_bottleneck_mem_exec_bound_cycles", + "PublicDescription": "Percentage of time that retirement is stalle= d by the Memory Cluster due to a pipeline stall. See Info.Mem_Exec_Bound", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Branch (lower number means h= igher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipbranch" + }, + { + "BriefDescription": "Instruction per (near) call (lower number mea= ns higher occurrence rate)", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL", + "MetricName": "tma_info_br_inst_mix_ipcall" + }, + { + "BriefDescription": "Instructions per Far Branch ( Far Branches ap= ply upon transition from application to operating system, handling interrup= ts, exceptions) [lower number means higher occurrence rate]", + "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u", + "MetricName": "tma_info_br_inst_mix_ipfarbranch" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was not taken", + "MetricExpr": "INST_RETIRED.ANY / (BR_MISP_RETIRED.COND - BR_MISP_= RETIRED.COND_TAKEN)", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_ntaken" + }, + { + "BriefDescription": "Instructions per retired conditional Branch M= isprediction where the branch was taken", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.COND_TAKEN", + "MetricName": "tma_info_br_inst_mix_ipmisp_cond_taken" + }, + { + "BriefDescription": "Instructions per retired indirect call or jum= p Branch Misprediction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.INDIRECT", + "MetricName": "tma_info_br_inst_mix_ipmisp_indirect" + }, + { + "BriefDescription": "Instructions per retired return Branch Mispre= diction", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.RETURN", + "MetricName": "tma_info_br_inst_mix_ipmisp_ret" + }, + { + "BriefDescription": "Instructions per retired Branch Misprediction= ", + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES", + "MetricName": "tma_info_br_inst_mix_ipmispredict" + }, + { + "BriefDescription": "Ratio of all branches which mispredict", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.ALL_= BRANCHES", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_rati= o" + }, + { + "BriefDescription": "Ratio between Mispredicted branches and unkno= wn branches", + "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / BACLEARS.ANY", + "MetricName": "tma_info_br_mispredict_bound_branch_mispredict_to_u= nknown_branch_ratio" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_load_buffer_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_mem_rsv_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "MetricName": "tma_info_buffer_stalls_%_store_buffer_stall_cycles" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to load buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.LD_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_load_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to memory reservation stations full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.RSV / CPU_CLK_UNHALTED.CO= RE", + "MetricName": "tma_info_buffer_stalls_mem_rsv_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of time that allocation is stalled= due to store buffer full", + "MetricExpr": "100 * MEM_SCHEDULER_BLOCK.ST_BUF / CPU_CLK_UNHALTED= .CORE", + "MetricName": "tma_info_buffer_stalls_store_buffer_stall_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Cycles Per Instruction", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / INST_RETIRED.ANY", + "MetricName": "tma_info_core_cpi" + }, + { + "BriefDescription": "Floating Point Operations Per Cycle", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "Flops", + "MetricName": "tma_info_core_flopc" + }, + { + "BriefDescription": "Instructions Per Cycle", + "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.CORE", + "MetricName": "tma_info_core_ipc" + }, + { + "BriefDescription": "Uops Per Instruction", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / INST_RETIRED.ANY", + "MetricName": "tma_info_core_upi" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2h= it", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 2hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3h= it", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3hit" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss subsequently misses in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_MISS / MEM_BOUND_= STALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_%_ifetchmissbound_with_l= 3miss" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.L2_HIT / MEM_BOUND_ST= ALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l2h= it", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of ifetch miss bound stalls, where= the ifetch miss hits in the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_IFETCH.LLC_HIT / MEM_BOUND_S= TALLS_IFETCH.ALL", + "MetricName": "tma_info_ifetch_miss_bound_ifetchmissbound_with_l3h= it", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l2hit" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3hit" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that subsequently misses the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_MISS / MEM_BOUND_ST= ALLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_%_loadmissbound_with_l3mis= s" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L2", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.L2_HIT / MEM_BOUND_STAL= LS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l2hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of memory bound stalls where retir= ement is stalled due to an L1 miss that hit the L3", + "MetricExpr": "100 * MEM_BOUND_STALLS_LOAD.LLC_HIT / MEM_BOUND_STA= LLS_LOAD.ALL", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_miss_bound_loadmissbound_with_l3hit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement due to a pipeline block", + "MetricExpr": "100 * LD_HEAD.L1_BOUND_AT_RET / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_l1_bound" + }, + { + "BriefDescription": "Counts the number of cycles that the oldest l= oad of the load buffer is stalled at retirement", + "MetricExpr": "100 * (LD_HEAD.L1_BOUND_AT_RET + MEM_BOUND_STALLS_L= OAD.ALL) / CPU_CLK_UNHALTED.CORE", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_load_bound" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to store buffer full", + "MetricExpr": "100 * (MEM_SCHEDULER_BLOCK.ST_BUF / MEM_SCHEDULER_B= LOCK.ALL) * tma_mem_scheduler", + "MetricGroup": "load_store_bound", + "MetricName": "tma_info_load_store_bound_store_bound" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to floating point assists", + "MetricExpr": "1e3 * MACHINE_CLEARS.FP_ASSIST / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_fp_assi= st_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to page faults", + "MetricExpr": "1e3 * MACHINE_CLEARS.PAGE_FAULT / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_page_fa= ult_pki" + }, + { + "BriefDescription": "Counts the number of machine clears relative = to thousands of instructions retired, due to self-modifying code", + "MetricExpr": "1e3 * MACHINE_CLEARS.SMC / INST_RETIRED.ANY", + "MetricName": "tma_info_machine_clear_bound_machine_clears_smc_pki" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_adressaliasin= g" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "MetricName": "tma_info_mem_exec_blocks_%_loads_with_storefwdblk" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h an address aliasing block", + "MetricExpr": "100 * LD_BLOCKS.ADDRESS_ALIAS / MEM_UOPS_RETIRED.AL= L_LOADS", + "MetricName": "tma_info_mem_exec_blocks_loads_with_adressaliasing", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of total non-speculative loads wit= h a store forward or unknown store address block", + "MetricExpr": "100 * LD_BLOCKS.DATA_UNKNOWN / MEM_UOPS_RETIRED.ALL= _LOADS", + "MetricName": "tma_info_mem_exec_blocks_loads_with_storefwdblk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_l1miss" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_otherpipeline= blks", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_otherpipeli= neblks" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_pagewalk" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_stlbhit" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "MetricName": "tma_info_mem_exec_bound_%_loadhead_with_storefwding" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= first level data cache miss", + "MetricExpr": "100 * LD_HEAD.L1_MISS_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_l1miss", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to o= ther block cases, such as pipeline conflicts, fences, etc", + "MetricExpr": "100 * LD_HEAD.OTHER_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_otherpipeline= blks", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= pagewalk", + "MetricExpr": "100 * LD_HEAD.PGWALK_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_pagewalk", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= second level TLB miss", + "MetricExpr": "100 * LD_HEAD.DTLB_MISS_AT_RET / LD_HEAD.ANY_AT_RET= ", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_stlbhit", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Percentage of Memory Execution Bound due to a= store forward address match", + "MetricExpr": "100 * LD_HEAD.ST_ADDR_AT_RET / LD_HEAD.ANY_AT_RET", + "MetricName": "tma_info_mem_exec_bound_loadhead_with_storefwding", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Instructions per Load", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_ipload" + }, + { + "BriefDescription": "Instructions per Store", + "MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES", + "MetricName": "tma_info_mem_mix_ipstore" + }, + { + "BriefDescription": "Percentage of total non-speculative loads tha= t perform one or more locks", + "MetricExpr": "100 * MEM_UOPS_RETIRED.LOCK_LOADS / MEM_UOPS_RETIRE= D.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_locks_ratio" + }, + { + "BriefDescription": "Percentage of total non-speculative loads tha= t are splits", + "MetricExpr": "100 * MEM_UOPS_RETIRED.SPLIT_LOADS / MEM_UOPS_RETIR= ED.ALL_LOADS", + "MetricName": "tma_info_mem_mix_load_splits_ratio" + }, + { + "BriefDescription": "Ratio of mem load uops to all uops", + "MetricExpr": "1e3 * MEM_UOPS_RETIRED.ALL_LOADS / TOPDOWN_RETIRING= .ALL_P", + "MetricName": "tma_info_mem_mix_memload_ratio" + }, + { + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "tma_info_serialization_tpause_cycles", + "MetricName": "tma_info_serialization _%_tpause_cycles" + }, + { + "BriefDescription": "Percentage of time that the core is stalled d= ue to a TPAUSE or UMWAIT instruction", + "MetricExpr": "100 * SERIALIZATION.C01_MS_SCB / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricName": "tma_info_serialization_tpause_cycles", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Average CPU Utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricName": "tma_info_system_cpu_utilization" + }, + { + "BriefDescription": "Giga Floating Point Operations Per Second", + "MetricExpr": "FP_FLOPS_RETIRED.ALL / (duration_time * 1e9)", + "MetricGroup": "Flops", + "MetricName": "tma_info_system_gflops", + "PublicDescription": "Giga Floating Point Operations Per Second. A= ggregate across all supported options of: FP precisions, scalar and vector = instructions, vector-width" + }, + { + "BriefDescription": "Fraction of cycles spent in Kernel mode", + "MetricExpr": "cpu@CPU_CLK_UNHALTED.CORE_P@k / CPU_CLK_UNHALTED.CO= RE", + "MetricGroup": "Summary", + "MetricName": "tma_info_system_kernel_utilization" + }, + { + "BriefDescription": "Average Frequency Utilization relative nomina= l frequency", + "MetricExpr": "CPU_CLK_UNHALTED.CORE / CPU_CLK_UNHALTED.REF_TSC", + "MetricGroup": "Power", + "MetricName": "tma_info_system_turbo_utilization" + }, + { + "BriefDescription": "Percentage of all uops which are FPDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.FPDIV / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_fpdiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are IDiv uops", + "MetricExpr": "100 * UOPS_RETIRED.IDIV / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_idiv_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are microcode op= s", + "MetricExpr": "100 * UOPS_RETIRED.MS / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_microcode_uop_ratio" + }, + { + "BriefDescription": "Percentage of all uops which are x87 uops", + "MetricExpr": "100 * UOPS_RETIRED.X87 / TOPDOWN_RETIRING.ALL_P", + "MetricName": "tma_info_uop_mix_x87_uop_ratio" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to Instruction Table Lookaside Buffer (ITLB= ) misses.", + "MetricExpr": "TOPDOWN_FE_BOUND.ITLB_MISS / (6 * CPU_CLK_UNHALTED.= CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_latency_group", + "MetricName": "tma_itlb_misses", + "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_ifetch_latency >= 0.15 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS / (6 * CPU_C= LK_UNHALTED.CORE)", + "MetricGroup": "TopdownL2;tma_L2_group;tma_bad_speculation_group", + "MetricName": "tma_machine_clears", + "MetricThreshold": "tma_machine_clears > 0.05 & tma_bad_speculatio= n > 0.15", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to memory reservation stalls in which a sched= uler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.MEM_SCHEDULER / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_mem_scheduler", + "MetricThreshold": "tma_mem_scheduler > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to IEC or FPC RAT stalls, which can be due to= FIQ or IEC reservation stalls in which the integer, floating point or SIMD= scheduler is not able to accept uops", + "MetricExpr": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER / (6 * CPU_CLK_U= NHALTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_non_mem_scheduler", + "MetricThreshold": "tma_non_mem_scheduler > 0.1 & (tma_resource_bo= und > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to a machine clear that requires the use of m= icrocode (slow nuke)", + "MetricExpr": "TOPDOWN_BAD_SPECULATION.NUKE / (6 * CPU_CLK_UNHALTE= D.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_machine_clears_group", + "MetricName": "tma_nuke", + "MetricThreshold": "tma_nuke > 0.05 & (tma_machine_clears > 0.05 &= tma_bad_speculation > 0.15)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to other common frontend stalls not categor= ized.", + "MetricExpr": "TOPDOWN_FE_BOUND.OTHER / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_other_fb", + "MetricThreshold": "tma_other_fb > 0.05 & (tma_ifetch_bandwidth > = 0.1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t delivered by the frontend due to wrong predecodes.", + "MetricExpr": "TOPDOWN_FE_BOUND.PREDECODE / (6 * CPU_CLK_UNHALTED.= CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_ifetch_bandwidth_group", + "MetricName": "tma_predecode", + "MetricThreshold": "tma_predecode > 0.05 & (tma_ifetch_bandwidth >= 0.1 & tma_frontend_bound > 0.2)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the physical register file unable to accep= t an entry (marble stalls)", + "MetricExpr": "TOPDOWN_BE_BOUND.REGISTER / (6 * CPU_CLK_UNHALTED.C= ORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_register", + "MetricThreshold": "tma_register > 0.1 & (tma_resource_bound > 0.2= & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to the reorder buffer being full (ROB stalls)= ", + "MetricExpr": "TOPDOWN_BE_BOUND.REORDER_BUFFER / (6 * CPU_CLK_UNHA= LTED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_reorder_buffer", + "MetricThreshold": "tma_reorder_buffer > 0.1 & (tma_resource_bound= > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of cycles the core is stall= ed due to a resource limitation", + "MetricExpr": "tma_backend_bound - tma_core_bound", + "MetricGroup": "TopdownL2;tma_L2_group;tma_backend_bound_group", + "MetricName": "tma_resource_bound", + "MetricThreshold": "tma_resource_bound > 0.2 & tma_backend_bound >= 0.1", + "MetricgroupNoGroup": "TopdownL2", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that result = in retirement slots", + "MetricExpr": "TOPDOWN_RETIRING.ALL_P / (6 * CPU_CLK_UNHALTED.CORE= )", + "MetricGroup": "TopdownL1;tma_L1_group", + "MetricName": "tma_retiring", + "MetricThreshold": "tma_retiring > 0.75", + "MetricgroupNoGroup": "TopdownL1", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Counts the number of issue slots that were no= t consumed by the backend due to scoreboards from the instruction queue (IQ= ), jump execution unit (JEU), or microcode sequencer (MS)", + "MetricExpr": "TOPDOWN_BE_BOUND.SERIALIZATION / (6 * CPU_CLK_UNHAL= TED.CORE)", + "MetricGroup": "TopdownL3;tma_L3_group;tma_resource_bound_group", + "MetricName": "tma_serialization", + "MetricThreshold": "tma_serialization > 0.1 & (tma_resource_bound = > 0.2 & tma_backend_bound > 0.1)", + "ScaleUnit": "100%" + }, + { + "BriefDescription": "Uncore operating frequency in GHz", + "MetricExpr": "UNC_CHA_CLOCKTICKS / (source_count(UNC_CHA_CLOCKTIC= KS) * #num_packages) / 1e9 / duration_time", + "MetricName": "uncore_frequency", + "ScaleUnit": "1GHz" + }, + { + "BriefDescription": "Intel(R) Ultra Path Interconnect (UPI) data t= ransmit bandwidth (MB/sec)", + "MetricExpr": "UNC_UPI_TxL_FLITS.ALL_DATA * 7.111111111111111 / 1e= 6 / duration_time", + "MetricName": "upi_data_transmit_bw", + "ScaleUnit": "1MB/s" + } +] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json = b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json index a3aafbbc3484..f37107373e3b 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clockticks for CMS units attached to CHA", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHACMS_CLOCKTICKS", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of CHA clock cycles while the event is= enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", @@ -18,38 +20,47 @@ }, { "BriefDescription": "Counts transactions that looked into the mult= i-socket cacheline Directory state, and therefore did not send a snoop beca= use the Directory indicated it was not needed.", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts transactions that looked into the mul= ti-socket cacheline Directory state, and sent one or more snoops, because t= he Directory indicated it was needed.", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts only multi-socket cacheline Directory = state updates memory writes issued from the HA pipe. This does not include = memory write requests which are for I (Invalid) or E (Exclusive) cachelines= .", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts only multi-socket cacheline Directory = state updates due to memory writes issued from the TOR pipe which are the r= esult of remote transaction hitting the SF/LLC and returning data Core2Core= . This does not include memory write requests which are for I (Invalid) or = E (Exclusive) cachelines.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR o= r IRQ (immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_ANY", "PerPkg": "1", @@ -59,6 +70,7 @@ }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in IRQ (= immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_IRQ", "PerPkg": "1", @@ -67,6 +79,7 @@ }, { "BriefDescription": "Distress signal assertion for dynamic prefetc= h throttle (DPT). Threshold for distress signal assertion reached in TOR (= immediate cause for triggering).", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_TOR", "PerPkg": "1", @@ -75,40 +88,50 @@ }, { "BriefDescription": "Counts when a normal (Non-Isochronous) full l= ine write is issued from the CHA to the any of the memory controller channe= ls.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line : Counts the total number of full line writes issued from the HA in= to the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH : Counts the total number of full line writes issued from the HA = into the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial : Counts the total number of full line writes issued from the HA into= the memory controller.", + "Counter": "0,1,2,3", "EventCode": "0x5b", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups: All Requests to Remotely Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All transactions from Remote= Agents", "UMask": "0x17e0ff", @@ -116,8 +139,10 @@ }, { "BriefDescription": "Cache Lookups: CRd Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1bd0ff", @@ -125,8 +150,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1bc1ff", @@ -134,8 +161,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Reads", "UMask": "0x1fc1ff", @@ -143,8 +172,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Demand Data Reads, Core and = LLC prefetches", "UMask": "0x841ff", @@ -152,8 +183,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests, Read Prefetches= , and Snoops which miss the Cache", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses", "UMask": "0x1fc101", @@ -161,8 +194,10 @@ }, { "BriefDescription": "Cache Lookups: All Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCALLY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally", "UMask": "0xbdfff", @@ -170,8 +205,10 @@ }, { "BriefDescription": "Cache Lookups: Code Read Requests and Code Re= ad Prefetches to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x19d0ff", @@ -179,8 +216,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests and Read Prefetc= hes to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x19c1ff", @@ -188,8 +227,10 @@ }, { "BriefDescription": "Cache Lookups: Code Read Requests to Locally = Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1850ff", @@ -197,8 +238,10 @@ }, { "BriefDescription": "Cache Lookups: Read Requests to Locally Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1841ff", @@ -206,8 +249,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests to Locally Homed = Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_DMND_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x1848ff", @@ -215,8 +260,10 @@ }, { "BriefDescription": "Cache Lookups: LLC Prefetch Requests to Local= ly Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_LLC_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x189dff", @@ -224,8 +271,10 @@ }, { "BriefDescription": "Cache Lookups: All Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x199dff", @@ -233,8 +282,10 @@ }, { "BriefDescription": "Cache Lookups: Code Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1910ff", @@ -242,8 +293,10 @@ }, { "BriefDescription": "Cache Lookups: Read Prefetches to Locally Hom= ed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1981ff", @@ -251,8 +304,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Prefetches to Locally Home= d Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_PF_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x1908ff", @@ -260,8 +315,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x19c8ff", @@ -269,8 +326,10 @@ }, { "BriefDescription": "Cache Lookups: All Requests to Remotely Homed= Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTELY_HOMED_ADDRESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed remotely = : Counts the number of times the LLC was accessed - this includes code, dat= a, prefetches and hints coming from L2. This has numerous filters availabl= e. Note the non-standard filtering equation. This event will count reques= ts that lookup the cache multiple times with multiple increments. One must= ALWAYS set umask bit 0 and select a state or states to match. Otherwise, = the event will count nothing. : Transaction whose address resides in a remo= te MC", "UMask": "0x15dfff", @@ -278,8 +337,10 @@ }, { "BriefDescription": "Cache Lookups: Code Read/Prefetch Requests fr= om a Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_CODE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Requests", "UMask": "0x1a10ff", @@ -287,8 +348,10 @@ }, { "BriefDescription": "Cache Lookups: Data Read/Prefetch Requests fr= om a Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_DATA_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state. Read transactions", "UMask": "0x1a01ff", @@ -296,8 +359,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests/Prefetches from a= Remote Socket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests", "UMask": "0x1a08ff", @@ -305,8 +370,10 @@ }, { "BriefDescription": "Cache Lookups: Snoop Requests from a Remote S= ocket", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed", "UMask": "0x1c19ff", @@ -314,8 +381,10 @@ }, { "BriefDescription": "Cache Lookups: All RFO and RFO Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All RFOs - Demand and Prefet= ches", "UMask": "0x1bc8ff", @@ -323,8 +392,10 @@ }, { "BriefDescription": "Cache Lookups: RFO Requests and RFO Prefetche= s to Locally Homed Memory", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally HOMed RFOs - Demand = and Prefetches", "UMask": "0x9c8ff", @@ -332,8 +403,10 @@ }, { "BriefDescription": "Cache Lookups: Writes to Locally Homed Memory= (includes writebacks from L1/L2)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Writes", "UMask": "0x842ff", @@ -341,8 +414,10 @@ }, { "BriefDescription": "Cache Lookups: Writes to Remotely Homed Memor= y (includes writebacks from L1/L2)", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remote Writes", "UMask": "0x17c2ff", @@ -350,8 +425,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : All Lines Victimized", "UMask": "0xf", @@ -359,24 +436,30 @@ }, { "BriefDescription": "Lines Victimized : IA traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : IO traffic : Counts the nu= mber of lines that were victimized on a fill. This can be filtered by the = state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - All Lines", "UMask": "0x200f", @@ -384,8 +467,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in E State", "UMask": "0x2002", @@ -393,8 +478,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in F State", "UMask": "0x2008", @@ -402,8 +489,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in M State", "UMask": "0x2001", @@ -411,8 +500,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in S State", "UMask": "0x2004", @@ -420,8 +511,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - All Lines", "UMask": "0x800f", @@ -429,8 +522,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in E State= ", "UMask": "0x8002", @@ -438,8 +533,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in M State= ", "UMask": "0x8001", @@ -447,8 +544,10 @@ }, { "BriefDescription": "Lines Victimized : Counts the number of lines= that were victimized on a fill. This can be filtered by the state that th= e line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Remote - Lines in S State= ", "UMask": "0x8004", @@ -456,8 +555,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state", "UMask": "0x2", @@ -465,8 +566,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state", "UMask": "0x1", @@ -474,8 +577,10 @@ }, { "BriefDescription": "Counts the number of lines that were victimiz= ed on a fill. This can be filtered by the state that the line was in.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State", "UMask": "0x4", @@ -483,6 +588,7 @@ }, { "BriefDescription": "Counts when a RFO (the Read for Ownership iss= ued before a write) request hit a cacheline in the S (Shared) state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", @@ -492,38 +598,47 @@ }, { "BriefDescription": "OSB Snoop Broadcast : Local InvItoE : Count o= f OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be br= oadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_INVITOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Local Rd : Count of OSB= snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadca= st. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.LOCAL_READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Off : Count of OSB snoo= p broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. D= oes not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.OFF_PWRHEURISTIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : Remote Rd : Count of OS= B snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadc= ast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.REMOTE_READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "OSB Snoop Broadcast : RFO HitS Snoop Broadcas= t : Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoo= ps to be broadcast. Does not count all the snoops generated by OSB.", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB.RFO_HITS_SNP_BCAST", "PerPkg": "1", @@ -532,60 +647,75 @@ }, { "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.ALLOC_EXCLUSIVE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.ALLOC_SHARED", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.ALLOC_SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.DEALLOC_EVCTCLN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.DIRBACKED_ONLY", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.HIT_EXCLUSIVE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.HIT_SHARED", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.HIT_SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.INCLUSIVE_ONLY", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.MISS", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.MISS", "PerPkg": "1", @@ -594,35 +724,44 @@ }, { "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.UPDATE_EXCLUSIVE", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.UPDATE_SHARED", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.UPDATE_SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.VICTIM_EXCLUSIVE", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "UNC_CHA_REMOTE_SF.VICTIM_SHARED", + "Counter": "0,1,2,3", "EventCode": "0x69", "EventName": "UNC_CHA_REMOTE_SF.VICTIM_SHARED", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", "PerPkg": "1", @@ -632,6 +771,7 @@ }, { "BriefDescription": "Counts the total number of requests coming fr= om a unit on this socket for exclusive ownership of a cache line without re= ceiving data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -640,6 +780,7 @@ }, { "BriefDescription": "Counts the total number of requests coming fr= om a remote socket for exclusive ownership of a cache line without receivin= g data (INVITOE) to the CHA.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -648,6 +789,7 @@ }, { "BriefDescription": "Counts read requests made into this CHA. Read= s include all read opcodes (including RFO: the Read for Ownership issued be= fore a write) .", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -657,6 +799,7 @@ }, { "BriefDescription": "Counts read requests coming from a unit on th= is socket made into this CHA. Reads include all read opcodes (including RFO= : the Read for Ownership issued before a write).", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -665,6 +808,7 @@ }, { "BriefDescription": "Counts read requests coming from a remote soc= ket made into the CHA. Reads include all read opcodes (including RFO: the R= ead for Ownership issued before a write).", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -673,6 +817,7 @@ }, { "BriefDescription": "Counts write requests made into the CHA, incl= uding streaming, evictions, HitM (Reads from another core to a Modified cac= heline), etc.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -682,6 +827,7 @@ }, { "BriefDescription": "Counts write requests coming from a unit on = this socket made into this CHA, including streaming, evictions, HitM (Reads= from another core to a Modified cacheline), etc.", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -690,6 +836,7 @@ }, { "BriefDescription": "Counts the total number of read requests made= into the Home Agent. Reads include all read opcodes (including RFO). Writ= es include all writes (streaming, evictions, HitM, etc).", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -698,8 +845,10 @@ }, { "BriefDescription": "All TOR Inserts", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All", "UMask": "0xc001ffff", @@ -707,152 +856,190 @@ }, { "BriefDescription": "CLFlush transactions from a CXL device which = hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8c7fd20", "Unit": "CHA" }, { "BriefDescription": "FsRdCur transactions from a CXL device which = hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCUR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8effd20", "Unit": "CHA" }, { "BriefDescription": "FsRdCurPtl transactions from a CXL device whi= ch hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_FSRDCURPTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c9effd20", "Unit": "CHA" }, { "BriefDescription": "ItoM transactions from a CXL device which hit= in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc47fd20", "Unit": "CHA" }, { "BriefDescription": "ItoMWr transactions from a CXL device which h= it in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_ITOMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc4ffd20", "Unit": "CHA" }, { "BriefDescription": "MemPushWr transactions from a CXL device whic= h hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_MEMPUSHWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc6ffd20", "Unit": "CHA" }, { "BriefDescription": "WCiL transactions from a CXL device which hit= in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c86ffd20", "Unit": "CHA" }, { "BriefDescription": "WcilF transactions from a CXL device which hi= t in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WCILF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c867fd20", "Unit": "CHA" }, { "BriefDescription": "WiL transactions from a CXL device which hit = in the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_HIT_WIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c87ffd20", "Unit": "CHA" }, { "BriefDescription": "CLFlush transactions from a CXL device which = miss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8c7fe20", "Unit": "CHA" }, { "BriefDescription": "FsRdCur transactions from a CXL device which = miss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCUR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8effe20", "Unit": "CHA" }, { "BriefDescription": "FsRdCurPtl transactions from a CXL device whi= ch miss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_FSRDCURPTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c9effe20", "Unit": "CHA" }, { "BriefDescription": "ItoM transactions from a CXL device which mis= s the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc47fe20", "Unit": "CHA" }, { "BriefDescription": "ItoMWr transactions from a CXL device which m= iss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_ITOMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc4ffe20", "Unit": "CHA" }, { "BriefDescription": "MemPushWr transactions from a CXL device whic= h miss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_MEMPUSHWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc6ffe20", "Unit": "CHA" }, { "BriefDescription": "WCiL transactions from a CXL device which mis= s the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c86ffe20", "Unit": "CHA" }, { "BriefDescription": "WcilF transactions from a CXL device which mi= ss the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c867fe20", "Unit": "CHA" }, { "BriefDescription": "WiL transactions from a CXL device which miss= the L3.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.CXL_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c87ffe20", "Unit": "CHA" }, { "BriefDescription": "All locally initiated requests from IA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from iA Cores", "UMask": "0xc001ff01", @@ -860,6 +1047,7 @@ }, { "BriefDescription": "CLFlush events that are initiated from the Co= re", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -869,6 +1057,7 @@ }, { "BriefDescription": "CLFlushOpt events that are initiated from the= Core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", "PerPkg": "1", @@ -878,6 +1067,7 @@ }, { "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -887,6 +1077,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", "PerPkg": "1", @@ -896,6 +1087,7 @@ }, { "BriefDescription": "Data read opt from local IA that miss the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", "PerPkg": "1", @@ -905,6 +1097,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that mis= s the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -914,8 +1107,10 @@ }, { "BriefDescription": "All locally initiated requests from IA Cores = which hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from iA Cores tha= t Hit the LLC", "UMask": "0xc001fd01", @@ -923,6 +1118,7 @@ }, { "BriefDescription": "Code read from local IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -932,6 +1128,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that hit the= cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -941,6 +1138,7 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that hit the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CXL_ACC", "PerPkg": "1", @@ -949,6 +1147,7 @@ }, { "BriefDescription": "Data read opt from local IA that hit the cach= e", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -958,6 +1157,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that hit= the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -967,6 +1167,7 @@ }, { "BriefDescription": "ItoM requests from local IA cores that hit th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_ITOM", "PerPkg": "1", @@ -976,6 +1177,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFCODE", "PerPkg": "1", @@ -985,6 +1187,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFDATA", "PerPkg": "1", @@ -994,6 +1197,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -1003,6 +1207,7 @@ }, { "BriefDescription": "Read for ownership from local IA that hit the= cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -1012,6 +1217,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -1021,6 +1227,7 @@ }, { "BriefDescription": "ItoM events that are initiated from the Core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOM", "PerPkg": "1", @@ -1030,6 +1237,7 @@ }, { "BriefDescription": "ItoMCacheNear requests from local IA cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_ITOMCACHENEAR", "PerPkg": "1", @@ -1039,6 +1247,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFCODE", "PerPkg": "1", @@ -1048,6 +1257,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFDATA", "PerPkg": "1", @@ -1057,6 +1267,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_LLCPREFRFO", "PerPkg": "1", @@ -1066,6 +1277,7 @@ }, { "BriefDescription": "All locally initiated requests from IA Cores = which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -1075,6 +1287,7 @@ }, { "BriefDescription": "Code read from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -1084,6 +1297,7 @@ }, { "BriefDescription": "CRDs from local IA cores to locally homed mem= ory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_LOCAL", "PerPkg": "1", @@ -1093,6 +1307,7 @@ }, { "BriefDescription": "Code read prefetch from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -1102,6 +1317,7 @@ }, { "BriefDescription": "CRD Prefetches from local IA cores to locally= homed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", @@ -1111,6 +1327,7 @@ }, { "BriefDescription": "CRD Prefetches from local IA cores to remotel= y homed memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF_REMOTE", "PerPkg": "1", @@ -1120,6 +1337,7 @@ }, { "BriefDescription": "CRDs from local IA cores to remotely homed me= mory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_REMOTE", "PerPkg": "1", @@ -1129,6 +1347,7 @@ }, { "BriefDescription": "All requests issued from IA cores to CXL acce= lerator memory regions that miss the LLC.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CXL_ACC", "PerPkg": "1", @@ -1137,6 +1356,7 @@ }, { "BriefDescription": "DRds and equivalent opcodes issued from an IA= core which miss the L3 and target memory in a CXL type 2 memory expander c= ard.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_CXL_ACC", "PerPkg": "1", @@ -1146,6 +1366,7 @@ }, { "BriefDescription": "Data read opt from local IA that miss the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -1155,6 +1376,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRd_Opt, and which target l= ocal memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_LOCAL", "PerPkg": "1", @@ -1164,6 +1386,7 @@ }, { "BriefDescription": "Data read opt prefetch from local IA that mis= s the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", @@ -1173,6 +1396,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target lo= cal memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_LOCAL", "PerPkg": "1", @@ -1182,6 +1406,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRD_PREF_OPT, and target re= mote memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF_REMOTE", "PerPkg": "1", @@ -1191,6 +1416,7 @@ }, { "BriefDescription": "Inserts into the TOR from local IA cores whic= h miss the LLC and snoop filter with the opcode DRd_Opt, and target remote = memory", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_REMOTE", "PerPkg": "1", @@ -1200,6 +1426,7 @@ }, { "BriefDescription": "L2 data prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_CXL_ACC", "PerPkg": "1", @@ -1208,6 +1435,7 @@ }, { "BriefDescription": "ItoM requests from local IA cores that miss t= he cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_ITOM", "PerPkg": "1", @@ -1217,6 +1445,7 @@ }, { "BriefDescription": "Last level cache prefetch code read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFCODE", "PerPkg": "1", @@ -1226,6 +1455,7 @@ }, { "BriefDescription": "Last level cache prefetch data read from loca= l IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -1235,6 +1465,7 @@ }, { "BriefDescription": "LLC data prefetches issued from an IA core wh= ich miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA_CXL_ACC", "PerPkg": "1", @@ -1243,6 +1474,7 @@ }, { "BriefDescription": "Last level cache prefetch read for ownership = from local IA that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -1252,6 +1484,7 @@ }, { "BriefDescription": "L2 RFO prefetches issued from an IA core whic= h miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFRFO_CXL_ACC", "PerPkg": "1", @@ -1260,6 +1493,7 @@ }, { "BriefDescription": "WCILF requests from local IA cores to locally= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", @@ -1269,8 +1503,10 @@ }, { "BriefDescription": "WCILF requests from local IA cores to locally= homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed locally", "UMask": "0xc8668a01", @@ -1278,6 +1514,7 @@ }, { "BriefDescription": "WCIL requests from local IA cores to locally = homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", @@ -1287,8 +1524,10 @@ }, { "BriefDescription": "WCIL requests from local IA cores to locally = homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed locally", "UMask": "0xc86e8a01", @@ -1296,6 +1535,7 @@ }, { "BriefDescription": "WCILF requests from local IA cores to remotel= y homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_DDR", "PerPkg": "1", @@ -1305,8 +1545,10 @@ }, { "BriefDescription": "WCILF requests from local IA cores to remotel= y homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC - HOMed remotely", "UMask": "0xc8670a01", @@ -1314,6 +1556,7 @@ }, { "BriefDescription": "WCIL requests from local IA cores to remotely= homed DDR addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_DDR", "PerPkg": "1", @@ -1323,8 +1566,10 @@ }, { "BriefDescription": "WCIL requests from local IA cores to remotely= homed PMM addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC - HOMed remotely", "UMask": "0xc86f0a01", @@ -1332,6 +1577,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -1341,6 +1587,7 @@ }, { "BriefDescription": "RFOs issued from an IA core which miss the L3= and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_CXL_ACC", "PerPkg": "1", @@ -1349,6 +1596,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -1358,6 +1606,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -1367,6 +1616,7 @@ }, { "BriefDescription": "LLC RFO prefetches issued from an IA core whi= ch miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_CXL_ACC", "PerPkg": "1", @@ -1375,6 +1625,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -1384,6 +1635,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -1393,6 +1645,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -1402,6 +1655,7 @@ }, { "BriefDescription": "UCRDF requests from local IA cores that miss = the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", @@ -1411,6 +1665,7 @@ }, { "BriefDescription": "WCIL requests from a local IA core that miss = the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", @@ -1420,6 +1675,7 @@ }, { "BriefDescription": "WCILF requests from local IA core that miss t= he cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", @@ -1429,6 +1685,7 @@ }, { "BriefDescription": "WCILF requests from local IA cores to DDR hom= ed addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_DDR", "PerPkg": "1", @@ -1438,8 +1695,10 @@ }, { "BriefDescription": "WCILF requests from local IA cores to PMM hom= ed addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLFs issued by iA Cores targ= eting PMM that missed the LLC", "UMask": "0xc8678a01", @@ -1447,6 +1706,7 @@ }, { "BriefDescription": "WCIL requests from local IA cores to DDR home= d addresses which miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_DDR", "PerPkg": "1", @@ -1456,8 +1716,10 @@ }, { "BriefDescription": "WCIL requests from a local IA core to PMM hom= ed addresses that miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores targe= ting PMM that missed the LLC", "UMask": "0xc86f8a01", @@ -1465,6 +1727,7 @@ }, { "BriefDescription": "WIL requests from local IA cores that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", @@ -1474,6 +1737,7 @@ }, { "BriefDescription": "Read for ownership from local IA that miss th= e cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -1483,6 +1747,7 @@ }, { "BriefDescription": "Read for ownership prefetch from local IA tha= t miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -1492,6 +1757,7 @@ }, { "BriefDescription": "SpecItoM events that are initiated from the C= ore", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_SPECITOM", "PerPkg": "1", @@ -1501,6 +1767,7 @@ }, { "BriefDescription": "WbEFtoEs issued by iA Cores. (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", "PerPkg": "1", @@ -1510,6 +1777,7 @@ }, { "BriefDescription": "WbEFtoIs issued by iA Cores . (Non Modified = Write Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", "PerPkg": "1", @@ -1519,6 +1787,7 @@ }, { "BriefDescription": "WbMtoEs issued by iA Cores . (Modified Write= Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", "PerPkg": "1", @@ -1528,6 +1797,7 @@ }, { "BriefDescription": "WbMtoI requests from local IA cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", "PerPkg": "1", @@ -1537,6 +1807,7 @@ }, { "BriefDescription": "WbStoIs issued by iA Cores . (Non Modified W= rite Backs)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", "PerPkg": "1", @@ -1546,6 +1817,7 @@ }, { "BriefDescription": "WCIL requests from a local IA core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", "PerPkg": "1", @@ -1555,6 +1827,7 @@ }, { "BriefDescription": "WCILF requests from local IA core", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", "PerPkg": "1", @@ -1564,8 +1837,10 @@ }, { "BriefDescription": "All TOR inserts from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from IO Devices", "UMask": "0xc001ff04", @@ -1573,6 +1848,7 @@ }, { "BriefDescription": "CLFlush requests from IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", "PerPkg": "1", @@ -1582,8 +1858,10 @@ }, { "BriefDescription": "All TOR inserts from local IO devices which h= it the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat hit the LLC", "UMask": "0xc001fd04", @@ -1591,6 +1869,7 @@ }, { "BriefDescription": "ItoMs from local IO devices which hit the cac= he", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -1600,6 +1879,7 @@ }, { "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -1609,6 +1889,7 @@ }, { "BriefDescription": "PCIRDCURs issued by IO devices which hit the = LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -1618,6 +1899,7 @@ }, { "BriefDescription": "RFOs from local IO devices which hit the cach= e", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", "PerPkg": "1", @@ -1627,6 +1909,7 @@ }, { "BriefDescription": "All TOR ItoM inserts from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -1636,6 +1919,7 @@ }, { "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -1644,70 +1928,79 @@ "Unit": "CHA" }, { - "BriefDescription": "All TOR inserts from local IO devices which m= iss the cache", + "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_LOCAL", "PerPkg": "1", - "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC", - "UMask": "0xc001fe04", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that address memory on the local sock= et", + "UMask": "0xcd42ff04", "Unit": "CHA" }, { - "BriefDescription": "All TOR ItoM inserts from local IO devices wh= ich miss the cache", + "BriefDescription": "ItoMCacheNear (partial write) transactions fr= om an IO device that addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR_REMOTE", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC", - "UMask": "0xcc43fe04", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that address memory on a remote socke= t", + "UMask": "0xcd437f04", "Unit": "CHA" }, { - "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that missed the LLC", + "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on the local socket", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_LOCAL", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC", - "UMask": "0xcd43fe04", + "PublicDescription": "TOR Inserts : ItoM, indicating a write reque= st, from IO Devices that address memory on the local socket", + "UMask": "0xcc42ff04", "Unit": "CHA" }, { - "BriefDescription": "ItoMCacheNear transactions from an IO device = on the local socket that miss the cache", + "BriefDescription": "ItoM (write) transactions from an IO device t= hat addresses memory on a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR_LOCAL", + "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM_REMOTE", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC", - "UMask": "0xcd42fe04", + "PublicDescription": "TOR Inserts : ItoM, indicating a write reque= st, from IO Devices that address memory on a remote socket", + "UMask": "0xcc437f04", "Unit": "CHA" }, { - "BriefDescription": "ItoMCacheNear transactions from an IO device = on a remote socket that miss the cache", + "BriefDescription": "All TOR inserts from local IO devices which m= iss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR_REMOTE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", + "Experimental": "1", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC", - "UMask": "0xcd437e04", + "PublicDescription": "TOR Inserts : All requests from IO Devices t= hat missed the LLC", + "UMask": "0xc001fe04", "Unit": "CHA" }, { - "BriefDescription": "ItoM transactions from an IO device on the lo= cal socket that miss the cache", + "BriefDescription": "All TOR ItoM inserts from local IO devices wh= ich miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM_LOCAL", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC", - "UMask": "0xcc42fe04", + "UMask": "0xcc43fe04", "Unit": "CHA" }, { - "BriefDescription": "ItoM transactions from an IO device on a remo= te socket that miss the cache", + "BriefDescription": "ItoMCacheNears, indicating a partial write re= quest, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", - "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM_REMOTE", + "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", - "PublicDescription": "TOR Inserts : ItoMs issued by IO Devices tha= t missed the LLC", - "UMask": "0xcc437e04", + "PublicDescription": "TOR Inserts : ItoMCacheNears, indicating a p= artial write request, from IO Devices that missed the LLC", + "UMask": "0xcd43fe04", "Unit": "CHA" }, { "BriefDescription": "PCIRDCURs issued by IO devices which miss the= LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -1717,6 +2010,7 @@ }, { "BriefDescription": "All TOR RFO inserts from local IO devices whi= ch miss the cache", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", "PerPkg": "1", @@ -1726,6 +2020,7 @@ }, { "BriefDescription": "PCIRDCURs issued by IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -1733,8 +2028,29 @@ "UMask": "0xc8f3ff04", "Unit": "CHA" }, + { + "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on the local socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_LOCAL", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that addresses memory on the local socket", + "UMask": "0xc8f2ff04", + "Unit": "CHA" + }, + { + "BriefDescription": "PCIRDCUR (read) transactions from an IO devic= e that addresses memory on a remote socket", + "Counter": "0,1,2,3", + "EventCode": "0x35", + "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR_REMOTE", + "PerPkg": "1", + "PublicDescription": "TOR Inserts : PCIRdCurs issued by IO Devices= that addresses memory on a remote socket", + "UMask": "0xc8f37f04", + "Unit": "CHA" + }, { "BriefDescription": "RFOs from local IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", "PerPkg": "1", @@ -1744,6 +2060,7 @@ }, { "BriefDescription": "WBMtoI requests from IO devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", "PerPkg": "1", @@ -1753,6 +2070,7 @@ }, { "BriefDescription": "TOR Inserts for SF or LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LLC_OR_SF_EVICTIONS", "PerPkg": "1", @@ -1762,8 +2080,10 @@ }, { "BriefDescription": "All locally initiated requests", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO", "UMask": "0xc000ff05", @@ -1771,8 +2091,10 @@ }, { "BriefDescription": "All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA", "UMask": "0xc000ff01", @@ -1780,8 +2102,10 @@ }, { "BriefDescription": "All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO", "UMask": "0xc000ff04", @@ -1789,8 +2113,10 @@ }, { "BriefDescription": "All remote requests (e.g. snoops, writebacks)= that came from remote sockets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All Remote Requests", "UMask": "0xc001ffc8", @@ -1798,8 +2124,10 @@ }, { "BriefDescription": "All snoops to this LLC that came from remote = sockets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All Snoops from Remote", "UMask": "0xc001ff08", @@ -1807,8 +2135,10 @@ }, { "BriefDescription": "Occupancy for all TOR entries", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All", "UMask": "0xc001ffff", @@ -1816,152 +2146,190 @@ }, { "BriefDescription": "TOR Occupancy for CLFlush transactions from a= CXL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8c7fd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for FsRdCur transactions from a= CXL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCUR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8effd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions fro= m a CXL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_FSRDCURPTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c9effd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for ItoM transactions from a CX= L device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc47fd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for ItoMWr transactions from a = CXL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_ITOMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc4ffd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for MemPushWr transactions from= a CXL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_MEMPUSHWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc6ffd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WCiL transactions from a CX= L device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c86ffd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WcilF transactions from a C= XL device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WCILF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c867fd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WiL transactions from a CXL= device which hit in the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_HIT_WIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c87ffd20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for CLFlush transactions from a= CXL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8c7fe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for FsRdCur transactions from a= CXL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCUR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c8effe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for FsRdCurPtl transactions fro= m a CXL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_FSRDCURPTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c9effe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for ItoM transactions from a CX= L device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc47fe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for ItoMWr transactions from a = CXL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_ITOMWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc4ffe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for MemPushWr transactions from= a CXL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_MEMPUSHWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78cc6ffe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WCiL transactions from a CX= L device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c86ffe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WcilF transactions from a C= XL device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c867fe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for WiL transactions from a CXL= device which miss the L3.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.CXL_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x78c87ffe20", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores", "UMask": "0xc001ff01", @@ -1969,6 +2337,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlush events that are ini= tiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", "PerPkg": "1", @@ -1978,6 +2347,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlushOpt events that are = initiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", "PerPkg": "1", @@ -1987,6 +2357,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -1996,6 +2367,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", "PerPkg": "1", @@ -2005,8 +2377,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", "UMask": "0xc827ff01", @@ -2014,8 +2388,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores", "UMask": "0xc8a7ff01", @@ -2023,8 +2399,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Hit the LLC", "UMask": "0xc001fd01", @@ -2032,6 +2410,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "PerPkg": "1", @@ -2041,6 +2420,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -2050,6 +2430,7 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that hit the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CXL_ACC", "PerPkg": "1", @@ -2058,8 +2439,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opts issued by iA Cores = that hit the LLC", "UMask": "0xc827fd01", @@ -2067,8 +2450,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that hit the LLC", "UMask": "0xc8a7fd01", @@ -2076,6 +2461,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_ITOM", "PerPkg": "1", @@ -2085,6 +2471,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFCODE", "PerPkg": "1", @@ -2094,6 +2481,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFDATA", "PerPkg": "1", @@ -2103,6 +2491,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LLCPREFRFO", "PerPkg": "1", @@ -2112,6 +2501,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "PerPkg": "1", @@ -2121,6 +2511,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -2130,6 +2521,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM events that are initia= ted from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOM", "PerPkg": "1", @@ -2139,6 +2531,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNear requests from= local IA cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_ITOMCACHENEAR", "PerPkg": "1", @@ -2148,6 +2541,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFCODE", "PerPkg": "1", @@ -2157,6 +2551,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFDATA", "PerPkg": "1", @@ -2166,6 +2561,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_LLCPREFRFO", "PerPkg": "1", @@ -2175,8 +2571,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts from IA Cores which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from iA Cores t= hat Missed the LLC", "UMask": "0xc001fe01", @@ -2184,6 +2582,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read from local IA tha= t miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -2193,6 +2592,7 @@ }, { "BriefDescription": "TOR Occupancy for CRDs from local IA cores to= locally homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_LOCAL", "PerPkg": "1", @@ -2202,6 +2602,7 @@ }, { "BriefDescription": "TOR Occupancy for Code read prefetch from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -2211,6 +2612,7 @@ }, { "BriefDescription": "TOR Occupancy for CRD Prefetches from local I= A cores to locally homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_LOCAL", "PerPkg": "1", @@ -2220,6 +2622,7 @@ }, { "BriefDescription": "TOR Occupancy for CRD Prefetches from local I= A cores to remotely homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF_REMOTE", "PerPkg": "1", @@ -2229,6 +2632,7 @@ }, { "BriefDescription": "TOR Occupancy for CRDs from local IA cores to= remotely homed memory", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_REMOTE", "PerPkg": "1", @@ -2238,6 +2642,7 @@ }, { "BriefDescription": "TOR Occupancy for All requests issued from IA= cores to CXL accelerator memory regions that miss the LLC.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CXL_ACC", "PerPkg": "1", @@ -2246,6 +2651,7 @@ }, { "BriefDescription": "TOR Occupancy for DRds and equivalent opcodes= issued from an IA core which miss the L3 and target memory in a CXL type 2= memory expander card.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_CXL_ACC", "PerPkg": "1", @@ -2254,8 +2660,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt from local IA= that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt issued by iA Cores t= hat missed the LLC", "UMask": "0xc827fe01", @@ -2263,8 +2671,10 @@ }, { "BriefDescription": "TOR Occupancy for Data read opt prefetch from= local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC", "UMask": "0xc8a7fe01", @@ -2272,6 +2682,7 @@ }, { "BriefDescription": "TOR Occupancy for L2 data prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_PREF_CXL_ACC", "PerPkg": "1", @@ -2280,6 +2691,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoM requests from local IA= cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_ITOM", "PerPkg": "1", @@ -2289,6 +2701,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch c= ode read from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFCODE", "PerPkg": "1", @@ -2298,6 +2711,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch d= ata read from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA", "PerPkg": "1", @@ -2307,6 +2721,7 @@ }, { "BriefDescription": "TOR Occupancy for LLC data prefetches issued = from an IA core which miss the L3 and target memory in a CXL type 2 acceler= ator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFDATA_CXL_ACC", "PerPkg": "1", @@ -2315,6 +2730,7 @@ }, { "BriefDescription": "TOR Occupancy for Last level cache prefetch r= ead for ownership from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO", "PerPkg": "1", @@ -2324,6 +2740,7 @@ }, { "BriefDescription": "TOR Occupancy for L2 RFO prefetches issued fr= om an IA core which miss the L3 and target memory in a CXL type 2 accelerat= or.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LLCPREFRFO_CXL_ACC", "PerPkg": "1", @@ -2332,6 +2749,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to locally homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_DDR", "PerPkg": "1", @@ -2341,8 +2759,10 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to locally homed PMM addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed locally", "UMask": "0xc8668a01", @@ -2350,6 +2770,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to locally homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_DDR", "PerPkg": "1", @@ -2359,8 +2780,10 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to locally homed PMM addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LOCAL_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed locally", "UMask": "0xc86e8a01", @@ -2368,6 +2791,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to remotely homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_DDR", "PerPkg": "1", @@ -2377,8 +2801,10 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to remotely homed PMM addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC - HOMed remotely", "UMask": "0xc8670a01", @@ -2386,6 +2812,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to remotely homed DDR addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_DDR", "PerPkg": "1", @@ -2395,8 +2822,10 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to remotely homed PMM addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_REMOTE_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC - HOMed remotely", "UMask": "0xc86f0a01", @@ -2404,6 +2833,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -2413,6 +2843,7 @@ }, { "BriefDescription": "TOR Occupancy for RFOs issued from an IA core= which miss the L3 and target memory in a CXL type 2 accelerator.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_CXL_ACC", "PerPkg": "1", @@ -2421,6 +2852,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_LOCAL", "PerPkg": "1", @@ -2430,6 +2862,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -2439,6 +2872,7 @@ }, { "BriefDescription": "TOR Occupancy for LLC RFO prefetches issued f= rom an IA core which miss the L3 and target memory in a CXL type 2 accelera= tor.", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_CXL_ACC", "PerPkg": "1", @@ -2447,6 +2881,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_LOCAL", "PerPkg": "1", @@ -2456,6 +2891,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF_REMOTE", "PerPkg": "1", @@ -2465,6 +2901,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_REMOTE", "PerPkg": "1", @@ -2474,6 +2911,7 @@ }, { "BriefDescription": "TOR Occupancy for UCRDF requests from local I= A cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", "PerPkg": "1", @@ -2483,6 +2921,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", "PerPkg": "1", @@ -2492,6 +2931,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", "PerPkg": "1", @@ -2501,6 +2941,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to DDR homed addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_DDR", "PerPkg": "1", @@ -2510,8 +2951,10 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A cores to PMM homed addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLFs issued by iA Cores ta= rgeting PMM that missed the LLC", "UMask": "0xc8678a01", @@ -2519,6 +2962,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from local IA= cores to DDR homed addresses which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_DDR", "PerPkg": "1", @@ -2528,8 +2972,10 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core to PMM homed addresses that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL_PMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tar= geting PMM that missed the LLC", "UMask": "0xc86f8a01", @@ -2537,6 +2983,7 @@ }, { "BriefDescription": "TOR Occupancy for WIL requests from local IA = cores that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", "PerPkg": "1", @@ -2546,6 +2993,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership from loc= al IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -2555,6 +3003,7 @@ }, { "BriefDescription": "TOR Occupancy for Read for ownership prefetch= from local IA that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", "PerPkg": "1", @@ -2564,6 +3013,7 @@ }, { "BriefDescription": "TOR Occupancy for SpecItoM events that are in= itiated from the Core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_SPECITOM", "PerPkg": "1", @@ -2573,6 +3023,7 @@ }, { "BriefDescription": "TOR Occupancy for WbMtoI requests from local = IA cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", "PerPkg": "1", @@ -2582,6 +3033,7 @@ }, { "BriefDescription": "TOR Occupancy for WCIL requests from a local = IA core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", "PerPkg": "1", @@ -2591,6 +3043,7 @@ }, { "BriefDescription": "TOR Occupancy for WCILF requests from local I= A core", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", "PerPkg": "1", @@ -2600,8 +3053,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= ", "UMask": "0xc001ff04", @@ -2609,6 +3064,7 @@ }, { "BriefDescription": "TOR Occupancy for CLFlush requests from IO de= vices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", "PerPkg": "1", @@ -2618,8 +3074,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= that hit the LLC", "UMask": "0xc001fd04", @@ -2627,6 +3085,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMs from local IO devices= which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", "PerPkg": "1", @@ -2636,6 +3095,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -2645,6 +3105,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -2654,6 +3115,7 @@ }, { "BriefDescription": "TOR Occupancy for RFOs from local IO devices = which hit the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", "PerPkg": "1", @@ -2663,6 +3125,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", "PerPkg": "1", @@ -2672,6 +3135,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -2681,8 +3145,10 @@ }, { "BriefDescription": "TOR Occupancy for All TOR inserts from local = IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All requests from IO Devices= that missed the LLC", "UMask": "0xc001fe04", @@ -2690,6 +3156,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR ItoM inserts from l= ocal IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", "PerPkg": "1", @@ -2699,6 +3166,7 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNears, indicating = a partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -2708,8 +3176,10 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions = from an IO device on the local socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC", "UMask": "0xcd42fe04", @@ -2717,8 +3187,10 @@ }, { "BriefDescription": "TOR Occupancy for ItoMCacheNear transactions = from an IO device on a remote socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC", "UMask": "0xcd437e04", @@ -2726,8 +3198,10 @@ }, { "BriefDescription": "TOR Occupancy for ItoM transactions from an I= O device on the local socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC", "UMask": "0xcc42fe04", @@ -2735,8 +3209,10 @@ }, { "BriefDescription": "TOR Occupancy for ItoM transactions from an I= O device on a remote socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC", "UMask": "0xcc437e04", @@ -2744,6 +3220,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces which miss the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -2753,8 +3230,10 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from = an IO device on the local socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC", "UMask": "0xc8f2fe04", @@ -2762,8 +3241,10 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCUR transactions from = an IO device on a remote socket that miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that missed the LLC", "UMask": "0xc8f37e04", @@ -2771,6 +3252,7 @@ }, { "BriefDescription": "TOR Occupancy for All TOR RFO inserts from lo= cal IO devices which miss the cache", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", "PerPkg": "1", @@ -2780,6 +3262,7 @@ }, { "BriefDescription": "TOR Occupancy for PCIRDCURs issued by IO devi= ces", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -2789,6 +3272,7 @@ }, { "BriefDescription": "TOR Occupancy for RFOs from local IO devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", "PerPkg": "1", @@ -2798,6 +3282,7 @@ }, { "BriefDescription": "TOR Occupancy for WBMtoI requests from IO dev= ices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", "PerPkg": "1", @@ -2807,8 +3292,10 @@ }, { "BriefDescription": "TOR Occupancy for All locally initiated reque= sts", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO", "UMask": "0xc000ff05", @@ -2816,8 +3303,10 @@ }, { "BriefDescription": "TOR Occupancy for All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA", "UMask": "0xc000ff01", @@ -2825,8 +3314,10 @@ }, { "BriefDescription": "TOR Occupancy for All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO", "UMask": "0xc000ff04", @@ -2834,8 +3325,10 @@ }, { "BriefDescription": "TOR Occupancy for All remote requests (e.g. s= noops, writebacks) that came from remote sockets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All Remote Requests", "UMask": "0xc001ffc8", @@ -2843,8 +3336,10 @@ }, { "BriefDescription": "TOR Occupancy for All snoops to this LLC that= came from remote sockets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.REM_SNPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All Snoops from Remote", "UMask": "0xc001ff08", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json b/= tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json index dc676c7aa37f..383a5ba5a697 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-cxl.json @@ -1,10 +1,31 @@ [ { "BriefDescription": "B2CXL Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_B2CXL_CLOCKTICKS", "PerPkg": "1", "PortMask": "0x000", "Unit": "B2CXL" + }, + { + "BriefDescription": "Number of Allocation to Mem Data Packing buff= er", + "Counter": "4,5,6,7", + "EventCode": "0x41", + "EventName": "UNC_CXLCM_RxC_PACK_BUF_INSERTS.MEM_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x10", + "Unit": "CXLCM" + }, + { + "BriefDescription": "Number of Allocation to M2S Data AGF", + "Counter": "0,1,2,3", + "EventCode": "0x02", + "EventName": "UNC_CXLDP_TxC_AGF_INSERTS.M2S_DATA", + "Experimental": "1", + "PerPkg": "1", + "UMask": "0x20", + "Unit": "CXLDP" } ] diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnec= t.json b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnect.js= on index 6932b2fea3a5..80440edac431 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Clockticks of the mesh to memory (B2CMI)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_B2CMI_CLOCKTICKS", "PerPkg": "1", @@ -8,14 +9,17 @@ }, { "BriefDescription": "Counts the number of time D2C was not honoure= d by egress due to directory state constraints", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_B2CMI_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Counts the number of times B2CMI egress did D= 2C (direct to core)", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_B2CMI_DIRECT2CORE_TAKEN", "PerPkg": "1", @@ -24,14 +28,17 @@ }, { "BriefDescription": "Counts the number of times D2C wasn't honoure= d even though the incoming request had d2c set for non cisgress txn", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_B2CMI_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Counts the number of d2k wasn't done due to c= redit constraints", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", @@ -40,6 +47,7 @@ }, { "BriefDescription": "Direct to UPI Transactions - Ignored due to l= ack of credits : All : Counts the number of d2k wasn't done due to credit c= onstraints", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_CREDITS.EGRESS", "PerPkg": "1", @@ -48,6 +56,7 @@ }, { "BriefDescription": "Counts the number of time D2K was not honoure= d by egress due to directory state constraints", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", @@ -56,6 +65,7 @@ }, { "BriefDescription": "Cycles when Direct2UPI was Disabled : Egress = Ignored D2U : Counts the number of time D2K was not honoured by egress due = to directory state constraints", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_B2CMI_DIRECT2UPI_NOT_TAKEN_DIRSTATE.EGRESS", "PerPkg": "1", @@ -64,6 +74,7 @@ }, { "BriefDescription": "Counts the number of times egress did D2K (Di= rect to KTI)", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_B2CMI_DIRECT2UPI_TAKEN", "PerPkg": "1", @@ -72,6 +83,7 @@ }, { "BriefDescription": "Counts the number of times D2K wasn't honoure= d even though the incoming request had d2k set for non cisgress txn", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_B2CMI_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", @@ -80,70 +92,87 @@ }, { "BriefDescription": "Directory Hit Clean", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x38", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit Dirty (modified)", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Directory Hit : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_B2CMI_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "B2CMI" }, { "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with any directory to non persistent memory", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -152,6 +181,7 @@ }, { "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory A to non persistent memory", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -160,6 +190,7 @@ }, { "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory I to non persistent memory", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -168,6 +199,7 @@ }, { "BriefDescription": "Counts the number of 1lm or 2lm hit read data= returns to egress with directory S to non persistent memory", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_B2CMI_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -177,70 +209,87 @@ }, { "BriefDescription": "Directory Miss Clean", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x38", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss Dirty (modified)", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Directory Miss : On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_B2CMI_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "B2CMI" }, { "BriefDescription": "Any A2I Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2I", "PerPkg": "1", @@ -249,6 +298,7 @@ }, { "BriefDescription": "Any A2S Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.A2S", "PerPkg": "1", @@ -257,6 +307,7 @@ }, { "BriefDescription": "Counts cisgress directory updates", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -265,38 +316,47 @@ }, { "BriefDescription": "Counts any 1lm or 2lm hit data return that wo= uld result in directory update to non persistent memory (DRAM)", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "B2CMI" }, { "BriefDescription": "Directory update in near memory to the A stat= e", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x114", "Unit": "B2CMI" }, { "BriefDescription": "Directory update in near memory to the I stat= e", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x128", "Unit": "B2CMI" }, { "BriefDescription": "Directory update in near memory to the S stat= e", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.HIT_X2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x142", "Unit": "B2CMI" }, { "BriefDescription": "Any I2A Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2A", "PerPkg": "1", @@ -305,6 +365,7 @@ }, { "BriefDescription": "Any I2S Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.I2S", "PerPkg": "1", @@ -313,70 +374,87 @@ }, { "BriefDescription": "Directory update in far memory to the A state= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x214", "Unit": "B2CMI" }, { "BriefDescription": "Directory update in far memory to the I state= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x228", "Unit": "B2CMI" }, { "BriefDescription": "Directory update in far memory to the S state= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.MISS_X2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x242", "Unit": "B2CMI" }, { "BriefDescription": "Any S2A Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x310", "Unit": "B2CMI" }, { "BriefDescription": "Any S2I Transition", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.S2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x308", "Unit": "B2CMI" }, { "BriefDescription": "Directory update to the A state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x314", "Unit": "B2CMI" }, { "BriefDescription": "Directory update to the I state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x328", "Unit": "B2CMI" }, { "BriefDescription": "Directory update to the S state", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_B2CMI_DIRECTORY_UPDATE.X2S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x342", "Unit": "B2CMI" }, { "BriefDescription": "Counts any read", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.ALL", "PerPkg": "1", @@ -385,6 +463,7 @@ }, { "BriefDescription": "Counts normal reads issue to CMI", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.NORMAL", "PerPkg": "1", @@ -393,22 +472,27 @@ }, { "BriefDescription": "Count reads to NM region", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x110", "Unit": "B2CMI" }, { "BriefDescription": "Counts reads to 1lm non persistent memory reg= ions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_B2CMI_IMC_READS.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "B2CMI" }, { "BriefDescription": "All Writes - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.ALL", "PerPkg": "1", @@ -417,6 +501,7 @@ }, { "BriefDescription": "Full Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.FULL", "PerPkg": "1", @@ -425,20 +510,25 @@ }, { "BriefDescription": "Non-Inclusive - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.NI", + "Experimental": "1", "PerPkg": "1", "Unit": "B2CMI" }, { "BriefDescription": "Non-Inclusive Miss - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "B2CMI" }, { "BriefDescription": "Partial Non-ISOCH - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -447,38 +537,47 @@ }, { "BriefDescription": "DDR, acting as Cache - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "B2CMI" }, { "BriefDescription": "DDR - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_B2CMI_IMC_WRITES.TO_DDR_AS_MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x120", "Unit": "B2CMI" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "B2CMI" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Prefetch CAM Inserts : UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.UPI_ALLCH", "PerPkg": "1", @@ -487,6 +586,7 @@ }, { "BriefDescription": "Prefetch CAM Inserts : XPT -All Channels", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_B2CMI_PREFCAM_INSERTS.XPT_ALLCH", "PerPkg": "1", @@ -496,118 +596,147 @@ }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_B2CMI_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm reads and WRNI which were a hi= t", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_B2CMI_TAG_HIT.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm reads which were a hit clean", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_B2CMI_TAG_HIT.RD_CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm reads which were a hit dirty", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_B2CMI_TAG_HIT.RD_DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm WRNI which were a hit clean", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_B2CMI_TAG_HIT.WR_CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm WRNI which were a hit dirty", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_B2CMI_TAG_HIT.WR_DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm second way read miss for a Rd", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.RD_2WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm reads which were a miss and th= e cache line is unmodified", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.RD_CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm reads which were a miss and th= e cache line is modified", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.RD_DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm second way read miss for a WrN= I", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.WR_2WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm WRNI which were a miss and the= cache line is unmodified", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.WR_CLEAN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "B2CMI" }, { "BriefDescription": "Counts the 2lm WRNI which were a miss and the= cache line is modified", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_B2CMI_TAG_MISS.WR_DIRTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "B2CMI" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_B2CMI_TRACKER_INSERTS.CH0", "PerPkg": "1", @@ -616,6 +745,7 @@ }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_B2CMI_TRACKER_OCCUPANCY.CH0", "PerPkg": "1", @@ -624,14 +754,17 @@ }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_B2CMI_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "B2CMI" }, { "BriefDescription": "UNC_B2HOT_CLOCKTICKS", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_B2HOT_CLOCKTICKS", "PerPkg": "1", @@ -640,6 +773,7 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_B2UPI_CLOCKTICKS", "PerPkg": "1", @@ -647,14 +781,17 @@ }, { "BriefDescription": "Total Write Cache Occupancy : Mem", + "Counter": "0,1,2,3", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "IRP Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -662,6 +799,7 @@ }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -669,21 +807,26 @@ }, { "BriefDescription": "FAF occupancy", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward : Snoop pu= lled away ownership before a write was committed", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.LOST_FWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Inbound write (fast path) requests to coheren= t memory, received by the IRP resulting in write ownership requests issued = by IRP to the mesh.", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -692,6 +835,7 @@ }, { "BriefDescription": "MDF Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_MDF_CLOCKTICKS", "PerPkg": "1", @@ -699,6 +843,7 @@ }, { "BriefDescription": "Number of UPI LL clock cycles while the event= is enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -707,45 +852,56 @@ }, { "BriefDescription": "Cycles in L1 : Number of UPI qfclk cycles spe= nt in L1 power mode. L1 is a mode that totally shuts down a UPI link. Use= edge detect to count the number of instances when the UPI link entered L1.= Link power states are per link and per direction, so for example the Tx d= irection could be in one state while Rx was in another. Because L1 totally = shuts down the link, it takes a good amount of time to exit this mode.", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10e", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Non-C= oherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10f", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", "PerPkg": "1", @@ -754,78 +910,97 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Reque= st, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Respo= nse - No Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10a", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= ", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Snoop= , Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x109", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port : Write= back", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", "PerPkg": "1", @@ -834,14 +1009,17 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port : Write= back, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10d", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : All Data : Shows legal= flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -850,8 +1028,10 @@ }, { "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Valid Flits Received : Null FLITs received f= rom any slot", "UMask": "0x27", @@ -859,38 +1039,47 @@ }, { "BriefDescription": "Valid Flits Received : Data : Shows legal fli= t time (hides impact of L0p and L0c). : Count Data Flits (which consume all= slots), but how much to count is based on Slot0-2 mask, so count can be 0-= 3 depending on which slots are enabled for counting..", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : Idle : Shows legal fli= t time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x47", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : LLCRD Not Empty : Show= s legal flit time (hides impact of L0p and L0c). : Enables counting of LLCR= D (with non-zero payload). This only applies to slot 2 since LLCRD is only = allowed in slot 2", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : LLCTRL : Shows legal f= lit time (hides impact of L0p and L0c). : Equivalent to an idle packet. En= ables counting of slot 0 LLCTRL messages.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : All Non Data : Shows l= egal flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -899,222 +1088,277 @@ }, { "BriefDescription": "Valid Flits Received : Slot NULL or LLCRD Emp= ty : Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all = zeros is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual= slot. This can apply to slot 0,1, or 2.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : Protocol Header : Show= s legal flit time (hides impact of L0p and L0c). : Enables count of protoco= l headers in slot 0,1,2 (depending on slot uMask bits)", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : Slot 0 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : Slot 1 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received : Slot 2 : Shows legal f= lit time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits de= termine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 0 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 1 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "RxQ Flit Buffer Allocations : Slot 2 : Number= of allocations into the UPI Rx Flit Buffer. Generally, when data is trans= mitted across UPI, it will bypass the RxQ and pass directly to the ring int= erface. If things back up getting transmitted onto the ring, however, it m= ay need to allocate into this buffer, thus increasing the latency. This ev= ent can be used in conjunction with the Flit Buffer Occupancy event in orde= r to calculate the average flit buffer lifetime.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "RxQ Occupancy - All Packets : Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Bypass, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10e", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Non-= Coherent Standard, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10f", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Requ= est, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x108", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10c", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Resp= onse - No Data, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10a", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Snoo= p, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x109", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port : Writ= eback, Match Opcode", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10d", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : All Data : Counts number o= f data flits across this UPI link.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -1123,6 +1367,7 @@ }, { "BriefDescription": "All Null Flits", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -1132,14 +1377,17 @@ }, { "BriefDescription": "Valid Flits Sent : Data : Shows legal flit ti= me (hides impact of L0p and L0c). : Count Data Flits (which consume all slo= ts), but how much to count is based on Slot0-2 mask, so count can be 0-3 de= pending on which slots are enabled for counting..", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : Idle : Shows legal flit ti= me (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.IDLE", "PerPkg": "1", @@ -1148,22 +1396,27 @@ }, { "BriefDescription": "Valid Flits Sent : LLCRD Not Empty : Shows le= gal flit time (hides impact of L0p and L0c). : Enables counting of LLCRD (w= ith non-zero payload). This only applies to slot 2 since LLCRD is only allo= wed in slot 2", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : LLCTRL : Shows legal flit = time (hides impact of L0p and L0c). : Equivalent to an idle packet. Enable= s counting of slot 0 LLCTRL messages.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : All Non Data : Shows legal= flit time (hides impact of L0p and L0c).", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -1173,55 +1426,69 @@ }, { "BriefDescription": "Valid Flits Sent : Slot NULL or LLCRD Empty := Shows legal flit time (hides impact of L0p and L0c). : LLCRD with all zero= s is treated as NULL. Slot 1 is not treated as NULL if slot 0 is a dual slo= t. This can apply to slot 0,1, or 2.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.NULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : Protocol Header : Shows le= gal flit time (hides impact of L0p and L0c). : Enables count of protocol he= aders in slot 0,1,2 (depending on slot uMask bits)", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : Slot 0 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 0 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : Slot 1 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 1 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent : Slot 2 : Shows legal flit = time (hides impact of L0p and L0c). : Count Slot 2 - Other mask bits determ= ine types of headers to count.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Allocations : Number of alloca= tions into the UPI Tx Flit Buffer. Generally, when data is transmitted acr= oss UPI, it will bypass the TxQ and pass directly to the link. However, th= e TxQ will be used with L0p and when LLR occurs, increasing latency to tran= sfer out to the link. This event can be used in conjunction with the Flit = Buffer Occupancy event in order to calculate the average flit buffer lifeti= me.", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy : Accumulates the nu= mber of flits in the TxQ. Generally, when data is transmitted across UPI, = it will bypass the TxQ and pass directly to the link. However, the TxQ wil= l be used with L0p and when LLR occurs, increasing latency to transfer out = to the link. This can be used with the cycles not empty event to track aver= age occupancy, or the allocations event to track average lifetime in the Tx= Q.", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" } diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json b/t= ools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json index 9495cb0f68ea..cffb9d94b53d 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "IIO Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -9,8 +10,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -19,8 +22,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -29,8 +34,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -39,8 +46,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -49,8 +58,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -59,8 +70,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -69,8 +82,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -79,8 +94,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -89,8 +106,10 @@ }, { "BriefDescription": "PCIE Completion Buffer Inserts. Counts once = per 64 byte read issued from this PCIE device.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -99,8 +118,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -109,8 +130,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -119,8 +142,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -129,8 +154,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -139,8 +166,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -149,8 +178,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -159,8 +190,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -169,8 +202,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -179,8 +214,10 @@ }, { "BriefDescription": "Count of allocations in the completion buffer= ", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -189,8 +226,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -199,8 +238,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -209,8 +250,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -219,8 +262,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -229,8 +274,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -239,8 +286,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -249,8 +298,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -259,8 +310,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -269,8 +322,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -279,8 +334,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -289,6 +346,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -299,6 +357,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -309,6 +368,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -319,6 +379,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -329,6 +390,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -339,6 +401,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -349,6 +412,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -359,6 +423,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ards MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -369,6 +434,7 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.ALL_PARTS", "FCMask": "0x07", @@ -379,6 +445,7 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", "FCMask": "0x07", @@ -389,6 +456,7 @@ }, { "BriefDescription": "Counts once for every 4 bytes read from this = card to memory. This event does include reads to IO.", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.ALL_PARTS", "FCMask": "0x07", @@ -399,6 +467,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -409,6 +478,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -419,6 +489,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -429,6 +500,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -439,6 +511,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -449,6 +522,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -459,6 +533,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -469,6 +544,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -479,6 +555,7 @@ }, { "BriefDescription": "Counts once for every 4 bytes written from th= is card to memory. This event does include writes to IO.", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.ALL_PARTS", "FCMask": "0x07", @@ -489,6 +566,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -499,6 +577,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -509,6 +588,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -519,6 +599,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -529,6 +610,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -539,6 +621,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -549,6 +632,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -559,6 +643,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -569,8 +654,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -579,8 +666,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -589,8 +678,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -599,8 +690,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -609,8 +702,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -619,8 +714,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -629,8 +726,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -639,8 +738,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -649,8 +750,10 @@ }, { "BriefDescription": "Counts once for every 4 bytes written from th= is card to a peer device's IO space.", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.ALL_PARTS", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -659,8 +762,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -669,8 +774,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -679,8 +786,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -689,8 +798,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -699,8 +810,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -709,8 +822,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -719,8 +834,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -729,8 +846,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -739,8 +858,10 @@ }, { "BriefDescription": "IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10", @@ -748,8 +869,10 @@ }, { "BriefDescription": "IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x8", @@ -757,8 +880,10 @@ }, { "BriefDescription": "IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x4", @@ -766,8 +891,10 @@ }, { "BriefDescription": "IOTLB lookups all", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x2", @@ -775,8 +902,10 @@ }, { "BriefDescription": "Context cache hits", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x80", @@ -784,8 +913,10 @@ }, { "BriefDescription": "Context cache lookups", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x40", @@ -793,8 +924,10 @@ }, { "BriefDescription": "IOTLB lookups first", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x1", @@ -802,8 +935,10 @@ }, { "BriefDescription": "IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20", @@ -811,8 +946,10 @@ }, { "BriefDescription": "IOMMU memory access (both low and high priori= ty)", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0xc0", @@ -820,8 +957,10 @@ }, { "BriefDescription": "IOMMU high priority memory access", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_HIGH", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x80", @@ -829,8 +968,10 @@ }, { "BriefDescription": "IOMMU low priority memory access", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES_LOW", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x40", @@ -838,8 +979,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 1G page= ", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x4", @@ -847,8 +990,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 256T pa= ge", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_256T_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10", @@ -856,8 +1001,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 2M page= ", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x2", @@ -865,8 +1012,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache Hit to a 512G pa= ge", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x8", @@ -874,8 +1023,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20", @@ -883,8 +1034,10 @@ }, { "BriefDescription": "Second Level Page Walk Cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.SLPWC_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x1", @@ -892,8 +1045,10 @@ }, { "BriefDescription": "Cycles PWT full", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.CYC_PWT_FULL", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x2", @@ -901,8 +1056,10 @@ }, { "BriefDescription": "Interrupt Entry cache hit", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x80", @@ -910,8 +1067,10 @@ }, { "BriefDescription": "Interrupt Entry cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x40", @@ -919,8 +1078,10 @@ }, { "BriefDescription": "Context Cache invalidation events", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_CTXT_CACHE", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x8", @@ -928,8 +1089,10 @@ }, { "BriefDescription": "Interrupt Entry Cache invalidation events", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_INT_CACHE", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x20", @@ -937,8 +1100,10 @@ }, { "BriefDescription": "IOTLB invalidation events", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_IOTLB", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x4", @@ -946,8 +1111,10 @@ }, { "BriefDescription": "PASID Cache invalidation events", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PASID_CACHE", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "UMask": "0x10", @@ -955,8 +1122,10 @@ }, { "BriefDescription": "Occupancy of outbound request queue : To devi= ce : Counts number of outbound requests/completions IIO is currently proces= sing", + "Counter": "2,3", "EventCode": "0xc5", "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -965,8 +1134,10 @@ }, { "BriefDescription": "Passing data to be written", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -975,8 +1146,10 @@ }, { "BriefDescription": "Issuing final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -985,8 +1158,10 @@ }, { "BriefDescription": "Processing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -995,8 +1170,10 @@ }, { "BriefDescription": "Issuing to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1005,8 +1182,10 @@ }, { "BriefDescription": "Request Ownership", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1015,8 +1194,10 @@ }, { "BriefDescription": "Writing line", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1025,8 +1206,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1035,8 +1218,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1045,8 +1230,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1055,8 +1242,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1065,8 +1254,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1075,8 +1266,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1085,8 +1278,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1095,8 +1290,10 @@ }, { "BriefDescription": "-", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x0FF", @@ -1105,14 +1302,17 @@ }, { "BriefDescription": "All 9 bits of Page Walk Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PortMask": "0x000", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.ALL_PARTS", "FCMask": "0x07", @@ -1123,6 +1323,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1133,6 +1334,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1143,6 +1345,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1153,6 +1356,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1163,6 +1367,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1173,6 +1378,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1183,6 +1389,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1193,6 +1400,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1203,6 +1411,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.ALL_PARTS", "FCMask": "0x07", @@ -1213,6 +1422,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1223,6 +1433,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1233,6 +1444,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1243,6 +1455,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1253,6 +1466,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1263,6 +1477,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1273,6 +1488,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1283,6 +1499,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Cards MMIO space", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1293,6 +1510,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.ALL_PARTS", "FCMask": "0x07", @@ -1303,6 +1521,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.ALL_PARTS", "FCMask": "0x07", @@ -1313,6 +1532,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1323,6 +1543,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1333,6 +1554,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1343,6 +1565,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1353,6 +1576,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1363,6 +1587,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1373,6 +1598,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1383,6 +1609,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1393,6 +1620,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1403,6 +1631,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1413,6 +1642,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1423,6 +1653,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1433,6 +1664,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1443,6 +1675,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1453,6 +1686,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1463,6 +1697,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1473,8 +1708,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -1483,8 +1720,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -1493,8 +1732,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -1503,8 +1744,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -1513,8 +1756,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -1523,8 +1768,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -1533,8 +1780,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -1543,8 +1792,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", @@ -1553,8 +1804,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x001", @@ -1563,8 +1816,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x002", @@ -1573,8 +1828,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x004", @@ -1583,8 +1840,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x008", @@ -1593,8 +1852,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x010", @@ -1603,8 +1864,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x020", @@ -1613,8 +1876,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x040", @@ -1623,8 +1888,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x080", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json= b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json index a2405ed640c9..7e6e6764f181 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DRAM Activate Count : Counts the number of DR= AM Activate commands sent on this channel. Activate commands are issued to= open up a page on the DRAM devices so that it can be read or written to wi= th a CAS. One can calculate the number of Page Misses by subtracting the n= umber of Page Miss precharges from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -9,30 +10,37 @@ }, { "BriefDescription": "DRAM Activate Count : Read transaction on Pag= e Empty or Page Miss : Counts the number of DRAM Activate commands sent on = this channel. Activate commands are issued to open up a page on the DRAM d= evices so that it can be read or written to with a CAS. One can calculate = the number of Page Misses by subtracting the number of Page Miss precharges= from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf1", "Unit": "IMC" }, { "BriefDescription": "DRAM Activate Count : Underfill Read transact= ion on Page Empty or Page Miss : Counts the number of DRAM Activate command= s sent on this channel. Activate commands are issued to open up a page on = the DRAM devices so that it can be read or written to with a CAS. One can = calculate the number of Page Misses by subtracting the number of Page Miss = precharges from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf4", "Unit": "IMC" }, { "BriefDescription": "DRAM Activate Count : Write transaction on Pa= ge Empty or Page Miss : Counts the number of DRAM Activate commands sent on= this channel. Activate commands are issued to open up a page on the DRAM = devices so that it can be read or written to with a CAS. One can calculate= the number of Page Misses by subtracting the number of Page Miss precharge= s from the number of Activates.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_ACT_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf2", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 0, all CAS operation= s", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.ALL", "PerPkg": "1", @@ -41,6 +49,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0, all reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD", "PerPkg": "1", @@ -49,6 +58,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0 regular reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG", "PerPkg": "1", @@ -57,6 +67,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0 underfill reads", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL", "PerPkg": "1", @@ -65,6 +76,7 @@ }, { "BriefDescription": "CAS count for SubChannel 0, all writes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR", "PerPkg": "1", @@ -73,22 +85,27 @@ }, { "BriefDescription": "CAS count for SubChannel 0 regular writes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 0 auto-precharge wri= tes", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 1, all CAS operation= s", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.ALL", "PerPkg": "1", @@ -97,6 +114,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1, all reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD", "PerPkg": "1", @@ -105,6 +123,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1 regular reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG", "PerPkg": "1", @@ -113,6 +132,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1 underfill reads", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL", "PerPkg": "1", @@ -121,6 +141,7 @@ }, { "BriefDescription": "CAS count for SubChannel 1, all writes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR", "PerPkg": "1", @@ -129,22 +150,27 @@ }, { "BriefDescription": "CAS count for SubChannel 1 regular writes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd0", "Unit": "IMC" }, { "BriefDescription": "CAS count for SubChannel 1 auto-precharge wri= tes", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe0", "Unit": "IMC" }, { "BriefDescription": "Number of DRAM DCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", @@ -154,14 +180,17 @@ }, { "BriefDescription": "Number of DRAM HCLK clock cycles while the ev= ent is enabled", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_HCLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Clockticks", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -170,6 +199,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to (= ?) : Counts the number of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -178,46 +208,57 @@ }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf1", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.UFILL", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf4", "Unit": "IMC" }, { "BriefDescription": "DRAM Precharge commands. : Counts the number = of DRAM Precharge commands sent on this channel.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf2", "Unit": "IMC" }, { "BriefDescription": "Read buffer inserts on subchannel 0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.SCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IMC" }, { "BriefDescription": "Read buffer inserts on subchannel 1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS.SCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IMC" }, { "BriefDescription": "Read buffer occupancy on subchannel 0", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M_RDB_OCCUPANCY_SCH0", "PerPkg": "1", @@ -225,6 +266,7 @@ }, { "BriefDescription": "Read buffer occupancy on subchannel 1", + "Counter": "0,1,2,3", "EventCode": "0x1b", "EventName": "UNC_M_RDB_OCCUPANCY_SCH1", "PerPkg": "1", @@ -232,22 +274,27 @@ }, { "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "IMC" }, { "BriefDescription": "Read Pending Queue Allocations : Counts the n= umber of allocations into the Read Pending Queue. This queue is used to sc= hedule reads out to the memory controller and to track the requests. Reque= sts allocate into the RPQ soon after they enter the memory controller, and = need credits for an entry in this buffer before being sent from the HA to t= he iMC. They deallocate after the CAS command has been issued to memory. = This includes both ISOCH and non-ISOCH requests.", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "IMC" }, { "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0", "PerPkg": "1", @@ -256,6 +303,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 0, = pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1", "PerPkg": "1", @@ -264,6 +312,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0", "PerPkg": "1", @@ -272,6 +321,7 @@ }, { "BriefDescription": "Read Pending Queue inserts for subchannel 1, = pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1", "PerPkg": "1", @@ -280,6 +330,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0", "PerPkg": "1", @@ -287,6 +338,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 0= , pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1", "PerPkg": "1", @@ -294,6 +346,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0", "PerPkg": "1", @@ -301,6 +354,7 @@ }, { "BriefDescription": "Read pending queue occupancy for subchannel 1= , pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1", "PerPkg": "1", @@ -308,22 +362,27 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.PCH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "IMC" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.PCH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "IMC" }, { "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0", "PerPkg": "1", @@ -332,6 +391,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 0,= pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1", "PerPkg": "1", @@ -340,6 +400,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0", "PerPkg": "1", @@ -348,6 +409,7 @@ }, { "BriefDescription": "Write Pending Queue inserts for subchannel 1,= pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1", "PerPkg": "1", @@ -356,6 +418,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0", "PerPkg": "1", @@ -363,6 +426,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 0, pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1", "PerPkg": "1", @@ -370,6 +434,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0", "PerPkg": "1", @@ -377,6 +442,7 @@ }, { "BriefDescription": "Write pending queue occupancy for subchannel = 1, pseudochannel 1", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json = b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json index e3a66166e28c..02e59f64a544 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/uncore-power.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCU Clockticks", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.jso= n b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json index 371974c6d6c3..35cc5b6d41f2 100644 --- a/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/sierraforest/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccounts for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or Loads (demand or SW prefetch) in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for Loads (demand or SW prefetch) in PMH every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Accounts= for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "SampleAfterValue": "2000003", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -61,6 +69,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A PMH page walk is o= utstanding from page walk start till PMH becomes idle again (ready to serve= next walk). Includes EPT-walk intervals.", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Counts the number of page walks initiated by = a instruction fetch that missed the first and second level TLBs.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSED_WALK", "SampleAfterValue": "1000003", @@ -84,6 +95,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -91,6 +103,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -99,6 +112,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -107,6 +121,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -115,6 +130,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or iside in PMH every cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for iside in PMH every cycle. A PMH page walk is outstanding from page wal= k start till PMH becomes idle again (ready to serve next walk). Includes EP= T-walk intervals. Walks could be counted by edge detecting on this event, = but would count restarted suspended walks.", @@ -123,6 +139,7 @@ }, { "BriefDescription": "Counts the number of cycles that the head (ol= dest load) of the load buffer and retirement are both stalled due to a DTLB= miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x05", "EventName": "LD_HEAD.DTLB_MISS_AT_RET", "SampleAfterValue": "1000003", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-yb1-f201.google.com (mail-yb1-f201.google.com [209.85.219.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 043171B29DA for ; Thu, 20 Jun 2024 18:20:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718907669; cv=none; b=SPphhoIJzeynjrc1+Jc2EOUPnSKOYTIgdjl0fLWy25Uyroz/Ybx8Kh8XgX31cYVQ1fE4D+VwqeLj2HGloPB3Ly7EVwC/WqVN1cPDsGbKU+wE2fpA7zl30EHl6kpwW7BKAa3F1fcY8oCwCQULswUscsnDYyuL7wT/1RrN0q5871k= ARC-Message-Signature: i=1; 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charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/silvermont/cache.json | 77 +++++++++++++++++++ .../arch/x86/silvermont/counter.json | 7 ++ .../arch/x86/silvermont/floating-point.json | 1 + .../arch/x86/silvermont/frontend.json | 8 ++ .../arch/x86/silvermont/memory.json | 1 + .../pmu-events/arch/x86/silvermont/other.json | 2 + .../arch/x86/silvermont/pipeline.json | 34 ++++++++ .../arch/x86/silvermont/virtual-memory.json | 7 ++ 8 files changed, 137 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/silvermont/counter.json diff --git a/tools/perf/pmu-events/arch/x86/silvermont/cache.json b/tools/p= erf/pmu-events/arch/x86/silvermont/cache.json index 818e0664a3a6..5e5e2170fd8f 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/cache.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of request that were not ac= cepted into the L2Q because the L2Q is FULL.", + "Counter": "0,1", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ALL", "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2Q due to a full or nearly full w condi= tion which likely indicates back pressure from L2Q. It also counts request= s that would have gone directly to the XQ, but are rejected due to a full o= r nearly full condition, indicating back pressure from the IDI link. The L= 2Q may also reject transactions from a core to insure fairness between cor= es, or to delay a core?s dirty eviction when the address conflicts incoming= external snoops. (Note that L2 prefetcher requests that are dropped are n= ot counted by this event.)", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ICache miss.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "FETCH_STALL.ICACHE_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ICache miss. That is, the decoder queue is able to accept byt= es, but the fetch unit is unable to provide bytes due to an ICache miss. N= ote: this event is not the same as the total number of cycles spent retriev= ing instruction cache lines from the memory hierarchy.\r\nCounts cycles tha= t fetch is stalled due to any reason. That is, the decoder queue is able to= accept bytes, but the fetch unit is unable to provide bytes. This will in= clude cycles due to an ITLB miss, ICache miss and other events.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of request from the L2 that= were not accepted into the XQ", + "Counter": "0,1", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ALL", "PublicDescription": "This event counts the number of demand and p= refetch transactions that the L2 XQ rejects due to a full or near full cond= ition which likely indicates back pressure from the IDI link. The XQ may re= ject transactions from the L2Q (non-cacheable requests), BBS (L2 misses) an= d WOB (L2 write-back victims).", @@ -23,6 +26,7 @@ }, { "BriefDescription": "L2 cache request misses", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "This event counts the total number of L2 cac= he references and the number of L2 cache misses respectively.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "L2 cache requests from this core", + "Counter": "0,1", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "This event counts requests originating from = the core that references a cache line in the L2 cache.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "All Loads", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "PublicDescription": "This event counts the number of load ops ret= ired.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "All Stores", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", "PublicDescription": "This event counts the number of store ops re= tired.", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Cross core or cross module hitm", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.HITM", "PEBS": "1", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Loads missed L1", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L1_MISS_LOADS", "PublicDescription": "This event counts the number of load ops ret= ired that miss in L1 Data cache. Note that prefetch misses will not be coun= ted.", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Loads hit L2", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_HIT_LOADS", "PEBS": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Loads missed L2", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.L2_MISS_LOADS", "PEBS": "1", @@ -90,6 +101,7 @@ }, { "BriefDescription": "Loads missed UTLB", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.UTLB_MISS", "PublicDescription": "This event counts the number of load ops ret= ired that had UTLB miss.", @@ -98,6 +110,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -106,6 +119,7 @@ }, { "BriefDescription": "Counts any code reads (demand & prefetch) tha= t have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Counts any code reads (demand & prefetch) tha= t hit in the other module where modified copies were found in other core's = L1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -133,6 +149,7 @@ }, { "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 and the snoops to sibling cores hit in either E/S state and the l= ine is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -142,6 +159,7 @@ }, { "BriefDescription": "Counts any code reads (demand & prefetch) tha= t miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -151,6 +169,7 @@ }, { "BriefDescription": "Counts any data read (demand & prefetch) that= have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -160,6 +179,7 @@ }, { "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -169,6 +189,7 @@ }, { "BriefDescription": "Counts any data read (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +199,7 @@ }, { "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Counts any data read (demand & prefetch) that= miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +219,7 @@ }, { "BriefDescription": "Counts any request that have any response typ= e.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +229,7 @@ }, { "BriefDescription": "Counts any request that hit in the other modu= le where modified copies were found in other core's L1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HITM_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +239,7 @@ }, { "BriefDescription": "Counts any request that miss L2 and the snoop= s to sibling cores hit in either E/S state and the line is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.HIT_OTHER_CORE_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +249,7 @@ }, { "BriefDescription": "Counts any request that miss L2 with a snoop = miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +259,7 @@ }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that= have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +269,7 @@ }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -250,6 +279,7 @@ }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that= hit in the other module where modified copies were found in other core's L= 1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -259,6 +289,7 @@ }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.HIT_OTHER_CORE_NO_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -268,6 +299,7 @@ }, { "BriefDescription": "Counts any rfo reads (demand & prefetch) that= miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -277,6 +309,7 @@ }, { "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -286,6 +319,7 @@ }, { "BriefDescription": "Counts writeback (modified to exclusive) that= miss L2 with no details on snoop-related information.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.L2_MISS.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -295,6 +329,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +339,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -313,6 +349,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 and the snoops to sibling cores hit in either E/S stat= e and the line is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -322,6 +359,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -331,6 +369,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch instruction ca= cheline that are are outstanding, per cycle, from the time of the L2 miss t= o when any response is received.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -340,6 +379,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -349,6 +389,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -358,6 +399,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HITM_OTHER_C= ORE", "MSRIndex": "0x1a6,0x1a7", @@ -367,6 +409,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.HIT_OTHER_CO= RE_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -376,6 +419,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -385,6 +429,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch data read that= are are outstanding, per cycle, from the time of the L2 miss to when any r= esponse is received.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -394,6 +439,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -403,6 +449,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that hit = in the other module where modified copies were found in other core's L1 cac= he.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -412,6 +459,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 and the snoops to sibling cores hit in either E/S state and the line is= not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that miss= L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -430,6 +479,7 @@ }, { "BriefDescription": "Counts demand and DCU prefetch RFOs that are = are outstanding, per cycle, from the time of the L2 miss to when any respon= se is received.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -439,6 +489,7 @@ }, { "BriefDescription": "Counts demand reads of partial cache lines (i= ncluding UC and WC) that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_READS.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -448,6 +499,7 @@ }, { "BriefDescription": "Countsof demand RFO requests to write to part= ial cache lines that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PARTIAL_WRITES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -457,6 +509,7 @@ }, { "BriefDescription": "Counts DCU hardware prefetcher data read that= have any response type.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -466,6 +519,7 @@ }, { "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -475,6 +529,7 @@ }, { "BriefDescription": "Counts DCU hardware prefetcher data read that= hit in the other module where modified copies were found in other core's L= 1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -484,6 +539,7 @@ }, { "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 and the snoops to sibling cores hit in either E/S state and the li= ne is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -493,6 +549,7 @@ }, { "BriefDescription": "Counts DCU hardware prefetcher data read that= miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L1_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -502,6 +559,7 @@ }, { "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -511,6 +569,7 @@ }, { "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 and the snoops to sibling cores hit in either E/S state and t= he line is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -520,6 +579,7 @@ }, { "BriefDescription": "Counts code reads generated by L2 prefetchers= that miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -529,6 +589,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -538,6 +599,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that hit in the other module where modified copies were found in= other core's L1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -547,6 +609,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 and the snoops to sibling cores hit in either E/S s= tate and the line is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -556,6 +619,7 @@ }, { "BriefDescription": "Counts data cacheline reads generated by L2 p= refetchers that miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -565,6 +629,7 @@ }, { "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +639,7 @@ }, { "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that hit in the other module where modified copies were found in other c= ore's L1 cache.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -583,6 +649,7 @@ }, { "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 and the snoops to sibling cores hit in either E/S state and= the line is not forwarded.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -592,6 +659,7 @@ }, { "BriefDescription": "Counts RFO requests generated by L2 prefetche= rs that miss L2 with a snoop miss response.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L2_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -601,6 +669,7 @@ }, { "BriefDescription": "Counts streaming store that miss L2.", + "Counter": "0,1", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.STREAMING_STORES.L2_MISS.ANY", "MSRIndex": "0x1a6,0x1a7", @@ -610,6 +679,7 @@ }, { "BriefDescription": "Any reissued load uops", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ANY_LD", "PublicDescription": "This event counts the number of load uops re= issued from Rehabq.", @@ -618,6 +688,7 @@ }, { "BriefDescription": "Any reissued store uops", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ANY_ST", "PublicDescription": "This event counts the number of store uops r= eissued from Rehabq.", @@ -626,6 +697,7 @@ }, { "BriefDescription": "Loads blocked due to store data not ready", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_BLOCK_STD_NOTREADY", "PublicDescription": "This event counts the cases where a forward = was technically possible, but did not occur because the store data was not = available at the right time.", @@ -634,6 +706,7 @@ }, { "BriefDescription": "Loads blocked due to store forward restrictio= n", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_BLOCK_ST_FORWARD", "PEBS": "1", @@ -643,6 +716,7 @@ }, { "BriefDescription": "Load uops that split cache line boundary", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LD_SPLITS", "PEBS": "1", @@ -652,6 +726,7 @@ }, { "BriefDescription": "Uops with lock semantics", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.LOCK", "PublicDescription": "This event counts the number of retired memo= ry operations with lock semantics. These are either implicit locked instruc= tions such as the XCHG instruction or instructions with an explicit LOCK pr= efix (0xF0).", @@ -660,6 +735,7 @@ }, { "BriefDescription": "Store address buffer full", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.STA_FULL", "PublicDescription": "This event counts the number of retired stor= es that are delayed because there is not a store address buffer available.", @@ -668,6 +744,7 @@ }, { "BriefDescription": "Store uops that split cache line boundary", + "Counter": "0,1", "EventCode": "0x03", "EventName": "REHABQ.ST_SPLITS", "PublicDescription": "This event counts the number of retire store= s that experienced cache line boundary splits.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/counter.json b/tools= /perf/pmu-events/arch/x86/silvermont/counter.json new file mode 100644 index 000000000000..eb89b55f31bd --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/silvermont/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json = b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json index f2b1e8f08d68..aa4faf110512 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Stalls due to FP assists", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "This event counts the number of times that p= ipeline stalled due to FP operations needing assists.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json b/tool= s/perf/pmu-events/arch/x86/silvermont/frontend.json index cd6ed3f59e26..fc6cfb291249 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/frontend.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of baclears", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.ALL", "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.ANY event counts the number of ba= clears for any type of branch.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of JCC baclears", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.COND", "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.COND event counts the number of J= CC (Jump on Conditional Code) baclears.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of RETURN baclears", + "Counter": "0,1", "EventCode": "0xE6", "EventName": "BACLEARS.RETURN", "PublicDescription": "The BACLEARS event counts the number of time= s the front end is resteered, mainly when the Branch Prediction Unit cannot= provide a correct prediction and this is corrected by the Branch Address C= alculator at the front end. The BACLEARS.RETURN event counts the number of= RETURN baclears.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of times a decode restricti= on reduced the decode throughput due to wrong instruction length prediction= ", + "Counter": "0,1", "EventCode": "0xE9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "PublicDescription": "Counts the number of times a decode restrict= ion reduced the decode throughput due to wrong instruction length predictio= n.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Instruction fetches", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "This event counts all instruction fetches, n= ot including most uncacheable\r\nfetches.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Instruction fetches from Icache", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "This event counts all instruction fetches fr= om the instruction cache.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Icache miss", + "Counter": "0,1", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "This event counts all instruction fetches th= at miss the Instruction cache or produce memory requests. This includes unc= acheable fetches. An instruction fetch miss is counted only once and not on= ce for every cycle it is outstanding.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts the number of times entered into a uco= de flow in the FEC. Includes inserted flows due to front-end detected faul= ts or assists. Speculative count.", + "Counter": "0,1", "EventCode": "0xE7", "EventName": "MS_DECODED.MS_ENTRY", "PublicDescription": "Counts the number of times the MSROM starts = a flow of UOPS. It does not count every time a UOP is read from the microco= de ROM. The most common case that this counts is when a micro-coded instru= ction is encountered by the front end of the machine. Other cases include = when an instruction encounters a fault, trap, or microcode assist of any so= rt. The event will count MSROM startups for UOPS that are speculative, and= subsequently cleared by branch mispredict or machine clear. Background: U= OPS are produced by two mechanisms. Either they are generated by hardware = that decodes instructions into UOPS, or they are delivered by a ROM (called= the MSROM) that holds UOPS associated with a specific instruction. MSROM = UOPS might also be delivered in response to some condition such as a fault = or other exceptional condition. This event is an excellent mechanism for d= etecting instructions that require the use of MSROM instructions.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/memory.json b/tools/= perf/pmu-events/arch/x86/silvermont/memory.json index 15ea45187210..0f5fba43da4c 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Stalls due to Memory ordering", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "This event counts the number of times that p= ipeline was cleared due to memory ordering issues.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/other.json b/tools/p= erf/pmu-events/arch/x86/silvermont/other.json index cff113adb823..4db59d84c144 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/other.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles code-fetch stalled due to any reason.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "FETCH_STALL.ALL", "PublicDescription": "Counts cycles that fetch is stalled due to a= ny reason. That is, the decoder queue is able to accept bytes, but the fetc= h unit is unable to provide bytes. This will include cycles due to an ITLB= miss, ICache miss and other events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles code-fetch stalled due to an outstandi= ng ITLB miss.", + "Counter": "0,1", "EventCode": "0x86", "EventName": "FETCH_STALL.ITLB_FILL_PENDING_CYCLES", "PublicDescription": "Counts cycles that fetch is stalled due to a= n outstanding ITLB miss. That is, the decoder queue is able to accept bytes= , but the fetch unit is unable to provide bytes due to an ITLB miss. Note:= this event is not the same as page walk cycles to retrieve an instruction = translation.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json b/tool= s/perf/pmu-events/arch/x86/silvermont/pipeline.json index 2d4214bf9e39..48ca8bb2656b 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of branch instructions reti= red...", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of taken branch instruction= s retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_TAKEN_BRANCHES", "PEBS": "2", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", @@ -45,6 +50,7 @@ }, { "BriefDescription": "Counts the number of JCC branch instructions = retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", @@ -54,6 +60,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -63,6 +70,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -72,6 +80,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", @@ -81,6 +90,7 @@ }, { "BriefDescription": "Counts the number of taken JCC branch instruc= tions retired", + "Counter": "0,1", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -90,6 +100,7 @@ }, { "BriefDescription": "Counts the number of mispredicted branch inst= ructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC branch = instructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC b= ranch instructions retired", + "Counter": "0,1", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = core clock cycles", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. This event is a component in many key event ratios.= The core frequency may change from time to time. For this reason this eve= nt may have a changing ratio with regards to time. In systems with a consta= nt core frequency, this event can give you a measurement of the elapsed tim= e while the core was not in halt state by dividing the event count by the c= ore frequency. This event is architecturally defined and is a designated fi= xed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P use the cor= e frequency which may change from time to time. CPU_CLK_UNHALTE.REF_TSC an= d CPU_CLK_UNHALTED.REF are not affected by core frequency changes but count= s as if the core is running at the maximum frequency all the time. The fix= ed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC and the pr= ogrammable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTED.REF.", "SampleAfterValue": "2000003", @@ -150,6 +167,7 @@ }, { "BriefDescription": "Core cycles when core is not halted", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "This event counts the number of core cycles = while the core is not in a halt state. The core enters the halt state when = it is running the HLT instruction. In mobile systems the core frequency may= change from time to time. For this reason this event may have a changing r= atio with regards to time.", @@ -157,6 +175,7 @@ }, { "BriefDescription": "Reference cycles when core is not halted", + "Counter": "0,1", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "This event counts the number of reference cy= cles that the core is not in a halt state. The core enters the halt state w= hen it is running the HLT instruction. In mobile systems the core frequency= may change from time. This event is not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= .", @@ -165,6 +184,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of unhalted = reference clock cycles", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles while = the core is not in a halt state. The core enters the halt state when it is = running the HLT instruction. This event is a component in many key event ra= tios. The core frequency may change from time. This event is not affected = by core frequency changes but counts as if the core is running at the maxim= um frequency all the time. Divide this event count by core frequency to de= termine the elapsed time while the core was not in halt state. Divide this= event count by core frequency to determine the elapsed time while the core= was not in halt state. This event is architecturally defined and is a des= ignated fixed counter. CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.CORE_P u= se the core frequency which may change from time to time. CPU_CLK_UNHALTE.= REF_TSC and CPU_CLK_UNHALTED.REF are not affected by core frequency changes= but counts as if the core is running at the maximum frequency all the time= . The fixed events are CPU_CLK_UNHALTED.CORE and CPU_CLK_UNHALTED.REF_TSC = and the programmable events are CPU_CLK_UNHALTED.CORE_P and CPU_CLK_UNHALTE= D.REF.", "SampleAfterValue": "2000003", @@ -172,6 +192,7 @@ }, { "BriefDescription": "Cycles the divider is busy. Does not imply a= stall waiting for the divider.", + "Counter": "0,1", "EventCode": "0xCD", "EventName": "CYCLES_DIV_BUSY.ALL", "PublicDescription": "Cycles the divider is busy.This event counts= the cycles when the divide unit is unable to accept a new divide UOP becau= se it is busy processing a previously dispatched UOP. The cycles will be co= unted irrespective of whether or not another divide UOP is waiting to enter= the divide unit (from the RS). This event might count cycles while a divid= e is in progress even if the RS is empty. The divide instruction is one of= the longest latency instructions in the machine. Hence, it has a special = event associated with it to help determine if divides are delaying the reti= rement of instructions.", @@ -180,6 +201,7 @@ }, { "BriefDescription": "Fixed Counter: Counts the number of instructi= ons retired", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "PublicDescription": "This event counts the number of instructions= that retire. For instructions that consist of multiple micro-ops, this ev= ent counts exactly once, as the last micro-op of the instruction retires. = The event continues counting while instructions retire, including during in= terrupt service routines caused by hardware interrupts, faults or traps. B= ackground: Modern microprocessors employ extensive pipelining and speculati= ve techniques. Since sometimes an instruction is started but never complet= ed, the notion of \"retirement\" is introduced. A retired instruction is o= ne that commits its states. Or stated differently, an instruction might be = abandoned at some point. No instruction is truly finished until it retires.= This counter measures the number of completed instructions. The fixed ev= ent is INST_RETIRED.ANY and the programmable event is INST_RETIRED.ANY_P.", "SampleAfterValue": "2000003", @@ -187,6 +209,7 @@ }, { "BriefDescription": "Instructions retired", + "Counter": "0,1", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PublicDescription": "This event counts the number of instructions= that retire execution. For instructions that consist of multiple micro-ops= , this event counts the retirement of the last micro-op of the instruction.= The counter continues counting during hardware interrupts, traps, and insi= de interrupt handlers.", @@ -194,6 +217,7 @@ }, { "BriefDescription": "Counts all machine clears", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.ALL", "PublicDescription": "Machine clears happen when something happens= in the machine that causes the hardware to need to take special care to ge= t the right answer. When such a condition is signaled on an instruction, th= e front end of the machine is notified that it must restart, so no more ins= tructions will be decoded from the current path. All instructions \"older\= " than this one will be allowed to finish. This instruction and all \"youn= ger\" instructions must be cleared, since they must not be allowed to compl= ete. Essentially, the hardware waits until the problematic instruction is = the oldest instruction in the machine. This means all older instructions a= re retired, and all pending stores (from older instructions) are completed.= Then the new path of instructions from the front end are allowed to start= into the machine. There are many conditions that might cause a machine cl= ear (including the receipt of an interrupt, or a trap or a fault). All tho= se conditions (including but not limited to MACHINE_CLEARS.MEMORY_ORDERING,= MACHINE_CLEARS.SMC, and MACHINE_CLEARS.FP_ASSIST) are captured in the ANY = event. In addition, some conditions can be specifically counted (i.e. SMC, = MEMORY_ORDERING, FP_ASSIST). However, the sum of SMC, MEMORY_ORDERING, and= FP_ASSIST machine clears will not necessarily equal the number of ANY.", @@ -202,6 +226,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "This event counts the number of times that a= program writes to a code section. Self-modifying code causes a severe pena= lty in all Intel? architecture processors.", @@ -210,6 +235,7 @@ }, { "BriefDescription": "Counts the number of cycles when no uops are = allocated for any reason.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.ALL", "PublicDescription": "The NO_ALLOC_CYCLES.ALL event counts the num= ber of cycles when the front-end does not provide any instructions to be al= located for any reason. This event indicates the cycles where an allocation= stalls occurs, and no UOPS are allocated in that cycle.", @@ -218,6 +244,7 @@ }, { "BriefDescription": "Counts the number of cycles when no uops are = allocated and the alloc pipe is stalled waiting for a mispredicted jump to = retire. After the misprediction is detected, the front end will start imme= diately but the allocate pipe stalls until the mispredicted", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.MISPREDICTS", "PublicDescription": "Counts the number of cycles when no uops are= allocated and the alloc pipe is stalled waiting for a mispredicted jump to= retire. After the misprediction is detected, the front end will start imm= ediately but the allocate pipe stalls until the mispredicted.", @@ -226,6 +253,7 @@ }, { "BriefDescription": "Counts the number of cycles when no uops are = allocated, the IQ is empty, and no other condition is blocking allocation.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.NOT_DELIVERED", "PublicDescription": "The NO_ALLOC_CYCLES.NOT_DELIVERED event is u= sed to measure front-end inefficiencies, i.e. when front-end of the machine= is not delivering micro-ops to the back-end and the back-end is not stalle= d. This event can be used to identify if the machine is truly front-end bou= nd. When this event occurs, it is an indication that the front-end of the = machine is operating at less than its theoretical peak performance. Backgr= ound: We can think of the processor pipeline as being divided into 2 broade= r parts: Front-end and Back-end. Front-end is responsible for fetching the = instruction, decoding into micro-ops (uops) in machine understandable forma= t and putting them into a micro-op queue to be consumed by back end. The ba= ck-end then takes these micro-ops, allocates the required resources. When = all resources are ready, micro-ops are executed. If the back-end is not rea= dy to accept micro-ops from the front-end, then we do not want to count the= se as front-end bottlenecks. However, whenever we have bottlenecks in the = back-end, we will have allocation unit stalls and eventually forcing the fr= ont-end to wait until the back-end is ready to receive more UOPS. This even= t counts the cycles only when back-end is requesting more uops and front-en= d is not able to provide them. Some examples of conditions that cause front= -end efficiencies are: Icache misses, ITLB misses, and decoder restrictions= that limit the front-end bandwidth.", @@ -234,6 +262,7 @@ }, { "BriefDescription": "Counts the number of cycles when no uops are = allocated and a RATstall is asserted.", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.RAT_STALL", "SampleAfterValue": "200003", @@ -241,6 +270,7 @@ }, { "BriefDescription": "Counts the number of cycles when no uops are = allocated and the ROB is full (less than 2 entries available)", + "Counter": "0,1", "EventCode": "0xCA", "EventName": "NO_ALLOC_CYCLES.ROB_FULL", "PublicDescription": "Counts the number of cycles when no uops are= allocated and the ROB is full (less than 2 entries available).", @@ -249,6 +279,7 @@ }, { "BriefDescription": "Counts the number of cycles the Alloc pipelin= e is stalled when any one of the RSs (IEC, FPC and MEC) is full. This event= is a superset of all the individual RS stall event counts.", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "RS_FULL_STALL.ALL", "SampleAfterValue": "200003", @@ -256,6 +287,7 @@ }, { "BriefDescription": "Counts the number of cycles and allocation pi= peline is stalled and is waiting for a free MEC reservation station entry. = The cycles should be appropriately counted in case of the cracked ops e.g.= In case of a cracked load-op, the load portion is sent to M", + "Counter": "0,1", "EventCode": "0xCB", "EventName": "RS_FULL_STALL.MEC", "PublicDescription": "Counts the number of cycles and allocation p= ipeline is stalled and is waiting for a free MEC reservation station entry.= The cycles should be appropriately counted in case of the cracked ops e.g= . In case of a cracked load-op, the load portion is sent to M.", @@ -264,6 +296,7 @@ }, { "BriefDescription": "Micro-ops retired", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ALL", "PublicDescription": "This event counts the number of micro-ops re= tired. The processor decodes complex macro instructions into a sequence of = simpler micro-ops. Most instructions are composed of one or two micro-ops. = Some instructions are decoded into longer sequences such as repeat instruct= ions, floating point transcendental instructions, and assists. In some case= s micro-op sequences are fused or whole instructions are fused into one mic= ro-op. See other UOPS_RETIRED events for differentiating retired fused and = non-fused micro-ops.", @@ -272,6 +305,7 @@ }, { "BriefDescription": "MSROM micro-ops retired", + "Counter": "0,1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MS", "PublicDescription": "This event counts the number of micro-ops re= tired that were supplied from MSROM.", diff --git a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json index 1be3fa5c4ad3..b50cee3a5e4c 100644 --- a/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/silvermont/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads missed DTLB", + "Counter": "0,1", "EventCode": "0x04", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", "PEBS": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Total cycles for all the page walks. (I-side = and D-side)", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.CYCLES", "PublicDescription": "This event counts every cycle when a data (D= ) page walk or instruction (I) page walk is in progress. Since a pagewalk = implies a TLB miss, the approximate cost of a TLB miss can be determined fr= om this event.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Duration of D-side page-walks in core cycles", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_CYCLES", "PublicDescription": "This event counts every cycle when a D-side = (walks due to a load) page walk is in progress. Page walk duration divided = by number of page walks is the average duration of page-walks.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "D-side page-walks", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.D_SIDE_WALKS", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Duration of I-side page-walks in core cycles", + "Counter": "0,1", "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_CYCLES", "PublicDescription": "This event counts every cycle when a I-side = (walks due to an instruction fetch) page walk is in progress. Page walk dur= ation divided by number of page walks is the average duration of page-walks= .", @@ -43,6 +48,7 @@ }, { "BriefDescription": "I-side page-walks", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.I_SIDE_WALKS", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Total page walks that are completed (I-side a= nd D-side)", + "Counter": "0,1", "EdgeDetect": "1", "EventCode": "0x05", "EventName": "PAGE_WALKS.WALKS", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pj1-f73.google.com (mail-pj1-f73.google.com [209.85.216.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 64A211BBBCA for ; Thu, 20 Jun 2024 18:20:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1718907715; cv=none; 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Thu, 20 Jun 2024 11:20:28 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:45 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-32-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 31/37] perf vendor events: Add/update skylake events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v58 to v59. Update TMA metrics from v4.7 to v4.8. Bring in the event updates v59: https://github.com/intel/perfmon/commit/5d36f1835b02f056031a06e777e4bf54a59= 64930 The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ Adds the event SW_PREFETCH_ACCESS.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/skylake/cache.json | 250 ++++++++++++++++++ .../pmu-events/arch/x86/skylake/counter.json | 22 ++ .../arch/x86/skylake/floating-point.json | 10 + .../pmu-events/arch/x86/skylake/frontend.json | 49 ++++ .../pmu-events/arch/x86/skylake/memory.json | 131 +++++++++ .../arch/x86/skylake/metricgroups.json | 13 + .../pmu-events/arch/x86/skylake/other.json | 2 + .../pmu-events/arch/x86/skylake/pipeline.json | 103 +++++++- .../arch/x86/skylake/skl-metrics.json | 196 ++++++++------ .../arch/x86/skylake/uncore-cache.json | 23 ++ .../arch/x86/skylake/uncore-interconnect.json | 8 + .../arch/x86/skylake/uncore-other.json | 10 - .../arch/x86/skylake/virtual-memory.json | 28 ++ 14 files changed, 756 insertions(+), 91 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylake/counter.json delete mode 100644 tools/perf/pmu-events/arch/x86/skylake/uncore-other.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 30a3966d02b7..70631bcfa8eb 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -29,7 +29,7 @@ GenuineIntel-6-2A,v19,sandybridge,core GenuineIntel-6-8F,v1.23,sapphirerapids,core GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core -GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v58,skylake,core +GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-55-[01234],v1.33,skylakex,core GenuineIntel-6-86,v1.22,snowridgex,core GenuineIntel-6-8[CD],v1.15,tigerlake,core diff --git a/tools/perf/pmu-events/arch/x86/skylake/cache.json b/tools/perf= /pmu-events/arch/x86/skylake/cache.json index ce592d871949..3dd61a325859 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines are in Modified = state. Modified lines are written back to L3", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "SampleAfterValue": "200003", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared or Exclusive state. A non-threaded event.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "SampleAfterValue": "200003", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "SampleAfterValue": "200003", @@ -72,6 +81,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", @@ -80,6 +90,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -88,6 +99,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Demand requests that miss L2 cache.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Demand requests to L2 cache.", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -136,6 +153,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -144,6 +162,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", @@ -152,6 +171,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -160,6 +180,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "All requests that miss L2 cache.", @@ -168,6 +189,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", @@ -176,6 +198,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", @@ -184,6 +207,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "All L2 requests.", @@ -192,6 +216,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -200,6 +225,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -208,6 +234,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -216,6 +243,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", @@ -225,6 +253,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", @@ -234,6 +263,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -244,6 +274,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -254,6 +285,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ANY", @@ -264,6 +296,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -273,6 +306,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -283,6 +317,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -293,6 +328,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -303,6 +339,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -313,6 +350,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -323,6 +361,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -333,6 +372,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -342,6 +382,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -352,6 +393,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -361,6 +403,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -371,6 +414,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -381,6 +425,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -391,6 +436,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -401,6 +447,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -411,6 +458,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -431,6 +480,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -439,6 +489,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -447,6 +498,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", @@ -455,6 +507,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -463,6 +516,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -471,6 +525,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", @@ -479,6 +534,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -487,6 +543,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -496,6 +553,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -505,6 +563,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -514,6 +573,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -523,6 +583,7 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -531,6 +592,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", @@ -539,6 +601,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -547,6 +610,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", @@ -555,6 +619,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -563,6 +628,7 @@ }, { "BriefDescription": "Counts all demand code reads have any respons= e type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -572,6 +638,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -581,6 +648,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -590,6 +658,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -599,6 +668,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -608,6 +678,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -617,6 +688,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -626,6 +698,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -635,6 +708,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -644,6 +718,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -653,6 +728,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -662,6 +738,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -671,6 +748,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -680,6 +758,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -689,6 +768,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -698,6 +778,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -707,6 +788,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -716,6 +798,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -725,6 +808,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -734,6 +818,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -743,6 +828,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -752,6 +838,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -761,6 +848,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -770,6 +858,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -779,6 +868,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -788,6 +878,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -797,6 +888,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -806,6 +898,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -815,6 +908,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -824,6 +918,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -833,6 +928,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -842,6 +938,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -851,6 +948,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -860,6 +958,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +968,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +978,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +988,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +998,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1008,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1018,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1028,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1038,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1048,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1058,7 @@ }, { "BriefDescription": "Counts demand data reads have any response ty= pe.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1068,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1078,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1088,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1098,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1108,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1118,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1128,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1138,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1148,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1158,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1168,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1178,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1188,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1198,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1208,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1218,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1228,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1238,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1248,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1258,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1268,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1278,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1288,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1298,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_HIT_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1308,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1318,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1328,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NOT_N= EEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1338,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1348,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.ANY_= SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1358,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1368,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1378,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1388,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1398,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1408,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SPL_= HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1418,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.ANY_SN= OOP", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1428,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1438,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1448,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1458,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1468,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1478,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SPL_HI= T", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1488,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) have any= response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1498,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1508,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1518,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1528,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1538,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1548,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1558,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1568,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1578,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1588,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1598,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1608,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1618,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1628,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1638,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1648,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1658,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1668,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1678,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1688,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1698,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1708,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1718,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1728,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1738,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1748,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1758,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1768,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1778,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.ANY_SNOO= P", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1788,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= TM", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1798,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_HI= T_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1808,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_MI= SS", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1818,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= NE", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1828,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= T_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1838,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1848,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1858,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1868,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1878,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1888,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1898,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1908,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1918,7 @@ }, { "BriefDescription": "Counts any other requests have any response t= ype.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1928,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1938,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1948,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +1958,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +1968,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +1978,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +1988,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +1998,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2008,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2018,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2028,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2038,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2048,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2058,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2068,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2078,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2088,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2098,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2108,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2118,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2128,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2138,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2148,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2158,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2168,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2178,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2188,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2198,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2208,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2218,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2228,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_HIT_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -2012,6 +2238,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2021,6 +2248,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2030,6 +2258,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NOT_NEE= DED", "MSRIndex": "0x1a6,0x1a7", @@ -2039,6 +2268,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2048,6 +2278,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -2057,6 +2288,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2066,6 +2298,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_HIT_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -2075,6 +2308,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -2084,6 +2318,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -2093,6 +2328,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NOT_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -2102,6 +2338,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2111,14 +2348,24 @@ }, { "BriefDescription": "Number of cache line split locks sent to unco= re.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "SampleAfterValue": "2000003", @@ -2126,6 +2373,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", @@ -2133,6 +2381,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", @@ -2140,6 +2389,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylake/counter.json b/tools/pe= rf/pmu-events/arch/x86/skylake/counter.json new file mode 100644 index 000000000000..1be6522e2bbc --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylake/counter.json @@ -0,0 +1,22 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CBOX", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "cbox_0", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json b/t= ools/perf/pmu-events/arch/x86/skylake/floating-point.json index 5891bd74af60..f1ecda8aed07 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SU= B instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision and double precision floating-point instructions retire= d; some instructions will count twice as noted below. Each count represent= s 1 computational operation. Applies to SIMD scalar single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.= FM(N)ADD/SUB instructions count twice as they perform 2 calculations per = element. The DAZ and FTZ flags in the MXCSR register need to be set when us= ing these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylake/frontend.json b/tools/p= erf/pmu-events/arch/x86/skylake/frontend.json index d6f543471b24..0e1dedce00f2 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking = MITE requires two or three cycles delay.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -66,6 +73,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -86,6 +95,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -107,6 +118,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -118,6 +130,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -128,6 +141,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -149,6 +164,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "MSRIndex": "0x3F7", @@ -159,6 +175,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "MSRIndex": "0x3F7", @@ -169,6 +186,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -180,6 +198,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -190,6 +209,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -200,6 +220,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -210,6 +231,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -232,6 +255,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", @@ -240,6 +264,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "SampleAfterValue": "200003", @@ -247,6 +272,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "SampleAfterValue": "200003", @@ -254,6 +280,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "SampleAfterValue": "200003", @@ -261,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "SampleAfterValue": "200003", @@ -268,6 +296,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -277,6 +306,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -286,6 +316,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -295,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -304,6 +336,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -313,6 +346,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -322,6 +356,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -331,6 +366,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", @@ -339,6 +375,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -348,6 +385,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", @@ -356,6 +394,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -365,6 +404,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -374,6 +414,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -382,6 +423,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -392,6 +434,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -400,6 +443,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", @@ -408,6 +452,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -417,6 +462,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -426,6 +472,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -435,6 +482,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -444,6 +492,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/skylake/memory.json b/tools/per= f/pmu-events/arch/x86/skylake/memory.json index f047862f9735..5e61d3e291ca 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "Errata": "SKL089", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -135,6 +150,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -159,6 +176,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -171,6 +189,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -183,6 +202,7 @@ }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -191,6 +211,7 @@ }, { "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -199,6 +220,7 @@ }, { "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -206,6 +228,7 @@ }, { "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -214,6 +237,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +247,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_E.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +257,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_M.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +267,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT_S.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -250,6 +277,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -259,6 +287,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -268,6 +297,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -277,6 +307,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -286,6 +317,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -295,6 +327,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NON_DR= AM", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +337,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -313,6 +347,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -322,6 +357,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -331,6 +367,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -340,6 +377,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -349,6 +387,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -358,6 +397,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -367,6 +407,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -376,6 +417,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -385,6 +427,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -394,6 +437,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -403,6 +447,7 @@ }, { "BriefDescription": "Counts all demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -412,6 +457,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -421,6 +467,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_E.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -430,6 +477,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_M.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -439,6 +487,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT_S.SNOOP_NON_D= RAM", "MSRIndex": "0x1a6,0x1a7", @@ -448,6 +497,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -457,6 +507,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -466,6 +517,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_HIT_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -475,6 +527,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -484,6 +537,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -493,6 +547,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NON_DR= AM", "MSRIndex": "0x1a6,0x1a7", @@ -502,6 +557,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_NOT_NE= EDED", "MSRIndex": "0x1a6,0x1a7", @@ -511,6 +567,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -520,6 +577,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.A= NY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -529,6 +587,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -538,6 +597,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -547,6 +607,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -556,6 +617,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -565,6 +627,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +637,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -583,6 +647,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= PL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -592,6 +657,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L4_HIT_LOCAL_L4.SNOO= P_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -601,6 +667,7 @@ }, { "BriefDescription": "Counts demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.SUPPLIER_NONE.SNOOP_= NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -610,6 +677,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -619,6 +687,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_E.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -628,6 +697,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_M.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -637,6 +707,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT_S.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -646,6 +717,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -655,6 +727,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -664,6 +737,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_HIT_NO_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -673,6 +747,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -682,6 +757,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -691,6 +767,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -700,6 +777,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_NOT_NEEDED= ", "MSRIndex": "0x1a6,0x1a7", @@ -709,6 +787,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -718,6 +797,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.ANY_S= NOOP", "MSRIndex": "0x1a6,0x1a7", @@ -727,6 +807,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HITM", "MSRIndex": "0x1a6,0x1a7", @@ -736,6 +817,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -745,6 +827,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS", "MSRIndex": "0x1a6,0x1a7", @@ -754,6 +837,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NONE", "MSRIndex": "0x1a6,0x1a7", @@ -763,6 +847,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -772,6 +857,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -781,6 +867,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SPL_H= IT", "MSRIndex": "0x1a6,0x1a7", @@ -790,6 +877,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L4_HIT_LOCAL_L4.SNOOP_NO= N_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -799,6 +887,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs)", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.SUPPLIER_NONE.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -808,6 +897,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -817,6 +907,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_E.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -826,6 +917,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_M.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -835,6 +927,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_HIT_S.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -844,6 +937,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -853,6 +947,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -862,6 +957,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -871,6 +967,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -880,6 +977,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NONE", "MSRIndex": "0x1a6,0x1a7", @@ -889,6 +987,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -898,6 +997,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -907,6 +1007,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -916,6 +1017,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -925,6 +1027,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -934,6 +1037,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_HIT_= NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -943,6 +1047,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_MISS= ", "MSRIndex": "0x1a6,0x1a7", @@ -952,6 +1057,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NONE= ", "MSRIndex": "0x1a6,0x1a7", @@ -961,6 +1067,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NON_= DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -970,6 +1077,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SNOOP_NOT_= NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -979,6 +1087,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L3_MISS_LOCAL_DRAM.SPL_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -988,6 +1097,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.L4_HIT_LOCAL_L4.SNOOP_NON_DRA= M", "MSRIndex": "0x1a6,0x1a7", @@ -997,6 +1107,7 @@ }, { "BriefDescription": "Counts any other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.SUPPLIER_NONE.SNOOP_NON_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1006,6 +1117,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "2", @@ -1015,6 +1127,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -1023,6 +1136,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -1031,6 +1145,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", @@ -1039,6 +1154,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -1046,6 +1162,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", @@ -1054,6 +1171,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -1062,6 +1180,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", @@ -1070,6 +1189,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -1077,6 +1197,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", @@ -1085,6 +1206,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -1093,6 +1215,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -1101,6 +1224,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", @@ -1109,6 +1233,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", @@ -1116,6 +1241,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -1124,6 +1250,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -1132,6 +1259,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -1140,6 +1268,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -1148,6 +1277,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -1156,6 +1286,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/skylake/metricgroups.json b/too= ls/perf/pmu-events/arch/x86/skylake/metricgroups.json index 5452a1448ded..3a88260194d1 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/skylake/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/skylake/other.json b/tools/perf= /pmu-events/arch/x86/skylake/other.json index d75d53279b4e..f14eeeb85d39 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/other.json +++ b/tools/perf/pmu-events/arch/x86/skylake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of hardware interrupts received by the= processor.", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json b/tools/p= erf/pmu-events/arch/x86/skylake/pipeline.json index fe202d1e368a..6d57930afbfd 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -9,6 +10,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", @@ -17,6 +19,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.CONDITIONAL]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.COND", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.COND]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", @@ -75,6 +83,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", @@ -85,6 +94,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -95,6 +105,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -112,6 +124,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -120,6 +133,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -162,6 +180,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -177,6 +197,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -184,6 +205,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -191,6 +213,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -198,6 +221,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -206,6 +230,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -213,6 +238,7 @@ }, { "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x3C", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", @@ -230,12 +257,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -244,12 +273,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -258,6 +289,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -266,6 +298,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -274,6 +307,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -282,6 +316,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -290,6 +325,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "20", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -298,6 +334,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -306,6 +343,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -314,6 +352,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -322,6 +361,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -330,6 +370,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -338,6 +379,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "SampleAfterValue": "2000003", @@ -345,6 +387,7 @@ }, { "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", @@ -353,6 +396,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -361,6 +405,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -369,6 +414,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", @@ -376,6 +422,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -384,15 +431,17 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.NOP", - "PEBS": "2", + "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -403,6 +452,7 @@ }, { "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", + "Counter": "0,2,3", "CounterMask": "10", "Errata": "SKL091, SKL044", "EventCode": "0xC0", @@ -415,6 +465,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -425,6 +476,7 @@ }, { "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", @@ -432,6 +484,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", @@ -441,6 +494,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", @@ -448,6 +502,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -456,6 +511,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -464,6 +520,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", @@ -472,6 +529,7 @@ }, { "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -480,6 +538,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -489,6 +548,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -498,6 +558,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_OK", @@ -507,6 +568,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", @@ -515,6 +577,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -524,6 +587,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -532,6 +596,7 @@ }, { "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", @@ -539,6 +604,7 @@ }, { "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", @@ -547,6 +613,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Counts resource-related stall cycles.", @@ -555,6 +622,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -563,6 +631,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -571,6 +640,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.PAUSE_INST", "SampleAfterValue": "2000003", @@ -578,6 +648,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", @@ -586,6 +657,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -597,6 +669,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -605,6 +678,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -613,6 +687,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", @@ -621,6 +696,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", @@ -629,6 +705,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", @@ -637,6 +714,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -645,6 +723,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -653,6 +732,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", @@ -661,6 +741,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -669,6 +750,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -677,6 +759,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -685,6 +768,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -693,6 +777,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -701,6 +786,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -710,6 +796,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -719,6 +806,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -728,6 +816,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -737,6 +826,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -746,6 +836,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -756,6 +847,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -764,6 +856,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -772,6 +865,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -780,6 +874,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -787,6 +882,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -797,6 +893,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -805,6 +902,7 @@ }, { "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", @@ -813,6 +911,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PublicDescription": "Counts the retirement slots used.", @@ -821,6 +920,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -831,6 +931,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json b/tool= s/perf/pmu-events/arch/x86/skylake/skl-metrics.json index 3af71b84bb9d..4e954fe8547c 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylake/skl-metrics.json @@ -89,7 +89,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info= _thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -98,7 +98,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (IN= T_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) /= tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -119,7 +119,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -157,7 +157,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(18.5 * tma_info_system_core_frequency * MEM_LOAD_L= 3_HIT_RETIRED.XSNP_HITM + 16.5 * tma_info_system_core_frequency * MEM_LOAD_= L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED= .L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -178,7 +178,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "16.5 * tma_info_system_core_frequency * MEM_LOAD_L3= _HIT_RETIRED.XSNP_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_= MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -196,7 +196,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -227,14 +227,14 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -243,7 +243,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -253,7 +253,7 @@ "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "22 * tma_info_system_core_frequency * OFFCORE_RESPO= NSE.DEMAND_RFO.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -263,7 +263,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -276,7 +276,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -291,6 +291,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;= tma_issueD0", "MetricName": "tma_few_uops_instructions", @@ -319,7 +320,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -329,7 +330,7 @@ { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0x3c@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -357,7 +358,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -367,7 +368,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / U= OPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", @@ -386,7 +387,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDAT= A_STALL\\,cmask\\=3D1\\,edge@) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -427,6 +428,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -434,7 +443,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -444,40 +453,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tm= a_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_= latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_laten= cy + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -485,23 +488,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -509,8 +512,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store /= (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency= )))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_spl= it_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma= _dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)= ) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_store= s + tma_store_latency)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -518,7 +521,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (t= ma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_d= ata_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores = + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 - tma_o= ther_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -527,18 +530,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -592,7 +602,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0x3c@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -609,7 +619,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 4 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -670,7 +680,7 @@ { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0x3c@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -752,12 +762,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -790,7 +800,7 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -808,7 +818,7 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -844,13 +854,19 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -925,11 +941,23 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.A= NY)", @@ -952,13 +980,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1068,7 +1096,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1077,7 +1105,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1092,11 +1120,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_M= ISS) / tma_info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1114,7 +1151,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "6.5 * tma_info_system_core_frequency * (MEM_LOAD_RE= TIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2)= ) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1126,7 +1163,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1171,14 +1208,14 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1188,7 +1225,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1197,7 +1234,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1224,6 +1261,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.M= S_UOPS / tma_info_thread_slots", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operatio= ns_group;tma_issueMC;tma_issueMS", "MetricName": "tma_microcode_sequencer", @@ -1234,7 +1272,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1270,7 +1308,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", @@ -1279,7 +1317,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETI= RED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1297,7 +1335,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1305,7 +1343,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1393,7 +1431,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * = RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOT= AL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks", + "MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_cl= ks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1421,7 +1459,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else= UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1429,7 +1467,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1439,7 +1477,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clk= s", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related me= trics: tma_ms_switches", @@ -1467,7 +1505,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1495,7 +1533,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "(L2_RQSTS.RFO_HIT * 9 * (1 - MEM_INST_RETIRED.LOCK_= LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / M= EM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS= _OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1528,7 +1566,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-cache.json index b4e061477c1a..46ba98ab3ba4 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_ES", "PerPkg": "1", @@ -10,6 +11,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in I-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_I", "PerPkg": "1", @@ -19,6 +21,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in M-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_M", "PerPkg": "1", @@ -28,6 +31,7 @@ }, { "BriefDescription": "L3 Lookup any request that access cache and f= ound line in MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.ANY_MESI", "PerPkg": "1", @@ -37,6 +41,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_ES", "PerPkg": "1", @@ -46,6 +51,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in I-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_I", "PerPkg": "1", @@ -55,6 +61,7 @@ }, { "BriefDescription": "L3 Lookup read request that access cache and = found line in any MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.READ_MESI", "PerPkg": "1", @@ -64,6 +71,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in E or S-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_ES", "PerPkg": "1", @@ -73,6 +81,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in M-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_M", "PerPkg": "1", @@ -82,6 +91,7 @@ }, { "BriefDescription": "L3 Lookup write request that access cache and= found line in MESI-state", + "Counter": "0,1", "EventCode": "0x34", "EventName": "UNC_CBO_CACHE_LOOKUP.WRITE_MESI", "PerPkg": "1", @@ -91,6 +101,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a modified line in some proces= sor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HITM_XCORE", "PerPkg": "1", @@ -99,6 +110,7 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which hits a non-modified line in some pr= ocessor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.HIT_XCORE", "PerPkg": "1", @@ -107,6 +119,7 @@ }, { "BriefDescription": "A cross-core snoop resulted from L3 Eviction = which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_EVICTION", "PerPkg": "1", @@ -115,10 +128,20 @@ }, { "BriefDescription": "A cross-core snoop initiated by this Cbox due= to processor core memory request which misses in some processor core.", + "Counter": "0,1", "EventCode": "0x22", "EventName": "UNC_CBO_XSNP_RESPONSE.MISS_XCORE", "PerPkg": "1", "UMask": "0x41", "Unit": "CBOX" + }, + { + "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", + "Counter": "FIXED", + "EventCode": "0xff", + "EventName": "UNC_CLOCK.SOCKET", + "PerPkg": "1", + "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", + "Unit": "cbox_0" } ] diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.jso= n b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json index fe7e19717371..6b9fbed5847c 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/skylake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Number of entries allocated. Account for Any = type: e.g. Snoop, Core aperture, etc.", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of all Core entries outstanding for th= e memory controller. The outstanding interval starts after LLC miss till re= turn of first data chunk. Accounts for Coherent and non-coherent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles with at least one request outstanding = is waiting for data return from memory controller. Account for coherent and= non-coherent requests initiated by IA Cores, Processor Graphics Unit, or L= LC.", + "Counter": "0", "CounterMask": "1", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.CYCLES_WITH_ANY_REQUEST", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of Core Data Read entries outstanding = for the memory controller. The outstanding interval starts after LLC miss t= ill return of first data chunk.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.DATA_READ", "PerPkg": "1", @@ -34,6 +38,7 @@ }, { "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.DATA_READ", "PerPkg": "1", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Number of Core coherent Data Read requests se= nt to memory controller whose data is returned directly to requesting agent= .", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.DRD_DIRECT", "PerPkg": "1", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Number of Writes allocated - any write transa= ctions: full/partials writes and evictions.", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.WRITES", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json b/too= ls/perf/pmu-events/arch/x86/skylake/uncore-other.json deleted file mode 100644 index 58be90d7cc93..000000000000 --- a/tools/perf/pmu-events/arch/x86/skylake/uncore-other.json +++ /dev/null @@ -1,10 +0,0 @@ -[ - { - "BriefDescription": "This 48-bit fixed counter counts the UCLK cyc= les", - "EventCode": "0xff", - "EventName": "UNC_CLOCK.SOCKET", - "PerPkg": "1", - "PublicDescription": "This 48-bit fixed counter counts the UCLK cy= cles.", - "Unit": "CLOCK" - } -] diff --git a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json b/t= ools/perf/pmu-events/arch/x86/skylake/virtual-memory.json index 73feadaf7674..ad33fff57c03 100644 --- a/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -162,6 +182,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -171,6 +192,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -179,6 +201,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -187,6 +210,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake microarchitecture.", @@ -211,6 +237,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -219,6 +246,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F9AC1B29B1 for ; Thu, 20 Jun 2024 18:20:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 20 Jun 2024 11:20:30 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:46 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-33-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 32/37] perf vendor events: Add/update skylakex events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.33 to v1.35. Update TMA metrics from v4.7 to v4.8. Bring in the event updates v1.35: https://github.com/intel/perfmon/commit/c99b60c147b96f40f96dd961abfae54909f= 47e5f The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ Adds the event SW_PREFETCH_ACCESS.ANY. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/skylakex/cache.json | 155 + .../pmu-events/arch/x86/skylakex/counter.json | 52 + .../arch/x86/skylakex/floating-point.json | 13 + .../arch/x86/skylakex/frontend.json | 49 + .../pmu-events/arch/x86/skylakex/memory.json | 115 + .../arch/x86/skylakex/metricgroups.json | 13 + .../pmu-events/arch/x86/skylakex/other.json | 15 + .../arch/x86/skylakex/pipeline.json | 104 +- .../arch/x86/skylakex/skx-metrics.json | 310 +- .../arch/x86/skylakex/uncore-cache.json | 2274 +++++++++++++++ .../x86/skylakex/uncore-interconnect.json | 2521 +++++++++++++++++ .../arch/x86/skylakex/uncore-io.json | 703 +++++ .../arch/x86/skylakex/uncore-memory.json | 804 ++++++ .../arch/x86/skylakex/uncore-power.json | 50 + .../arch/x86/skylakex/virtual-memory.json | 28 + 16 files changed, 7019 insertions(+), 189 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/skylakex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index 70631bcfa8eb..b5d40fa2a29f 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -30,7 +30,7 @@ GenuineIntel-6-8F,v1.23,sapphirerapids,core GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core -GenuineIntel-6-55-[01234],v1.33,skylakex,core +GenuineIntel-6-55-[01234],v1.35,skylakex,core GenuineIntel-6-86,v1.22,snowridgex,core GenuineIntel-6-8[CD],v1.15,tigerlake,core GenuineIntel-6-2C,v5,westmereep-dp,core diff --git a/tools/perf/pmu-events/arch/x86/skylakex/cache.json b/tools/per= f/pmu-events/arch/x86/skylakex/cache.json index 14229f4b29d8..2ce070629c52 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "L1D data line replacements", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of times a request needed a FB entry b= ut there was no entry available for it. That is the FB unavailability was d= ominant reason for blocking the request. A request includes cacheable/uncac= heable demands that is load, store or SW prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Number of times a request needed a FB (Fill = Buffer) entry but there was no entry available for it. A request includes c= acheable/uncacheable demands that are load, store or SW prefetch instructio= ns.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "L1D miss outstandings duration in cycles", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts duration of L1D miss outstanding, tha= t is each cycle number of Fill Buffers (FB) outstanding required by Demand = Reads. FB either is held by demand loads, or it is held by non-demand loads= and gets hit at least once by demand. The valid outstanding interval is de= fined until the FB deallocation by one of the following ways: from FB alloc= ation, if FB is allocated by demand from the demand Hit FB, if it is alloca= ted by hardware or software prefetch.Note: In the L1D, a Demand Read contai= ns cacheable or noncacheable demand loads, including ones causing cache-lin= e splits and reads due to page walks resulted from any request type.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -35,6 +39,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles with L1D load Misses outstanding from = any thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", @@ -43,6 +48,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts the number of lines that are evicted b= y L2 cache when triggered by an L2 cache fill. Those lines can be either in= modified state or clean state. Modified lines may either be written back t= o L3 or directly written to memory and not allocated in L3. Clean lines ma= y either be allocated in L3 or dropped", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines can be either i= n modified state or clean state. Modified lines may either be written back = to L3 or directly written to memory and not allocated in L3. Clean lines m= ay either be allocated in L3 or dropped.", @@ -59,6 +66,7 @@ }, { "BriefDescription": "Counts the number of lines that are silently = dropped by L2 cache when triggered by an L2 cache fill. These lines are typ= ically in Shared state. A non-threaded event.", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.SILENT", "SampleAfterValue": "200003", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Counts the number of lines that have been har= dware prefetched but not used and now evicted by L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_HWPF", "SampleAfterValue": "200003", @@ -73,6 +82,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = L2_LINES_OUT.USELESS_HWPF", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.USELESS_PREF", @@ -81,6 +91,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Demand Data Read requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts the number of demand Data Read reques= ts (including requests from L1D hardware prefetchers). These loads may hit = or miss L2 cache. Only non rejected loads are counted.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Demand requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_MISS", "PublicDescription": "Demand requests that miss L2 cache.", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Demand requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "PublicDescription": "Demand requests to L2 cache.", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_PF", "PublicDescription": "Counts the total number of requests from the= L2 hardware prefetchers.", @@ -121,6 +136,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -129,6 +145,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -137,6 +154,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -145,6 +163,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts, initiated by load instructions, that hit L2 cache", @@ -153,6 +172,7 @@ }, { "BriefDescription": "Demand Data Read miss L2, no rejects", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts the number of demand Data Read reques= ts that miss L2 cache. Only not rejected loads are counted.", @@ -161,6 +181,7 @@ }, { "BriefDescription": "All requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "All requests that miss L2 cache.", @@ -169,6 +190,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_HIT", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that hit L2 cache.", @@ -177,6 +199,7 @@ }, { "BriefDescription": "Requests from the L1/L2/L3 hardware prefetche= rs or Load software prefetches that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PF_MISS", "PublicDescription": "Counts requests from the L1/L2/L3 hardware p= refetchers or Load software prefetches that miss L2 cache.", @@ -185,6 +208,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "All L2 requests.", @@ -193,6 +217,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -201,6 +226,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -209,6 +235,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -217,6 +244,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests mis= sed L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", @@ -226,6 +254,7 @@ }, { "BriefDescription": "Core-originated cacheable demand requests tha= t refer to L3", + "Counter": "0,1,2,3", "Errata": "SKL057", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", @@ -235,6 +264,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -245,6 +275,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -255,6 +286,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.ANY", @@ -265,6 +297,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -274,6 +307,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -284,6 +318,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -304,6 +340,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -314,6 +351,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 and cross-core snoop hits in on-pkg core cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT", @@ -324,6 +362,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were HitM responses from shared L3", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM", @@ -334,6 +373,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -343,6 +383,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -353,6 +394,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from local dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM", @@ -363,6 +405,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = missed L3 but serviced from remote dram", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM", @@ -372,6 +415,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was forwarded from a remote cache", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD", @@ -382,6 +426,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = was remote HITM", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD3", "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM", @@ -392,6 +437,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -401,6 +447,7 @@ }, { "BriefDescription": "Retired load instructions which data sources = were load missed L1 but hit FB due to preceding miss to the same cache line= with data not ready", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -411,6 +458,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -421,6 +469,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -431,6 +480,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -441,6 +491,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -451,6 +502,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -461,6 +513,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xD1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -471,6 +524,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -479,6 +533,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -487,6 +542,7 @@ }, { "BriefDescription": "Cacheable and non-cacheable code read request= s", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "PublicDescription": "Counts both cacheable and non-cacheable code= read requests.", @@ -495,6 +551,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -503,6 +560,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -511,6 +569,7 @@ }, { "BriefDescription": "Offcore requests buffer cannot take more entr= ies for this thread core.", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "PublicDescription": "Counts the number of cases when the offcore = requests buffer cannot take more entries for the core. This can happen when= the superqueue does not contain eligible entries, or when L1D writeback pe= nding FIFO requests is full.Note: Writeback pending FIFO has six entries.", @@ -519,6 +578,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -527,6 +587,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -536,6 +597,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding Code Reads tr= ansactions in the SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE= _RD", @@ -545,6 +607,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -554,6 +617,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -563,6 +627,7 @@ }, { "BriefDescription": "Offcore outstanding Code Reads transactions i= n the SuperQueue (SQ), queue to uncore, every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", "PublicDescription": "Counts the number of offcore outstanding Cod= e Reads transactions in the super queue every cycle. The 'Offcore outstandi= ng' state of the transaction lasts from the L2 miss until the sending trans= action completion to requestor (SQ deallocation). See the corresponding Uma= sk under OFFCORE_REQUESTS.", @@ -571,6 +636,7 @@ }, { "BriefDescription": "Offcore outstanding Demand Data Read transact= ions in uncore queue.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding Dem= and Data Read transactions in the super queue (SQ) every cycle. A transacti= on is considered to be in the Offcore outstanding state between L2 miss and= transaction completion sent to requestor. See the corresponding Umask unde= r OFFCORE_REQUESTS.Note: A prefetch promoted to Demand is counted from the = promotion point.", @@ -579,6 +645,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -587,6 +654,7 @@ }, { "BriefDescription": "Offcore outstanding demand rfo reads transact= ions in SuperQueue (SQ), queue to uncore, every cycle", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of offcore outstanding RFO= (store) transactions in the super queue (SQ) every cycle. A transaction is= considered to be in the Offcore outstanding state between L2 miss and tran= saction completion sent to requestor (SQ de-allocation). See corresponding = Umask under OFFCORE_REQUESTS.", @@ -595,6 +663,7 @@ }, { "BriefDescription": "Offcore response can be programmed only with = a specific pair of event select and counter MSR, and with specific event co= des and predefine mask bit value in a dedicated MSR to specify attributes o= f the offcore transaction", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE", "PublicDescription": "Offcore response can be programmed only with= a specific pair of event select and counter MSR, and with specific event c= odes and predefine mask bit value in a dedicated MSR to specify attributes = of the offcore transaction.", @@ -603,6 +672,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -612,6 +682,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -621,6 +692,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and the snoop to one of the sibling cores hits the line in M = state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -630,6 +702,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and the snoop to one of the sibling cores hits the line in M = state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.HIT_OTHER_CORE_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -639,6 +712,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = hit in the L3 and sibling core snoops are not needed as either the core-val= id bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -648,6 +722,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT= _WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_HIT.SNOOP_HIT_WITH_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -657,6 +732,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that have any = response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -666,6 +742,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -675,6 +752,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -684,6 +762,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and the snoop to one of the sibling cores hits the line in M state and= the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -693,6 +772,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that hit in th= e L3 and sibling core snoops are not needed as either the core-valid bit is= not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -702,6 +782,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -711,6 +792,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that have any response t= ype.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -720,6 +802,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -729,6 +812,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -738,6 +822,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and t= he snoop to one of the sibling cores hits the line in M state and the line = is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -747,6 +832,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that hit in the L3 and s= ibling core snoops are not needed as either the core-valid bit is not set o= r the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -756,6 +842,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_= WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -765,6 +852,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_C= ORE_FWD hit in the L3 and the snoop to one of the sibling cores hits the li= ne in E/S/F state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_READS.L3_HIT.HIT_OTHER_CORE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -774,6 +862,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that have a= ny response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -783,6 +872,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -792,6 +882,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -801,6 +892,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and the snoop to one of the sibling cores hits the line in M state = and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.HIT_OTHER_CORE_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -810,6 +902,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that hit in= the L3 and sibling core snoops are not needed as either the core-valid bit= is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -819,6 +912,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WIT= H_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -828,6 +922,7 @@ }, { "BriefDescription": "Counts all demand code reads that have any re= sponse type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -837,6 +932,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -846,6 +942,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -855,6 +952,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and the snoop to one of the sibling cores hits the line in M state and t= he line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -864,6 +962,7 @@ }, { "BriefDescription": "Counts all demand code reads that hit in the = L3 and sibling core snoops are not needed as either the core-valid bit is n= ot set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -873,6 +972,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -882,6 +982,7 @@ }, { "BriefDescription": "Counts demand data reads that have any respon= se type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -891,6 +992,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -900,6 +1002,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CO= RE", "MSRIndex": "0x1a6,0x1a7", @@ -909,6 +1012,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd the snoop to one of the sibling cores hits the line in M state and the l= ine is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HIT_OTHER_COR= E_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -918,6 +1022,7 @@ }, { "BriefDescription": "Counts demand data reads that hit in the L3 a= nd sibling core snoops are not needed as either the core-valid bit is not s= et or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.NO_SNOOP_NEED= ED", "MSRIndex": "0x1a6,0x1a7", @@ -927,6 +1032,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_= HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WIT= H_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -936,6 +1042,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hav= e any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -945,6 +1052,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -954,6 +1062,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -963,6 +1072,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and the snoop to one of the sibling cores hits the line in M sta= te and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.HIT_OTHER_CORE_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -972,6 +1082,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that hit= in the L3 and sibling core snoops are not needed as either the core-valid = bit is not set or the shared line is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -981,6 +1092,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_= WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -990,6 +1102,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -999,6 +1112,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1008,6 +1122,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and the snoop to one o= f the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1017,6 +1132,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and the snoop to one o= f the sibling cores hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1026,6 +1142,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that hit in the L3 and sibling core snoop= s are not needed as either the core-valid bit is not set or the shared line= is present in multiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1035,6 +1152,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_H= IT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1044,6 +1162,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1053,6 +1172,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1062,6 +1182,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and the snoop to one of the sibling cores hits the= line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1071,6 +1192,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and the snoop to one of the sibling cores hits the= line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1080,6 +1202,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that hit in the L3 and sibling core snoops are not needed as either t= he core-valid bit is not set or the shared line is present in multiple core= s.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1089,6 +1212,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_H= IT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1098,6 +1222,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1107,6 +1232,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1116,6 +1242,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and the snoop to one of the sibling cores hits the l= ine in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1125,6 +1252,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and the snoop to one of the sibling cores hits the l= ine in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1134,6 +1262,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that hit in the L3 and sibling core snoops are not needed as either the= core-valid bit is not set or the shared line is present in multiple cores.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1143,6 +1272,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_W= ITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1152,6 +1282,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1161,6 +1292,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1170,6 +1302,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and the snoop to one of the sibling core= s hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HITM_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1179,6 +1312,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and the snoop to one of the sibling core= s hits the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.HIT_OTHER_CORE= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1188,6 +1322,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that hit in the L3 and sibling core snoops are not needed a= s either the core-valid bit is not set or the shared line is present in mul= tiple cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.NO_SNOOP_NEEDE= D", "MSRIndex": "0x1a6,0x1a7", @@ -1197,6 +1332,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_H= IT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_HIT.SNOOP_HIT_WITH= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1206,6 +1342,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that have any response type.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -1215,6 +1352,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -1224,6 +1362,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and the snoop to one of the sibling cores hits= the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HITM_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1233,6 +1372,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and the snoop to one of the sibling cores hits= the line in M state and the line is forwarded.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.HIT_OTHER_CORE_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -1242,6 +1382,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that hit in the L3 and sibling core snoops are not needed as eith= er the core-valid bit is not set or the shared line is present in multiple = cores.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.NO_SNOOP_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -1251,6 +1392,7 @@ }, { "BriefDescription": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_W= ITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_HIT.SNOOP_HIT_WITH_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -1260,14 +1402,24 @@ }, { "BriefDescription": "Number of cache line split locks sent to unco= re.", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "PublicDescription": "Counts the number of cache line split locks = sent to the uncore.", "SampleAfterValue": "100003", "UMask": "0x10" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "2000003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "SampleAfterValue": "2000003", @@ -1275,6 +1427,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "SampleAfterValue": "2000003", @@ -1282,6 +1435,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "SampleAfterValue": "2000003", @@ -1289,6 +1443,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/counter.json b/tools/p= erf/pmu-events/arch/x86/skylakex/counter.json new file mode 100644 index 000000000000..e94b76404856 --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/skylakex/counter.json @@ -0,0 +1,52 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + }, + { + "Unit": "M3UPI", + "CountersNumFixed": "0", + "CountersNumGeneric": "3" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": "1", + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json b/= tools/perf/pmu-events/arch/x86/skylakex/floating-point.json index 384b3c551a1f..25a864613c7d 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational double precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational double precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 2 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DP= P FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element. The DAZ and FTZ flags in the MXCSR register= need to be set when using these events.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts once for most SIMD 128-bit packed comp= utational single precision floating-point instruction retired. Counts twice= for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 128-bit packed com= putational single precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed doub= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Counts once for most SIMD 256-bit packed dou= ble computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 4 computati= on operations, one for each element. Applies to packed double precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM= (N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calcul= ations per element. The DAZ and FTZ flags in the MXCSR register need to be = set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts once for most SIMD 256-bit packed sing= le computational precision floating-point instructions retired. Counts twic= e for DPP and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Counts once for most SIMD 256-bit packed sin= gle computational precision floating-point instructions retired; some instr= uctions will count twice as noted below. Each count represents 8 computati= on operations, one for each element. Applies to packed single precision fl= oating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RS= QRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as= they perform 2 calculations per element. The DAZ and FTZ flags in the MXCS= R register need to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l floating-point instructions retired. Counts twice for DPP and FM(N)ADD/SU= B instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision and double precision floating-point instructions retire= d; some instructions will count twice as noted below. Each count represent= s 1 computational operation. Applies to SIMD scalar single precision floati= ng-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB.= FM(N)ADD/SUB instructions count twice as they perform 2 calculations per = element. The DAZ and FTZ flags in the MXCSR register need to be set when us= ing these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l double precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Counts once for most SIMD scalar computation= al double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar double precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions cou= nt twice as they perform 2 calculations per element. The DAZ and FTZ flags = in the MXCSR register need to be set when using these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts once for most SIMD scalar computationa= l single precision floating-point instructions retired. Counts twice for DP= P and FM(N)ADD/SUB instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Counts once for most SIMD scalar computation= al single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 1 computational ope= ration. Applies to SIMD scalar single precision floating-point instructions= : ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instru= ctions count twice as they perform 2 calculations per element. The DAZ and = FTZ flags in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "2000003", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Cycles with any input/output SSE or FP assist= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xCA", "EventName": "FP_ASSIST.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json b/tools/= perf/pmu-events/arch/x86/skylakex/frontend.json index d6f543471b24..0e1dedce00f2 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switches", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.COUNT", "PublicDescription": "This event counts the number of the Decode S= tream Buffer (DSB)-to-MITE switches including all misses because of missing= Decode Stream Buffer (DSB) cache and u-arch forced misses. Note: Invoking = MITE requires two or three cycles delay.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch tru= e penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Counts Decode Stream Buffer (DSB)-to-MITE sw= itch true penalty cycles. These cycles do not include uops routed through b= ecause of the switch itself, for example, when Instruction Decode Queue (ID= Q) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full= . SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) re= ceives Decode Stream Buffer (DSB) Sync-indication until receiving the first= MITE uop. MM is placed before Instruction Decode Queue (IDQ) to merge uops= being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Strea= m Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer = (DSB)-to-MITE switch occurs.Penalty: A Decode Stream Buffer (DSB) hit follo= wed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which= no uops are delivered to the IDQ. Most often, such switches from the Decod= e Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -66,6 +73,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -76,6 +84,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -86,6 +95,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -97,6 +107,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -107,6 +118,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -118,6 +130,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 2 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -128,6 +141,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -138,6 +152,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -149,6 +164,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 2 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_2", "MSRIndex": "0x3F7", @@ -159,6 +175,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 3 bubble-slots for a period of = 2 cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_3", "MSRIndex": "0x3F7", @@ -169,6 +186,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -180,6 +198,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -190,6 +209,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -200,6 +220,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -210,6 +231,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -221,6 +243,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3", "EventCode": "0xC6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -232,6 +255,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Cycles where a code line fetch is stalled du= e to an L1 instruction cache miss. The legacy decode pipeline works at a 16= Byte granularity.", @@ -240,6 +264,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "SampleAfterValue": "200003", @@ -247,6 +272,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "SampleAfterValue": "200003", @@ -254,6 +280,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "SampleAfterValue": "200003", @@ -261,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "SampleAfterValue": "200003", @@ -268,6 +296,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.DSB_CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", @@ -277,6 +306,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.DSB_CYCLES_ANY]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", @@ -286,6 +316,7 @@ }, { "BriefDescription": "Cycles MITE is delivering 4 Uops", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", @@ -295,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", @@ -304,6 +336,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES", @@ -313,6 +346,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop [This event is alias to IDQ.ALL_DSB_CYCLES_ANY_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -322,6 +356,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng 4 or more Uops [This event is alias to IDQ.ALL_DSB_CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", @@ -331,6 +366,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Countin= g includes uops that may 'bypass' the IDQ.", @@ -339,6 +375,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) from MITE path", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES", @@ -348,6 +385,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. Counting includes uops that m= ay 'bypass' the IDQ. This also means that uops are not being delivered from= the Decode Stream Buffer (DSB).", @@ -356,6 +394,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES", @@ -365,6 +404,7 @@ }, { "BriefDescription": "Cycles when uops initiated by Decode Stream B= uffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Mic= rocode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_DSB_CYCLES", @@ -374,6 +414,7 @@ }, { "BriefDescription": "Uops initiated by MITE and delivered to Instr= uction Decode Queue (IDQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_MITE_UOPS", "PublicDescription": "Counts the number of uops initiated by MITE = and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenc= er (MS) is busy. Counting includes uops that may 'bypass' the IDQ.", @@ -382,6 +423,7 @@ }, { "BriefDescription": "Number of switches from DSB (Decode Stream Bu= ffer) or MITE (legacy decode pipeline) to the Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -392,6 +434,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) while Microcode Sequencer (MS) is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -400,6 +443,7 @@ }, { "BriefDescription": "Uops not delivered to Resource Allocation Tab= le (RAT) per thread when backend of the machine is not stalled", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to R= esource Allocation Table (RAT) per thread adding 4 x when Resource Allocat= ion Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers = x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). C= ounting does not cover cases when: a. IDQ-Resource Allocation Table (RAT) p= ipe serves the other thread. b. Resource Allocation Table (RAT) is stalled = for the thread (including uop drops and clear BE conditions). c. Instructi= on Decode Queue (IDQ) delivers four uops.", @@ -408,6 +452,7 @@ }, { "BriefDescription": "Cycles per thread when 4 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -417,6 +462,7 @@ }, { "BriefDescription": "Counts cycles FE delivered 4 uops or Resource= Allocation Table (RAT) was stalling FE.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", @@ -426,6 +472,7 @@ }, { "BriefDescription": "Cycles per thread when 3 or more uops are not= delivered to Resource Allocation Table (RAT) when backend of the machine i= s not stalled", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", @@ -435,6 +482,7 @@ }, { "BriefDescription": "Cycles with less than 2 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", @@ -444,6 +492,7 @@ }, { "BriefDescription": "Cycles with less than 3 uops delivered by the= front end.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x9C", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/memory.json b/tools/pe= rf/pmu-events/arch/x86/skylakex/memory.json index dba3cd6b3690..9ee7a9d44fd2 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles while L3 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to unfriendly events (such as interrupts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_EVENTS", "SampleAfterValue": "2000003", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to various memory events (e.g., read/write capacity and conflicts).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEM", "SampleAfterValue": "2000003", @@ -40,6 +45,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an HLE execution aborted due= to incompatible memory type.", @@ -48,6 +54,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to hardware timer expiration.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Number of times an HLE execution aborted due = to HLE-unfriendly instructions and certain unfriendly events (such as AD as= sists etc.).", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.ABORTED_UNFRIENDLY", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Number of times an HLE execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.COMMIT", "PublicDescription": "Number of times HLE commit succeeded.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Number of times an HLE execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "HLE_RETIRED.START", "PublicDescription": "Number of times we entered an HLE region. Do= es not count nested transactions.", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to me= mory order conflicts.", + "Counter": "0,1,2,3", "Errata": "SKL089", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", @@ -87,6 +98,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -111,6 +124,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -123,6 +137,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -135,6 +150,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -147,6 +163,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -159,6 +176,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -171,6 +189,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -183,6 +202,7 @@ }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -191,6 +211,7 @@ }, { "BriefDescription": "Cycles with at least 1 Demand Data Read reque= sts who miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_L3_MISS_DEM= AND_DATA_RD", @@ -199,6 +220,7 @@ }, { "BriefDescription": "Counts number of Offcore outstanding Demand D= ata Read requests that miss L3 cache in the superQ every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD", "SampleAfterValue": "2000003", @@ -206,6 +228,7 @@ }, { "BriefDescription": "Cycles with at least 6 Demand Data Read reque= sts that miss L3 cache in the superQ.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.L3_MISS_DEMAND_DATA_RD_= GE_6", @@ -214,6 +237,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +247,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +257,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.REMOTE_HIT_FORW= ARD", "MSRIndex": "0x1a6,0x1a7", @@ -241,6 +267,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS.SNOOP_MISS_OR_N= O_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -250,6 +277,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_LOCAL_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -259,6 +287,7 @@ }, { "BriefDescription": "Counts all demand & prefetch data reads that = miss the L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.L3_MISS_REMOTE_DRAM.SNO= OP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -268,6 +297,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss in t= he L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -277,6 +307,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -286,6 +317,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -295,6 +327,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -304,6 +337,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -313,6 +347,7 @@ }, { "BriefDescription": "Counts all prefetch data reads that miss the = L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -322,6 +357,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -331,6 +367,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -340,6 +377,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and cle= an or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", @@ -349,6 +387,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -358,6 +397,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -367,6 +407,7 @@ }, { "BriefDescription": "Counts prefetch RFOs that miss the L3 and the= data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_PF_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -376,6 +417,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss i= n the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -385,6 +427,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -394,6 +437,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.REMOTE_HIT_FORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -403,6 +447,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS.SNOOP_MISS_OR_NO_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -412,6 +457,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_LOCAL_DRAM.SNOOP_MI= SS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -421,6 +467,7 @@ }, { "BriefDescription": "Counts all demand & prefetch RFOs that miss t= he L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ALL_RFO.L3_MISS_REMOTE_DRAM.SNOOP_M= ISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -430,6 +477,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss in the= L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -439,6 +487,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -448,6 +497,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the L3= and clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -457,6 +507,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -466,6 +517,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -475,6 +527,7 @@ }, { "BriefDescription": "Counts all demand code reads that miss the L3= and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -484,6 +537,7 @@ }, { "BriefDescription": "Counts demand data reads that miss in the L3.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -493,6 +547,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -502,6 +557,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the L3 and= clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.REMOTE_HIT_F= ORWARD", "MSRIndex": "0x1a6,0x1a7", @@ -511,6 +567,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS.SNOOP_MISS_O= R_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -520,6 +577,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_LOCAL_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -529,6 +587,7 @@ }, { "BriefDescription": "Counts demand data reads that miss the L3 and= the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_MISS_REMOTE_DRAM.= SNOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -538,6 +597,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -547,6 +607,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the modified data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -556,6 +617,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and clean or shared data is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.REMOTE_HIT_FORWA= RD", "MSRIndex": "0x1a6,0x1a7", @@ -565,6 +627,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS.SNOOP_MISS_OR_NO= _FWD", "MSRIndex": "0x1a6,0x1a7", @@ -574,6 +637,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_LOCAL_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -583,6 +647,7 @@ }, { "BriefDescription": "Counts all demand data writes (RFOs) that mis= s the L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.L3_MISS_REMOTE_DRAM.SNOO= P_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -592,6 +657,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -601,6 +667,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the modified data is= transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -610,6 +677,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and clean or shared data= is transferred from remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", @@ -619,6 +687,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -628,6 +697,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -637,6 +707,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetch reques= ts and software prefetch requests that miss the L3 and the data is returned= from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L1D_AND_SW.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -646,6 +717,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -655,6 +727,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the modified data is transferred from remote cac= he.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -664,6 +737,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and clean or shared data is transferred from remote = cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", @@ -673,6 +747,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -682,6 +757,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -691,6 +767,7 @@ }, { "BriefDescription": "Counts prefetch (that bring data to L2) data = reads that miss the L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -700,6 +777,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -709,6 +787,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the modified data is transferred from remote cache= .", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -718,6 +797,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and clean or shared data is transferred from remote ca= che.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", @@ -727,6 +807,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from local or remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -736,6 +817,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -745,6 +827,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to L2) R= FOs that miss the L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -754,6 +837,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -763,6 +847,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the modified data is transferred from = remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -772,6 +857,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and clean or shared data is transferred fr= om remote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.REMOTE_HIT_FO= RWARD", "MSRIndex": "0x1a6,0x1a7", @@ -781,6 +867,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from local or rem= ote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS.SNOOP_MISS_OR= _NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -790,6 +877,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_LOCAL_DRAM.SN= OOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -799,6 +887,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) data reads that miss the L3 and the data is returned from remote dram.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_DATA_RD.L3_MISS_REMOTE_DRAM.S= NOOP_MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -808,6 +897,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.ANY_SNOOP", "MSRIndex": "0x1a6,0x1a7", @@ -817,6 +907,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the modified data is transferred from remote= cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -826,6 +917,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and clean or shared data is transferred from rem= ote cache.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.REMOTE_HIT_FORWAR= D", "MSRIndex": "0x1a6,0x1a7", @@ -835,6 +927,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from local or remote dr= am.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS.SNOOP_MISS_OR_NO_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -844,6 +937,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from local dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_LOCAL_DRAM.SNOOP_= MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -853,6 +947,7 @@ }, { "BriefDescription": "Counts all prefetch (that bring data to LLC o= nly) RFOs that miss the L3 and the data is returned from remote dram.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_L3_RFO.L3_MISS_REMOTE_DRAM.SNOOP= _MISS_OR_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -862,6 +957,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to any reasons (multiple categories may count as one).", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED", "PEBS": "2", @@ -871,6 +967,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Number of times an RTM execution aborted due= to none of the previous 4 categories (e.g. interrupt).", @@ -879,6 +976,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Number of times an RTM execution aborted due= to various memory events (e.g. read/write capacity and conflicts).", @@ -887,6 +985,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Number of times an RTM execution aborted due= to incompatible memory type.", @@ -895,6 +994,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to uncommon conditions.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_TIMER", "SampleAfterValue": "2000003", @@ -902,6 +1002,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Number of times an RTM execution aborted due= to HLE-unfriendly instructions.", @@ -910,6 +1011,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Number of times RTM commit succeeded.", @@ -918,6 +1020,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3", "EventCode": "0xC9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Number of times we entered an RTM region. Do= es not count nested transactions.", @@ -926,6 +1029,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed. Since this is the = count of execution, it may not always cause a transactional abort.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC1", "SampleAfterValue": "2000003", @@ -933,6 +1037,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions (e.g., vzeroupper) that may cause a transactional abort was executed = inside a transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupp= er instruction.", @@ -941,6 +1046,7 @@ }, { "BriefDescription": "Counts the number of times an instruction exe= cution caused the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Unfriendly TSX abort triggered by a nest cou= nt that is too deep.", @@ -949,6 +1055,7 @@ }, { "BriefDescription": "Counts the number of times a XBEGIN instructi= on was executed inside an HLE transactional region.", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC4", "PublicDescription": "RTM region detected inside HLE.", @@ -957,6 +1064,7 @@ }, { "BriefDescription": "Counts the number of times an HLE XACQUIRE in= struction was executed inside an RTM transactional region", + "Counter": "0,1,2,3", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC5", "PublicDescription": "Counts the number of times an HLE XACQUIRE i= nstruction was executed inside an RTM transactional region.", @@ -965,6 +1073,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data capacity limitation for transactional reads or writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY", "SampleAfterValue": "2000003", @@ -972,6 +1081,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Number of times a TSX line had a cache confl= ict.", @@ -980,6 +1090,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to XRELEASE lock not satisfying the address and value require= ments in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "PublicDescription": "Number of times a TSX Abort was triggered du= e to release/commit but data and address mismatch.", @@ -988,6 +1099,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to NoAllocatedElisionBuffer being non-zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "PublicDescription": "Number of times a TSX Abort was triggered du= e to commit but Lock Buffer not empty.", @@ -996,6 +1108,7 @@ }, { "BriefDescription": "Number of times an HLE transactional executio= n aborted due to an unsupported read alignment from the elision buffer.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMEN= T", "PublicDescription": "Number of times a TSX Abort was triggered du= e to attempting an unsupported alignment from Lock Buffer.", @@ -1004,6 +1117,7 @@ }, { "BriefDescription": "Number of times a HLE transactional region ab= orted due to a non XRELEASE prefixed instruction writing to an elided lock = in the elision buffer", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "PublicDescription": "Number of times a TSX Abort was triggered du= e to a non-release/commit store to lock.", @@ -1012,6 +1126,7 @@ }, { "BriefDescription": "Number of times HLE lock could not be elided = due to ElisionBufferAvailable being zero.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "PublicDescription": "Number of times we could not allocate Lock B= uffer.", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/metricgroups.json b/to= ols/perf/pmu-events/arch/x86/skylakex/metricgroups.json index 904d299c95a3..cccfcab3425e 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/other.json b/tools/per= f/pmu-events/arch/x86/skylakex/other.json index 2511d722327a..44c820518e12 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/other.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for baseline license level 0. This includes non-AVX codes, = SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 1. This includes high current AVX 256-bit= instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Core cycles the core was throttled due to a p= ending power level request.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.THROTTLE", "PublicDescription": "Core cycles the out-of-order engine was thro= ttled due to a pending power level request.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDFE", "SampleAfterValue": "2000003", @@ -40,6 +45,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IFWDM", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IFWDM", "SampleAfterValue": "2000003", @@ -47,6 +53,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITFSE", "SampleAfterValue": "2000003", @@ -54,6 +61,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_IHITI", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_IHITI", "SampleAfterValue": "2000003", @@ -61,6 +69,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDFE", "SampleAfterValue": "2000003", @@ -68,6 +77,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SFWDM", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SFWDM", "SampleAfterValue": "2000003", @@ -75,6 +85,7 @@ }, { "BriefDescription": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", + "Counter": "0,1,2,3", "EventCode": "0xEF", "EventName": "CORE_SNOOP_RESPONSE.RSP_SHITFSE", "SampleAfterValue": "2000003", @@ -82,6 +93,7 @@ }, { "BriefDescription": "Number of hardware interrupts received by the= processor.", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "HW_INTERRUPTS.RECEIVED", "PublicDescription": "Counts the number of hardware interruptions = received by the processor.", @@ -90,6 +102,7 @@ }, { "BriefDescription": "Counts number of cache lines that are dropped= and not written back to L3 as they are deemed to be less likely to be reus= ed shortly", + "Counter": "0,1,2,3", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_DOWNGRADE", "PublicDescription": "Counts number of cache lines that are droppe= d and not written back to L3 as they are deemed to be less likely to be reu= sed shortly.", @@ -98,6 +111,7 @@ }, { "BriefDescription": "Counts number of cache lines that are allocat= ed and written back to L3 with the intention that they are more likely to b= e reused shortly", + "Counter": "0,1,2,3", "EventCode": "0xFE", "EventName": "IDI_MISC.WB_UPGRADE", "PublicDescription": "Counts number of cache lines that are alloca= ted and written back to L3 with the intention that they are more likely to = be reused shortly.", @@ -106,6 +120,7 @@ }, { "BriefDescription": "MEMORY_DISAMBIGUATION.HISTORY_RESET", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "MEMORY_DISAMBIGUATION.HISTORY_RESET", "SampleAfterValue": "2000003", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json b/tools/= perf/pmu-events/arch/x86/skylakex/pipeline.json index c50ddf5b40dd..3dd296ab4d78 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations. Accounts for integer and floating-point oper= ations.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -9,6 +10,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", @@ -17,6 +19,7 @@ }, { "BriefDescription": "All (macro) branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES_PEBS", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.CONDITIONAL]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.COND", @@ -36,6 +40,7 @@ }, { "BriefDescription": "Conditional branch instructions retired. [Thi= s event is alias to BR_INST_RETIRED.COND]", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", @@ -65,6 +72,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", @@ -75,6 +83,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", @@ -85,6 +94,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", @@ -95,6 +105,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3", "Errata": "SKL091", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NOT_TAKEN", @@ -104,6 +115,7 @@ }, { "BriefDescription": "Speculative and retired mispredicted macro co= nditional branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ALL_BRANCHES", "PublicDescription": "This event counts both taken and not taken s= peculative and retired mispredicted branch instructions.", @@ -112,6 +124,7 @@ }, { "BriefDescription": "Speculative mispredicted indirect branches", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT", "PublicDescription": "Counts speculatively miss-predicted indirect= branches at execution time. Counts for indirect near CALL or JMP instructi= ons (RET excluded).", @@ -120,6 +133,7 @@ }, { "BriefDescription": "All mispredicted macro branch instructions re= tired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PublicDescription": "Counts all the retired branch instructions t= hat were mispredicted by the processor. A branch misprediction occurs when = the processor incorrectly predicts the destination of the branch. When the= misprediction is discovered at execution, all the instructions executed in= the wrong (speculative) path must be discarded, and the processor must sta= rt fetching from the correct path.", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Mispredicted macro branch instructions retire= d.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES_PEBS", "PEBS": "2", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Mispredicted direct and indirect near call in= structions retired.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -162,6 +180,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -171,6 +190,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -178,6 +198,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -186,6 +207,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "SampleAfterValue": "25003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the four (eight when Hyperthre= ading is disabled) programmable counters available for other events. Note: = On all current platforms this event stops counting during 'throttling (TM)'= states duty off periods the processor is 'halted'. The counter update is = done at a lower clock rate then the core clock the overflow status bit for = this counter may appear 'sticky'. After the counter has overflowed and sof= tware clears the overflow status bit and resets the counter to less than MA= X. The reset value to the counter is not clocked immediately so the overflo= w status bit will flip 'high (1)' and generate another PMI (if enabled) aft= er which the reset value gets clocked into the counter. Therefore, software= will get the interrupt, read the overflow status bit '1 for bit 34 while t= he counter value is less than MAX. Software should ignore this case.", "SampleAfterValue": "2000003", @@ -207,6 +231,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "SampleAfterValue": "25003", @@ -215,6 +240,7 @@ { "AnyThread": "1", "BriefDescription": "Core crystal clock cycles when at least one t= hread on the physical core is unhalted.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_XCLK_ANY", "SampleAfterValue": "25003", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Counts when there is a transition from ring 1= , 2 or 3 to ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x3C", @@ -231,6 +258,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the four (eight when Hyperthreading is disabled) programmable counters a= vailable for other events.", "SampleAfterValue": "2000003", @@ -239,12 +267,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD_ANY", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -253,12 +283,14 @@ { "AnyThread": "1", "BriefDescription": "Core cycles when at least one thread on the p= hysical core is not in halt state.", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P_ANY", "SampleAfterValue": "2000003" }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -267,6 +299,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -275,6 +308,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -283,6 +317,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -291,6 +326,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -299,6 +335,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3", "CounterMask": "20", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -307,6 +344,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -315,6 +353,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -323,6 +362,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -331,6 +371,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -339,6 +380,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -347,6 +389,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= outstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", "SampleAfterValue": "2000003", @@ -354,6 +397,7 @@ }, { "BriefDescription": "Cycles where no uops were executed, the Reser= vation Station was not empty, the Store Buffer was full and there was no ou= tstanding load.", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Counts cycles during which no uops were exec= uted on all ports and Reservation Station (RS) was not empty.", @@ -362,6 +406,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -370,6 +415,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -378,6 +424,7 @@ }, { "BriefDescription": "Instructions retired from execution.", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PublicDescription": "Counts the number of instructions retired fr= om execution. For instructions that consist of multiple micro-ops, Counts t= he retirement of the last micro-op of the instruction. Counting continues d= uring hardware interrupts, traps, and inside interrupt handlers. Notes: INS= T_RETIRED.ANY is counted by a designated fixed counter, leaving the four (e= ight when Hyperthreading is disabled) programmable counters available for o= ther events. INST_RETIRED.ANY_P is counted by a programmable counter and it= is an architectural performance event. Counting: Faulting executions of GE= TSEC/VM entry/VM Exit/MWait will not count as retired instructions.", "SampleAfterValue": "2000003", @@ -385,6 +432,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", @@ -393,15 +441,17 @@ }, { "BriefDescription": "Number of all retired NOP instructions.", + "Counter": "0,1,2,3", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.NOP", - "PEBS": "2", + "PEBS": "1", "SampleAfterValue": "2000003", "UMask": "0x2" }, { "BriefDescription": "Precise instruction retired event with HW to = reduce effect of PEBS shadow in IP distribution", + "Counter": "1", "Errata": "SKL091, SKL044", "EventCode": "0xC0", "EventName": "INST_RETIRED.PREC_DIST", @@ -412,6 +462,7 @@ }, { "BriefDescription": "Number of cycles using always true condition = applied to PEBS instructions retired event.", + "Counter": "0,2,3", "CounterMask": "10", "Errata": "SKL091, SKL044", "EventCode": "0xC0", @@ -424,6 +475,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0D", @@ -434,6 +486,7 @@ }, { "BriefDescription": "Cycles the issue-stage is waiting for front-e= nd to fetch from resteered path following branch misprediction or machine c= lear events.", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "SampleAfterValue": "2000003", @@ -441,6 +494,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread (e.g. misprediction or me= mory nuke)", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Core cycles the Resource allocator was stall= ed due to recovery from an earlier branch misprediction or machine clear ev= ent.", @@ -450,6 +504,7 @@ { "AnyThread": "1", "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for any thread running on the physical co= re (e.g. misprediction or memory nuke).", + "Counter": "0,1,2,3", "EventCode": "0x0D", "EventName": "INT_MISC.RECOVERY_CYCLES_ANY", "SampleAfterValue": "2000003", @@ -457,6 +512,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "The number of times that split load operatio= ns are temporarily blocked because all resources for handling the split acc= esses are in use.", @@ -465,6 +521,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -473,6 +530,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts false dependencies in MOB when the pa= rtial comparison upon loose net check and dependency was resolved by the En= hanced Loose net mechanism. This may not result in high performance penalti= es. Loose net checks can fail when loads and stores are 4k aliased.", @@ -481,6 +539,7 @@ }, { "BriefDescription": "Demand load dispatches that hit L1D fill buff= er (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE.SW_PF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -489,6 +548,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_OK]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_4_UOPS", @@ -498,6 +558,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.CYCLES_ACTIVE", @@ -507,6 +568,7 @@ }, { "BriefDescription": "Cycles 4 Uops delivered by the LSD, but didn'= t come from the decoder. [This event is alias to LSD.CYCLES_4_UOPS]", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xA8", "EventName": "LSD.CYCLES_OK", @@ -516,6 +578,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "LSD.UOPS", "PublicDescription": "Number of uops delivered to the back-end by = the LSD(Loop Stream Detector).", @@ -524,6 +587,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xC3", @@ -533,6 +597,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -541,6 +606,7 @@ }, { "BriefDescription": "Number of times a microcode assist is invoked= by HW other than FP-assist. Examples include AD (page Access Dirty) and AV= X* related assists.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "OTHER_ASSISTS.ANY", "SampleAfterValue": "100003", @@ -548,6 +614,7 @@ }, { "BriefDescription": "Cycles where the pipeline is stalled due to s= erializing operations.", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "PARTIAL_RAT_STALLS.SCOREBOARD", "PublicDescription": "This event counts cycles during which the mi= crocode scoreboard stalls happen.", @@ -556,6 +623,7 @@ }, { "BriefDescription": "Resource-related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.ANY", "PublicDescription": "Counts resource-related stall cycles.", @@ -564,6 +632,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -572,6 +641,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -580,6 +650,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions (that do= not end up with a VMExit to the VMM; TSX aborted Instructions may be count= ed). This event is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "ROB_MISC_EVENTS.PAUSE_INST", "SampleAfterValue": "2000003", @@ -587,6 +658,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for the thread.; Note: In ST-mode, not active thread s= hould drive 0. This is usually caused by severely costly branch mispredicti= ons, or allocator/FE issues.", @@ -595,6 +667,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty. Could be useful to precisely locate Frontend Latency= Bound issues.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5E", @@ -606,6 +679,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 0", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -614,6 +688,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 1", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -622,6 +697,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 2", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_2", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 2.", @@ -630,6 +706,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 3", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 3.", @@ -638,6 +715,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 4", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_4", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 4.", @@ -646,6 +724,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 5", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -654,6 +733,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 6", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -662,6 +742,7 @@ }, { "BriefDescription": "Cycles per thread when uops are executed in p= ort 7", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UOPS_DISPATCHED_PORT.PORT_7", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 7.", @@ -670,6 +751,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Number of uops executed from any thread.", @@ -678,6 +760,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -686,6 +769,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -694,6 +778,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -702,6 +787,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -710,6 +796,7 @@ }, { "BriefDescription": "Cycles with no micro-ops executed from any th= read on physical core.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_NONE", @@ -719,6 +806,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", @@ -728,6 +816,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2_UOPS_EXEC", @@ -737,6 +826,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3_UOPS_EXEC", @@ -746,6 +836,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3", "CounterMask": "4", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4_UOPS_EXEC", @@ -755,6 +846,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -765,6 +857,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.THREAD", "PublicDescription": "Number of uops to be executed per-thread eac= h cycle.", @@ -773,6 +866,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -781,6 +875,7 @@ }, { "BriefDescription": "Uops that Resource Allocation Table (RAT) iss= ues to Reservation Station (RS)", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -789,6 +884,7 @@ }, { "BriefDescription": "Number of slow LEA uops being allocated. A uo= p is generally considered SlowLea if it has 3 sources (e.g. 2 sources + imm= ediate) regardless if as a result of LEA instruction or not.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.SLOW_LEA", "SampleAfterValue": "2000003", @@ -796,6 +892,7 @@ }, { "BriefDescription": "Cycles when Resource Allocation Table (RAT) d= oes not issue Uops to Reservation Station (RS) for the thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -806,6 +903,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3", "EventCode": "0x0E", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -814,6 +912,7 @@ }, { "BriefDescription": "Number of macro-fused uops retired. (non prec= ise)", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PublicDescription": "Counts the number of macro-fused uops retire= d. (non precise)", @@ -822,6 +921,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PublicDescription": "Counts the retirement slots used.", @@ -830,6 +930,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -840,6 +941,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json b/too= ls/perf/pmu-events/arch/x86/skylakex/skx-metrics.json index 8126f952a30c..e5e86892d7bb 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/skx-metrics.json @@ -68,7 +68,7 @@ }, { "BriefDescription": "Percentage of time spent in the active CPU po= wer state C0", - "MetricExpr": "tma_info_system_cpu_utilization", + "MetricExpr": "tma_info_system_cpus_utilized", "MetricName": "cpu_utilization", "ScaleUnit": "100%" }, @@ -163,7 +163,7 @@ }, { "BriefDescription": "Ratio of number of code read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12C= C0233@ / INST_RETIRED.ANY", + "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12c= c0233@ / INST_RETIRED.ANY", "MetricName": "llc_code_read_mpi_demand_plus_prefetch", "ScaleUnit": "1per_instr" }, @@ -187,7 +187,7 @@ }, { "BriefDescription": "Ratio of number of data read requests missing= last level core cache (includes demand w/ prefetches) to the total number = of completed instructions", - "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12D= 40433@ / INST_RETIRED.ANY", + "MetricExpr": "cha@UNC_CHA_TOR_INSERTS.IA_MISS\\,config1\\=3D0x12d= 40433@ / INST_RETIRED.ANY", "MetricName": "llc_data_read_mpi_demand_plus_prefetch", "ScaleUnit": "1per_instr" }, @@ -310,7 +310,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * (FP_ASSIST.ANY + OTHER_ASSISTS.ANY) / tma_info= _thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: OTHER_ASSISTS.AN= Y", @@ -319,7 +319,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "MetricExpr": "1 - tma_frontend_bound - (UOPS_ISSUED.ANY + 4 * (IN= T_MISC.RECOVERY_CYCLES_ANY / 2 if #SMT_on else INT_MISC.RECOVERY_CYCLES)) /= tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1", @@ -340,7 +340,7 @@ "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -378,7 +378,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(44 * tma_info_system_core_frequency * (MEM_LOAD_L3= _HIT_RETIRED.XSNP_HITM * (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER= _CORE / (OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_R= ESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) + 44 * tma_info_system_= core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS) * (1 + MEM_LOAD_RETIRED= .FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_HITM_PS;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS_PS. Re= lated metrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma= _remote_cache", @@ -399,7 +399,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "44 * tma_info_system_core_frequency * (MEM_LOAD_L3_= HIT_RETIRED.XSNP_HIT + MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM * (1 - OFFCORE_RES= PONSE.DEMAND_DATA_RD.L3_HIT.HITM_OTHER_CORE / (OFFCORE_RESPONSE.DEMAND_DATA= _RD.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.DEMAND_DATA_RD.L3_HIT.SNOOP_H= IT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / = 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_HIT_PS. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -417,7 +417,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -448,14 +448,14 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "min(9 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -464,7 +464,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(9 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -474,7 +474,7 @@ "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(110 * tma_info_system_core_frequency * (OFFCORE_RE= SPONSE.DEMAND_RFO.L3_MISS.REMOTE_HITM + OFFCORE_RESPONSE.PF_L2_RFO.L3_MISS.= REMOTE_HITM) + 47.5 * tma_info_system_core_frequency * (OFFCORE_RESPONSE.DE= MAND_RFO.L3_HIT.HITM_OTHER_CORE + OFFCORE_RESPONSE.PF_L2_RFO.L3_HIT.HITM_OT= HER_CORE)) / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: MEM_LOAD_L3_HIT_= RETIRED.XSNP_HITM_PS;OFFCORE_RESPONSE.DEMAND_RFO.L3_HIT.SNOOP_HITM. Related= metrics: tma_contested_accesses, tma_data_sharing, tma_machine_clears, tma= _remote_cache", @@ -484,7 +484,7 @@ "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_info_memory_load_miss_real_latency * cpu@L1D_PE= ND_MISS.FB_FULL\\,cmask\\=3D1@ / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -497,7 +497,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -512,6 +512,7 @@ }, { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring instructions that that are decoder into two or up to= ([SNB+] four; [ADL+] five) uops", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "tma_heavy_operations - tma_microcode_sequencer", "MetricGroup": "TopdownL3;tma_L3_group;tma_heavy_operations_group;= tma_issueD0", "MetricName": "tma_few_uops_instructions", @@ -540,7 +541,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / UOPS_RETIRED.RETIRE_SLOTS", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / UOPS_RETIRED.RETIRE_= SLOTS", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -587,7 +588,7 @@ { "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / tma_info_thread_slots= ", - "MetricGroup": "PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;PGO;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1", @@ -597,7 +598,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring fused instructions -- where one uop can represent mu= ltiple contiguous instructions", "MetricExpr": "tma_light_operations * UOPS_RETIRED.MACRO_FUSED / U= OPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_fused_instructions", "MetricThreshold": "tma_fused_instructions > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring fused instructions -- where one uop can represent m= ultiple contiguous instructions. CMP+JCC or DEC+JCC are common examples of = legacy fusions. {([MTL] Note new MOV+OP and Load+OP fusions appear under Ot= her_Light_Ops in MTL!)}", @@ -616,7 +617,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "(ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16B.IFDAT= A_STALL\\,cmask\\=3D1\\,edge@) / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -649,24 +650,6 @@ "MetricGroup": "BrMispredicts", "MetricName": "tma_info_bad_spec_spec_clears_ratio" }, - { - "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", - "MetricExpr": "(100 * (1 - tma_core_bound / (((EXE_ACTIVITY.EXE_BO= UND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTED.T= HREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / CPU= _CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_UTIL= + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD if = ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_= MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_POR= TS_UTIL) / CPU_CLK_UNHALTED.THREAD) if tma_core_bound < (((EXE_ACTIVITY.EXE= _BOUND_0_PORTS + tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / CPU_CLK_UNHALTE= D.THREAD * (CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / = CPU_CLK_UNHALTED.THREAD * CPU_CLK_UNHALTED.THREAD + (EXE_ACTIVITY.1_PORTS_U= TIL + tma_retiring * EXE_ACTIVITY.2_PORTS_UTIL)) / CPU_CLK_UNHALTED.THREAD = if ARITH.DIVIDER_ACTIVE < CYCLE_ACTIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STAL= LS_MEM_ANY else (EXE_ACTIVITY.1_PORTS_UTIL + tma_retiring * EXE_ACTIVITY.2_= PORTS_UTIL) / CPU_CLK_UNHALTED.THREAD) else 1) if tma_info_system_smt_2t_ut= ilization > 0.5 else 0)", - "MetricGroup": "Cor;SMT", - "MetricName": "tma_info_botlnk_core_bound_likely" - }, - { - "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck.", - "MetricExpr": "100 * (100 * (tma_fetch_latency * (DSB2MITE_SWITCHE= S.PENALTY_CYCLES / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2= * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@) / CPU_CLK_U= NHALTED.THREAD + ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CL= EAR_RESTEER_CYCLES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_U= NHALTED.THREAD) + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + D= ECODE.LCP / CPU_CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CP= U_CLK_UNHALTED.THREAD) + tma_fetch_bandwidth * tma_mite / (tma_mite + tma_d= sb)))", - "MetricGroup": "DSBmiss;Fed", - "MetricName": "tma_info_botlnk_dsb_misses" - }, - { - "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck.", - "MetricExpr": "100 * (100 * (tma_fetch_latency * ((ICACHE_16B.IFDA= TA_STALL + 2 * cpu@ICACHE_16B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@)= / CPU_CLK_UNHALTED.THREAD) / ((ICACHE_16B.IFDATA_STALL + 2 * cpu@ICACHE_16= B.IFDATA_STALL\\,cmask\\=3D0x1\\,edge\\=3D0x1@) / CPU_CLK_UNHALTED.THREAD += ICACHE_TAG.STALLS / CPU_CLK_UNHALTED.THREAD + (INT_MISC.CLEAR_RESTEER_CYCL= ES / CPU_CLK_UNHALTED.THREAD + 9 * BACLEARS.ANY / CPU_CLK_UNHALTED.THREAD) = + min(2 * IDQ.MS_SWITCHES / CPU_CLK_UNHALTED.THREAD, 1) + DECODE.LCP / CPU_= CLK_UNHALTED.THREAD + DSB2MITE_SWITCHES.PENALTY_CYCLES / CPU_CLK_UNHALTED.T= HREAD)))", - "MetricGroup": "Fed;FetchLat;IcMiss", - "MetricName": "tma_info_botlnk_ic_misses" - }, { "BriefDescription": "Probability of Core Bound bottleneck hidden b= y SMT-profiling artifacts", "MetricConstraint": "NO_GROUP_EVENTS", @@ -675,6 +658,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_mite= )))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -682,7 +673,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -692,40 +683,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency)) + tma_memory_bound * (tma_l1_bound / (tma_dram_bound + tm= a_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_l1_hit_= latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_full + tma_l1_hit_laten= cy + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -733,23 +718,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -757,8 +742,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store /= (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency= )))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_spl= it_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma= _dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)= ) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_store= s + tma_store_latency)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -766,7 +751,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) * tma_remote_cach= e / (tma_local_mem + tma_remote_cache + tma_remote_mem) + tma_l3_bound / (t= ma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_boun= d) * (tma_contested_accesses + tma_data_sharing) / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / = (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bo= und) * tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_= stores + tma_store_latency - tma_store_latency)) + tma_machine_clears * (1 = - tma_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -775,18 +760,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -840,7 +832,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + cpu@FP_ARITH_INST_R= ETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) / (2 * tma_info_core_core_clks= )", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -857,7 +849,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 4 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -918,7 +910,7 @@ { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -1008,18 +1000,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 9", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" - }, - { - "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", - "MetricExpr": "tma_info_memory_tlb_code_stlb_mpki", - "MetricGroup": "Fed;MemoryTLB", - "MetricName": "tma_info_memory_code_stlb_mpki" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -1057,12 +1043,6 @@ "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_core_l3_cache_fill_bw_2t" }, - { - "BriefDescription": "Average Parallel L2 cache miss data reads", - "MetricExpr": "tma_info_memory_latency_data_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_data_l2_mlp" - }, { "BriefDescription": "Fill Buffer (FB) hits per kilo instructions f= or retired demand loads (L1D misses that merge into ongoing miss-handling e= ntries)", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.FB_HIT / INST_RETIRED.ANY", @@ -1070,17 +1050,11 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", - "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l1d_cache_fill_bw_2t" - }, { "BriefDescription": "L1 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L1_MISS / INST_RETIRED.ANY", @@ -1094,29 +1068,11 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 2 cache [GB / sec]", - "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / (duration_time * 1e3 /= 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l2_cache_fill_bw_2t" - }, - { - "BriefDescription": "Rate of non silent evictions from the L2 cach= e per Kilo instruction", - "MetricExpr": "1e3 * L2_LINES_OUT.NON_SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_nonsilent_pki" - }, - { - "BriefDescription": "Rate of silent evictions from the L2 cache pe= r Kilo instruction where the evicted lines are dropped (no writeback to L3 = or memory)", - "MetricExpr": "1e3 * L2_LINES_OUT.SILENT / INST_RETIRED.ANY", - "MetricGroup": "L2Evicts;Mem;Server", - "MetricName": "tma_info_memory_l2_evictions_silent_pki" - }, { "BriefDescription": "L2 cache hits per kilo instruction for all re= quest types (including speculative)", "MetricExpr": "1e3 * (L2_RQSTS.REFERENCES - L2_RQSTS.MISS) / INST_= RETIRED.ANY", @@ -1148,29 +1104,23 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", - "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw" + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * OFFCORE_REQUESTS.DEMAND_RFO / INST_RETIRED.AN= Y", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" }, { - "BriefDescription": "Average per-core data access bandwidth to the= L3 cache [GB / sec]", - "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / (duratio= n_time * 1e3 / 1e3)", + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", + "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", - "MetricName": "tma_info_memory_l3_cache_access_bw_2t" + "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" }, - { - "BriefDescription": "Average per-core data fill bandwidth to the L= 3 cache [GB / sec]", - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / (duration_time = * 1e3 / 1e3)", - "MetricGroup": "Mem;MemoryBW", - "MetricName": "tma_info_memory_l3_cache_fill_bw_2t" - }, { "BriefDescription": "L3 cache true misses per kilo instruction for= retired demand loads", "MetricExpr": "1e3 * MEM_LOAD_RETIRED.L3_MISS / INST_RETIRED.ANY", @@ -1183,29 +1133,17 @@ "MetricGroup": "Memory_BW;Offcore", "MetricName": "tma_info_memory_latency_data_l2_mlp" }, - { - "BriefDescription": "Average Latency for L2 cache miss demand Load= s", - "MetricExpr": "tma_info_memory_load_l2_miss_latency", - "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_miss_latency" - }, - { - "BriefDescription": "Average Parallel L2 cache miss demand Loads", - "MetricExpr": "tma_info_memory_load_l2_mlp", - "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_latency_load_l2_mlp" - }, { "BriefDescription": "Average Latency for L2 cache miss demand Load= s", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS.DEMAND_DATA_RD", "MetricGroup": "Memory_Lat;Offcore", - "MetricName": "tma_info_memory_load_l2_miss_latency" + "MetricName": "tma_info_memory_latency_load_l2_miss_latency" }, { "BriefDescription": "Average Parallel L2 cache miss demand Loads", "MetricExpr": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD / OFFCO= RE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", "MetricGroup": "Memory_BW;Offcore", - "MetricName": "tma_info_memory_load_l2_mlp" + "MetricName": "tma_info_memory_latency_load_l2_mlp" }, { "BriefDescription": "Actual Average Latency for L1 data-cache miss= demand load operations (in core cycles)", @@ -1213,15 +1151,9 @@ "MetricGroup": "Mem;MemoryBound;MemoryLat", "MetricName": "tma_info_memory_load_miss_real_latency" }, - { - "BriefDescription": "STLB (2nd level TLB) data load speculative mi= sses per kilo instruction (misses of any page-size that complete the page w= alk)", - "MetricExpr": "tma_info_memory_tlb_load_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_load_stlb_mpki" - }, { "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "tma_info_memory_uc_load_pki", + "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", "MetricGroup": "Mem", "MetricName": "tma_info_memory_mix_uc_load_pki" }, @@ -1232,18 +1164,6 @@ "MetricName": "tma_info_memory_mlp", "PublicDescription": "Memory-Level-Parallelism (average number of = L1 miss demand load when there is at least one such miss. Per-Logical Proce= ssor)" }, - { - "BriefDescription": "Utilization of the core's Page Walker(s) serv= ing STLB misses triggered by instruction/Load/Store accesses", - "MetricExpr": "tma_info_memory_tlb_page_walks_utilization", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_page_walks_utilization" - }, - { - "BriefDescription": "STLB (2nd level TLB) data store speculative m= isses per kilo instruction (misses of any page-size that complete the page = walk)", - "MetricExpr": "tma_info_memory_tlb_store_stlb_mpki", - "MetricGroup": "Mem;MemoryTLB", - "MetricName": "tma_info_memory_store_stlb_mpki" - }, { "BriefDescription": "STLB (2nd level TLB) code speculative misses = per kilo instruction (misses of any page-size that complete the page walk)", "MetricExpr": "1e3 * ITLB_MISSES.WALK_COMPLETED / INST_RETIRED.ANY= ", @@ -1271,17 +1191,23 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "Un-cacheable retired load per kilo instructio= n", - "MetricExpr": "1e3 * MEM_LOAD_MISC_RETIRED.UC / INST_RETIRED.ANY", - "MetricGroup": "Mem", - "MetricName": "tma_info_memory_uc_load_pki" - }, - { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / (FP_ASSIST.ANY + OTHER_ASSISTS.A= NY)", @@ -1304,13 +1230,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1470,7 +1396,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TA= KEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1479,7 +1405,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1494,11 +1420,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + cpu@L1D_PEND_MISS.FB_FULL\\,cm= ask\\=3D1@) * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_M= ISS) / tma_info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1516,7 +1451,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "17 * tma_info_system_core_frequency * (MEM_LOAD_RET= IRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2))= / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1528,7 +1463,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1573,7 +1508,7 @@ "MetricGroup": "Server;TopdownL5;tma_L5_group;tma_mem_latency_grou= p", "MetricName": "tma_local_mem", "MetricThreshold": "tma_local_mem > 0.1 & (tma_mem_latency > 0.1 &= (tma_dram_bound > 0.1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2)= ))", - "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM_PS", + "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling loads from local memory. Caching will = improve the latency and increase performance. Sample with: MEM_LOAD_L3_MISS= _RETIRED.LOCAL_DRAM", "ScaleUnit": "100%" }, { @@ -1582,14 +1517,14 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "tma_bad_speculation - tma_branch_mispredicts", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1599,7 +1534,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1608,7 +1543,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1635,6 +1570,7 @@ }, { "BriefDescription": "This metric represents fraction of slots the = CPU was retiring uops fetched by the Microcode Sequencer (MS) unit", + "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / UOPS_ISSUED.ANY * IDQ.M= S_UOPS / tma_info_thread_slots", "MetricGroup": "MicroSeq;TopdownL3;tma_L3_group;tma_heavy_operatio= ns_group;tma_issueMC;tma_issueMS", "MetricName": "tma_microcode_sequencer", @@ -1645,7 +1581,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1681,7 +1617,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions that were not fused", "MetricExpr": "tma_light_operations * (BR_INST_RETIRED.ALL_BRANCHE= S - UOPS_RETIRED.MACRO_FUSED) / UOPS_RETIRED.RETIRE_SLOTS", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_non_fused_branches", "MetricThreshold": "tma_non_fused_branches > 0.1 & tma_light_opera= tions > 0.6", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring branch instructions that were not fused. Non-condit= ional branches like direct JMP or CALL would count here. Can be used to exa= mine fusible conditional jumps that were not fused.", @@ -1690,7 +1626,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / UOPS_RETI= RED.RETIRE_SLOTS", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1708,7 +1644,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1716,7 +1652,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1804,7 +1740,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(EXE_ACTIVITY.EXE_BOUND_0_PORTS + tma_core_bound * = RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_ACTIVITY.STALLS_TOT= AL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks", + "MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_cl= ks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1832,7 +1768,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise).", "MetricExpr": "(UOPS_EXECUTED.CORE_CYCLES_GE_3 / 2 if #SMT_on else= UOPS_EXECUTED.CORE_CYCLES_GE_3) / tma_info_core_core_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "ScaleUnit": "100%" @@ -1859,7 +1795,7 @@ { "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / tma_info_thread_slots", - "MetricGroup": "TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1", @@ -1869,7 +1805,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "PARTIAL_RAT_STALLS.SCOREBOARD / tma_info_thread_clk= s", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: PARTIAL_RAT_STALLS.SCOREBOARD. Related me= trics: tma_ms_switches", @@ -1897,7 +1833,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "(OFFCORE_REQUESTS_BUFFER.SQ_FULL / 2 if #SMT_on els= e OFFCORE_REQUESTS_BUFFER.SQ_FULL) / tma_info_core_core_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1925,7 +1861,7 @@ "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricConstraint": "NO_GROUP_EVENTS_NMI", "MetricExpr": "(L2_RQSTS.RFO_HIT * 11 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1958,7 +1894,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "9 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-cache.json index 543dfc1e5ad7..da46a3aeb58c 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-cache.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -19,8 +23,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -28,8 +34,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -37,8 +45,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -46,8 +56,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -55,8 +67,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -64,8 +78,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -73,8 +89,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -82,8 +100,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -91,8 +111,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -100,8 +122,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -109,8 +133,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -118,8 +144,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -127,8 +155,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -136,8 +166,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -145,8 +177,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -154,8 +188,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -163,8 +199,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -172,8 +210,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -181,8 +221,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -190,8 +232,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -199,8 +243,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -208,8 +254,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -217,8 +265,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -226,8 +276,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -235,8 +287,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -244,8 +298,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -253,8 +309,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -262,8 +320,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -271,8 +331,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -280,8 +342,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -289,8 +353,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -298,8 +364,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -307,8 +375,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -316,8 +386,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -325,8 +397,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -334,8 +408,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -343,8 +419,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -352,8 +430,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -361,8 +441,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -370,8 +452,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -379,8 +463,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -388,8 +474,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -397,8 +485,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -406,8 +496,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -415,8 +507,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -424,8 +518,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -433,8 +529,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Intermediate bypass Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the intermediate bypass.", "UMask": "0x2", @@ -442,8 +540,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that could not take the bypass, and issues a read to memory.= Note that transactions that did not take the bypass but did not issue read= to memory will not be counted.", "UMask": "0x4", @@ -451,8 +551,10 @@ }, { "BriefDescription": "CHA to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = able to bypass HA pipe on the way to iMC. This is a latency optimization f= or situations when there is light loadings on the memory subsystem. This c= an be filtered by when the bypass was taken and when it was not.; Filter fo= r transactions that succeeded in taking the full bypass.", "UMask": "0x1", @@ -460,6 +562,7 @@ }, { "BriefDescription": "Clockticks of the uncore caching & home agent= (CHA)", + "Counter": "0,1,2,3", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts clockticks of the clock controlling t= he uncore caching and home agent (CHA).", @@ -467,55 +570,69 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C1 State", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C1_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C1 Transition", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C1_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C6 State", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C6_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; C6 Transition", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.C6_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Core PMA Events; GV", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_CHA_CORE_PMA.GV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Core Cross Snoops Issued; Any Cycle with Mult= iple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe2", @@ -523,8 +640,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe1", @@ -532,8 +651,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Any Snoop to Remote= Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0xe4", @@ -541,6 +662,7 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple Core Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", "PerPkg": "1", @@ -550,8 +672,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single Core Request= s", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x41", @@ -559,8 +683,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Core Request to Rem= ote Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x44", @@ -568,6 +694,7 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", "PerPkg": "1", @@ -577,8 +704,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x81", @@ -586,8 +715,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Eviction to Remote = Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x84", @@ -595,8 +726,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Multiple External S= noops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x22", @@ -604,8 +737,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; Single External Sno= ops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x21", @@ -613,8 +748,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued; External Snoop to R= emote Node", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of transactions that trigg= er a configurable number of cross snoops. Cores are snooped if the transac= tion looks up the cache and determines that it is necessary based on the op= eration type and what CoreValid bits are set. For example, if 2 CV bits ar= e set on a data read, the cores must have the data in S state so it is not = necessary to snoop them. However, if only 1 CV bit is set the core my have= modified the data. If the transaction was an RFO, it would need to invali= date the lines. This event can be filtered based on who triggered the init= ial snoop(s).", "UMask": "0x24", @@ -622,14 +759,17 @@ }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Since occupancy counts can only be captured = in the Cbo's 0 counter, this event allows a user to capture occupancy relat= ed information by filtering the Cb0 occupancy count captured in Counter 0. = The filtering available is found in the control register - threshold, inv= ert and edge detect. E.g. setting threshold to 1 can effectively monitor = how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Not Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.NO_SNP", "PerPkg": "1", @@ -639,6 +779,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state lookup= s; Snoop Needed", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_CHA_DIR_LOOKUP.SNP", "PerPkg": "1", @@ -648,6 +789,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from the HA pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.HA", "PerPkg": "1", @@ -657,6 +799,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory state update= s; Directory Updated memory write from TOR pipe", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_CHA_DIR_UPDATE.TOR", "PerPkg": "1", @@ -666,8 +809,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -675,8 +820,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -684,6 +831,7 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_FAST_ASSERTED.HORZ", "PerPkg": "1", @@ -693,8 +841,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -702,6 +852,7 @@ }, { "BriefDescription": "Read request from a remote socket which hit i= n the HitMe Cache to a line In the E state", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.EX_RDS", "PerPkg": "1", @@ -711,80 +862,100 @@ }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; Shared = hit and op is RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoE", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Hits in HitMe Cache; op is W= bMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is RdCode, RdData, RdDataMigratory, RdCur, RdInvOwn, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times HitMe Cache is accesse= d; op is WbMtoE, WbMtoI, WbPushMtoI, WbFlush, or WbMtoS", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_CHA_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; No SF= /LLC HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; op is= RdCode, RdData, RdDataMigratory, RdCur, RdInv, Inv*", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Counts Number of Misses in HitMe Cache; SF/LL= C HitS/F and op is RdInvOwn", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Deallocate HitME$ on Reads without RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a local request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Received RspFwdI* for a local request, but c= onverted HitME$ to SF entry", "UMask": "0x1", @@ -792,16 +963,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache on RdInvOwn even if not RspFwdI*", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; op is RspIFwd or RspIFwdWb for a remote request", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Updated HitME$ on RspFwdI* or local HitM/E r= eceived for a remote request", "UMask": "0x2", @@ -809,16 +984,20 @@ }, { "BriefDescription": "Counts the number of Allocate/Update to HitMe= Cache; Update HitMe Cache to SHARed", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_CHA_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -826,8 +1005,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -835,8 +1016,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -844,8 +1027,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -853,8 +1038,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -862,8 +1049,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -871,8 +1060,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -880,8 +1071,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -889,8 +1082,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -898,8 +1093,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -907,8 +1104,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -916,8 +1115,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -925,8 +1126,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -934,8 +1137,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -943,6 +1148,7 @@ }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -952,8 +1158,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued; ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count of the number of reads issued to any o= f the memory controller channels. This can be filtered by the priority of = the reads.", "UMask": "0x2", @@ -961,6 +1169,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued; Full Line= Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -970,8 +1179,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Full Line= MIG", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x10", @@ -979,8 +1190,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Ful= l Line", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x4", @@ -988,8 +1201,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Partial N= on-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x2", @@ -997,8 +1212,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; Partial M= IG", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.; Filter for memory c= ontroller 5 only.", "UMask": "0x20", @@ -1006,8 +1223,10 @@ }, { "BriefDescription": "Writes Issued to the iMC by the HA; ISOCH Par= tial", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of writes issued fro= m the HA into the memory controller. This counts for all four channels. I= t can be filtered by full/partial and ISOCH/non-ISOCH.", "UMask": "0x8", @@ -1015,64 +1234,80 @@ }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.INVITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IODC allocations dropped due to IODC Full", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.IODCFULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts Number of times IODC entry allocation = is attempted; Number of IDOC allocation dropped due to OSB gate", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_CHA_IODC_ALLOC.OSBGATED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to any reason", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to conflicting transaction", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.SNPOUT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoE", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbMtoI", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Counts number of IODC deallocations; IODC dea= llocated due to WbPushMtoI", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Moved to Cbo section", "UMask": "0x4", @@ -1080,8 +1315,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x11", @@ -1089,8 +1326,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Read transactions", "UMask": "0x3", @@ -1098,8 +1337,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Local", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", "UMask": "0x31", @@ -1107,8 +1348,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Remote", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.", "UMask": "0x91", @@ -1116,8 +1359,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; External Snoo= p Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for only snoop requests c= oming from the remote socket(s) through the IPQ.", "UMask": "0x9", @@ -1125,8 +1370,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Write Request= s", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Writeback transactions from L2 to= the LLC This includes all write transactions -- both Cacheable and UC.", "UMask": "0x5", @@ -1134,35 +1381,43 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.F_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x2f", @@ -1170,8 +1425,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x22", @@ -1179,8 +1436,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x28", @@ -1188,8 +1447,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x21", @@ -1197,8 +1458,10 @@ }, { "BriefDescription": "Lines Victimized; Local - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x24", @@ -1206,26 +1469,32 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Remote - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x8f", @@ -1233,8 +1502,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x82", @@ -1242,8 +1513,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x88", @@ -1251,8 +1524,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x81", @@ -1260,8 +1535,10 @@ }, { "BriefDescription": "Lines Victimized; Remote - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.REMOTE_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of lines that were victimi= zed on a fill. This can be filtered by the state that the line was in.", "UMask": "0x84", @@ -1269,15 +1546,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized; Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_E", "PerPkg": "1", @@ -1287,6 +1567,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in F State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_F", "PerPkg": "1", @@ -1296,6 +1577,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_M", "PerPkg": "1", @@ -1305,6 +1587,7 @@ }, { "BriefDescription": "Lines Victimized; Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.TOTAL_S", "PerPkg": "1", @@ -1314,8 +1597,10 @@ }, { "BriefDescription": "Cbo Misc; CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x20", @@ -1323,8 +1608,10 @@ }, { "BriefDescription": "Cbo Misc; CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.", "UMask": "0x10", @@ -1332,6 +1619,7 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", "PerPkg": "1", @@ -1341,8 +1629,10 @@ }, { "BriefDescription": "Cbo Misc; Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times when a Snoop hit in FSE states and triggered a silent evic= tion. This is useful because this information is lost in the PRE encodings= .", "UMask": "0x1", @@ -1350,8 +1640,10 @@ }, { "BriefDescription": "Cbo Misc; Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Miscellaneous events in the Cbo.; Counts the= number of times that a USWC write (WCIL(F)) transaction hit in the LLC in = M state, triggering a WBMtoI followed by the USWC write. This occurs when = there is WC aliasing.", "UMask": "0x2", @@ -1359,16 +1651,20 @@ }, { "BriefDescription": "OSB Snoop Broadcast", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_CHA_OSB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count of OSB snoop broadcasts. Counts by 1 p= er request causing OSB snoops to be broadcast. Does not count all the snoop= s generated by OSB.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 2 only.", "UMask": "0x4", @@ -1376,8 +1672,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 3 only.", "UMask": "0x8", @@ -1385,8 +1683,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 4 only.", "UMask": "0x10", @@ -1394,8 +1694,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 5 only.", "UMask": "0x20", @@ -1403,8 +1705,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 0 only.", "UMask": "0x1", @@ -1412,8 +1716,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending reads from the CHA into the iMC. In order t= o send reads into the memory controller, the HA must first acquire a credit= for the iMC's AD Ingress queue.; Filter for memory controller 1 only.", "UMask": "0x2", @@ -1421,6 +1727,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_LOCAL", "PerPkg": "1", @@ -1430,6 +1737,7 @@ }, { "BriefDescription": "Local requests for exclusive ownership of a c= ache line without receiving data", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE_REMOTE", "PerPkg": "1", @@ -1439,6 +1747,7 @@ }, { "BriefDescription": "Read requests", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -1448,6 +1757,7 @@ }, { "BriefDescription": "Read requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_LOCAL", "PerPkg": "1", @@ -1457,6 +1767,7 @@ }, { "BriefDescription": "Read requests from a remote socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS_REMOTE", "PerPkg": "1", @@ -1466,6 +1777,7 @@ }, { "BriefDescription": "Write requests", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -1475,6 +1787,7 @@ }, { "BriefDescription": "Write Requests from a unit on this socket", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_LOCAL", "PerPkg": "1", @@ -1484,6 +1797,7 @@ }, { "BriefDescription": "Read and Write Requests; Writes Remote", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES_REMOTE", "PerPkg": "1", @@ -1493,8 +1807,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -1502,8 +1818,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -1511,8 +1829,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -1520,8 +1840,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -1529,8 +1851,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -1538,8 +1862,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -1547,8 +1873,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -1556,8 +1884,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -1565,87 +1895,109 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Allocations; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x4", @@ -1653,6 +2005,7 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", "PerPkg": "1", @@ -1662,8 +2015,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; IRQ Rejected", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x2", @@ -1671,8 +2026,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x10", @@ -1680,8 +2037,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x20", @@ -1689,8 +2048,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; RRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x40", @@ -1698,8 +2059,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations; WBQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of allocations per cycle into = the specified Ingress queue.", "UMask": "0x80", @@ -1707,238 +2070,297 @@ }, { "BriefDescription": "Ingress Probe Queue Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Non UPI AK Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Non UPI IV Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_CHA_RxC_IPQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Merging these tw= o together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress Probe Queue Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Mer= ging these two together to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", "PerPkg": "1", @@ -1947,24 +2369,30 @@ }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -1972,8 +2400,10 @@ }, { "BriefDescription": "ISMQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -1981,8 +2411,10 @@ }, { "BriefDescription": "ISMQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x40", @@ -1990,8 +2422,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x10", @@ -1999,8 +2433,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x20", @@ -2008,8 +2444,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x4", @@ -2017,8 +2455,10 @@ }, { "BriefDescription": "ISMQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x8", @@ -2026,8 +2466,10 @@ }, { "BriefDescription": "ISMQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x80", @@ -2035,8 +2477,10 @@ }, { "BriefDescription": "ISMQ Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2044,8 +2488,10 @@ }, { "BriefDescription": "ISMQ Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2053,8 +2499,10 @@ }, { "BriefDescription": "ISMQ Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x40", @@ -2062,8 +2510,10 @@ }, { "BriefDescription": "ISMQ Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x10", @@ -2071,8 +2521,10 @@ }, { "BriefDescription": "ISMQ Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x20", @@ -2080,8 +2532,10 @@ }, { "BriefDescription": "ISMQ Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x4", @@ -2089,8 +2543,10 @@ }, { "BriefDescription": "ISMQ Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x8", @@ -2098,8 +2554,10 @@ }, { "BriefDescription": "ISMQ Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x80", @@ -2107,8 +2565,10 @@ }, { "BriefDescription": "ISMQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2116,8 +2576,10 @@ }, { "BriefDescription": "ISMQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2125,8 +2587,10 @@ }, { "BriefDescription": "ISMQ Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x1", @@ -2134,8 +2598,10 @@ }, { "BriefDescription": "ISMQ Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the ISMQ had to retry. Transaction pass through the ISMQ as responses fo= r requests that already exist in the Cbo. Some examples include: when data= is returned or when snoop responses come back from the cores.", "UMask": "0x2", @@ -2143,8 +2609,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; IPQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x4", @@ -2152,6 +2620,7 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", "PerPkg": "1", @@ -2161,8 +2630,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; RRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x40", @@ -2170,8 +2641,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy; WBQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of entries in the specified In= gress queue in each cycle.", "UMask": "0x80", @@ -2179,8 +2652,10 @@ }, { "BriefDescription": "Other Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x1", @@ -2188,8 +2663,10 @@ }, { "BriefDescription": "Other Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x2", @@ -2197,8 +2674,10 @@ }, { "BriefDescription": "Other Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x40", @@ -2206,8 +2685,10 @@ }, { "BriefDescription": "Other Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x10", @@ -2215,8 +2696,10 @@ }, { "BriefDescription": "Other Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x20", @@ -2224,8 +2707,10 @@ }, { "BriefDescription": "Other Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x4", @@ -2233,8 +2718,10 @@ }, { "BriefDescription": "Other Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x8", @@ -2242,8 +2729,10 @@ }, { "BriefDescription": "Other Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x80", @@ -2251,8 +2740,10 @@ }, { "BriefDescription": "Other Retries; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x40", @@ -2260,8 +2751,10 @@ }, { "BriefDescription": "Other Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x1", @@ -2269,8 +2762,10 @@ }, { "BriefDescription": "Other Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x2", @@ -2278,8 +2773,10 @@ }, { "BriefDescription": "Other Retries; Merging these two together to = make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x20", @@ -2287,8 +2784,10 @@ }, { "BriefDescription": "Other Retries; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x4", @@ -2296,8 +2795,10 @@ }, { "BriefDescription": "Other Retries; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x80", @@ -2305,8 +2806,10 @@ }, { "BriefDescription": "Other Retries; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x8", @@ -2314,8 +2817,10 @@ }, { "BriefDescription": "Other Retries; Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Retry Queue Inserts of Transactions that wer= e already in another Retry Q (sub-events encode the reason for the next rej= ect)", "UMask": "0x10", @@ -2323,136 +2828,170 @@ }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; AD = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; BL = WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Non= UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; All= ow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; ANY= 0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; LLC= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; SF = Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Vic= tim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x1", @@ -2460,8 +2999,10 @@ }, { "BriefDescription": "Request Queue Retries; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x2", @@ -2469,8 +3010,10 @@ }, { "BriefDescription": "Request Queue Retries; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x40", @@ -2478,8 +3021,10 @@ }, { "BriefDescription": "Request Queue Retries; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", @@ -2487,8 +3032,10 @@ }, { "BriefDescription": "Request Queue Retries; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", @@ -2496,8 +3043,10 @@ }, { "BriefDescription": "Request Queue Retries; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x4", @@ -2505,8 +3054,10 @@ }, { "BriefDescription": "Request Queue Retries; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x8", @@ -2514,8 +3065,10 @@ }, { "BriefDescription": "Request Queue Retries; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x80", @@ -2523,8 +3076,10 @@ }, { "BriefDescription": "Request Queue Retries; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x40", @@ -2532,8 +3087,10 @@ }, { "BriefDescription": "Request Queue Retries; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x1", @@ -2541,8 +3098,10 @@ }, { "BriefDescription": "Request Queue Retries; HA", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x2", @@ -2550,8 +3109,10 @@ }, { "BriefDescription": "Request Queue Retries; Merging these two toge= ther to make room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x20", @@ -2559,8 +3120,10 @@ }, { "BriefDescription": "Request Queue Retries; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x4", @@ -2568,8 +3131,10 @@ }, { "BriefDescription": "Request Queue Retries; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x80", @@ -2577,8 +3142,10 @@ }, { "BriefDescription": "Request Queue Retries; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x8", @@ -2586,8 +3153,10 @@ }, { "BriefDescription": "Request Queue Retries; Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ = (everything except for ISMQ)", "UMask": "0x10", @@ -2595,8 +3164,10 @@ }, { "BriefDescription": "RRQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x1", @@ -2604,8 +3175,10 @@ }, { "BriefDescription": "RRQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2613,8 +3186,10 @@ }, { "BriefDescription": "RRQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x40", @@ -2622,8 +3197,10 @@ }, { "BriefDescription": "RRQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x10", @@ -2631,8 +3208,10 @@ }, { "BriefDescription": "RRQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x20", @@ -2640,8 +3219,10 @@ }, { "BriefDescription": "RRQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x4", @@ -2649,8 +3230,10 @@ }, { "BriefDescription": "RRQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x8", @@ -2658,8 +3241,10 @@ }, { "BriefDescription": "RRQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_CHA_RxC_RRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x80", @@ -2667,8 +3252,10 @@ }, { "BriefDescription": "RRQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x40", @@ -2676,8 +3263,10 @@ }, { "BriefDescription": "RRQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x1", @@ -2685,8 +3274,10 @@ }, { "BriefDescription": "RRQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x2", @@ -2694,8 +3285,10 @@ }, { "BriefDescription": "RRQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x20", @@ -2703,8 +3296,10 @@ }, { "BriefDescription": "RRQ Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x4", @@ -2712,8 +3307,10 @@ }, { "BriefDescription": "RRQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x80", @@ -2721,8 +3318,10 @@ }, { "BriefDescription": "RRQ Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x8", @@ -2730,8 +3329,10 @@ }, { "BriefDescription": "RRQ Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the RRQ (Remote Response Queue) had to retry.", "UMask": "0x10", @@ -2739,8 +3340,10 @@ }, { "BriefDescription": "WBQ Rejects; AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x1", @@ -2748,8 +3351,10 @@ }, { "BriefDescription": "WBQ Rejects; AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2757,8 +3362,10 @@ }, { "BriefDescription": "WBQ Rejects; Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x40", @@ -2766,8 +3373,10 @@ }, { "BriefDescription": "WBQ Rejects; BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2775,8 +3384,10 @@ }, { "BriefDescription": "WBQ Rejects; BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x20", @@ -2784,8 +3395,10 @@ }, { "BriefDescription": "WBQ Rejects; BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x4", @@ -2793,8 +3406,10 @@ }, { "BriefDescription": "WBQ Rejects; BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x8", @@ -2802,8 +3417,10 @@ }, { "BriefDescription": "WBQ Rejects; Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_CHA_RxC_WBQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x80", @@ -2811,8 +3428,10 @@ }, { "BriefDescription": "WBQ Rejects; Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x40", @@ -2820,8 +3439,10 @@ }, { "BriefDescription": "WBQ Rejects; ANY0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x1", @@ -2829,8 +3450,10 @@ }, { "BriefDescription": "WBQ Rejects; HA", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x2", @@ -2838,8 +3461,10 @@ }, { "BriefDescription": "WBQ Rejects; Merging these two together to ma= ke room for ANY_REJECT_*0", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x20", @@ -2847,8 +3472,10 @@ }, { "BriefDescription": "WBQ Rejects; LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x4", @@ -2856,8 +3483,10 @@ }, { "BriefDescription": "WBQ Rejects; PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x80", @@ -2865,8 +3494,10 @@ }, { "BriefDescription": "WBQ Rejects; SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x8", @@ -2874,8 +3505,10 @@ }, { "BriefDescription": "WBQ Rejects; Victim", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a transaction flowing throug= h the WBQ (Writeback Queue) had to retry.", "UMask": "0x10", @@ -2883,8 +3516,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -2892,8 +3527,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -2901,8 +3538,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -2910,8 +3549,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -2919,8 +3560,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -2928,8 +3571,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -2937,8 +3582,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -2946,8 +3593,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -2955,8 +3604,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -2964,8 +3615,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -2973,8 +3626,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -2982,8 +3637,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -2991,8 +3648,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -3000,8 +3659,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -3009,8 +3670,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -3018,8 +3681,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -3027,8 +3692,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -3036,8 +3703,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -3045,8 +3714,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -3054,8 +3725,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -3063,8 +3736,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -3072,8 +3747,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -3081,8 +3758,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -3090,8 +3769,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -3099,8 +3780,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -3108,8 +3791,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -3117,8 +3802,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -3126,8 +3813,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -3135,8 +3824,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -3144,6 +3835,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", @@ -3153,6 +3845,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", @@ -3162,6 +3855,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", @@ -3171,8 +3865,10 @@ }, { "BriefDescription": "Snoops Sent; All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .", "UMask": "0x1", @@ -3180,8 +3876,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast snoop for Local Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA. This filter incl= udes only requests coming from local sockets.", "UMask": "0x10", @@ -3189,8 +3887,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast snoops for Remote Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast snoops issued by the HA.This filter inclu= des only requests coming from remote sockets.", "UMask": "0x20", @@ -3198,8 +3898,10 @@ }, { "BriefDescription": "Snoops Sent; Directed snoops for Local Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from local sockets.", "UMask": "0x40", @@ -3207,8 +3909,10 @@ }, { "BriefDescription": "Snoops Sent; Directed snoops for Remote Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of directed snoops issued by the HA. This filter inclu= des only requests coming from remote sockets.", "UMask": "0x80", @@ -3216,8 +3920,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the local socket.", "UMask": "0x4", @@ -3225,8 +3931,10 @@ }, { "BriefDescription": "Snoops Sent; Broadcast or directed Snoops sen= t for Remote Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of snoops issued by the HA= .; Counts the number of broadcast or directed snoops issued by the HA per r= equest. This filter includes only requests coming from the remote socket.", "UMask": "0x8", @@ -3234,6 +3942,7 @@ }, { "BriefDescription": "RspCnflct* Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPCNFLCTS", "PerPkg": "1", @@ -3243,8 +3952,10 @@ }, { "BriefDescription": "Snoop Responses Received; RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of RspI snoop respon= ses received. Whenever a snoops are issued, one or more snoop responses wi= ll be returned depending on the topology of the system. In systems larger= than 2s, when multiple snoops are returned this will count all the snoops = that are received. For example, if 3 snoops were issued and returned RspI,= RspS, and RspSFwd; then each of these sub-events would increment by 1.; Fi= lters for a snoop response of RspFwd to a CA request. This snoop response = is only possible for RdCur when a snoop HITM/E in a remote caching agent an= d it directly forwards data to a requestor without changing the requestor's= cache line state.", "UMask": "0x80", @@ -3252,6 +3963,7 @@ }, { "BriefDescription": "RspI Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPI", "PerPkg": "1", @@ -3261,6 +3973,7 @@ }, { "BriefDescription": "RspIFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPIFWD", "PerPkg": "1", @@ -3270,8 +3983,10 @@ }, { "BriefDescription": "Snoop Responses Received : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received : RspS : Counts the= total number of RspI snoop responses received. Whenever a snoops are issu= ed, one or more snoop responses will be returned depending on the topology = of the system. In systems larger than 2s, when multiple snoops are return= ed this will count all the snoops that are received. For example, if 3 sno= ops were issued and returned RspI, RspS, and RspSFwd; then each of these su= b-events would increment by 1. : Filters for snoop responses of RspS. RspS= is returned when a remote cache has data but is not forwarding it. It is = a way to let the requesting socket know that it cannot allocate the data in= E state. No data is sent with S RspS.", "UMask": "0x2", @@ -3279,6 +3994,7 @@ }, { "BriefDescription": "RspSFwd Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSPSFWD", "PerPkg": "1", @@ -3288,6 +4004,7 @@ }, { "BriefDescription": "Rsp*Fwd*WB Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_FWD_WB", "PerPkg": "1", @@ -3297,6 +4014,7 @@ }, { "BriefDescription": "Rsp*WB Snoop Responses Received", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_CHA_SNOOP_RESP.RSP_WBWB", "PerPkg": "1", @@ -3306,8 +4024,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspConflict to local CA reques= ts. This is returned when a snoop finds an existing outstanding transactio= n in a remote caching agent when it CAMs that caching agent. This triggers= conflict resolution hardware. This covers both RspCnflct and RspCnflctWbI= .", "UMask": "0x40", @@ -3315,8 +4035,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspFwd to local CA requests. = This snoop response is only possible for RdCur when a snoop HITM/E in a rem= ote caching agent and it directly forwards data to a requestor without chan= ging the requestor's cache line state.", "UMask": "0x80", @@ -3324,8 +4046,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspI", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoops responses of RspI to local CA requests. Rs= pI is returned when the remote cache does not have the data, or when the re= mote cache silently evicts data (such as when an RFO hits non-modified data= ).", "UMask": "0x1", @@ -3333,8 +4057,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspIFwd to local CA requests. = This is returned when a remote caching agent forwards data and the requesti= ng agent is able to acquire the data in E or M states. This is commonly re= turned with RFO transactions. It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -3342,8 +4068,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspS", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for snoop responses of RspS to local CA requests. Rsp= S is returned when a remote cache has data but is not forwarding it. It is= a way to let the requesting socket know that it cannot allocate the data i= n E state. No data is sent with S RspS.", "UMask": "0x2", @@ -3351,8 +4079,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspSFwd to local CA requests. = This is returned when a remote caching agent forwards data but holds on to= its current copy. This is common for data and code reads that hit in a re= mote socket in E or F state.", "UMask": "0x8", @@ -3360,8 +4090,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of Rsp*Fwd*WB to local CA request= s. This snoop response is only used in 4s systems. It is used when a snoo= p HITM's in a remote caching agent and it directly forwards data to a reque= stor, and simultaneously returns data to the home to be written back to mem= ory.", "UMask": "0x20", @@ -3369,8 +4101,10 @@ }, { "BriefDescription": "Snoop Responses Received Local; Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snoop responses received for a Loc= al request; Filters for a snoop response of RspIWB or RspSWB to local CA r= equests. This is returned when a non-RFO request hits in M state. Data an= d Code Reads can return either RspIWB or RspSWB depending on how the system= has been configured. InvItoE transactions will also return RspIWB because= they must acquire ownership.", "UMask": "0x10", @@ -3378,8 +4112,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3387,8 +4123,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3396,8 +4134,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3405,8 +4145,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3414,8 +4156,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3423,8 +4167,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3432,8 +4178,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3441,8 +4189,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3450,8 +4200,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3459,8 +4211,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3468,8 +4222,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3477,8 +4233,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3486,8 +4244,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3495,8 +4255,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3504,8 +4266,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3513,8 +4277,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3522,8 +4288,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3531,8 +4299,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3540,8 +4310,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3549,8 +4321,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3558,8 +4332,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3567,8 +4343,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3576,8 +4354,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3585,8 +4365,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3594,8 +4376,10 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x15", @@ -3603,8 +4387,10 @@ }, { "BriefDescription": "TOR Inserts; All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_IO_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally initiated requests", "UMask": "0x35", @@ -3612,8 +4398,10 @@ }, { "BriefDescription": "TOR Inserts; Misses from Local", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x25", @@ -3621,8 +4409,10 @@ }, { "BriefDescription": "TOR Inserts; SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; T= OR allocation occurred as a result of SF/LLC evictions (came from the ISMQ)= ", "UMask": "0x2", @@ -3630,8 +4420,10 @@ }, { "BriefDescription": "TOR Inserts; Hit (Not a Miss)", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; H= ITs (hit is defined to be not a miss [see below], as a result for any reque= st allocated into the TOR, one of either HIT or MISS must be true)", "UMask": "0x10", @@ -3639,6 +4431,7 @@ }, { "BriefDescription": "TOR Inserts; All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -3648,6 +4441,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -3657,6 +4451,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "Filter": "config1=3D0x40233", @@ -3667,6 +4462,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD", "Filter": "config1=3D0x40433", @@ -3677,6 +4473,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -3686,6 +4483,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -3695,6 +4493,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -3705,6 +4504,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "Filter": "config1=3D0x40033", @@ -3715,6 +4515,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -3724,6 +4525,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "Filter": "config1=3D0x40233", @@ -3734,6 +4536,7 @@ }, { "BriefDescription": "TOR Inserts : DRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD", "Filter": "config1=3D0x40433", @@ -3744,6 +4547,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -3753,6 +4557,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -3762,6 +4567,7 @@ }, { "BriefDescription": "TOR Inserts : LLCPrefRFO issued by iA Cores t= hat missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -3772,6 +4578,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "Filter": "config1=3D0x40033", @@ -3782,8 +4589,10 @@ }, { "BriefDescription": "TOR Inserts; All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; A= ll locally generated IO traffic", "UMask": "0x34", @@ -3791,6 +4600,7 @@ }, { "BriefDescription": "TOR Inserts; Hits from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -3800,6 +4610,7 @@ }, { "BriefDescription": "TOR Inserts; Misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -3809,8 +4620,10 @@ }, { "BriefDescription": "TOR Inserts; ItoM misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", + "Experimental": "1", "Filter": "config1=3D0x49033", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO ItoM requests that mis= s the LLC. An ItoM request is used by IIO to request a data write without f= irst reading the data for ownership.", @@ -3819,8 +4632,10 @@ }, { "BriefDescription": "TOR Inserts; RdCur misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RDCUR", + "Experimental": "1", "Filter": "config1=3D0x43C33", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RdCur requests and mis= s the LLC. A RdCur request is used by IIO to read data without changing sta= te.", @@ -3829,8 +4644,10 @@ }, { "BriefDescription": "TOR Inserts; RFO misses from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Experimental": "1", "Filter": "config1=3D0x40033", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that are generated from local IO RFO requests that miss= the LLC. A read for ownership (RFO) requests a cache line to be cached in = E state with the intent to modify.", @@ -3839,8 +4656,10 @@ }, { "BriefDescription": "TOR Inserts; IPQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x8", @@ -3848,26 +4667,32 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; IRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x1", @@ -3875,17 +4700,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts; Miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.; M= isses. (a miss is defined to be any transaction from the IRQ, PRQ, RRQ, IP= Q or (in the victim case) the ISMQ, that required the CHA to spawn a new UP= I/SMI3 request on the UPI fabric (including UPI snoops and/or any RD/WR to = a local memory controller, in the event that the CHA is the home node)). B= asically, if the LLC/SF/MLC complex were not able to service the request wi= thout involving another agent...it is a miss. If only IDI snoops were requ= ired, it is not a miss (that means the SF/MLC com", "UMask": "0x20", @@ -3893,8 +4722,10 @@ }, { "BriefDescription": "TOR Inserts; PRQ", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of entries successfully in= serted into the TOR that match qualifications specified by the subevent.", "UMask": "0x4", @@ -3902,6 +4733,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.REM_ALL", @@ -3911,44 +4743,54 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.RRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x60", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.WBQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; All from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. There are a number of subevent 'filters' but only a subset of= the subevent combinations are valid. Subevents that require an opcode or = NID match require the Cn_MSR_PMON_BOX_FILTER.{opc, nid} field to be set. I= f, for example, one wanted to count DRD Local Misses, one should select MIS= S_OPC_MATCH and set Cn_MSR_PMON_BOX_FILTER.opc to DRD (0x182); All remotely= generated requests", "UMask": "0x37", @@ -3956,8 +4798,10 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x17", @@ -3965,8 +4809,10 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x27", @@ -3974,8 +4820,10 @@ }, { "BriefDescription": "TOR Occupancy; SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; TOR allocation occurred as a result of SF/LLC evictions (c= ame from the ISMQ)", "UMask": "0x2", @@ -3983,8 +4831,10 @@ }, { "BriefDescription": "TOR Occupancy; Hit (Not a Miss)", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; HITs (hit is defined to be not a miss [see below], as a re= sult for any request allocated into the TOR, one of either HIT or MISS must= be true)", "UMask": "0x10", @@ -3992,6 +4842,7 @@ }, { "BriefDescription": "TOR Occupancy; All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4001,6 +4852,7 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4010,6 +4862,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", "Filter": "config1=3D0x40233", @@ -4020,6 +4873,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD", "Filter": "config1=3D0x40433", @@ -4030,6 +4884,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -4039,6 +4894,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -4048,6 +4904,7 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -4058,6 +4915,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", "Filter": "config1=3D0x40033", @@ -4068,6 +4926,7 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -4077,6 +4936,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "Filter": "config1=3D0x40233", @@ -4087,6 +4947,7 @@ }, { "BriefDescription": "TOR Occupancy : DRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD", "Filter": "config1=3D0x40433", @@ -4097,6 +4958,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefCRD", "Filter": "config1=3D0x4b233", @@ -4106,6 +4968,7 @@ }, { "BriefDescription": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefDRD", "Filter": "config1=3D0x4b433", @@ -4115,6 +4978,7 @@ }, { "BriefDescription": "TOR Occupancy : LLCPrefRFO issued by iA Cores= that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_LlcPrefRFO", "Filter": "config1=3D0x4b033", @@ -4125,6 +4989,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "Filter": "config1=3D0x40033", @@ -4135,8 +5000,10 @@ }, { "BriefDescription": "TOR Occupancy; All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; All locally generated IO traffic", "UMask": "0x34", @@ -4144,8 +5011,10 @@ }, { "BriefDescription": "TOR Occupancy; Hits from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x14", @@ -4153,8 +5022,10 @@ }, { "BriefDescription": "TOR Occupancy; Misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x24", @@ -4162,8 +5033,10 @@ }, { "BriefDescription": "TOR Occupancy; ITOM Misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Experimental": "1", "Filter": "config1=3D0x49033", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO ItoM req= uests that miss the LLC. An ItoM is used by IIO to request a data write wit= hout first reading the data for ownership.", @@ -4172,8 +5045,10 @@ }, { "BriefDescription": "TOR Occupancy; RDCUR misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RDCUR", + "Experimental": "1", "Filter": "config1=3D0x43C33", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RdCur re= quests that miss the LLC. A RdCur request is used by IIO to read data witho= ut changing state.", @@ -4182,8 +5057,10 @@ }, { "BriefDescription": "TOR Occupancy; RFO misses from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "Filter": "config1=3D0x40033", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that are generated from local IO RFO requ= ests that miss the LLC. A read for ownership (RFO) requests data to be cach= ed in E state with the intent to modify.", @@ -4192,8 +5069,10 @@ }, { "BriefDescription": "TOR Occupancy; IPQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x8", @@ -4201,26 +5080,32 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; IRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x1", @@ -4228,17 +5113,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.ALL_FROM_LOC", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy; Miss", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T; Misses. (a miss is defined to be any transaction from the= IRQ, PRQ, RRQ, IPQ or (in the victim case) the ISMQ, that required the CHA= to spawn a new UPI/SMI3 request on the UPI fabric (including UPI snoops an= d/or any RD/WR to a local memory controller, in the event that the CHA is t= he home node)). Basically, if the LLC/SF/MLC complex were not able to serv= ice the request without involving another agent...it is a miss. If only ID= I snoops were required, it is not a miss (that means the SF/MLC com", "UMask": "0x20", @@ -4246,8 +5135,10 @@ }, { "BriefDescription": "TOR Occupancy; PRQ", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. T", "UMask": "0x4", @@ -4255,8 +5146,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4264,8 +5157,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4273,8 +5168,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4282,8 +5179,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4291,8 +5190,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4300,8 +5201,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4309,8 +5212,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4318,8 +5223,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4327,8 +5234,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4336,8 +5245,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4345,8 +5256,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -4354,8 +5267,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4363,8 +5278,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4372,8 +5289,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4381,8 +5300,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4390,8 +5311,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4399,8 +5322,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4408,8 +5333,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4417,8 +5344,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4426,8 +5355,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4435,8 +5366,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4444,8 +5377,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4453,8 +5388,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4462,8 +5399,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4471,8 +5410,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4480,8 +5421,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4489,8 +5432,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4498,8 +5443,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4507,8 +5454,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4516,8 +5465,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -4525,8 +5476,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -4534,8 +5487,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -4543,8 +5498,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -4552,8 +5509,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -4561,8 +5520,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -4570,8 +5531,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4579,8 +5542,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -4588,8 +5553,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4597,8 +5564,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4606,8 +5575,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -4615,8 +5586,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4624,8 +5597,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -4633,8 +5608,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -4642,8 +5619,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -4651,8 +5630,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -4660,8 +5641,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4669,8 +5652,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4678,8 +5663,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4687,8 +5674,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -4696,8 +5685,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4705,8 +5696,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4714,8 +5707,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -4723,8 +5718,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -4732,8 +5729,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -4741,8 +5740,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -4750,8 +5751,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -4759,8 +5762,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -4768,8 +5773,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -4777,8 +5784,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -4786,8 +5795,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4795,8 +5806,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4804,8 +5817,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -4813,8 +5828,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -4822,8 +5839,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -4831,8 +5850,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -4840,8 +5861,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -4849,8 +5872,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4858,8 +5883,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4867,8 +5894,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -4876,8 +5905,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -4885,8 +5916,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -4894,8 +5927,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -4903,8 +5938,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -4912,8 +5949,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -4921,8 +5960,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4930,8 +5971,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -4939,8 +5982,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -4948,8 +5993,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -4957,8 +6004,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -4966,8 +6015,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -4975,8 +6026,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -4984,8 +6037,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -4993,8 +6048,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -5002,8 +6059,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -5011,8 +6070,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -5020,8 +6081,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -5029,8 +6092,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -5038,8 +6103,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -5047,8 +6114,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5056,8 +6125,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -5065,8 +6136,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -5074,8 +6147,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -5083,8 +6158,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5092,8 +6169,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -5101,8 +6180,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -5110,8 +6191,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -5119,8 +6202,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -5128,8 +6213,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -5137,8 +6224,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -5146,8 +6235,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -5155,8 +6246,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; AD REQ Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x4", @@ -5164,8 +6257,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; AD RSP VN0 Cr= edits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x8", @@ -5173,8 +6268,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL NCB Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x40", @@ -5182,8 +6279,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL NCS Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x80", @@ -5191,8 +6290,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL RSP Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x10", @@ -5200,8 +6301,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; BL DRS Credit= s", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x20", @@ -5209,8 +6312,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; VN0 Credits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x2", @@ -5218,8 +6323,10 @@ }, { "BriefDescription": "UPI Ingress Credit Allocations; VNA Credits", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_CHA_UPI_CREDITS_ACQUIRED.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of UPI credits acquired fo= r either the AD or BL ring. In order to send snoops, snoop responses, requ= ests, data, etc to the UPI agent on the ring, it is necessary to first acqu= ire a credit for the UPI ingress buffer. This can be used with the Credit = Occupancy event in order to calculate average credit lifetime. This event = supports filtering to cover the VNA/VN0 credits and the different message c= lasses. Note that you must select the link that you would like to monitor = using the link select register, and you can only monitor 1 link at a time.", "UMask": "0x1", @@ -5227,8 +6334,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD REQ VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x4", @@ -5236,8 +6345,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD RSP VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x8", @@ -5245,8 +6356,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCB VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x40", @@ -5254,6 +6367,7 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL NCS VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_NCS", "PerPkg": "1", @@ -5263,8 +6377,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL RSP VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x10", @@ -5272,8 +6388,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL DRS VN0= Credits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VN0_BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x20", @@ -5281,8 +6399,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; AD VNA Cre= dits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x1", @@ -5290,8 +6410,10 @@ }, { "BriefDescription": "UPI Ingress Credits In Use Cycles; BL VNA Cre= dits", + "Counter": "0", "EventCode": "0x3B", "EventName": "UNC_CHA_UPI_CREDIT_OCCUPANCY.VNA_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of UPI credits availa= ble in each cycle for either the AD or BL ring. In order to send snoops, s= noop responses, requests, data, etc to the UPI agent on the ring, it is nec= essary to first acquire a credit for the UPI ingress buffer. This stat inc= rements by the number of credits that are available each cycle. This can b= e used in conjunction with the Credit Acquired event in order to calculate = average credit lifetime. This event supports filtering for the different t= ypes of credits that are available. Note that you must select the link tha= t you would like to monitor using the link select register, and you can onl= y monitor 1 link at a time.", "UMask": "0x2", @@ -5299,8 +6421,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -5308,8 +6432,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -5317,8 +6443,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -5326,8 +6454,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -5335,8 +6465,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -5344,8 +6476,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -5353,8 +6487,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -5362,8 +6498,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -5371,8 +6509,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -5380,8 +6520,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -5389,8 +6531,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -5398,8 +6542,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -5407,8 +6553,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -5416,8 +6564,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -5425,8 +6575,10 @@ }, { "BriefDescription": "WbPushMtoI; Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was able to pu= sh WbPushMToI to LLC", "UMask": "0x1", @@ -5434,8 +6586,10 @@ }, { "BriefDescription": "WbPushMtoI; Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when the CHA was = received WbPushMtoI; Counts the number of times when the CHA was unable to = push WbPushMToI to LLC (hence pushed it to MEM)", "UMask": "0x2", @@ -5443,8 +6597,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC0_SMI2", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 2 only.", "UMask": "0x4", @@ -5452,8 +6608,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC1_SMI3", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 3 only.", "UMask": "0x8", @@ -5461,8 +6619,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC2_SMI4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 4 only.", "UMask": "0x10", @@ -5470,8 +6630,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; EDC3_SMI5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 5 only.", "UMask": "0x20", @@ -5479,8 +6641,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC0_SMI0", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 0 only.", "UMask": "0x1", @@ -5488,8 +6652,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty; MC1_SMI1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times when there are no= credits available for sending WRITEs from the CHA into the iMC. In order = to send WRITEs into the memory controller, the HA must first acquire a cred= it for the iMC's BL Ingress queue.; Filter for memory controller 1 only.", "UMask": "0x2", @@ -5497,8 +6663,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd F/E", "UMask": "0xe4", @@ -5506,8 +6674,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response I to Fwd M", "UMask": "0xf0", @@ -5515,8 +6685,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd F/E", "UMask": "0xe2", @@ -5524,8 +6696,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response S to Fwd M", "UMask": "0xe8", @@ -5533,8 +6707,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Any RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Any Request - Response any to Hit F/S/E= ", "UMask": "0xe1", @@ -5542,8 +6718,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd F/E", "UMask": "0x44", @@ -5551,8 +6729,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspIFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response I to Fwd M", "UMask": "0x50", @@ -5560,8 +6740,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd F/E", "UMask": "0x42", @@ -5569,8 +6751,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response S to Fwd M", "UMask": "0x48", @@ -5578,8 +6762,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Core RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Core Request - Response any to Hit F/S/= E", "UMask": "0x41", @@ -5587,8 +6773,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd F/= E", "UMask": "0x84", @@ -5596,8 +6784,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspIFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response I to Fwd M", "UMask": "0x90", @@ -5605,8 +6795,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdFE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd F/= E", "UMask": "0x82", @@ -5614,8 +6806,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspSFwdM", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response S to Fwd M", "UMask": "0x88", @@ -5623,8 +6817,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; Evict RspHitFSE", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; Eviction Request - Response any to Hit = F/S/E", "UMask": "0x81", @@ -5632,8 +6828,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspIFwdF= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd F/= E", "UMask": "0x24", @@ -5641,8 +6839,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response I to Fwd M", "UMask": "0x30", @@ -5650,8 +6850,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspSFwdF= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd F/= E", "UMask": "0x22", @@ -5659,8 +6861,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspSFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response S to Fwd M", "UMask": "0x28", @@ -5668,8 +6872,10 @@ }, { "BriefDescription": "Core Cross Snoop Responses; External RspHitFS= E", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of core cross snoops. Cor= es are snooped if the transaction looks up the cache and determines that it= is necessary based on the operation type. This event can be filtered based= on who triggered the initial snoop(s): from Evictions, Core or External = (i.e. from a remote node) Requests. And the event can be filtered based on= the responses: RspX_Fwd/HitY where Y is the state prior to the snoop resp= onse and X is the state following.; External Request - Response any to Hit = F/S/E", "UMask": "0x21", @@ -5677,6 +6883,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CLOCKTICKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventName": "UNC_C_CLOCKTICKS", "PerPkg": "1", @@ -5684,6 +6891,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_FAST_ASSERTED.HORZ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA5", "EventName": "UNC_C_FAST_ASSERTED", @@ -5693,15 +6901,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.ANY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.DATA_READ", @@ -5711,24 +6922,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x91", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.REMOTE_SNOOP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.REMOTE_SNOOP", @@ -5738,15 +6954,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.WRITE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_C_LLC_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_E", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.E_STATE", @@ -5756,6 +6975,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_F", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.F_STATE", @@ -5765,15 +6985,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2f", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_M", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.M_STATE", @@ -5783,15 +7006,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.REMOTE_ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_VICTIMS.TOTAL_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x37", "EventName": "UNC_C_LLC_VICTIMS.S_STATE", @@ -5801,59 +7027,72 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SRC_THRTL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA4", "EventName": "UNC_C_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.EVICT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IPQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ", @@ -5863,6 +7102,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_HIT", @@ -5872,6 +7112,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.IRQ_MISS", @@ -5881,51 +7122,62 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x34", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.PRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_HIT", @@ -5935,6 +7187,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.IO_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.PRQ_MISS", @@ -5944,6 +7197,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.REM_ALL", @@ -5953,87 +7207,106 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.RRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.RRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x60", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WBQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_C_TOR_INSERTS.WBQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.EVICT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IPQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x18", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IPQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ", @@ -6043,6 +7316,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_HIT", @@ -6052,6 +7326,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA_MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.IRQ_MISS", @@ -6061,608 +7336,743 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x37", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IA", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x31", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x34", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.PRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_HIT", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_OCCUPANCY.IO_MISS", + "Counter": "0", "Deprecated": "1", "EventCode": "0x36", "EventName": "UNC_C_TOR_OCCUPANCY.PRQ_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x80", "EventName": "UNC_H_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_AD_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x82", "EventName": "UNC_H_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x88", "EventName": "UNC_H_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG0_BL_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8A", "EventName": "UNC_H_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_H_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_AD_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x86", "EventName": "UNC_H_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CRD_OCCUPANCY.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8E", "EventName": "UNC_H_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x8C", "EventName": "UNC_H_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x57", "EventName": "UNC_H_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CMS_CLOCKTICKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_H_CLOCK", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C1_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C1_TRANSITION", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C1_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C6_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.C6_TRANSITION", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.C6_TRANSITION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_PMA.GV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x17", "EventName": "UNC_H_CORE_PMA.GV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.ANY_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.ANY_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_GTONE", @@ -6672,24 +8082,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x41", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.CORE_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.CORE_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_GTONE", @@ -6699,59 +8114,72 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EVICT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EVICT_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_GTONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_ONE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_CORE_SNP.EXT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x33", "EventName": "UNC_H_CORE_SNP.EXT_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_COUNTER0_OCCUPANCY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x1F", "EventName": "UNC_H_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.NO_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x53", "EventName": "UNC_H_DIR_LOOKUP.NO_SNP", @@ -6761,6 +8189,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_LOOKUP.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x53", "EventName": "UNC_H_DIR_LOOKUP.SNP", @@ -6770,6 +8199,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x54", "EventName": "UNC_H_DIR_UPDATE.HA", @@ -6779,6 +8209,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_DIR_UPDATE.TOR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x54", "EventName": "UNC_H_DIR_UPDATE.TOR", @@ -6788,24 +8219,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAE", "EventName": "UNC_H_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.EX_RDS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.EX_RDS", @@ -6815,411 +8251,502 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.SHARED_OWNREQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.SHARED_OWNREQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_HIT.WBMTOI_OR_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5F", "EventName": "UNC_H_HITME_HIT.WBMTOI_OR_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5E", "EventName": "UNC_H_HITME_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_LOOKUP.WRITE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5E", "EventName": "UNC_H_HITME_LOOKUP.WRITE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.NOTSHARED_RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.NOTSHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.READ_OR_INV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.READ_OR_INV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_MISS.SHARED_RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x60", "EventName": "UNC_H_HITME_MISS.SHARED_RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RDINVOWN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.RDINVOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.RSPFWDI_REM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.RSPFWDI_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HITME_UPDATE.SHARED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x61", "EventName": "UNC_H_HITME_UPDATE.SHARED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA7", "EventName": "UNC_H_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA9", "EventName": "UNC_H_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAB", "EventName": "UNC_H_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAD", "EventName": "UNC_H_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.NORMAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x59", "EventName": "UNC_H_IMC_READS_COUNT.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x59", "EventName": "UNC_H_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_MIG", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_MIG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_MIG", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_MIG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5B", "EventName": "UNC_H_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.INVITOM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.INVITOM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.IODCFULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.IODCFULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_ALLOC.OSBGATED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x62", "EventName": "UNC_H_IODC_ALLOC.OSBGATED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.SNPOUT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.SNPOUT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBMTOE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBMTOI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_IODC_DEALLOC.WBPUSHMTOI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "UNC_H_IODC_DEALLOC.WBPUSHMTOI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.CV0_PREF_VIC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RFO_HIT_S", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.RFO_HIT_S", @@ -7229,86 +8756,105 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.RSPI_WAS_FSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_MISC.WC_ALIASING", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x39", "EventName": "UNC_H_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_OSB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x55", "EventName": "UNC_H_OSB", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC0_SMI2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC1_SMI3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC2_SMI4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.EDC3_SMI5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC0_SMI0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_READ_NO_CREDITS.MC1_SMI1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x58", "EventName": "UNC_H_READ_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.INVITOE_LOCAL", @@ -7318,6 +8864,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_REQUESTS.INVITOE_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.INVITOE_REMOTE", @@ -7327,6 +8874,7 @@ }, { "BriefDescription": "read requests from home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS", @@ -7336,6 +8884,7 @@ }, { "BriefDescription": "read requests from local home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS_LOCAL", @@ -7345,15 +8894,18 @@ }, { "BriefDescription": "read requests from remote home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.READS_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "write requests from home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES", @@ -7363,6 +8915,7 @@ }, { "BriefDescription": "write requests from local home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES_LOCAL", @@ -7372,177 +8925,216 @@ }, { "BriefDescription": "write requests from remote home agent", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x50", "EventName": "UNC_H_REQUESTS.WRITES_REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_HORZ.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA1", "EventName": "UNC_H_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_BOUNCES_VERT.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA0", "EventName": "UNC_H_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA3", "EventName": "UNC_H_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA2", "EventName": "UNC_H_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IPQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IRQ", @@ -7552,276 +9144,337 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.RRQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.RRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_INSERTS.WBQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x13", "EventName": "UNC_H_RxC_INSERTS.WBQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x22", "EventName": "UNC_H_RxC_IPQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.ANY_IPQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IPQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x23", "EventName": "UNC_H_RxC_IPQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x18", "EventName": "UNC_H_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.ANY_REJECT_IRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.PA_MATCH", @@ -7831,177 +9484,216 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x19", "EventName": "UNC_H_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x24", "EventName": "UNC_H_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2C", "EventName": "UNC_H_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x25", "EventName": "UNC_H_RxC_ISMQ1_REJECT.ANY_ISMQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x25", "EventName": "UNC_H_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2D", "EventName": "UNC_H_RxC_ISMQ1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2D", "EventName": "UNC_H_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IPQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.IPQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.IRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.IRQ", @@ -8011,1005 +9703,1228 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.RRQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.RRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OCCUPANCY.WBQ", + "Counter": "0", "Deprecated": "1", "EventCode": "0x11", "EventName": "UNC_H_RxC_OCCUPANCY.WBQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2E", "EventName": "UNC_H_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2F", "EventName": "UNC_H_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x20", "EventName": "UNC_H_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.ANY_PRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x21", "EventName": "UNC_H_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2A", "EventName": "UNC_H_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.ANY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2B", "EventName": "UNC_H_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x26", "EventName": "UNC_H_RxC_RRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.ANY_RRQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_RRQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x27", "EventName": "UNC_H_RxC_RRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ0_REJECT.BL_WB_VN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x28", "EventName": "UNC_H_RxC_WBQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ALLOW_SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.ANY0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.ANY_WBQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.HA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.LLC_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.PA_MATCH", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.SF_VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxC_WBQ1_REJECT.VICTIM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x29", "EventName": "UNC_H_RxC_WBQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB4", "EventName": "UNC_H_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_BYPASS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB2", "EventName": "UNC_H_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IFV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_CRD_STARVED.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB3", "EventName": "UNC_H_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_INSERTS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB1", "EventName": "UNC_H_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_RxR_OCCUPANCY.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xB0", "EventName": "UNC_H_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.E_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.E_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.M_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.M_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SF_EVICTION.S_STATE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3D", "EventName": "UNC_H_SF_EVICTION.S_STATE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.ALL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.BCST_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.BCST_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.BCST_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.DIRECT_LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.DIRECT_REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.DIRECT_REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOPS_SENT.REMOTE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x51", "EventName": "UNC_H_SNOOPS_SENT.REMOTE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPCNFLCTS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPCNFLCT", @@ -9019,24 +10934,29 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPIFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPIFWD", @@ -9046,15 +10966,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSPSFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSPSFWD", @@ -9064,6 +10987,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_FWD_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSP_FWD_WB", @@ -9073,1575 +10997,1925 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP.RSP_WBWB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5C", "EventName": "UNC_H_SNOOP_RESP.RSP_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_FWD_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_FWD_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_SNOOP_RESP_LOCAL.RSP_WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5D", "EventName": "UNC_H_SNP_RSP_RCV_LOCAL.RSP_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD0", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD2", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD4", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xD6", "EventName": "UNC_H_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9D", "EventName": "UNC_H_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_BYPASS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9F", "EventName": "UNC_H_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x96", "EventName": "UNC_H_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_CYCLES_NE.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x97", "EventName": "UNC_H_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_INSERTS.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x95", "EventName": "UNC_H_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_NACK.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x99", "EventName": "UNC_H_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_OCCUPANCY.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x94", "EventName": "UNC_H_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AD_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.AK_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.BL_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_HORZ_STARVED.IV_BNC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9B", "EventName": "UNC_H_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9C", "EventName": "UNC_H_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_BYPASS.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9E", "EventName": "UNC_H_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_FULL.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x92", "EventName": "UNC_H_TxR_VERT_CYCLES_FULL.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_CYCLES_NE.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x93", "EventName": "UNC_H_TxR_VERT_CYCLES_NE.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_INSERTS.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x91", "EventName": "UNC_H_TxR_VERT_INSERTS.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_NACK.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x98", "EventName": "UNC_H_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_OCCUPANCY.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x90", "EventName": "UNC_H_TxR_VERT_OCCUPANCY.IV_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AD_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.AK_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.BL_AG1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TxR_VERT_STARVED.IV", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x9A", "EventName": "UNC_H_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA6", "EventName": "UNC_H_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xA8", "EventName": "UNC_H_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAA", "EventName": "UNC_H_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xAC", "EventName": "UNC_H_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.LLC", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x56", "EventName": "UNC_H_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WB_PUSH_MTOI.MEM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x56", "EventName": "UNC_H_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC0_SMI2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC0_SMI2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC1_SMI3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC1_SMI3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC2_SMI4", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC2_SMI4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.EDC3_SMI5", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.EDC3_SMI5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC0_SMI0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.MC0_SMI0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_WRITE_NO_CREDITS.MC1_SMI1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5A", "EventName": "UNC_H_WRITE_NO_CREDITS.MC1_SMI1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe4", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf0", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe2", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe8", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.ANY_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.ANY_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe1", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x44", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x50", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x42", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x48", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.CORE_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.CORE_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x41", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x84", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x82", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EVICT_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EVICT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x81", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPI_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPI_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x30", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDFE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDFE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSPS_FWDM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSPS_FWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x28", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_XSNP_RESP.EXT_RSP_HITFSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x32", "EventName": "UNC_H_XSNP_RESP.EXT_RSP_HITFSE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "CHA" diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.js= on b/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json index f32d4d9d283a..216a00237cd1 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total Write Cache Occupancy; Any Source", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.; Tracks all requests f= rom any source port.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "Total Write Cache Occupancy; Snoops", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of reads and writes t= hat are outstanding in the uncore in each cycle. This is effectively the s= um of the READ_OCCUPANCY and WRITE_OCCUPANCY events.", "UMask": "0x2", @@ -19,6 +23,7 @@ }, { "BriefDescription": "Total IRP occupancy of inbound read and write= requests.", + "Counter": "0,1", "EventCode": "0xF", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", @@ -28,15 +33,19 @@ }, { "BriefDescription": "IRP Clocks", + "Counter": "0,1", "EventCode": "0x1", "EventName": "UNC_I_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Coherent Ops; CLFlush", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x80", @@ -44,8 +53,10 @@ }, { "BriefDescription": "Coherent Ops; CRd", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x2", @@ -53,8 +64,10 @@ }, { "BriefDescription": "Coherent Ops; DRd", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.DRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x4", @@ -62,8 +75,10 @@ }, { "BriefDescription": "Coherent Ops; PCIDCAHin5t", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCIDCAHINT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x20", @@ -71,8 +86,10 @@ }, { "BriefDescription": "Coherent Ops; PCIRdCur", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCIRDCUR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x1", @@ -80,6 +97,7 @@ }, { "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -89,6 +107,7 @@ }, { "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.RFO", "PerPkg": "1", @@ -98,8 +117,10 @@ }, { "BriefDescription": "Coherent Ops; WbMtoI", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of coherency related opera= tions serviced by the IRP", "UMask": "0x40", @@ -107,13 +128,16 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -122,6 +146,7 @@ }, { "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -130,95 +155,119 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Atomic = Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Read Tr= ansactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Cache Inserts of Write T= ransactions as Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Fastpath Transfers From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0; Prefetch Ack Hints From = Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 0", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_MISC0.UNKNOWN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1; Lost Forward", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.LOST_FWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop pulled away ownership before a write w= as committed", "UMask": "0x10", @@ -226,8 +275,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Invalid", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", "UMask": "0x20", @@ -235,8 +286,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Received Valid", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", "UMask": "0x40", @@ -244,8 +297,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of E Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did have = sufficient MESI state", "UMask": "0x4", @@ -253,8 +308,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of I Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", "UMask": "0x1", @@ -262,8 +319,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of M Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop took cacheline ownership before write = from data was committed.", "UMask": "0x8", @@ -271,8 +330,10 @@ }, { "BriefDescription": "Misc Events - Set 1; Slow Transfer of S Line", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Secondary received a transfer that did not h= ave sufficient MESI state", "UMask": "0x2", @@ -280,88 +341,110 @@ }, { "BriefDescription": "P2P Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_P2P_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P requests from the ITC", "Unit": "IRP" }, { "BriefDescription": "P2P Occupancy", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_P2P_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P B & S Queue Occupancy", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P completions", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if local only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if local and target m= atches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P Message", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P reads", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; Match if remote only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; match if remote and target = matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions; P2P Writes", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -369,8 +452,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -378,8 +463,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -387,8 +474,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M line in the IIO cache", "UMask": "0x78", @@ -396,8 +485,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -405,64 +496,80 @@ }, { "BriefDescription": "Snoop Responses; Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses; SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound Transaction Count; Atomic", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of atomic = transactions", "UMask": "0x10", @@ -470,8 +577,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Other", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of 'other'= kinds of transactions.", "UMask": "0x20", @@ -479,8 +588,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Read Prefetches", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.RD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks the number of read pr= efetches.", "UMask": "0x4", @@ -488,8 +599,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Reads", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.READS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only read requests (n= ot including read prefetches).", "UMask": "0x1", @@ -497,8 +610,10 @@ }, { "BriefDescription": "Inbound Transaction Count; Writes", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WRITES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of Inbound transactions fr= om the IRP to the Uncore. This can be filtered based on request type in ad= dition to the source queue. Note the special filtering equation. We do OR= -reduction on the request type. If the SOURCE bit is set, then we also do = AND qualification based on the source portID.; Tracks only write requests. = Each write request should have a prefetch, so there is no need to explicit= ly track these requests. For writes that are tickled and have to retry, th= e counter will be incremented for each retry.", "UMask": "0x2", @@ -506,6 +621,7 @@ }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -515,118 +631,150 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0xB", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x5", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x2", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x8", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x6", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x3", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x9", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x7", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x4", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0xA", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "No AD Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_TxR2_AD_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number times when it is not possi= ble to issue a request to the R2PCIe because there are no AD Egress Credits= available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1B", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number times when it is not possi= ble to issue data to the R2PCIe because there are no BL Egress Credits avai= lable.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xD", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0xE", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of requests issued to the = switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0xC", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of outstanding outbou= nd requests from the IRP to the switch (towards the devices). This can be = used in conjunction with the allocations event in order to calculate averag= e latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -634,8 +782,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -643,8 +793,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -652,8 +804,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -661,8 +815,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -670,8 +826,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -679,8 +837,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -688,8 +848,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -697,8 +859,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -706,8 +870,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -715,8 +881,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -724,8 +892,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -733,8 +903,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -742,8 +914,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -751,8 +925,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -760,8 +936,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -769,8 +947,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -778,8 +958,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -787,8 +969,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -796,8 +980,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -805,8 +991,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -814,8 +1002,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -823,8 +1013,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -832,8 +1024,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -841,8 +1035,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -850,8 +1046,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -859,8 +1057,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -868,8 +1068,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -877,8 +1079,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -886,8 +1090,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -895,8 +1101,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -904,8 +1112,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -913,8 +1123,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -922,8 +1134,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -931,8 +1145,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -940,8 +1156,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -949,8 +1167,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -958,8 +1178,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -967,8 +1189,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -976,8 +1200,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -985,8 +1211,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -994,8 +1222,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -1003,8 +1233,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -1012,8 +1244,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -1021,8 +1255,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -1030,8 +1266,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -1039,8 +1277,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -1048,8 +1288,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -1057,6 +1299,7 @@ }, { "BriefDescription": "Traffic in which the M2M to iMC Bypass was no= t taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_Egress.NOT_TAKEN", "PerPkg": "1", @@ -1066,43 +1309,54 @@ }, { "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_Egress.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass; Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass; Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles - at UCLK", + "Counter": "0,1,2,3", "EventName": "UNC_M2M_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles when direct to core mode (which bypass= es the CHA) was disabled", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", "PerPkg": "1", @@ -1111,6 +1365,7 @@ }, { "BriefDescription": "Messages sent direct to core (bypassing the C= HA)", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M2M_DIRECT2CORE_TAKEN", "PerPkg": "1", @@ -1119,6 +1374,7 @@ }, { "BriefDescription": "Number of reads in which direct to core trans= action were overridden", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", "PerPkg": "1", @@ -1127,6 +1383,7 @@ }, { "BriefDescription": "Number of reads in which direct to Intel(R) U= PI transactions were overridden", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_CREDITS", "PerPkg": "1", @@ -1135,6 +1392,7 @@ }, { "BriefDescription": "Cycles when direct to Intel(R) UPI was disabl= ed", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_M2M_DIRECT2UPI_NOT_TAKEN_DIRSTATE", "PerPkg": "1", @@ -1143,6 +1401,7 @@ }, { "BriefDescription": "Messages sent direct to the Intel(R) UPI", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_M2M_DIRECT2UPI_TAKEN", "PerPkg": "1", @@ -1151,6 +1410,7 @@ }, { "BriefDescription": "Number of reads that a message sent direct2 I= ntel(R) UPI was overridden", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_M2M_DIRECT2UPI_TXN_OVERRIDE", "PerPkg": "1", @@ -1159,70 +1419,87 @@ }, { "BriefDescription": "Directory Hit; On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Hit; On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_M2M_DIRECTORY_HIT.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory lookups (any= state found)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.ANY", "PerPkg": "1", @@ -1232,6 +1509,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookups (cac= heline found in A state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_A", "PerPkg": "1", @@ -1241,6 +1519,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in I state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_I", "PerPkg": "1", @@ -1250,6 +1529,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory lookup (cach= eline found in S state)", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_M2M_DIRECTORY_LOOKUP.STATE_S", "PerPkg": "1", @@ -1259,70 +1539,87 @@ }, { "BriefDescription": "Directory Miss; On NonDirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On NonDirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.CLEAN_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in A State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_A", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in I State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in L State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_P", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Directory Miss; On Dirty Line in S State", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_M2M_DIRECTORY_MISS.DIRTY_S", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to I", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2I", "PerPkg": "1", @@ -1332,6 +1629,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = A to S", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.A2S", "PerPkg": "1", @@ -1341,6 +1639,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from/= to Any state", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.ANY", "PerPkg": "1", @@ -1350,6 +1649,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to A", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2A", "PerPkg": "1", @@ -1359,6 +1659,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = I to S", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.I2S", "PerPkg": "1", @@ -1368,6 +1669,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to A", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2A", "PerPkg": "1", @@ -1377,6 +1679,7 @@ }, { "BriefDescription": "Multi-socket cacheline Directory update from = S to I", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_M2M_DIRECTORY_UPDATE.S2I", "PerPkg": "1", @@ -1386,8 +1689,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -1395,8 +1700,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -1404,8 +1711,10 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_FAST_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x2", @@ -1413,8 +1722,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -1422,8 +1733,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -1431,8 +1744,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -1440,8 +1755,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -1449,8 +1766,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -1458,8 +1777,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -1467,8 +1788,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -1476,8 +1799,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -1485,8 +1810,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA9", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -1494,8 +1821,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -1503,8 +1832,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -1512,8 +1843,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -1521,8 +1854,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -1530,8 +1865,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -1539,8 +1876,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -1548,6 +1887,7 @@ }, { "BriefDescription": "Reads to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ALL", "PerPkg": "1", @@ -1557,22 +1897,27 @@ }, { "BriefDescription": "M2M Reads Issued to iMC; All, regardless of p= riority.", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.FROM_TRANSGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC; Critical Priority", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Reads to iMC issued at Normal Priority (Non-I= sochronous)", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.NORMAL", "PerPkg": "1", @@ -1582,6 +1927,7 @@ }, { "BriefDescription": "Writes to iMC issued", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.ALL", "PerPkg": "1", @@ -1591,30 +1937,37 @@ }, { "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FROM_TRANSGRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; Full Line Non-ISOCH= ", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; ISOCH Full Line", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC; All, regardless of = priority.", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI", "PerPkg": "1", @@ -1623,6 +1976,7 @@ }, { "BriefDescription": "Partial Non-Isochronous writes to the iMC", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", "PerPkg": "1", @@ -1632,44 +1986,55 @@ }, { "BriefDescription": "M2M Writes Issued to iMC; ISOCH Partial", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches; MC Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches; Mesh Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x53", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch requests that got turn into a demand= request", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_PREFCAM_DEMAND_PROMOTIONS", "PerPkg": "1", @@ -1678,6 +2043,7 @@ }, { "BriefDescription": "Inserts into the Memory Controller Prefetch Q= ueue", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_M2M_PREFCAM_INSERTS", "PerPkg": "1", @@ -1686,15 +2052,19 @@ }, { "BriefDescription": "Prefetch CAM Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -1702,8 +2072,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -1711,8 +2083,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -1720,8 +2094,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -1729,8 +2105,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -1738,8 +2116,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -1747,8 +2127,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -1756,8 +2138,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -1765,174 +2149,217 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_NO_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 0", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 1", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular; Ch= annel 2", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special; Ch= annel 2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_CYCLES_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M2M_RxC_AD_INSERTS", "PerPkg": "1", @@ -1941,6 +2368,7 @@ }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", "PerPkg": "1", @@ -1948,20 +2376,25 @@ }, { "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M2M_RxC_BL_INSERTS", "PerPkg": "1", @@ -1969,6 +2402,7 @@ }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", "PerPkg": "1", @@ -1976,8 +2410,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -1985,8 +2421,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -1994,8 +2432,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -2003,8 +2443,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -2012,8 +2454,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -2021,8 +2465,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -2030,8 +2476,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -2039,8 +2487,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -2048,8 +2498,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -2057,8 +2509,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -2066,8 +2520,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -2075,8 +2531,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -2084,8 +2542,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -2093,8 +2553,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -2102,8 +2564,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -2111,8 +2575,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -2120,8 +2586,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -2129,8 +2597,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -2138,8 +2608,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -2147,8 +2619,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -2156,8 +2630,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -2165,8 +2641,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -2174,8 +2652,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -2183,8 +2663,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -2192,8 +2674,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -2201,8 +2685,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -2210,8 +2696,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -2219,8 +2707,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -2228,8 +2718,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -2237,8 +2729,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2246,8 +2740,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2255,8 +2751,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2264,8 +2762,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2273,8 +2773,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2282,8 +2784,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2291,8 +2795,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2300,8 +2806,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2309,8 +2817,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2318,8 +2828,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2327,8 +2839,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2336,8 +2850,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2345,8 +2861,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2354,8 +2872,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2363,8 +2883,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2372,8 +2894,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2381,8 +2905,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2390,8 +2916,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2399,8 +2927,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -2408,8 +2938,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -2417,8 +2949,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -2426,8 +2960,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -2435,8 +2971,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -2444,8 +2982,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -2453,151 +2993,190 @@ }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_CYCLES_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_CYCLES_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Pending Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "UNC_M2M_TRACKER_PENDING_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", "EventCode": "0xD", "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M2M_TxC_AD_INSERTS", "PerPkg": "1", @@ -2605,20 +3184,25 @@ }, { "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", "PerPkg": "1", @@ -2626,430 +3210,537 @@ }, { "BriefDescription": "Outbound Ring Transactions on AK; CRD Transac= tions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK; NDR Transac= tions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.NDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "UNC_M2M_TxC_AK_CREDIT_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; All", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Read Credit Request", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Compare Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full; Write Credit Request= ", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Read Credit Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Write Compare R= equest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty; Write Credit Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Prefetch Read= Cam Hit", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Read Credit R= equest", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Write Compare= Request", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations; Write Credit = Request", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Read Credit Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Write Compare R= equest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy; Write Credit Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_TxC_AK_SIDEBAND.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Sideband", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_TxC_AK_SIDEBAND.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Cache", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to Core", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache; Data= to QPI", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired; Common Me= sh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credits Occupancy; Common = Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M2M_TxC_BL_CREDIT_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; All", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - N= ear Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full; Common Mesh Stop - F= ar Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; All", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations; All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", "PerPkg": "1", @@ -3058,54 +3749,67 @@ }, { "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations; Common Mesh S= top - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits; Co= mmon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits; Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Occupancy; All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.ALL", "PerPkg": "1", @@ -3114,24 +3818,30 @@ }, { "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Occupancy; Common Mesh Sto= p - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2M_TxC_BL_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3139,8 +3849,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3148,8 +3860,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3157,8 +3871,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3166,8 +3882,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3175,8 +3893,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3184,8 +3904,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3193,8 +3915,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3202,8 +3926,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3211,8 +3937,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3220,8 +3948,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9F", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -3229,8 +3959,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3238,8 +3970,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3247,8 +3981,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3256,8 +3992,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3265,8 +4003,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3274,8 +4014,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3283,8 +4025,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3292,8 +4036,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3301,8 +4047,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3310,8 +4058,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3319,8 +4069,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3328,8 +4080,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3337,8 +4091,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3346,8 +4102,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3355,8 +4113,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3364,8 +4124,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3373,8 +4135,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3382,8 +4146,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3391,8 +4157,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -3400,8 +4168,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -3409,8 +4179,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -3418,8 +4190,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -3427,8 +4201,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -3436,8 +4212,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -3445,8 +4223,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -3454,8 +4234,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -3463,8 +4245,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -3472,8 +4256,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -3481,8 +4267,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -3490,8 +4278,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -3499,8 +4289,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -3508,8 +4300,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -3517,8 +4311,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -3526,8 +4322,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -3535,8 +4333,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3544,8 +4344,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3553,8 +4355,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3562,8 +4366,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -3571,8 +4377,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3580,8 +4388,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3589,8 +4399,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -3598,8 +4410,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -3607,8 +4421,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -3616,8 +4432,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -3625,8 +4443,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -3634,8 +4454,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -3643,8 +4465,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -3652,8 +4476,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -3661,8 +4487,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3670,8 +4498,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3679,8 +4509,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -3688,8 +4520,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -3697,8 +4531,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -3706,8 +4542,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3715,8 +4553,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -3724,8 +4564,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3733,8 +4575,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3742,8 +4586,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -3751,8 +4597,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -3760,8 +4608,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -3769,8 +4619,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3778,8 +4630,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -3787,8 +4641,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3796,8 +4652,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3805,8 +4663,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -3814,8 +4674,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -3823,8 +4685,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -3832,8 +4696,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3841,8 +4707,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -3850,8 +4718,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -3859,8 +4729,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -3868,8 +4740,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -3877,8 +4751,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -3886,8 +4762,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -3895,8 +4773,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -3904,8 +4784,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -3913,8 +4795,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -3922,8 +4806,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -3931,8 +4817,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -3940,8 +4828,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -3949,8 +4839,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -3958,8 +4850,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -3967,8 +4861,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -3976,8 +4872,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -3985,8 +4883,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -3994,8 +4894,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -4003,8 +4905,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -4012,8 +4916,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -4021,8 +4927,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -4030,8 +4938,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -4039,8 +4949,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -4048,8 +4960,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -4057,8 +4971,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -4066,8 +4982,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -4075,8 +4993,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -4084,8 +5004,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -4093,8 +5015,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xA8", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -4102,8 +5026,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -4111,8 +5037,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -4120,8 +5048,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -4129,8 +5059,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -4138,8 +5070,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -4147,8 +5081,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -4156,179 +5092,223 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_NO_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_CYCLES_REG_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 0", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 1", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special; Chan= nel 2", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_CYCLES_SPEC_CREDITS.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_FULL.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WRITE_TRACKER_CYCLES_NE.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x61", "EventName": "UNC_M2M_WRITE_TRACKER_INSERTS.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy; Channel 2", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_WRITE_TRACKER_OCCUPANCY.CH2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4336,8 +5316,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4345,8 +5327,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4354,8 +5338,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4363,8 +5349,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4372,8 +5360,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x80", "EventName": "UNC_M3UPI_AG0_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4381,8 +5371,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4390,8 +5382,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4399,8 +5393,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4408,8 +5404,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4417,8 +5415,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4426,8 +5426,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x82", "EventName": "UNC_M3UPI_AG0_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4435,8 +5437,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4444,8 +5448,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4453,8 +5459,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4462,8 +5470,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4471,8 +5481,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4480,8 +5492,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x88", "EventName": "UNC_M3UPI_AG0_BL_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4489,8 +5503,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4498,8 +5514,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4507,8 +5525,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4516,8 +5536,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4525,8 +5547,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4534,8 +5558,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x8A", "EventName": "UNC_M3UPI_AG0_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 0 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4543,8 +5569,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4552,8 +5580,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4561,8 +5591,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4570,8 +5602,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4579,8 +5613,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4588,8 +5624,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x84", "EventName": "UNC_M3UPI_AG1_AD_CRD_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4597,8 +5635,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 0", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4606,8 +5646,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 1", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4615,8 +5657,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 2", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4624,8 +5668,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 3", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4633,8 +5679,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 4", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4642,8 +5690,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy; For Transgre= ss 5", + "Counter": "0,1,2", "EventCode": "0x86", "EventName": "UNC_M3UPI_AG1_AD_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 AD credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4651,8 +5701,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 0", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x1", @@ -4660,8 +5712,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 1", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x2", @@ -4669,8 +5723,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 2", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x4", @@ -4678,8 +5734,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 3", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x8", @@ -4687,8 +5745,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 4", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x10", @@ -4696,8 +5756,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy; For Transgre= ss 5", + "Counter": "0", "EventCode": "0x8E", "EventName": "UNC_M3UPI_AG1_BL_CRD_OCCUPANCY.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits in use in a= given cycle, per transgress", "UMask": "0x20", @@ -4705,8 +5767,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 0", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x1", @@ -4714,8 +5778,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 1", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x2", @@ -4723,8 +5789,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 2", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x4", @@ -4732,8 +5800,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 3", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x8", @@ -4741,8 +5811,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 4", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x10", @@ -4750,8 +5822,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired; For Transgres= s 5", + "Counter": "0,1,2", "EventCode": "0x8C", "EventName": "UNC_M3UPI_AG1_BL_CREDITS_ACQUIRED.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CMS Agent 1 BL credits acquired in= a given cycle, per transgress.", "UMask": "0x20", @@ -4759,8 +5833,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Requests", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x4", @@ -4768,8 +5844,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Snoops", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x8", @@ -4777,8 +5855,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; VNA Messages", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x1", @@ -4786,8 +5866,10 @@ }, { "BriefDescription": "CBox AD Credits Empty; Writebacks", + "Counter": "0,1,2", "EventCode": "0x22", "EventName": "UNC_M3UPI_CHA_AD_CREDITS_EMPTY.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to Cbox on the = AD Ring (covers higher CBoxes)", "UMask": "0x2", @@ -4795,39 +5877,49 @@ }, { "BriefDescription": "Number of uclks in domain", + "Counter": "0,1,2", "EventCode": "0x1", "EventName": "UNC_M3UPI_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of uclks in the M3 uclk do= main. This could be slightly different than the count in the Ubox because = of enable/freeze delays. However, because the M3 is close to the Ubox, the= y generally should not diverge by more than a handful of cycles.", "Unit": "M3UPI" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2", "EventCode": "0xC0", "EventName": "UNC_M3UPI_CMS_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "D2C Sent", + "Counter": "0,1,2", "EventCode": "0x2B", "EventName": "UNC_M3UPI_D2C_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases BL sends direct to core", "Unit": "M3UPI" }, { "BriefDescription": "D2U Sent", + "Counter": "0,1,2", "EventCode": "0x2A", "EventName": "UNC_M3UPI_D2U_SENT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cases where SMI3 sends D2U command", "Unit": "M3UPI" }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Down", + "Counter": "0,1,2", "EventCode": "0xAE", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x4", @@ -4835,8 +5927,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements;= Up", + "Counter": "0,1,2", "EventCode": "0xAE", "EventName": "UNC_M3UPI_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of cycles IV was blocked in th= e TGR Egress due to SNP/GO Ordering requirements", "UMask": "0x1", @@ -4844,8 +5938,10 @@ }, { "BriefDescription": "FaST wire asserted; Horizontal", + "Counter": "0,1,2", "EventCode": "0xA5", "EventName": "UNC_M3UPI_FAST_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x2", @@ -4853,8 +5949,10 @@ }, { "BriefDescription": "FaST wire asserted; Vertical", + "Counter": "0,1,2", "EventCode": "0xA5", "EventName": "UNC_M3UPI_FAST_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles either the local= or incoming distress signals are asserted. Incoming distress includes up,= dn and across.", "UMask": "0x1", @@ -4862,8 +5960,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x1", @@ -4871,8 +5971,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x2", @@ -4880,8 +5982,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x4", @@ -4889,8 +5993,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xA7", "EventName": "UNC_M3UPI_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AD ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. We really have two rings -- a cloc= kwise ring and a counter-clockwise ring. On the left side of the ring, the= UP direction is on the clockwise ring and DN is on the counter-clockwise r= ing. On the right side of the ring, this is reversed. The first half of t= he CBos are on the left side of the ring, and the 2nd half are on the right= side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD= is NOT the same ring as CBo 2 UP AD because they are on opposite sides of = the ring.", "UMask": "0x8", @@ -4898,8 +6004,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x1", @@ -4907,8 +6015,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x2", @@ -4916,8 +6026,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x4", @@ -4925,8 +6037,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xA9", "EventName": "UNC_M3UPI_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal AK ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clockw= ise ring and a counter-clockwise ring. On the left side of the ring, the U= P direction is on the clockwise ring and DN is on the counter-clockwise rin= g. On the right side of the ring, this is reversed. The first half of the= CBos are on the left side of the ring, and the 2nd half are on the right s= ide of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD i= s NOT the same ring as CBo 2 UP AD because they are on opposite sides of th= e ring.", "UMask": "0x8", @@ -4934,8 +6048,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Even", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -4943,8 +6059,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Left and Odd", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -4952,8 +6070,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Even", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -4961,8 +6081,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use; Right and Odd", + "Counter": "0,1,2", "EventCode": "0xAB", "EventName": "UNC_M3UPI_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal BL ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop.We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -4970,8 +6092,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Left", + "Counter": "0,1,2", "EventCode": "0xAD", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x1", @@ -4979,8 +6103,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use; Right", + "Counter": "0,1,2", "EventCode": "0xAD", "EventName": "UNC_M3UPI_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Horizon= tal IV ring is being used at this ring stop. This includes when packets ar= e passing by and when packets are being sunk, but does not include when pac= kets are being sent from the ring stop. There is only 1 IV ring. Therefor= e, if one wants to monitor the Even ring, they should select both UP_EVEN a= nd DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN= _ODD.", "UMask": "0x4", @@ -4988,8 +6114,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO0 and IIO1 share the = same ring destination. (1 VN0 credit only)", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x1", @@ -4997,8 +6125,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO2", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO2_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x2", @@ -5006,8 +6136,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO3", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO3_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x4", @@ -5015,8 +6147,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO4", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO4_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x8", @@ -5024,8 +6158,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; IIO5", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.IIO5_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x10", @@ -5033,8 +6169,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; All IIO targets for NCS = are in single mask. ORs them together", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x20", @@ -5042,8 +6180,10 @@ }, { "BriefDescription": "M2 BL Credits Empty; Selected M2p BL NCS cred= its", + "Counter": "0,1,2", "EventCode": "0x23", "EventName": "UNC_M3UPI_M2_BL_CREDITS_EMPTY.NCS_SEL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No vn0 and vna credits available to send to = M2", "UMask": "0x40", @@ -5051,8 +6191,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x1", @@ -5060,8 +6202,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 1", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x2", @@ -5069,8 +6213,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AD - Slot 2", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x4", @@ -5078,8 +6224,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AK - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x10", @@ -5087,8 +6235,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; AK - Slot 2", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.AK_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x20", @@ -5096,8 +6246,10 @@ }, { "BriefDescription": "Multi Slot Flit Received; BL - Slot 0", + "Counter": "0,1,2", "EventCode": "0x3E", "EventName": "UNC_M3UPI_MULTI_SLOT_RCVD.BL_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Multi slot flit received - S0, S1 and/or S2 = populated (can use AK S0/S1 masks for AK allocations)", "UMask": "0x8", @@ -5105,8 +6257,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AD", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x1", @@ -5114,8 +6268,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; AK", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x2", @@ -5123,8 +6279,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; BL", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x4", @@ -5132,8 +6290,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= ; IV", + "Counter": "0,1,2", "EventCode": "0xA1", "EventName": "UNC_M3UPI_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Horizontal ring that were bounced, by ring type.", "UMask": "0x8", @@ -5141,8 +6301,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = AD", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x1", @@ -5150,8 +6312,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Acknowledgements to core", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x2", @@ -5159,8 +6323,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Data Responses to core", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x4", @@ -5168,8 +6334,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.; = Snoops of processor's cache.", + "Counter": "0,1,2", "EventCode": "0xA0", "EventName": "UNC_M3UPI_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles incoming messages from the = Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -5177,87 +6345,109 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AD", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; AK", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; Acknowled= gements to Agent 1", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; BL", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Horizontal Ring; IV", + "Counter": "0,1,2", "EventCode": "0xA3", "EventName": "UNC_M3UPI_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; AD", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Acknowledge= ments to core", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Data Respon= ses to core", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Sink Starvation on Vertical Ring; Snoops of p= rocessor's cache.", + "Counter": "0,1,2", "EventCode": "0xA2", "EventName": "UNC_M3UPI_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2", "EventCode": "0xA4", "EventName": "UNC_M3UPI_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Lost Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -5265,8 +6455,10 @@ }, { "BriefDescription": "Lost Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -5274,8 +6466,10 @@ }, { "BriefDescription": "Lost Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5283,8 +6477,10 @@ }, { "BriefDescription": "Lost Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -5292,8 +6488,10 @@ }, { "BriefDescription": "Lost Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5301,8 +6499,10 @@ }, { "BriefDescription": "Lost Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -5310,8 +6510,10 @@ }, { "BriefDescription": "Lost Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4B", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -5319,8 +6521,10 @@ }, { "BriefDescription": "Lost Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -5328,8 +6532,10 @@ }, { "BriefDescription": "Lost Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -5337,8 +6543,10 @@ }, { "BriefDescription": "Lost Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5346,8 +6554,10 @@ }, { "BriefDescription": "Lost Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -5355,8 +6565,10 @@ }, { "BriefDescription": "Lost Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5364,8 +6576,10 @@ }, { "BriefDescription": "Lost Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -5373,8 +6587,10 @@ }, { "BriefDescription": "Lost Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4C", "EventName": "UNC_M3UPI_RxC_ARB_LOST_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message requested but lost arbitration; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -5382,8 +6598,10 @@ }, { "BriefDescription": "Arb Miscellaneous; AD, BL Parallel Win", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.ADBL_PARALLEL_WIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD and BL messages won arbitration concurren= tly / in parallel", "UMask": "0x40", @@ -5391,8 +6609,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn0 messages because slotting stage cannot accept new message", "UMask": "0x4", @@ -5400,8 +6620,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending AD = VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_AD_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g ad vn1 messages because slotting stage cannot accept new message", "UMask": "0x8", @@ -5409,8 +6631,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn0 messages because slotting stage cannot accept new message", "UMask": "0x10", @@ -5418,8 +6642,10 @@ }, { "BriefDescription": "Arb Miscellaneous; No Progress on Pending BL = VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.NO_PROG_BL_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Arbitration stage made no progress on pendin= g bl vn1 messages because slotting stage cannot accept new message", "UMask": "0x20", @@ -5427,8 +6653,10 @@ }, { "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN0", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn0, delaying vn1 win, because vn0 offered parallel ad/bl", "UMask": "0x1", @@ -5436,8 +6664,10 @@ }, { "BriefDescription": "Arb Miscellaneous; Parallel Bias to VN1", + "Counter": "0,1,2", "EventCode": "0x4D", "EventName": "UNC_M3UPI_RxC_ARB_MISC.PAR_BIAS_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0/VN1 arbiter gave second, consecutive win= to vn1, delaying vn0 win, because vn1 offered parallel ad/bl", "UMask": "0x2", @@ -5445,8 +6675,10 @@ }, { "BriefDescription": "Can't Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", "UMask": "0x1", @@ -5454,8 +6686,10 @@ }, { "BriefDescription": "Can't Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", "UMask": "0x4", @@ -5463,8 +6697,10 @@ }, { "BriefDescription": "Can't Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5472,8 +6708,10 @@ }, { "BriefDescription": "Can't Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", "UMask": "0x20", @@ -5481,8 +6719,10 @@ }, { "BriefDescription": "Can't Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", "UMask": "0x40", @@ -5490,8 +6730,10 @@ }, { "BriefDescription": "Can't Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", "UMask": "0x8", @@ -5499,8 +6741,10 @@ }, { "BriefDescription": "Can't Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x49", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", "UMask": "0x10", @@ -5508,8 +6752,10 @@ }, { "BriefDescription": "Can't Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Home (REQ) messages on AD. R= EQ is generally used to send requests, request responses, and snoop respons= es.", "UMask": "0x1", @@ -5517,8 +6763,10 @@ }, { "BriefDescription": "Can't Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on AD= . RSP packets are used to transmit a variety of protocol flits including g= rants and completions (CMP).", "UMask": "0x4", @@ -5526,8 +6774,10 @@ }, { "BriefDescription": "Can't Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Snoops (SNP) messages on AD. = SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5535,8 +6785,10 @@ }, { "BriefDescription": "Can't Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Broadcast (NCB) = messages on BL. NCB is generally used to transmit data without coherency. = For example, non-coherent read data returns.", "UMask": "0x20", @@ -5544,8 +6796,10 @@ }, { "BriefDescription": "Can't Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Non-Coherent Standard (NCS) m= essages on BL.", "UMask": "0x40", @@ -5553,8 +6807,10 @@ }, { "BriefDescription": "Can't Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Response (RSP) messages on BL= . RSP packets are used to transmit a variety of protocol flits including gr= ants and completions (CMP).", "UMask": "0x8", @@ -5562,8 +6818,10 @@ }, { "BriefDescription": "Can't Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4A", "EventName": "UNC_M3UPI_RxC_ARB_NOAD_REQ_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message was not able to request arbitrat= ion while some other message won arbitration; Data Response (WB) messages o= n BL. WB is generally used to transmit data with coherency. For example, = remote reads and writes, or cache to cache transfers will transmit their da= ta using WB.", "UMask": "0x10", @@ -5571,8 +6829,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5580,8 +6840,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -5589,8 +6851,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -5598,8 +6862,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -5607,8 +6873,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -5616,8 +6884,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -5625,8 +6895,10 @@ }, { "BriefDescription": "No Credits to Arb for VN0; WB on BL", + "Counter": "0,1,2", "EventCode": "0x47", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -5634,8 +6906,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5643,8 +6917,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -5652,8 +6928,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -5661,8 +6939,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -5670,8 +6950,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -5679,8 +6961,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -5688,8 +6972,10 @@ }, { "BriefDescription": "No Credits to Arb for VN1; WB on BL", + "Counter": "0,1,2", "EventCode": "0x48", "EventName": "UNC_M3UPI_RxC_ARB_NOCRED_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN1 message is blocked from requesting arbit= ration due to lack of remote UPI credits; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -5697,8 +6983,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on BL Ar= b", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_BL_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while b= l message is in arbitration", "UMask": "0x2", @@ -5706,8 +6994,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD to Slot 0 on Idle", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S0_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to slot 0 of independent flit while p= ipeline is idle", "UMask": "0x1", @@ -5715,8 +7005,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 1", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S1_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 1 while merging with bl = message in same flit", "UMask": "0x4", @@ -5724,8 +7016,10 @@ }, { "BriefDescription": "Ingress Queue Bypasses; AD + BL to Slot 2", + "Counter": "0,1,2", "EventCode": "0x40", "EventName": "UNC_M3UPI_RxC_BYPASSED.AD_S2_BL_SLOT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times message is bypassed around t= he Ingress Queue; AD is taking bypass to flit slot 2 while merging with bl = message in same flit", "UMask": "0x8", @@ -5733,8 +7027,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5742,8 +7038,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x4", @@ -5751,8 +7049,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", "UMask": "0x2", @@ -5760,8 +7060,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", "UMask": "0x20", @@ -5769,8 +7071,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5778,8 +7082,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", "UMask": "0x8", @@ -5787,8 +7093,10 @@ }, { "BriefDescription": "VN0 message lost contest for flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x50", "EventName": "UNC_M3UPI_RxC_COLLISION_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN0 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -5796,8 +7104,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Home (REQ) messages on AD. REQ is generally u= sed to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -5805,8 +7115,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on AD. RSP packets ar= e used to transmit a variety of protocol flits including grants and complet= ions (CMP).", "UMask": "0x4", @@ -5814,8 +7126,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Snoops (SNP) messages on AD. SNP is used for = outgoing snoops.", "UMask": "0x2", @@ -5823,8 +7137,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Broadcast (NCB) messages on BL. = NCB is generally used to transmit data without coherency. For example, non= -coherent read data returns.", "UMask": "0x20", @@ -5832,8 +7148,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Non-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5841,8 +7159,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Response (RSP) messages on BL. RSP packets are= used to transmit a variety of protocol flits including grants and completi= ons (CMP).", "UMask": "0x8", @@ -5850,8 +7170,10 @@ }, { "BriefDescription": "VN1 message lost contest for flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x51", "EventName": "UNC_M3UPI_RxC_COLLISION_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress VN1 packets lost t= he contest for Flit Slot 0.; Data Response (WB) messages on BL. WB is gene= rally used to transmit data with coherency. For example, remote reads and = writes, or cache to cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -5859,8 +7181,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; Any In BGF FIFO", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf (fifo only)", "UMask": "0x1", @@ -5868,8 +7192,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; Any in BGF Path", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.ANY_BGF_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Indication that at least one packet (flit) i= s in the bgf path (i.e. pipe to fifo)", "UMask": "0x2", @@ -5877,8 +7203,10 @@ }, { "BriefDescription": "Miscellaneous Credit Events; No D2K For Arb", + "Counter": "0,1,2", "EventCode": "0x60", "EventName": "UNC_M3UPI_RxC_CRD_MISC.NO_D2K_FOR_ARB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VN0 or VN1 BL RSP message was blocked from a= rbitration request due to lack of D2K CMP credits", "UMask": "0x4", @@ -5886,8 +7214,10 @@ }, { "BriefDescription": "Credit Occupancy; D2K Credits", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.D2K_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "D2K completion fifo credit occupancy (credit= s in use), accumulated across all cycles", "UMask": "0x10", @@ -5895,8 +7225,10 @@ }, { "BriefDescription": "Credit Occupancy; Packets in BGF FIFO", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer= bgf; packets (flits) in fifo", "UMask": "0x2", @@ -5904,8 +7236,10 @@ }, { "BriefDescription": "Credit Occupancy; Packets in BGF Path", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.FLITS_IN_PATH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy of m3upi ingress -> upi link layer= bgf; packets (flits) in path (i.e. pipe to fifo or fifo)", "UMask": "0x4", @@ -5913,8 +7247,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_FIFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "count of bl messages in pump-1-pending state= , in completion fifo only", "UMask": "0x40", @@ -5922,8 +7258,10 @@ }, { "BriefDescription": "Credit Occupancy", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.P1P_TOTAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "count of bl messages in pump-1-pending state= , in marker table and in fifo", "UMask": "0x20", @@ -5931,8 +7269,10 @@ }, { "BriefDescription": "Credit Occupancy; Transmit Credits", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.TxQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Link layer transmit queue credit occupancy (= credits in use), accumulated across all cycles", "UMask": "0x8", @@ -5940,8 +7280,10 @@ }, { "BriefDescription": "Credit Occupancy; VNA In Use", + "Counter": "0,1,2", "EventCode": "0x61", "EventName": "UNC_M3UPI_RxC_CRD_OCC.VNA_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote UPI VNA credit occupancy (number of c= redits in use), accumulated across all cycles", "UMask": "0x1", @@ -5949,8 +7291,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -5958,8 +7302,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -5967,8 +7313,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -5976,8 +7324,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -5985,8 +7335,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -5994,8 +7346,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6003,8 +7357,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "Counter": "0,1,2", "EventCode": "0x43", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the UPI Ing= ress is not empty. This tracks one of the three rings that are used by the= UPI agent. This can be used in conjunction with the UPI Ingress Occupancy= Accumulator event in order to calculate average queue occupancy. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6012,8 +7368,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -6021,8 +7379,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -6030,8 +7390,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6039,8 +7401,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6048,8 +7412,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6057,8 +7423,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6066,8 +7434,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Cycles Not Emp= ty; WB on BL", + "Counter": "0,1,2", "EventCode": "0x44", "EventName": "UNC_M3UPI_RxC_CYCLES_NE_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6075,8 +7445,10 @@ }, { "BriefDescription": "Data Flit Not Sent; All", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x1", @@ -6084,8 +7456,10 @@ }, { "BriefDescription": "Data Flit Not Sent; No BGF Credits", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_BGF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x2", @@ -6093,8 +7467,10 @@ }, { "BriefDescription": "Data Flit Not Sent; No TxQ Credits", + "Counter": "0,1,2", "EventCode": "0x57", "EventName": "UNC_M3UPI_RxC_FLITS_DATA_NOT_SENT.NO_TXQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Data flit is ready for transmission but coul= d not be sent", "UMask": "0x4", @@ -6102,8 +7478,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 0", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 0", "UMask": "0x1", @@ -6111,8 +7489,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_AT_LIMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is at capacity (pending= table plus completion fifo at limit)", "UMask": "0x10", @@ -6120,8 +7500,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_BUSY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is tracking at least on= e message", "UMask": "0x8", @@ -6129,8 +7511,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_FIFO_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending completion fifo is full", "UMask": "0x40", @@ -6138,8 +7522,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_HOLD_P0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "pump-1-pending logic is at or near capacity,= such that pump-0-only bl messages are getting stalled in slotting stage", "UMask": "0x20", @@ -6147,8 +7533,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1P_TO_LIMBO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "a bl message finished but is in limbo and mo= ved to pump-1-pending logic", "UMask": "0x4", @@ -6156,8 +7544,10 @@ }, { "BriefDescription": "Generating BL Data Flit Sequence; Wait on Pum= p 1", + "Counter": "0,1,2", "EventCode": "0x59", "EventName": "UNC_M3UPI_RxC_FLITS_GEN_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "generating bl data flit sequence; waiting fo= r data pump 1", "UMask": "0x2", @@ -6165,15 +7555,19 @@ }, { "BriefDescription": "UNC_M3UPI_RxC_FLITS_MISC", + "Counter": "0,1,2", "EventCode": "0x5A", "EventName": "UNC_M3UPI_RxC_FLITS_MISC", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit; One Message", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "One message in flit; VNA or non-VNA flit", "UMask": "0x1", @@ -6181,8 +7575,10 @@ }, { "BriefDescription": "Sent Header Flit; One Message in non-VNA", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.1_MSG_VNX", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "One message in flit; non-VNA flit", "UMask": "0x8", @@ -6190,8 +7586,10 @@ }, { "BriefDescription": "Sent Header Flit; Two Messages", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.2_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Two messages in flit; VNA flit", "UMask": "0x2", @@ -6199,8 +7597,10 @@ }, { "BriefDescription": "Sent Header Flit; Three Messages", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.3_MSGS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Three messages in flit; VNA flit", "UMask": "0x4", @@ -6208,40 +7608,50 @@ }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Sent Header Flit", + "Counter": "0,1,2", "EventCode": "0x56", "EventName": "UNC_M3UPI_RxC_FLITS_SENT.SLOTS_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit; All", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "Slotting BL Message Into Header Flit; Needs D= ata Flit", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.NEED_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL message requires data flit sequence", "UMask": "0x2", @@ -6249,8 +7659,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 0", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P0_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Waiting for header pump 0", "UMask": "0x4", @@ -6258,8 +7670,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit", "UMask": "0x10", @@ -6267,8 +7681,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Bubble", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit but f= lit transmission delayed", "UMask": "0x20", @@ -6276,8 +7692,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Don't N= eed Pump 1 - Not Avail", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Header pump 1 is not required for flit and n= ot available", "UMask": "0x40", @@ -6285,8 +7703,10 @@ }, { "BriefDescription": "Slotting BL Message Into Header Flit; Wait on= Pump 1", + "Counter": "0,1,2", "EventCode": "0x58", "EventName": "UNC_M3UPI_RxC_FLITS_SLOT_BL.P1_WAIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Waiting for header pump 1", "UMask": "0x8", @@ -6294,8 +7714,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting control state machine is in any accumulate state= ; multi-message flit may be assembled over multiple cycles", "UMask": "0x1", @@ -6303,8 +7725,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate Ready", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; header flit slotting control state machine is in accum_ready state; f= lit is ready to send but transmission is blocked; more messages may be slot= ted into flit", "UMask": "0x2", @@ -6312,8 +7736,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Accumulate Wasted", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.ACCUM_WASTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Flit is being assembled over multiple cycles, but no additional messa= ge is being slotted into flit in current cycle; accumulate cycle is wasted", "UMask": "0x4", @@ -6321,8 +7747,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Blocked", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting entered run-ahead state; new header flit is star= ted while transmission of prior, fully assembled flit is blocked", "UMask": "0x8", @@ -6330,8 +7758,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Run-Ahead - Message", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.AHEAD_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit slotting is in run-ahead to start new flit, and message i= s actually slotted into new flit", "UMask": "0x10", @@ -6339,8 +7769,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Ok", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; New header flit construction may proceed in parallel with data flit s= equence", "UMask": "0x20", @@ -6348,8 +7780,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Flit Finished", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_FLIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Header flit finished assembly in parallel with data flit sequence", "UMask": "0x80", @@ -6357,8 +7791,10 @@ }, { "BriefDescription": "Flit Gen - Header 1; Parallel Message", + "Counter": "0,1,2", "EventCode": "0x53", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR1.PAR_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 1; Message is slotted into header flit in parallel with data flit sequen= ce", "UMask": "0x40", @@ -6366,8 +7802,10 @@ }, { "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall", + "Counter": "0,1,2", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate-matching stall injected", "UMask": "0x1", @@ -6375,8 +7813,10 @@ }, { "BriefDescription": "Flit Gen - Header 2; Rate-matching Stall - No= Message", + "Counter": "0,1,2", "EventCode": "0x54", "EventName": "UNC_M3UPI_RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Events related to Header Flit Generation - S= et 2; Rate matching stall injected, but no additional message slotted durin= g stall cycle", "UMask": "0x2", @@ -6384,8 +7824,10 @@ }, { "BriefDescription": "Header Not Sent; All", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent", "UMask": "0x1", @@ -6393,8 +7835,10 @@ }, { "BriefDescription": "Header Not Sent; No BGF Credits", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available", "UMask": "0x2", @@ -6402,8 +7846,10 @@ }, { "BriefDescription": "Header Not Sent; No BGF Credits + No Extra Me= ssage Slotted", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No BGF credits available; no additional message slotted in= to flit", "UMask": "0x8", @@ -6411,8 +7857,10 @@ }, { "BriefDescription": "Header Not Sent; No TxQ Credits", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available", "UMask": "0x4", @@ -6420,8 +7868,10 @@ }, { "BriefDescription": "Header Not Sent; No TxQ Credits + No Extra Me= ssage Slotted", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; No TxQ credits available; no additional message slotted in= to flit", "UMask": "0x10", @@ -6429,8 +7879,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - One Slot Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.ONE_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only one slot taken (two slots fr= ee)", "UMask": "0x20", @@ -6438,8 +7890,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - Three Slots Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.THREE_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with three slots taken (no slots free)= ", "UMask": "0x80", @@ -6447,8 +7901,10 @@ }, { "BriefDescription": "Header Not Sent; Sent - Two Slots Taken", + "Counter": "0,1,2", "EventCode": "0x55", "EventName": "UNC_M3UPI_RxC_FLIT_NOT_SENT.TWO_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "header flit is ready for transmission but co= uld not be sent; sending header flit with only two slots taken (one slots f= ree)", "UMask": "0x40", @@ -6456,8 +7912,10 @@ }, { "BriefDescription": "Message Held; Can't Slot AD", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some AD message could not be slotted (logica= l OR of all AD events under INGR_SLOT_CANT_MC_VN{0,1})", "UMask": "0x40", @@ -6465,8 +7923,10 @@ }, { "BriefDescription": "Message Held; Can't Slot BL", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.CANT_SLOT_BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some BL message could not be slotted (logica= l OR of all BL events under INGR_SLOT_CANT_MC_VN{0,1})", "UMask": "0x80", @@ -6474,8 +7934,10 @@ }, { "BriefDescription": "Message Held; Parallel AD Lost", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_AD_LOST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some AD message lost contest for slot 0 (log= ical OR of all AD events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x10", @@ -6483,8 +7945,10 @@ }, { "BriefDescription": "Message Held; Parallel Attempt", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_ATTEMPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ad and bl messages attempted to slot into th= e same flit in parallel", "UMask": "0x4", @@ -6492,8 +7956,10 @@ }, { "BriefDescription": "Message Held; Parallel BL Lost", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_BL_LOST", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "some BL message lost contest for slot 0 (log= ical OR of all BL events under INGR_SLOT_LOST_MC_VN{0,1})", "UMask": "0x20", @@ -6501,8 +7967,10 @@ }, { "BriefDescription": "Message Held; Parallel Success", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.PARALLEL_SUCCESS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ad and bl messages were actually slotted int= o the same flit in parallel", "UMask": "0x8", @@ -6510,8 +7978,10 @@ }, { "BriefDescription": "Message Held; VN0", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "vn0 message(s) that couldn't be slotted into= last vn0 flit are held in slotting stage while processing vn1 flit", "UMask": "0x1", @@ -6519,8 +7989,10 @@ }, { "BriefDescription": "Message Held; VN1", + "Counter": "0,1,2", "EventCode": "0x52", "EventName": "UNC_M3UPI_RxC_HELD.VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "vn1 message(s) that couldn't be slotted into= last vn1 flit are held in slotting stage while processing vn0 flit", "UMask": "0x2", @@ -6528,8 +8000,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Home (REQ) = messages on AD. REQ is generally used to send requests, request responses,= and snoop responses.", "UMask": "0x1", @@ -6537,8 +8011,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on AD. RSP packets are used to transmit a variety of protocol= flits including grants and completions (CMP).", "UMask": "0x4", @@ -6546,8 +8022,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Snoops (SNP= ) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6555,8 +8033,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Broadcast (NCB) messages on BL. NCB is generally used to transmit data w= ithout coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6564,8 +8044,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Non-Coheren= t Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6573,8 +8055,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Response (R= SP) messages on BL. RSP packets are used to transmit a variety of protocol = flits including grants and completions (CMP).", "UMask": "0x8", @@ -6582,8 +8066,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Inserts; WB on= BL", + "Counter": "0,1,2", "EventCode": "0x41", "EventName": "UNC_M3UPI_RxC_INSERTS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I Ingress. This tracks one of the three rings that are used by the UPI age= nt. This can be used in conjunction with the UPI Ingress Occupancy Accumul= ator event in order to calculate average queue latency. Multiple ingress b= uffers can be tracked at a given time using multiple counters.; Data Respon= se (WB) messages on BL. WB is generally used to transmit data with coheren= cy. For example, remote reads and writes, or cache to cache transfers will= transmit their data using WB.", "UMask": "0x10", @@ -6591,8 +8077,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; REQ o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; H= ome (REQ) messages on AD. REQ is generally used to send requests, request = responses, and snoop responses.", "UMask": "0x1", @@ -6600,8 +8088,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on AD. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -6609,8 +8099,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; SNP o= n AD", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; S= noops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -6618,8 +8110,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCB o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Broadcast (NCB) messages on BL. NCB is generally used to trans= mit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -6627,8 +8121,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; NCS o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; N= on-Coherent Standard (NCS) messages on BL.", "UMask": "0x40", @@ -6636,8 +8132,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; RSP o= n BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; R= esponse (RSP) messages on BL. RSP packets are used to transmit a variety of= protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -6645,8 +8143,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Inserts; WB on= BL", + "Counter": "0,1,2", "EventCode": "0x42", "EventName": "UNC_M3UPI_RxC_INSERTS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the UP= I VN1 Ingress. This tracks one of the three rings that are used by the UP= I agent. This can be used in conjunction with the UPI VN1 Ingress Occupan= cy Accumulator event in order to calculate average queue latency. Multiple= ingress buffers can be tracked at a given time using multiple counters.; D= ata Response (WB) messages on BL. WB is generally used to transmit data wi= th coherency. For example, remote reads and writes, or cache to cache tran= sfers will transmit their data using WB.", "UMask": "0x10", @@ -6654,8 +8154,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6663,8 +8165,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", "UMask": "0x4", @@ -6672,8 +8176,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", "UMask": "0x2", @@ -6681,8 +8187,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", "UMask": "0x20", @@ -6690,8 +8198,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", "UMask": "0x40", @@ -6699,8 +8209,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", "UMask": "0x8", @@ -6708,8 +8220,10 @@ }, { "BriefDescription": "VN0 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "Counter": "0,1,2", "EventCode": "0x45", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", "UMask": "0x10", @@ -6717,8 +8231,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; REQ= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Home (REQ) messages on AD. REQ is g= enerally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6726,8 +8242,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on AD. RSP = packets are used to transmit a variety of protocol flits including grants a= nd completions (CMP).", "UMask": "0x4", @@ -6735,8 +8253,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; SNP= on AD", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Snoops (SNP) messages on AD. SNP is= used for outgoing snoops.", "UMask": "0x2", @@ -6744,8 +8264,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCB= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Broadcast (NCB) message= s on BL. NCB is generally used to transmit data without coherency. For ex= ample, non-coherent read data returns.", "UMask": "0x20", @@ -6753,8 +8275,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; NCS= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Non-Coherent Standard (NCS) messages= on BL.", "UMask": "0x40", @@ -6762,8 +8286,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; RSP= on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Response (RSP) messages on BL. RSP p= ackets are used to transmit a variety of protocol flits including grants an= d completions (CMP).", "UMask": "0x8", @@ -6771,8 +8297,10 @@ }, { "BriefDescription": "VN1 Ingress (from CMS) Queue - Occupancy; WB = on BL", + "Counter": "0,1,2", "EventCode": "0x46", "EventName": "UNC_M3UPI_RxC_OCCUPANCY_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the occupancy of a given UPI VN1= Ingress queue in each cycle. This tracks one of the three ring Ingress b= uffers. This can be used with the UPI VN1 Ingress Not Empty event to calc= ulate average occupancy or the UPI VN1 Ingress Allocations event in order = to calculate average queuing latency.; Data Response (WB) messages on BL. = WB is generally used to transmit data with coherency. For example, remote = reads and writes, or cache to cache transfers will transmit their data usin= g WB.", "UMask": "0x10", @@ -6780,8 +8308,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6789,8 +8319,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -6798,8 +8330,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -6807,8 +8341,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -6816,8 +8352,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -6825,8 +8363,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -6834,8 +8374,10 @@ }, { "BriefDescription": "VN0 message can't slot into flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4E", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN0.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -6843,8 +8385,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Home (REQ) messages on AD. REQ i= s generally used to send requests, request responses, and snoop responses.", "UMask": "0x1", @@ -6852,8 +8396,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on AD. R= SP packets are used to transmit a variety of protocol flits including grant= s and completions (CMP).", "UMask": "0x4", @@ -6861,8 +8407,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.AD_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Snoops (SNP) messages on AD. SNP= is used for outgoing snoops.", "UMask": "0x2", @@ -6870,8 +8418,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Broadcast (NCB) mess= ages on BL. NCB is generally used to transmit data without coherency. For= example, non-coherent read data returns.", "UMask": "0x20", @@ -6879,8 +8429,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; NCS on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Non-Coherent Standard (NCS) messa= ges on BL.", "UMask": "0x40", @@ -6888,8 +8440,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Response (RSP) messages on BL. RS= P packets are used to transmit a variety of protocol flits including grants= and completions (CMP).", "UMask": "0x8", @@ -6897,8 +8451,10 @@ }, { "BriefDescription": "VN1 message can't slot into flit; WB on BL", + "Counter": "0,1,2", "EventCode": "0x4F", "EventName": "UNC_M3UPI_RxC_PACKING_MISS_VN1.BL_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Count cases where Ingress has packets to sen= d but did not have time to pack into flit before sending to Agent so slot w= as left NULL which could have been used.; Data Response (WB) messages on BL= . WB is generally used to transmit data with coherency. For example, remo= te reads and writes, or cache to cache transfers will transmit their data u= sing WB.", "UMask": "0x10", @@ -6906,32 +8462,40 @@ }, { "BriefDescription": "SMI3 Prefetch Messages; Lost Arbitration", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARB_LOST", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Arrived", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.ARRIVED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Dropped - Old", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_OLD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "SMI3 Prefetch Messages; Dropped - Wrap", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.DROP_WRAP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Dropped because it was overwritten by new me= ssage while prefetch queue was full", "UMask": "0x10", @@ -6939,16 +8503,20 @@ }, { "BriefDescription": "SMI3 Prefetch Messages; Slotted", + "Counter": "0,1,2", "EventCode": "0x62", "EventName": "UNC_M3UPI_RxC_SMI3_PFTCH.SLOTTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "Remote VNA Credits; Any In Use", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.ANY_IN_USE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "At least one remote vna credit is in use", "UMask": "0x20", @@ -6956,8 +8524,10 @@ }, { "BriefDescription": "Remote VNA Credits; Corrected", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.CORRECTED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of remote vna credits corrected (loca= l return) per cycle", "UMask": "0x2", @@ -6965,8 +8535,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 1", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 1 (i.e.= no vna credits available)", "UMask": "0x4", @@ -6974,8 +8546,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 4", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 4; bl (= or ad requiring 4 vna) cannot arb on vna", "UMask": "0x8", @@ -6983,8 +8557,10 @@ }, { "BriefDescription": "Remote VNA Credits; Level < 5", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.LT5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Remote vna credit level is less than 5; para= llel ad/bl arb on vna not possible", "UMask": "0x10", @@ -6992,8 +8568,10 @@ }, { "BriefDescription": "Remote VNA Credits; Used", + "Counter": "0,1,2", "EventCode": "0x5B", "EventName": "UNC_M3UPI_RxC_VNA_CRD.USED", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of remote vna credits consumed per cy= cle", "UMask": "0x1", @@ -7001,8 +8579,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x1", @@ -7010,8 +8590,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x10", @@ -7019,8 +8601,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x4", @@ -7028,8 +8612,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB4", "EventName": "UNC_M3UPI_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, because a mess= age from the other queue has higher priority", "UMask": "0x40", @@ -7037,8 +8623,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -7046,8 +8634,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -7055,8 +8645,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x2", @@ -7064,8 +8656,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -7073,8 +8667,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -7082,8 +8678,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB2", "EventName": "UNC_M3UPI_RxR_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the CMS Ingress", "UMask": "0x8", @@ -7091,8 +8689,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x1", @@ -7100,8 +8700,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x10", @@ -7109,8 +8711,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x2", @@ -7118,8 +8722,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x4", @@ -7127,8 +8733,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x40", @@ -7136,8 +8744,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IFV - Credit= ", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x80", @@ -7145,8 +8755,10 @@ }, { "BriefDescription": "Transgress Injection Starvation; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB3", "EventName": "UNC_M3UPI_RxR_CRD_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cycles under injection starvation mod= e. This starvation is triggered when the CMS Ingress cannot send a transac= tion onto the mesh for a long period of time. In this case, the Ingress is= unable to forward to the Egress due to a lack of credit.", "UMask": "0x8", @@ -7154,8 +8766,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -7163,8 +8777,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -7172,8 +8788,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -7181,8 +8799,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -7190,8 +8810,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -7199,8 +8821,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB1", "EventName": "UNC_M3UPI_RxR_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the CMS Ingress = The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -7208,8 +8832,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x1", @@ -7217,8 +8843,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AD - Credit", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x10", @@ -7226,8 +8854,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x2", @@ -7235,8 +8865,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x4", @@ -7244,8 +8876,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; BL - Credit", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x40", @@ -7253,8 +8887,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0xB0", "EventName": "UNC_M3UPI_RxR_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Ingress buffers in t= he CMS The Ingress is used to queue up requests received from the mesh", "UMask": "0x8", @@ -7262,8 +8898,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7271,8 +8909,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7280,8 +8920,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7289,8 +8931,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7298,8 +8942,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7307,8 +8953,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD0", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7316,8 +8964,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7325,8 +8975,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7334,8 +8986,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7343,8 +8997,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7352,8 +9008,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7361,8 +9019,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD2", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7370,8 +9030,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7379,8 +9041,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7388,8 +9052,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7397,8 +9063,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7406,8 +9074,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7415,8 +9085,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD4", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 0 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7424,8 +9096,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 0", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7433,8 +9107,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 1", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7442,8 +9118,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 2", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7451,8 +9129,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 3", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7460,8 +9140,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 4", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7469,8 +9151,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits; For= Transgress 5", + "Counter": "0,1,2", "EventCode": "0xD6", "EventName": "UNC_M3UPI_STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Agent 1 Egress Buffe= r is stalled waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7478,8 +9162,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x1", @@ -7487,8 +9173,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x4", @@ -7496,8 +9184,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x2", @@ -7505,8 +9195,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x8", @@ -7514,8 +9206,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x10", @@ -7523,8 +9217,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x40", @@ -7532,8 +9228,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x20", @@ -7541,8 +9239,10 @@ }, { "BriefDescription": "Failed ARB for AD; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x30", "EventName": "UNC_M3UPI_TxC_AD_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD arb but no win; arb request asserted but = not won", "UMask": "0x80", @@ -7550,8 +9250,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x1", @@ -7559,8 +9261,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x2", @@ -7568,8 +9272,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.AD_SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x4", @@ -7577,8 +9283,10 @@ }, { "BriefDescription": "AD FlowQ Bypass", + "Counter": "0,1,2", "EventCode": "0x2C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_BYPASS.BL_EARLY_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts cases when the AD flowQ is bypassed (= S0, S1 and S2 indicate which slot was bypassed with S0 having the highest p= riority and S2 the least)", "UMask": "0x8", @@ -7586,8 +9294,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x1", @@ -7595,8 +9305,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x4", @@ -7604,8 +9316,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x2", @@ -7613,8 +9327,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x8", @@ -7622,8 +9338,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x10", @@ -7631,8 +9349,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x40", @@ -7640,8 +9360,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x20", @@ -7649,8 +9371,10 @@ }, { "BriefDescription": "AD Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x27", "EventName": "UNC_M3UPI_TxC_AD_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the AD Egress queue is Not = Empty", "UMask": "0x80", @@ -7658,8 +9382,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x1", @@ -7667,8 +9393,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x4", @@ -7676,8 +9404,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x2", @@ -7685,8 +9415,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x8", @@ -7694,8 +9426,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x10", @@ -7703,8 +9437,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x40", @@ -7712,8 +9448,10 @@ }, { "BriefDescription": "AD Flow Q Inserts; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x2D", "EventName": "UNC_M3UPI_TxC_AD_FLQ_INSERTS.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x20", @@ -7721,64 +9459,80 @@ }, { "BriefDescription": "AD Flow Q Occupancy; VN0 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN0 WB Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 REQ Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "AD Flow Q Occupancy; VN1 SNP Messages", + "Counter": "0", "EventCode": "0x1C", "EventName": "UNC_M3UPI_TxC_AD_FLQ_OCCUPANCY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Number of Snoop Targets; CHA on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_CHA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to CHA", "UMask": "0x4", @@ -7786,8 +9540,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn0 Snpf", "UMask": "0x40", @@ -7795,8 +9551,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI0", "UMask": "0x1", @@ -7804,8 +9562,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN0", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN0 Snpf = to peer UPI1", "UMask": "0x2", @@ -7813,8 +9573,10 @@ }, { "BriefDescription": "Number of Snoop Targets; CHA on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_CHA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to CHA", "UMask": "0x20", @@ -7822,8 +9584,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Non Idle cycles on V= N1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of non-idle = cycles in issuing Vn1 Snpf", "UMask": "0x80", @@ -7831,8 +9595,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI0 on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI0", "UMask": "0x8", @@ -7840,8 +9606,10 @@ }, { "BriefDescription": "Number of Snoop Targets; Peer UPI1 on VN1", + "Counter": "0", "EventCode": "0x3C", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of snpfanout targets and non-idle cyc= les can be used to calculate average snpfanout latency; Number of VN1 Snpf = to peer UPI1", "UMask": "0x10", @@ -7849,8 +9617,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn0", "UMask": "0x1", @@ -7858,8 +9628,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n0 SnpF issued when SnpF pending on Vn1", "UMask": "0x4", @@ -7867,8 +9639,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ t= xn issued when SnpF pending on Vn1", "UMask": "0x2", @@ -7876,8 +9650,10 @@ }, { "BriefDescription": "Snoop Arbitration; FlowQ SnpF Won", + "Counter": "0,1,2", "EventCode": "0x3D", "EventName": "UNC_M3UPI_TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outcome of SnpF pending arbitration; FlowQ V= n1 SnpF issued when SnpF pending on Vn0", "UMask": "0x8", @@ -7885,8 +9661,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x1", @@ -7894,8 +9672,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x2", @@ -7903,8 +9683,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x8", @@ -7912,8 +9694,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x10", @@ -7921,8 +9705,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x20", @@ -7930,8 +9716,10 @@ }, { "BriefDescription": "Speculative ARB for AD - Credit Available; = VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x34", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request with prior cycle = credit check complete and credit avail", "UMask": "0x80", @@ -7939,8 +9727,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 RE= Q Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x1", @@ -7948,8 +9738,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 SN= P Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x2", @@ -7957,8 +9749,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x8", @@ -7966,8 +9760,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 RE= Q Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x10", @@ -7975,8 +9771,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 SN= P Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x20", @@ -7984,8 +9782,10 @@ }, { "BriefDescription": "Speculative ARB for AD - New Message; VN1 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x33", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x80", @@ -7993,8 +9793,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 REQ = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x1", @@ -8002,8 +9804,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 RSP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x4", @@ -8011,8 +9815,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 SNP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x2", @@ -8020,8 +9826,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN0 WB M= essages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x8", @@ -8029,8 +9837,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 REQ = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x10", @@ -8038,8 +9848,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 RSP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x40", @@ -8047,8 +9859,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 SNP = Messages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", @@ -8056,8 +9870,10 @@ }, { "BriefDescription": "Speculative ARB for AD - No Credit; VN1 WB M= essages", + "Counter": "0,1,2", "EventCode": "0x32", "EventName": "UNC_M3UPI_TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AD speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x80", @@ -8065,22 +9881,28 @@ }, { "BriefDescription": "AK Flow Q Inserts", + "Counter": "0,1,2", "EventCode": "0x2F", "EventName": "UNC_M3UPI_TxC_AK_FLQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "AK Flow Q Occupancy", + "Counter": "0", "EventCode": "0x1E", "EventName": "UNC_M3UPI_TxC_AK_FLQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M3UPI" }, { "BriefDescription": "Failed ARB for BL; VN0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x4", @@ -8088,8 +9910,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x8", @@ -8097,8 +9921,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x1", @@ -8106,8 +9932,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x2", @@ -8115,8 +9943,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x40", @@ -8124,8 +9954,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x80", @@ -8133,8 +9965,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x10", @@ -8142,8 +9976,10 @@ }, { "BriefDescription": "Failed ARB for BL; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x35", "EventName": "UNC_M3UPI_TxC_BL_ARB_FAIL.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL arb but no win; arb request asserted but = not won", "UMask": "0x20", @@ -8151,8 +9987,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x1", @@ -8160,8 +9998,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x4", @@ -8169,8 +10009,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x2", @@ -8178,8 +10020,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x8", @@ -8187,8 +10031,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x10", @@ -8196,8 +10042,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x40", @@ -8205,8 +10053,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x20", @@ -8214,8 +10064,10 @@ }, { "BriefDescription": "BL Flow Q Not Empty; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x28", "EventName": "UNC_M3UPI_TxC_BL_FLQ_CYCLES_NE.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the BL Egress queue is Not = Empty", "UMask": "0x80", @@ -8223,8 +10075,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x1", @@ -8232,8 +10086,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x2", @@ -8241,8 +10097,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x8", @@ -8250,8 +10108,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x4", @@ -8259,8 +10119,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x10", @@ -8268,8 +10130,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x20", @@ -8277,8 +10141,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1_NCB Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x80", @@ -8286,8 +10152,10 @@ }, { "BriefDescription": "BL Flow Q Inserts; VN1_NCS Messages", + "Counter": "0,1,2", "EventCode": "0x2E", "EventName": "UNC_M3UPI_TxC_BL_FLQ_INSERTS.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of allocations into the QP= I FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accum= ulator event in order to calculate average queue latency. Only a single Fl= owQ queue can be tracked at any given time. It is not possible to filter b= ased on direction or polarity.", "UMask": "0x40", @@ -8295,72 +10163,90 @@ }, { "BriefDescription": "BL Flow Q Occupancy; VN0 NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN0 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1_NCS Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1_NCB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1 RSP Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M3UPI" }, { "BriefDescription": "BL Flow Q Occupancy; VN1 WB Messages", + "Counter": "0", "EventCode": "0x1D", "EventName": "UNC_M3UPI_TxC_BL_FLQ_OCCUPANCY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M3UPI" }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x2", @@ -8368,8 +10254,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 NC= S Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x8", @@ -8377,8 +10265,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN0 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x1", @@ -8386,8 +10276,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 WB= Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x20", @@ -8395,8 +10287,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 NC= B Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x80", @@ -8404,8 +10298,10 @@ }, { "BriefDescription": "Speculative ARB for BL - New Message; VN1 RS= P Messages", + "Counter": "0,1,2", "EventCode": "0x38", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request due to new messag= e arriving on a specific channel (MC/VN)", "UMask": "0x10", @@ -8413,8 +10309,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x4", @@ -8422,8 +10320,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x8", @@ -8431,8 +10331,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x1", @@ -8440,8 +10342,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 0 WB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x2", @@ -8449,8 +10353,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCS Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x40", @@ -8458,8 +10364,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 NCB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x80", @@ -8467,8 +10375,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x10", @@ -8476,8 +10386,10 @@ }, { "BriefDescription": "Speculative ARB for AD Failed - No Credit; VN= 1 WB Messages", + "Counter": "0,1,2", "EventCode": "0x37", "EventName": "UNC_M3UPI_TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "BL speculative arb request asserted due to n= o other channel being active (have a valid entry but don't have credits to = send)", "UMask": "0x20", @@ -8485,8 +10397,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8494,8 +10408,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8503,8 +10419,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8512,8 +10430,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8521,8 +10441,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x9D", "EventName": "UNC_M3UPI_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Horizontal Anti-= Deadlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8530,8 +10452,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8539,8 +10463,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8548,8 +10474,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8557,8 +10485,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8566,8 +10496,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8575,8 +10507,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x9F", "EventName": "UNC_M3UPI_TxR_HORZ_BYPASS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Horizontal E= gress, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -8584,8 +10518,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8593,8 +10529,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= D - Credit", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8602,8 +10540,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; A= K - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8611,8 +10551,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8620,8 +10562,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; B= L - Credit", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8629,8 +10573,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full; I= V - Bounce", + "Counter": "0,1,2", "EventCode": "0x96", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_FULL.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Full. The egress is used to queue up requests destined for t= he Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8638,8 +10584,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8647,8 +10595,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8656,8 +10606,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8665,8 +10617,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8674,8 +10628,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8683,8 +10639,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x97", "EventName": "UNC_M3UPI_TxR_HORZ_CYCLES_NE.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles the Transgress buffers in the Common = Mesh Stop are Not-Empty. The egress is used to queue up requests destined = for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8692,8 +10650,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8701,8 +10661,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8710,8 +10672,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8719,8 +10683,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8728,8 +10694,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8737,8 +10705,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x95", "EventName": "UNC_M3UPI_TxR_HORZ_INSERTS.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Transgress bu= ffers in the Common Mesh Stop The egress is used to queue up requests dest= ined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8746,8 +10716,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x1", @@ -8755,8 +10727,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x20", @@ -8764,8 +10738,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x2", @@ -8773,8 +10749,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x4", @@ -8782,8 +10760,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x40", @@ -8791,8 +10771,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x99", "EventName": "UNC_M3UPI_TxR_HORZ_NACK.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Horizontal Ring", "UMask": "0x8", @@ -8800,8 +10782,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -8809,8 +10793,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AD - Credit", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x10", @@ -8818,8 +10804,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; AK - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8827,8 +10815,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -8836,8 +10826,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; BL - Credit", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x40", @@ -8845,8 +10837,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy; IV - Bounce", + "Counter": "0,1,2", "EventCode": "0x94", "EventName": "UNC_M3UPI_TxR_HORZ_OCCUPANCY.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Transgress buffers i= n the Common Mesh Stop The egress is used to queue up requests destined fo= r the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8854,8 +10848,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= D - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AD_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x1", @@ -8863,8 +10859,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; A= K - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.AK_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x2", @@ -8872,8 +10870,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; B= L - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.BL_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x4", @@ -8881,8 +10881,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation; I= V - Bounce", + "Counter": "0,1,2", "EventCode": "0x9B", "EventName": "UNC_M3UPI_TxR_HORZ_STARVED.IV_BNC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Transgress buffer cannot send a transaction ont= o the Horizontal ring for a long period of time.", "UMask": "0x8", @@ -8890,8 +10892,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8899,8 +10903,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8908,8 +10914,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8917,8 +10925,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -8926,8 +10936,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8935,8 +10947,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9C", "EventName": "UNC_M3UPI_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets using the Vertical Anti-De= adlock Slot, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8944,8 +10958,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x1", @@ -8953,8 +10969,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x10", @@ -8962,8 +10980,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x2", @@ -8971,8 +10991,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x20", @@ -8980,8 +11002,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x4", @@ -8989,8 +11013,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x40", @@ -8998,8 +11024,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used; IV", + "Counter": "0,1,2", "EventCode": "0x9E", "EventName": "UNC_M3UPI_TxR_VERT_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of packets bypassing the Vertical Egr= ess, broken down by ring type and CMS Agent.", "UMask": "0x8", @@ -9007,8 +11035,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= D ring. Some example include outbound requests, snoop requests, and snoop = responses.", "UMask": "0x1", @@ -9016,8 +11046,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AD = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= D ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9025,8 +11057,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the A= K ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9034,8 +11068,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; AK = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the A= K ring.", "UMask": "0x20", @@ -9043,8 +11079,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the B= L ring. This is commonly used to send data from the cache to various desti= nations.", "UMask": "0x4", @@ -9052,8 +11090,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; BL = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 1 destined for the B= L ring. This is commonly used for transferring writeback data to the cache= .", "UMask": "0x40", @@ -9061,8 +11101,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full; IV", + "Counter": "0,1,2", "EventCode": "0x92", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Full. The Egress is used to queue up requests destined for the Ve= rtical Ring on the Mesh.; Ring transactions from Agent 0 destined for the I= V ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9070,8 +11112,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AD ring. Some example include outbound requests, snoop requests, and snoop= responses.", "UMask": "0x1", @@ -9079,8 +11123,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9088,8 +11134,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9097,8 +11145,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = AK ring.", "UMask": "0x20", @@ -9106,8 +11156,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = BL ring. This is commonly used to send data from the cache to various dest= inations.", "UMask": "0x4", @@ -9115,8 +11167,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 1 destined for the = BL ring. This is commonly used for transferring writeback data to the cach= e.", "UMask": "0x40", @@ -9124,8 +11178,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= ; IV", + "Counter": "0,1,2", "EventCode": "0x93", "EventName": "UNC_M3UPI_TxR_VERT_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles the Common Mesh Stop Egress= was Not Empty. The Egress is used to queue up requests destined for the V= ertical Ring on the Mesh.; Ring transactions from Agent 0 destined for the = IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9133,8 +11189,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AD r= ing. Some example include outbound requests, snoop requests, and snoop res= ponses.", "UMask": "0x1", @@ -9142,8 +11200,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AD r= ing. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9151,8 +11211,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the AK r= ing. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9160,8 +11222,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the AK r= ing.", "UMask": "0x20", @@ -9169,8 +11233,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the BL r= ing. This is commonly used to send data from the cache to various destinat= ions.", "UMask": "0x4", @@ -9178,8 +11244,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 1 destined for the BL r= ing. This is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -9187,8 +11255,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations; IV", + "Counter": "0,1,2", "EventCode": "0x91", "EventName": "UNC_M3UPI_TxR_VERT_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the Common Mesh S= top Egress. The Egress is used to queue up requests destined for the Verti= cal Ring on the Mesh.; Ring transactions from Agent 0 destined for the IV r= ing. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9196,8 +11266,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x1", @@ -9205,8 +11277,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x10", @@ -9214,8 +11288,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x2", @@ -9223,8 +11299,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x20", @@ -9232,8 +11310,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x4", @@ -9241,8 +11321,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x40", @@ -9250,8 +11332,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs; IV", + "Counter": "0,1,2", "EventCode": "0x98", "EventName": "UNC_M3UPI_TxR_VERT_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts number of Egress packets NACK'ed on t= o the Vertical Ring", "UMask": "0x8", @@ -9259,8 +11343,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AD ring. Some example include outbound requests, snoop requests, and sn= oop responses.", "UMask": "0x1", @@ -9268,8 +11354,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AD - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AD ring. This is commonly used for outbound requests.", "UMask": "0x10", @@ -9277,8 +11365,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he AK ring. This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -9286,8 +11376,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; AK - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he AK ring.", "UMask": "0x20", @@ -9295,8 +11387,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 0", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he BL ring. This is commonly used to send data from the cache to various d= estinations.", "UMask": "0x4", @@ -9304,8 +11398,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; BL - Agent 1", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 1 destined for t= he BL ring. This is commonly used for transferring writeback data to the c= ache.", "UMask": "0x40", @@ -9313,8 +11409,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy; IV", + "Counter": "0,1,2", "EventCode": "0x90", "EventName": "UNC_M3UPI_TxR_VERT_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Occupancy event for the Egress buffers in th= e Common Mesh Stop The egress is used to queue up requests destined for th= e Vertical Ring on the Mesh.; Ring transactions from Agent 0 destined for t= he IV ring. This is commonly used for snoops to the cores.", "UMask": "0x8", @@ -9322,8 +11420,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x1", @@ -9331,8 +11431,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AD = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x10", @@ -9340,8 +11442,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x2", @@ -9349,8 +11453,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; AK = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x20", @@ -9358,8 +11464,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 0", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x4", @@ -9367,8 +11475,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; BL = - Agent 1", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x40", @@ -9376,8 +11486,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation; IV", + "Counter": "0,1,2", "EventCode": "0x9A", "EventName": "UNC_M3UPI_TxR_VERT_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts injection starvation. This starvatio= n is triggered when the CMS Egress cannot send a transaction onto the Verti= cal ring for a long period of time.", "UMask": "0x8", @@ -9385,8 +11497,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x2", @@ -9394,8 +11508,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x8", @@ -9403,8 +11519,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x4", @@ -9412,8 +11530,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x10", @@ -9421,8 +11541,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x40", @@ -9430,8 +11552,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x20", @@ -9439,8 +11563,10 @@ }, { "BriefDescription": "UPI0 AD Credits Empty; VNA", + "Counter": "0,1,2", "EventCode": "0x20", "EventName": "UNC_M3UPI_UPI_PEER_AD_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPIs on the = AD Ring", "UMask": "0x1", @@ -9448,8 +11574,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x4", @@ -9457,8 +11585,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x2", @@ -9466,8 +11596,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN0 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN0_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x8", @@ -9475,8 +11607,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 RSP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x20", @@ -9484,8 +11618,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 REQ Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x10", @@ -9493,8 +11629,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VN1 SNP Messages", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VN1_WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x40", @@ -9502,8 +11640,10 @@ }, { "BriefDescription": "UPI0 BL Credits Empty; VNA", + "Counter": "0,1,2", "EventCode": "0x21", "EventName": "UNC_M3UPI_UPI_PEER_BL_CREDITS_EMPTY.VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No credits available to send to UPI on the B= L Ring (diff between non-SMI and SMI mode)", "UMask": "0x1", @@ -9511,6 +11651,7 @@ }, { "BriefDescription": "Prefetches generated by the flow control queu= e of the M3UPI unit.", + "Counter": "0,1,2", "EventCode": "0x29", "EventName": "UNC_M3UPI_UPI_PREFETCH_SPAWN", "PerPkg": "1", @@ -9519,8 +11660,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -9528,8 +11671,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -9537,8 +11682,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -9546,8 +11693,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xA6", "EventName": "UNC_M3UPI_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AD ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. We really have two rings -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -9555,8 +11704,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x4", @@ -9564,8 +11715,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x8", @@ -9573,8 +11726,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x1", @@ -9582,8 +11737,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xA8", "EventName": "UNC_M3UPI_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l AK ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings in -- a clock= wise ring and a counter-clockwise ring. On the left side of the ring, the = UP direction is on the clockwise ring and DN is on the counter-clockwise ri= ng. On the right side of the ring, this is reversed. The first half of th= e CBos are on the left side of the ring, and the 2nd half are on the right = side of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD = is NOT the same ring as CBo 2 UP AD because they are on opposite sides of t= he ring.", "UMask": "0x2", @@ -9591,8 +11748,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Even", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x4", @@ -9600,8 +11759,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Down and Odd", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x8", @@ -9609,8 +11770,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Even", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x1", @@ -9618,8 +11781,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use; Up and Odd", + "Counter": "0,1,2", "EventCode": "0xAA", "EventName": "UNC_M3UPI_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l BL ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop.We really have two rings -- a clockwi= se ring and a counter-clockwise ring. On the left side of the ring, the UP= direction is on the clockwise ring and DN is on the counter-clockwise ring= . On the right side of the ring, this is reversed. The first half of the = CBos are on the left side of the ring, and the 2nd half are on the right si= de of the ring. In other words (for example), in a 4c part, Cbo 0 UP AD is= NOT the same ring as CBo 2 UP AD because they are on opposite sides of the= ring.", "UMask": "0x2", @@ -9627,8 +11792,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Down", + "Counter": "0,1,2", "EventCode": "0xAC", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x4", @@ -9636,8 +11803,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use; Up", + "Counter": "0,1,2", "EventCode": "0xAC", "EventName": "UNC_M3UPI_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Vertica= l IV ring is being used at this ring stop. This includes when packets are = passing by and when packets are being sunk, but does not include when packe= ts are being sent from the ring stop. There is only 1 IV ring. Therefore,= if one wants to monitor the Even ring, they should select both UP_EVEN and= DN_EVEN. To monitor the Odd ring, they should select both UP_ODD and DN_O= DD.", "UMask": "0x1", @@ -9645,8 +11814,10 @@ }, { "BriefDescription": "VN0 Credit Used; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Data Response (WB) messages on BL. WB is generally used to tran= smit data with coherency. For example, remote reads and writes, or cache t= o cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9654,8 +11825,10 @@ }, { "BriefDescription": "VN0 Credit Used; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally u= sed to transmit data without coherency. For example, non-coherent read dat= a returns.", "UMask": "0x20", @@ -9663,8 +11836,10 @@ }, { "BriefDescription": "VN0 Credit Used; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Home (REQ) messages on AD. REQ is generally used to send reques= ts, request responses, and snoop responses.", "UMask": "0x1", @@ -9672,8 +11847,10 @@ }, { "BriefDescription": "VN0 Credit Used; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on AD. RSP packets are used to transmit= a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9681,8 +11858,10 @@ }, { "BriefDescription": "VN0 Credit Used; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9690,8 +11869,10 @@ }, { "BriefDescription": "VN0 Credit Used; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5C", "EventName": "UNC_M3UPI_VN0_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN0 credit was used on the= DRS message channel. In order for a request to be transferred across UPI,= it must be guaranteed to have a flit buffer on the remote socket to sink i= nto. There are two credit pools, VNA and VN0. VNA is a shared pool used t= o achieve high performance. The VN0 pool has reserved entries for each mes= sage class and is used to prevent deadlock. Requests first attempt to acqu= ire a VNA credit, and then fall back to VN0 if they fail. This counts the = number of times a VN0 credit was used. Note that a single VN0 credit holds= access to potentially multiple flit buffers. For example, a transfer that= uses VNA could use 9 flit buffers and in that case uses 9 credits. A tran= sfer on VN0 will only count a single credit even though it may use multiple= buffers.; Response (RSP) messages on BL. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9699,8 +11880,10 @@ }, { "BriefDescription": "VN0 No Credits; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -9708,8 +11891,10 @@ }, { "BriefDescription": "VN0 No Credits; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -9717,8 +11902,10 @@ }, { "BriefDescription": "VN0 No Credits; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -9726,8 +11913,10 @@ }, { "BriefDescription": "VN0 No Credits; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9735,8 +11924,10 @@ }, { "BriefDescription": "VN0 No Credits; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9744,8 +11935,10 @@ }, { "BriefDescription": "VN0 No Credits; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5E", "EventName": "UNC_M3UPI_VN0_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN0 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9753,8 +11946,10 @@ }, { "BriefDescription": "VN1 Credit Used; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Data Response (WB) messages on BL. WB is generally used to trans= mit data with coherency. For example, remote reads and writes, or cache to= cache transfers will transmit their data using WB.", "UMask": "0x10", @@ -9762,8 +11957,10 @@ }, { "BriefDescription": "VN1 Credit Used; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Non-Coherent Broadcast (NCB) messages on BL. NCB is generally us= ed to transmit data without coherency. For example, non-coherent read data= returns.", "UMask": "0x20", @@ -9771,8 +11968,10 @@ }, { "BriefDescription": "VN1 Credit Used; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Home (REQ) messages on AD. REQ is generally used to send request= s, request responses, and snoop responses.", "UMask": "0x1", @@ -9780,8 +11979,10 @@ }, { "BriefDescription": "VN1 Credit Used; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on AD. RSP packets are used to transmit = a variety of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9789,8 +11990,10 @@ }, { "BriefDescription": "VN1 Credit Used; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9798,8 +12001,10 @@ }, { "BriefDescription": "VN1 Credit Used; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5D", "EventName": "UNC_M3UPI_VN1_CREDITS_USED.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times a VN1 credit was used on the= WB message channel. In order for a request to be transferred across QPI, = it must be guaranteed to have a flit buffer on the remote socket to sink in= to. There are two credit pools, VNA and VN1. VNA is a shared pool used to= achieve high performance. The VN1 pool has reserved entries for each mess= age class and is used to prevent deadlock. Requests first attempt to acqui= re a VNA credit, and then fall back to VN1 if they fail. This counts the n= umber of times a VN1 credit was used. Note that a single VN1 credit holds = access to potentially multiple flit buffers. For example, a transfer that = uses VNA could use 9 flit buffers and in that case uses 9 credits. A trans= fer on VN1 will only count a single credit even though it may use multiple = buffers.; Response (RSP) messages on BL. RSP packets are used to transmit a= variety of protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9807,8 +12012,10 @@ }, { "BriefDescription": "VN1 No Credits; WB on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Data Response (WB) messages on BL. WB is generally used to transmit data w= ith coherency. For example, remote reads and writes, or cache to cache tra= nsfers will transmit their data using WB.", "UMask": "0x10", @@ -9816,8 +12023,10 @@ }, { "BriefDescription": "VN1 No Credits; NCB on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Non-Coherent Broadcast (NCB) messages on BL. NCB is generally used to tran= smit data without coherency. For example, non-coherent read data returns.", "UMask": "0x20", @@ -9825,8 +12034,10 @@ }, { "BriefDescription": "VN1 No Credits; REQ on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Home (REQ) messages on AD. REQ is generally used to send requests, request= responses, and snoop responses.", "UMask": "0x1", @@ -9834,8 +12045,10 @@ }, { "BriefDescription": "VN1 No Credits; RSP on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on AD. RSP packets are used to transmit a variety = of protocol flits including grants and completions (CMP).", "UMask": "0x4", @@ -9843,8 +12056,10 @@ }, { "BriefDescription": "VN1 No Credits; SNP on AD", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Snoops (SNP) messages on AD. SNP is used for outgoing snoops.", "UMask": "0x2", @@ -9852,8 +12067,10 @@ }, { "BriefDescription": "VN1 No Credits; RSP on BL", + "Counter": "0,1,2", "EventCode": "0x5F", "EventName": "UNC_M3UPI_VN1_NO_CREDITS.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of Cycles there were no VN1 Credits; = Response (RSP) messages on BL. RSP packets are used to transmit a variety o= f protocol flits including grants and completions (CMP).", "UMask": "0x8", @@ -9861,15 +12078,18 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_M2M_TxC_BL.DRS_UPI", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x40", "EventName": "UNC_NoUnit_TxC_BL.DRS_UPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Clocks of the Intel(R) Ultra Path Interconnec= t (UPI)", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_UPI_CLOCKTICKS", "PerPkg": "1", @@ -9878,6 +12098,7 @@ }, { "BriefDescription": "Data Response packets that go direct to core", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2C", "PerPkg": "1", @@ -9887,6 +12108,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_DIRECT_ATTEMPTS.D2U", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2K", @@ -9896,6 +12118,7 @@ }, { "BriefDescription": "Data Response packets that go direct to Intel= (R) UPI", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_UPI_DIRECT_ATTEMPTS.D2U", "PerPkg": "1", @@ -9905,70 +12128,87 @@ }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AD_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.AK_VNA_EQ3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_UPI_FLOWQ_NO_VNA_CRD.BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "Cycles Intel(R) UPI is in L1 power mode (shut= down)", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_UPI_L1_POWER_CYCLES", "PerPkg": "1", @@ -9977,164 +12217,205 @@ }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_UPI_M3_BYP_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_UPI_M3_CRD_RETURN_BLOCKED", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.BGF_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THR= ESH", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_UPI_M3_RXQ_BLOCKED.GV_BLOCK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "Cycles where phy is not in L0, L0c, L0p, L1", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_UPI_PHY_INIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "L1 Req Nack", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_UPI_POWER_L1_NACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqNAck. When the UPI links would like to change power state, t= he Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wi= th an Ack, the power mode will change. If it replies with NAck, no change = will take place. This can be filtered based on Rx and Tx. An Rx LinkReqNA= ck refers to receiving an NAck (meaning this agent's Tx originally requeste= d the power change). A Tx LinkReqNAck refers to sending this command (mean= ing the peer agent's Tx originally requested the power change and this agen= t accepted it).", "Unit": "UPI" }, { "BriefDescription": "L1 Req (same as L1 Ack).", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_UPI_POWER_L1_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a link sends/rece= ives a LinkReqAck. When the UPI links would like to change power state, th= e Tx side initiates a request to the Rx side requesting to change states. = This requests can either be accepted or denied. If the Rx side replies wit= h an Ack, the power mode will change. If it replies with NAck, no change w= ill take place. This can be filtered based on Rx and Tx. An Rx LinkReqAck= refers to receiving an Ack (meaning this agent's Tx originally requested t= he power change). A Tx LinkReqAck refers to sending this command (meaning = the peer agent's Tx originally requested the power change and this agent ac= cepted it).", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.ACK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_UPI_REQ_SLOT2_FROM_M3.VNA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "Cycles the Rx of the Intel(R) UPI is in L0p p= ower mode", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_UPI_RxL0P_POWER_CYCLES", "PerPkg": "1", @@ -10143,16 +12424,20 @@ }, { "BriefDescription": "Cycles in L0. Receive side.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_UPI_RxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0xe", @@ -10160,8 +12445,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0x10e", @@ -10169,8 +12456,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0xf", @@ -10178,8 +12467,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Non-Co= herent Standard", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0x10f", @@ -10187,8 +12478,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQ Message Class", "UMask": "0x8", @@ -10196,8 +12489,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Reques= t Opcode", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", "UMask": "0x108", @@ -10205,24 +12500,30 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xc", @@ -10230,8 +12531,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10c", @@ -10239,8 +12542,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0xa", @@ -10248,8 +12553,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Respon= se - No Data", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0x10a", @@ -10257,8 +12564,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Snoop", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "SNP Message Class", "UMask": "0x9", @@ -10266,8 +12575,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Snoop = Opcode", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", "UMask": "0x109", @@ -10275,8 +12586,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xd", @@ -10284,8 +12597,10 @@ }, { "BriefDescription": "Matches on Receive path of a UPI Port; Writeb= ack", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10d", @@ -10293,6 +12608,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT0", "PerPkg": "1", @@ -10302,6 +12618,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT1", "PerPkg": "1", @@ -10311,6 +12628,7 @@ }, { "BriefDescription": "FLITs received which bypassed the Slot0 Recei= ve Buffer", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "UNC_UPI_RxL_BYPASSED.SLOT2", "PerPkg": "1", @@ -10320,46 +12638,57 @@ }, { "BriefDescription": "CRC Errors Detected", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "UNC_UPI_RxL_CRC_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of CRC errors detected in the UPI Age= nt. Each UPI flit incorporates 8 bits of CRC for error detection. This co= unts the number of flits where the CRC was able to detect an error. After = an error has been detected, the UPI agent will send a request to the transm= itting socket to resend the flit (as well as any flits that came after it).= ", "Unit": "UPI" }, { "BriefDescription": "LLR Requests Sent", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_UPI_RxL_CRC_LLR_REQ_TRANSMIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of LLR Requests were transmitted. Th= is should generally be <=3D the number of CRC errors detected. If multiple= errors are detected before the Rx side receives a LLC_REQ_ACK from the Tx = side, there is no need to send more LLR_REQ_NACKs.", "Unit": "UPI" }, { "BriefDescription": "VN0 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN0 c= redit was consumed (i.e. message uses a VN0 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "VN1 Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x3A", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VN1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VN1 c= redit was consumed (i.e. message uses a VN1 credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "VNA Credit Consumed", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_UPI_RxL_CREDITS_CONSUMED_VNA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that an RxQ VNA c= redit was consumed (i.e. message uses a VNA credit for the Rx Buffer). Thi= s includes packets that went through the RxQ and those that were bypasssed.= ", "Unit": "UPI" }, { "BriefDescription": "Valid data FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -10369,6 +12698,7 @@ }, { "BriefDescription": "Null FLITs received from any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -10378,8 +12708,10 @@ }, { "BriefDescription": "Valid Flits Received; Data", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Data Flits (which consume all slots), but how much to count= is based on Slot0-2 mask, so count can be 0-3 depending on which slots are= enabled for counting..", "UMask": "0x8", @@ -10387,8 +12719,10 @@ }, { "BriefDescription": "Valid Flits Received; Idle", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.IDLE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).", "UMask": "0x47", @@ -10396,8 +12730,10 @@ }, { "BriefDescription": "Valid Flits Received; LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", "UMask": "0x10", @@ -10405,8 +12741,10 @@ }, { "BriefDescription": "Valid Flits Received; LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", "UMask": "0x40", @@ -10414,6 +12752,7 @@ }, { "BriefDescription": "Protocol header and credit FLITs received fro= m any slot", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.NON_DATA", "PerPkg": "1", @@ -10423,6 +12762,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.NULL", @@ -10432,8 +12772,10 @@ }, { "BriefDescription": "Valid Flits Received; Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", "UMask": "0x80", @@ -10441,17 +12783,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.PROT_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Received; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", "UMask": "0x1", @@ -10459,8 +12805,10 @@ }, { "BriefDescription": "Valid Flits Received; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", "UMask": "0x2", @@ -10468,8 +12816,10 @@ }, { "BriefDescription": "Valid Flits Received; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_UPI_RxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", "UMask": "0x4", @@ -10477,62 +12827,76 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.RSP", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_RxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x5", "EventName": "UNC_UPI_RxL_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "UPI" }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x1", @@ -10540,8 +12904,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x2", @@ -10549,8 +12915,10 @@ }, { "BriefDescription": "RxQ Flit Buffer Allocations; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_UPI_RxL_INSERTS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Rx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = RxQ and pass directly to the ring interface. If things back up getting tra= nsmitted onto the ring, however, it may need to allocate into this buffer, = thus increasing the latency. This event can be used in conjunction with th= e Flit Buffer Occupancy event in order to calculate the average flit buffer= lifetime.", "UMask": "0x4", @@ -10558,8 +12926,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x1", @@ -10567,8 +12937,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x2", @@ -10576,8 +12948,10 @@ }, { "BriefDescription": "RxQ Occupancy - All Packets; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_UPI_RxL_OCCUPANCY.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of elements in the UP= I RxQ in each cycle. Generally, when data is transmitted across UPI, it wi= ll bypass the RxQ and pass directly to the ring interface. If things back = up getting transmitted onto the ring, however, it may need to allocate into= this buffer, thus increasing the latency. This event can be used in conju= nction with the Flit Buffer Not Empty event to calculate average occupancy,= or with the Flit Buffer Allocations event to track average lifetime.", "UMask": "0x4", @@ -10585,118 +12959,147 @@ }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S0_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S1_RXQ2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_UPI_RxL_SLOT_BYPASS.S2_RXQ1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.CFG_CTL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.DFX", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_BYPASS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.RXQ_CRED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.SPARE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_UPI_TxL0P_CLK_ACTIVE.TXQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UPI" }, { "BriefDescription": "Cycles in which the Tx of the Intel(R) Ultra = Path Interconnect (UPI) is in L0p power mode", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES", "PerPkg": "1", @@ -10705,30 +13108,38 @@ }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_LL_ENTER", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Counter": "0,1,2,3", "EventCode": "0x29", "EventName": "UNC_UPI_TxL0P_POWER_CYCLES_M3_EXIT", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "Cycles in L0. Transmit side.", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "UNC_UPI_TxL0_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of UPI qfclk cycles spent in L0 power= mode in the Link Layer. L0 is the default mode which provides the highest= performance with the most power. Use edge detect to count the number of i= nstances that the link entered L0. Link power states are per link and per = direction, so for example the Tx direction could be in one state while Rx w= as in another. The phy layer sometimes leaves L0 for training, which will= not be captured by this event.", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0xe", @@ -10736,8 +13147,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Bypass", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCB", "UMask": "0x10e", @@ -10745,8 +13158,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0xf", @@ -10754,8 +13169,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Non-C= oherent Standard", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.NCS_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - NCS", "UMask": "0x10f", @@ -10763,8 +13180,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "REQ Message Class", "UMask": "0x8", @@ -10772,8 +13191,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Reque= st Opcode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.REQ_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match REQ Opcodes - Specified in Umask[7:4]", "UMask": "0x108", @@ -10781,24 +13202,30 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPCNFLT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1aa", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Invalid", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12a", "Unit": "UPI" }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xc", @@ -10806,8 +13233,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10c", @@ -10815,8 +13244,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0xa", @@ -10824,8 +13255,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Respo= nse - No Data", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class - RSP", "UMask": "0x10a", @@ -10833,8 +13266,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= ", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "SNP Message Class", "UMask": "0x9", @@ -10842,8 +13277,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Snoop= Opcode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.SNP_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match SNP Opcodes - Specified in Umask[7:4]", "UMask": "0x109", @@ -10851,8 +13288,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0xd", @@ -10860,8 +13299,10 @@ }, { "BriefDescription": "Matches on Transmit path of a UPI Port; Write= back", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_BASIC_HDR_MATCH.WB_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Match Message Class -WB", "UMask": "0x10d", @@ -10869,6 +13310,7 @@ }, { "BriefDescription": "FLITs that bypassed the TxL Buffer", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_UPI_TxL_BYPASSED", "PerPkg": "1", @@ -10877,6 +13319,7 @@ }, { "BriefDescription": "Valid data FLITs transmitted via any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_DATA", "PerPkg": "1", @@ -10886,6 +13329,7 @@ }, { "BriefDescription": "Null FLITs transmitted from any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.ALL_NULL", "PerPkg": "1", @@ -10895,6 +13339,7 @@ }, { "BriefDescription": "Valid Flits Sent; Data", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.DATA", "PerPkg": "1", @@ -10904,6 +13349,7 @@ }, { "BriefDescription": "Idle FLITs transmitted", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.IDLE", "PerPkg": "1", @@ -10913,8 +13359,10 @@ }, { "BriefDescription": "Valid Flits Sent; LLCRD Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.LLCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables counting of LLCRD (with non-zero payload). This only appl= ies to slot 2 since LLCRD is only allowed in slot 2", "UMask": "0x10", @@ -10922,8 +13370,10 @@ }, { "BriefDescription": "Valid Flits Sent; LLCTRL", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.LLCTRL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Equivalent to an idle packet. Enables counting of slot 0 LLCTRL = messages.", "UMask": "0x40", @@ -10931,6 +13381,7 @@ }, { "BriefDescription": "Protocol header and credit FLITs transmitted = across any slot", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.NON_DATA", "PerPkg": "1", @@ -10940,6 +13391,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.ALL_NULL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.NULL", @@ -10949,8 +13401,10 @@ }, { "BriefDescription": "Valid Flits Sent; Protocol Header", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.PROTHDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Enables count of protocol headers in slot 0,1,2 (depending on slo= t uMask bits)", "UMask": "0x80", @@ -10958,17 +13412,21 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_FLITS.PROTHDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.PROT_HDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UPI" }, { "BriefDescription": "Valid Flits Sent; Slot 0", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 0 - Other mask bits determine types of headers to coun= t.", "UMask": "0x1", @@ -10976,8 +13434,10 @@ }, { "BriefDescription": "Valid Flits Sent; Slot 1", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 1 - Other mask bits determine types of headers to coun= t.", "UMask": "0x2", @@ -10985,8 +13445,10 @@ }, { "BriefDescription": "Valid Flits Sent; Slot 2", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_UPI_TxL_FLITS.SLOT2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Shows legal flit time (hides impact of L0p a= nd L0c).; Count Slot 2 - Other mask bits determine types of headers to coun= t.", "UMask": "0x4", @@ -10994,157 +13456,195 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.DATA_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.DUAL_SLOT_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.LOC", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.NCS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.NON_DATA_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.REM", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.REQ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_DATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_DATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.RSP_NODATA", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.RSP_NODATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.SGL_SLOT_HDR", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.SNP", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "UPI" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_UPI_TxL_BASIC_HDR_MATCH.WB", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x4", "EventName": "UNC_UPI_TxL_HDR_MATCH.WB", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Allocations", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_UPI_TxL_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of allocations into the UPI Tx Flit B= uffer. Generally, when data is transmitted across UPI, it will bypass the = TxQ and pass directly to the link. However, the TxQ will be used with L0p = and when LLR occurs, increasing latency to transfer out to the link. This = event can be used in conjunction with the Flit Buffer Occupancy event in or= der to calculate the average flit buffer lifetime.", "Unit": "UPI" }, { "BriefDescription": "Tx Flit Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_UPI_TxL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Accumulates the number of flits in the TxQ. = Generally, when data is transmitted across UPI, it will bypass the TxQ and= pass directly to the link. However, the TxQ will be used with L0p and whe= n LLR occurs, increasing latency to transfer out to the link. This can be u= sed with the cycles not empty event to track average occupancy, or the allo= cations event to track average lifetime in the TxQ.", "Unit": "UPI" }, { "BriefDescription": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_BLOCKED_VN01", + "Experimental": "1", "PerPkg": "1", "Unit": "UPI" }, { "BriefDescription": "VNA Credits Pending Return - Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_UPI_VNA_CREDIT_RETURN_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of VNA credits in the Rx side that ar= e waitng to be returned back across the link.", "Unit": "UPI" }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "Unit": "UBOX" }, { "BriefDescription": "Message Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x8", @@ -11152,8 +13652,10 @@ }, { "BriefDescription": "Message Received", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x10", @@ -11161,8 +13663,10 @@ }, { "BriefDescription": "Message Received; IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Inter Processor Interrupts", "UMask": "0x4", @@ -11170,8 +13674,10 @@ }, { "BriefDescription": "Message Received; MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.; Message Signaled Interrupts - interrupts sent by devi= ces (including PCIe via IOxAPIC) (Socket Mode only)", "UMask": "0x2", @@ -11179,8 +13685,10 @@ }, { "BriefDescription": "Message Received; VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Virtual Logical Wire (legacy) message were r= eceived from Uncore.", "UMask": "0x1", @@ -11188,16 +13696,20 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of times an IDI Lock/SplitLock sequen= ce was started", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack; Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PHOLD cycles.", "UMask": "0x1", @@ -11205,38 +13717,47 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number outstanding register requests within = message channel tracker", "Unit": "UBOX" }, { "BriefDescription": "UPI interconnect send bandwidth for payload. = Derived from unc_upi_txl_flits.all_data", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UPI_DATA_BANDWIDTH_TX", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json b/tools= /perf/pmu-events/arch/x86/skylakex/uncore-io.json index 743c91f3d2f0..bce46dd4f395 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_READ", "FCMask": "0x07", @@ -16,6 +17,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_WRITE", "FCMask": "0x07", @@ -31,6 +33,7 @@ }, { "BriefDescription": "Clockticks of the IIO Traffic Controller", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -39,6 +42,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", "FCMask": "0x4", @@ -49,6 +53,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", "FCMask": "0x4", @@ -59,6 +64,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", "FCMask": "0x4", @@ -69,6 +75,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", "FCMask": "0x4", @@ -79,6 +86,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", "FCMask": "0x4", @@ -89,8 +97,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 0", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x01", @@ -99,8 +109,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 1", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x02", @@ -109,8 +121,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 2", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x04", @@ -119,8 +133,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts; Port 3", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.PORT3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x08", @@ -129,6 +145,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0-3", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -138,6 +155,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 0", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", "FCMask": "0x04", @@ -147,6 +165,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 1", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", "FCMask": "0x04", @@ -156,6 +175,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 2", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", "FCMask": "0x04", @@ -165,6 +185,7 @@ }, { "BriefDescription": "PCIe Completion Buffer occupancy of completio= ns with data: Part 3", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", "FCMask": "0x04", @@ -174,8 +195,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -185,8 +208,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -196,8 +221,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -207,8 +234,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -218,8 +247,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -229,8 +260,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -240,8 +273,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -251,8 +286,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -262,8 +299,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -273,8 +312,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -284,8 +325,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -295,8 +338,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -306,8 +351,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -317,8 +364,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -328,8 +377,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -339,8 +390,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -350,8 +403,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -361,8 +416,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -372,8 +429,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -383,8 +442,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -394,8 +455,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -405,8 +468,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -416,8 +481,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -427,8 +494,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -438,6 +507,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part0", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -449,6 +519,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part1", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -460,6 +531,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part2", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -471,6 +543,7 @@ }, { "BriefDescription": "Read request for 4 bytes made by the CPU to I= IO Part3", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -482,8 +555,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -493,8 +568,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core reading from = Card's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -504,6 +581,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part0 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -515,6 +593,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part1 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -526,6 +605,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part2 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -537,6 +617,7 @@ }, { "BriefDescription": "Write request of 4 bytes made to IIO Part3 by= the CPU", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -548,8 +629,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -559,8 +642,10 @@ }, { "BriefDescription": "Data requested by the CPU; Core writing to Ca= rd's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -570,6 +655,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part0", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -581,6 +667,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part1", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -592,6 +679,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part2", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -603,6 +691,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= a different IIO unit to IIO Part3", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -614,8 +703,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -625,8 +716,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -636,6 +729,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part0 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -647,6 +741,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part1 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -658,6 +753,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part2 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -669,6 +765,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made to= IIO Part3 by a different IIO unit", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -680,8 +777,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -691,8 +790,10 @@ }, { "BriefDescription": "Data requested by the CPU; Another card (diff= erent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -702,8 +803,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -713,8 +816,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -724,8 +829,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -735,8 +842,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -746,8 +855,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -757,8 +868,10 @@ }, { "BriefDescription": "Data requested of the CPU; Atomic requests ta= rgeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -768,8 +881,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -779,8 +894,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -790,8 +907,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -801,8 +920,10 @@ }, { "BriefDescription": "Data requested of the CPU; Completion of atom= ic requests targeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -812,6 +933,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -823,6 +945,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -834,6 +957,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -845,6 +969,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -856,8 +981,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -867,8 +994,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -878,6 +1007,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -889,6 +1019,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -900,6 +1031,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -911,6 +1043,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -922,8 +1055,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -933,8 +1068,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to DR= AM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -944,8 +1081,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -955,8 +1094,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -966,8 +1107,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -977,8 +1120,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -988,8 +1133,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -999,8 +1146,10 @@ }, { "BriefDescription": "Data requested of the CPU; Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1010,6 +1159,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -1021,6 +1171,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part1 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -1032,6 +1183,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part2 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -1043,6 +1195,7 @@ }, { "BriefDescription": "Peer to peer read request for 4 bytes made by= IIO Part3 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -1054,8 +1207,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1065,8 +1220,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card reading from = another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1076,6 +1233,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -1087,6 +1245,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -1098,6 +1257,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -1109,6 +1269,7 @@ }, { "BriefDescription": "Peer to peer write request of 4 bytes made by= IIO Part0 to an IIO target", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -1120,8 +1281,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1131,8 +1294,10 @@ }, { "BriefDescription": "Data requested of the CPU; Card writing to an= other Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1142,29 +1307,37 @@ }, { "BriefDescription": "Num Link Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "UNC_IIO_LINK_NUM_CORR_ERR", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Num Link Retries", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UNC_IIO_LINK_NUM_RETRIES", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Number packets that passed the Mask/Match Fil= ter", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_IIO_MASK_MATCH", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x1", @@ -1172,8 +1345,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x8", @@ -1181,8 +1356,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x4", @@ -1190,8 +1367,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x2", @@ -1199,8 +1378,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus; !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x10", @@ -1208,8 +1389,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if all bits specified by mask match= ", "UMask": "0x20", @@ -1217,8 +1400,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x1", @@ -1226,8 +1411,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x8", @@ -1235,8 +1422,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; Non-PCIE bus and= !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x4", @@ -1244,8 +1433,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x2", @@ -1253,8 +1444,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and PCIE bus", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x10", @@ -1262,8 +1455,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus; !(Non-PCIE bus) = and !(PCIE bus)", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Asserted if any bits specified by mask match= ", "UMask": "0x20", @@ -1271,15 +1466,19 @@ }, { "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", "EventName": "UNC_IIO_NOTHING", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1288,9 +1487,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1299,9 +1500,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1310,9 +1513,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1321,9 +1526,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1332,9 +1539,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1343,9 +1552,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1354,9 +1565,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1365,9 +1578,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1376,9 +1591,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.ATOMICCMP.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1387,6 +1604,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART0", @@ -1398,6 +1616,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART1", @@ -1409,6 +1628,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART2", @@ -1420,6 +1640,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.PART3", @@ -1431,9 +1652,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1442,9 +1665,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1453,6 +1678,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART0", @@ -1464,6 +1690,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART1", @@ -1475,6 +1702,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART2", @@ -1486,6 +1714,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.PART3", @@ -1497,9 +1726,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1508,9 +1739,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1519,9 +1752,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1530,9 +1765,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1541,9 +1778,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1552,9 +1791,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1563,9 +1804,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1574,9 +1817,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.MSG.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.MSG.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1585,9 +1830,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1596,9 +1843,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1607,9 +1856,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1618,9 +1869,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1629,9 +1882,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1640,9 +1895,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1651,9 +1908,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1662,9 +1921,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1673,9 +1934,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1684,9 +1947,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1695,9 +1960,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD0", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1706,9 +1973,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.VTD1", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x83", "EventName": "UNC_IIO_PAYLOAD_BYTES_IN.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1717,9 +1986,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1728,9 +1999,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1739,9 +2012,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1750,9 +2025,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1761,9 +2038,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1772,9 +2051,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1783,9 +2064,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1794,9 +2077,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1805,9 +2090,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1816,9 +2103,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1827,9 +2116,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1838,9 +2129,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1849,9 +2142,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1860,9 +2155,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1871,9 +2168,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1882,9 +2181,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1893,9 +2194,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1904,9 +2207,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1915,9 +2220,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1926,9 +2233,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -1937,9 +2246,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -1948,9 +2259,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -1959,9 +2272,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -1970,9 +2285,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -1981,9 +2298,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -1992,9 +2311,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2003,9 +2324,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2014,9 +2337,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2025,9 +2350,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2036,9 +2363,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2047,9 +2376,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2058,9 +2389,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2069,9 +2402,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2080,9 +2415,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2091,9 +2428,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2102,9 +2441,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2113,9 +2454,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2124,9 +2467,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2135,9 +2480,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2146,9 +2493,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2157,9 +2506,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2168,9 +2519,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2179,9 +2532,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2190,9 +2545,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2201,9 +2558,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2212,9 +2571,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2223,9 +2584,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2234,9 +2597,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "2,3", "Deprecated": "1", "EventCode": "0xC0", "EventName": "UNC_IIO_PAYLOAD_BYTES_OUT.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2245,17 +2610,21 @@ }, { "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_IIO_SYMBOL_TIMES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Gen1 - increment once every 4nS, Gen2 - incr= ement once every 2nS, Gen3 - increment once every 1nS", "Unit": "IIO" }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2264,9 +2633,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2275,9 +2646,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2286,9 +2659,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2297,9 +2672,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2308,9 +2685,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2319,9 +2698,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2330,9 +2711,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2341,9 +2724,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2352,9 +2737,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2363,9 +2750,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2374,9 +2763,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2385,9 +2776,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2396,9 +2789,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2407,9 +2802,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2418,9 +2815,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2429,9 +2828,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2440,9 +2841,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2451,9 +2854,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2462,9 +2867,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2473,9 +2880,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2484,9 +2893,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2495,9 +2906,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2506,9 +2919,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2517,9 +2932,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2528,9 +2945,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2539,9 +2958,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2550,9 +2971,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.MSG.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2561,9 +2984,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2572,9 +2997,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2583,9 +3010,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2594,9 +3023,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2605,9 +3036,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2616,9 +3049,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2627,9 +3062,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2638,9 +3075,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2649,9 +3088,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2660,9 +3101,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2671,9 +3114,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2682,9 +3127,11 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_IN.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2693,9 +3140,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2704,9 +3153,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2715,9 +3166,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2726,9 +3179,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2737,9 +3192,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2748,9 +3205,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2759,9 +3218,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2770,9 +3231,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2781,9 +3244,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2792,9 +3257,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2803,9 +3270,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2814,9 +3283,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2825,9 +3296,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2836,9 +3309,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2847,9 +3322,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2858,9 +3335,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2869,9 +3348,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2880,9 +3361,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2891,9 +3374,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2902,9 +3387,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2913,9 +3400,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2924,9 +3413,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -2935,9 +3426,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -2946,9 +3439,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -2957,9 +3452,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -2968,9 +3465,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -2979,9 +3478,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -2990,9 +3491,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3001,9 +3504,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3012,9 +3517,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3023,9 +3530,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3034,9 +3543,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3045,9 +3556,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3056,9 +3569,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3067,9 +3582,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3078,9 +3595,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3089,9 +3608,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3100,9 +3621,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3111,9 +3634,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3122,9 +3647,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3133,9 +3660,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3144,9 +3673,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x1", @@ -3155,9 +3686,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x2", @@ -3166,9 +3699,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x4", @@ -3177,9 +3712,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x8", @@ -3188,9 +3725,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x10", @@ -3199,9 +3738,11 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_OUT.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x7", "PerPkg": "1", "PortMask": "0x20", @@ -3210,8 +3751,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3221,8 +3764,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3232,8 +3777,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3243,8 +3790,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3254,8 +3803,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3265,8 +3816,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3276,8 +3829,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3287,8 +3842,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3298,8 +3855,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3309,8 +3868,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3320,8 +3881,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3331,8 +3894,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3342,8 +3907,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3353,8 +3920,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3364,8 +3933,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3375,8 +3946,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3386,8 +3959,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3397,8 +3972,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3408,8 +3985,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3419,8 +3998,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3430,8 +4011,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3441,8 +4024,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3452,8 +4037,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3463,8 +4050,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3474,6 +4063,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3485,6 +4075,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3496,6 +4087,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3507,6 +4099,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by the CPU to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3518,8 +4111,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3529,8 +4124,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3540,6 +4137,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part0 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3551,6 +4149,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part1 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3562,6 +4161,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part2 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3573,6 +4173,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made to IIO Part3 by the CPU", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3584,8 +4185,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3595,8 +4198,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Cor= e writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3606,6 +4211,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part0", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -3617,6 +4223,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part1", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -3628,6 +4235,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part2", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -3639,6 +4247,7 @@ }, { "BriefDescription": "Peer to peer read request for up to a 64 byte= transaction is made by a different IIO unit to IIO Part3", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -3650,8 +4259,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3661,8 +4272,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3672,6 +4285,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part0 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -3683,6 +4297,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part1 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -3694,6 +4309,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part2 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -3705,6 +4321,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made to IIO Part3 by a different IIO unit", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -3716,8 +4333,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3727,8 +4346,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU; Ano= ther card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3738,8 +4359,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3749,8 +4372,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3760,8 +4385,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3771,8 +4398,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3782,8 +4411,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3793,8 +4424,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Ato= mic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3804,8 +4437,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3815,8 +4450,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3826,8 +4463,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3837,8 +4476,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Com= pletion of atomic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMICCMP.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3848,6 +4489,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3859,6 +4501,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3870,6 +4513,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3881,6 +4525,7 @@ }, { "BriefDescription": "Read request for up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3892,8 +4537,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3903,8 +4550,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3914,6 +4563,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part0 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3925,6 +4575,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part1 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3936,6 +4587,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part2 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3947,6 +4599,7 @@ }, { "BriefDescription": "Write request of up to a 64 byte transaction = is made by IIO Part3 to Memory", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3958,8 +4611,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3969,8 +4624,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3980,8 +4637,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3991,8 +4650,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4002,8 +4663,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4013,8 +4676,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4024,8 +4689,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4035,8 +4702,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Mes= sages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4046,6 +4715,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", "FCMask": "0x07", @@ -4057,6 +4727,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", "FCMask": "0x07", @@ -4068,6 +4739,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", "FCMask": "0x07", @@ -4079,6 +4751,7 @@ }, { "BriefDescription": "Peer to peer read request of up to a 64 byte = transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", "FCMask": "0x07", @@ -4090,8 +4763,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4101,8 +4776,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4112,6 +4789,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part0 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", "FCMask": "0x07", @@ -4123,6 +4801,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part1 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", "FCMask": "0x07", @@ -4134,6 +4813,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part2 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", "FCMask": "0x07", @@ -4145,6 +4825,7 @@ }, { "BriefDescription": "Peer to peer write request of up to a 64 byte= transaction is made by IIO Part3 to an IIO target", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", "FCMask": "0x07", @@ -4156,8 +4837,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4167,8 +4850,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU; Car= d writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.VTD1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4178,72 +4863,90 @@ }, { "BriefDescription": "VTd Access; context cache miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.CTXT_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L1 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L1_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L2 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L2_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IIO" }, { "BriefDescription": "VTd Access; L3 miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L3_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IIO" }, { "BriefDescription": "VTd Access; Vtd hit", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.L4_PAGE_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB1_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB is full", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IIO" }, { "BriefDescription": "VTd Access; TLB miss", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_VTD_ACCESS.TLB_MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IIO" }, { "BriefDescription": "VTd Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_VTD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" } diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json b/t= ools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json index 7a40aa0f1018..96cdb52f2778 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,8 +23,10 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Bypass", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", "UMask": "0x8", @@ -30,8 +34,10 @@ }, { "BriefDescription": "DRAM Activate Count; Activate due to Read", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Activate commands = sent on this channel. Activate commands are issued to open up a page on th= e DRAM devices so that it can be read or written to with a CAS. One can ca= lculate the number of Page Misses by subtracting the number of Page Miss pr= echarges from the number of Activates.", "UMask": "0x1", @@ -39,6 +45,7 @@ }, { "BriefDescription": "DRAM Page Activate commands sent due to a wri= te request", + "Counter": "0,1,2,3", "EventCode": "0x1", "EventName": "UNC_M_ACT_COUNT.WR", "PerPkg": "1", @@ -48,30 +55,37 @@ }, { "BriefDescription": "ACT command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.ACT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "CAS command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.CAS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "PRE command issued by 2 cycle bypass", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M_BYP_CMDS.PRE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "All DRAM CAS Commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -81,6 +95,7 @@ }, { "BriefDescription": "All DRAM Read CAS Commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -90,14 +105,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Read ISOCH Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "iMC" }, { "BriefDescription": "All DRAM Read CAS Commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_REG", "PerPkg": "1", @@ -107,14 +125,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in RMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_RMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iMC" }, { "BriefDescription": "DRAM Underfill Read CAS Commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", "PerPkg": "1", @@ -124,14 +145,17 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in WMM", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.RD_WMM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "All DRAM Write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -141,16 +165,20 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; R= ead CAS issued in Write ISOCH Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "iMC" }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_RMM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of Opportunistic DRA= M Write CAS commands issued on this channel while in Read-Major-Mode.", "UMask": "0x8", @@ -158,6 +186,7 @@ }, { "BriefDescription": "DRAM CAS (Column Address Strobe) Commands.; D= RAM WR_CAS (w/ and w/out auto-pre) in Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_M_CAS_COUNT.WR_WMM", "PerPkg": "1", @@ -167,6 +196,7 @@ }, { "BriefDescription": "Memory controller clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Counts clockticks of the fixed frequency clo= ck of the memory controller using one of the programmable counters.", @@ -174,23 +204,29 @@ }, { "BriefDescription": "Clockticks in the Memory Controller using a d= edicated 48-bit Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_F", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times that the precharg= e all command was sent.", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.HIGH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of refreshes issued.", "UMask": "0x4", @@ -198,8 +234,10 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_M_DRAM_REFRESH.PANIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of refreshes issued.", "UMask": "0x2", @@ -207,16 +245,20 @@ }, { "BriefDescription": "ECC Correctable Errors", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_M_ECC_CORRECTABLE_ERRORS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of ECC errors detected and= corrected by the iMC on this channel. This counter is only useful with EC= C DRAM devices. This count will increment one time for each correction reg= ardless of the number of bits corrected. The iMC can correct up to 4 bit e= rrors in independent channel mode and 8 bit errors in lockstep mode.", "Unit": "iMC" }, { "BriefDescription": "Cycles in a Major Mode; Isoch Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.ISOCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; We group these tw= o modes together so that we can use four counters to track each of the majo= r modes at one time. These major modes are used whenever there is an ISOCH= txn in the memory controller. In these mode, only ISOCH transactions are = processed.", "UMask": "0x8", @@ -224,8 +266,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Partial Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This major mode i= s used to drain starved underfill reads. Regular reads and writes are bloc= ked and only underfill reads will be processed.", "UMask": "0x4", @@ -233,8 +277,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Read Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; Read Major Mode i= s the default mode for the iMC, as reads are generally more critical to for= ward progress than writes.", "UMask": "0x1", @@ -242,8 +288,10 @@ }, { "BriefDescription": "Cycles in a Major Mode; Write Major Mode", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_M_MAJOR_MODES.WRITE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of cycles spent in a= major mode (selected by a filter) on the given channel. Major modea are = channel-wide, and not a per-rank (or dimm or bank) mode.; This mode is trig= gered when the WPQ hits high occupancy and causes writes to be higher prior= ity than reads. This can cause blips in the available read bandwidth in th= e system and temporarily increase read latencies in order to achieve better= bus utilizations and higher bandwidth.", "UMask": "0x2", @@ -251,14 +299,17 @@ }, { "BriefDescription": "Channel DLLOFF Cycles", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M_POWER_CHANNEL_DLLOFF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles when all the ranks in the c= hannel are in CKE Slow (DLLOFF) mode.", "Unit": "iMC" }, { "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100", @@ -269,8 +320,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x1", @@ -278,8 +331,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x2", @@ -287,8 +342,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x4", @@ -296,8 +353,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x8", @@ -305,8 +364,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x10", @@ -314,8 +375,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x20", @@ -323,8 +386,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x40", @@ -332,8 +397,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_POWER_CKE_CYCLES.RANK7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent in CKE ON mode. The = filter allows you to select a rank to monitor. If multiple ranks are in CK= E ON mode at one time, the counter will ONLY increment by one rather than d= oing accumulation. Multiple counters will need to be used to track multipl= e ranks simultaneously. There is no distinction between the different CKE = modes (APD, PPDS, PPDF). This can be determined based on the system progra= mming. These events should commonly be used with Invert to get the number = of cycles in power saving mode. Edge Detect is also useful here. Make sur= e that you do NOT use Invert with Edge Detect (this just confuses the syste= m and is not necessary).", "UMask": "0x80", @@ -341,21 +408,26 @@ }, { "BriefDescription": "Critical Throttle Cycles", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the iMC is = in critical thermal throttling. When this happens, all traffic is blocked.= This should be rare unless something bad is going on in the platform. Th= ere is no filtering by rank for this event.", "Unit": "iMC" }, { "BriefDescription": "UNC_M_POWER_PCU_THROTTLING", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M_POWER_PCU_THROTTLING", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Cycles Memory is in self refresh power mode", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", @@ -366,8 +438,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.; Thermal throttling is performed= per DIMM. We support 3 DIMMs per channel. This ID allows us to filter by= ID.", "UMask": "0x1", @@ -375,8 +449,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x2", @@ -384,8 +460,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x4", @@ -393,8 +471,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x8", @@ -402,8 +482,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x10", @@ -411,8 +493,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x20", @@ -420,8 +504,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x40", @@ -429,8 +515,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0; DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RANK7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles while the iMC is= being throttled by either thermal constraints or by the PCU throttling. I= t is not possible to distinguish between the two. This can be filtered by = rank. If multiple ranks are selected and are being throttled at the same t= ime, the counter will only increment by 1.", "UMask": "0x80", @@ -438,8 +526,10 @@ }, { "BriefDescription": "Read Preemption Count; Read over Read Preempt= ion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_RD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts another read.", "UMask": "0x1", @@ -447,8 +537,10 @@ }, { "BriefDescription": "Read Preemption Count; Read over Write Preemp= tion", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "UNC_M_PREEMPTION.RD_PREEMPT_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a read in the iMC= preempts another read or write. Generally reads to an open page are issue= d ahead of requests to closed pages. This improves the page hit rate of th= e system. However, high priority requests can cause pages of active reques= ts to be closed in order to get them out. This will reduce the latency of = the high-priority request at the expense of lower bandwidth and increased o= verall average latency.; Filter for when a read preempts a write.", "UMask": "0x2", @@ -456,8 +548,10 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to by= pass", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x10", @@ -465,8 +559,10 @@ }, { "BriefDescription": "DRAM Precharge commands.; Precharge due to ti= mer expiration", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_CLOSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.; Counts the number of DRAM Precharge commands sent o= n this channel as a result of the page close counter expiring. This does n= ot include implicit precharge commands sent in auto-precharge mode.", "UMask": "0x2", @@ -474,6 +570,7 @@ }, { "BriefDescription": "Pre-charges due to page misses", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", "PerPkg": "1", @@ -483,6 +580,7 @@ }, { "BriefDescription": "Pre-charge for reads", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -492,8 +590,10 @@ }, { "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", "EventCode": "0x2", "EventName": "UNC_M_PRE_COUNT.WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of DRAM Precharge commands= sent on this channel.", "UMask": "0x8", @@ -501,1390 +601,1739 @@ }, { "BriefDescription": "Read CAS issued with HIGH priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.HIGH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with LOW priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.LOW", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with MEDIUM priority", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.MED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Read CAS issued with PANIC NON ISOCH priority= (starved)", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_RD_CAS_PRIO.PANIC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M_RD_CAS_RANK0.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M_RD_CAS_RANK1.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M_RD_CAS_RANK2.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M_RD_CAS_RANK3.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M_RD_CAS_RANK4.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M_RD_CAS_RANK5.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M_RD_CAS_RANK6.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "RD_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M_RD_CAS_RANK7.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the Read Pe= nding Queue is full. When the RPQ is full, the HA will not be able to issu= e any additional read requests into the iMC. This count should be similar = count in the HA which tracks the number of cycles that the HA has no RPQ cr= edits, just somewhat smaller to account for the credit return overhead. We= generally do not expect to see RPQ become full except for potentially duri= ng Write Major Mode or while running with slow DRAM. This event only track= s non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Read Pe= nding Queue is not empty. This can then be used to calculate the average o= ccupancy (in conjunction with the Read Pending Queue Occupancy count). The= RPQ is used to schedule reads out to the memory controller and to track th= e requests. Requests allocate into the RPQ soon after they enter the memor= y controller, and need credits for an entry in this buffer before being sen= t from the HA to the iMC. They deallocate after the CAS command has been i= ssued to memory. This filter is to be used in conjunction with the occupan= cy filter so that one can correctly track the average occupancies for sched= ulable entries and scheduled requests.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS", "PerPkg": "1", @@ -1893,6 +2342,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY", "PerPkg": "1", @@ -1901,46 +2351,57 @@ }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold; Transition from WMM to RMM because of starve counter", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.LOW_THRESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.STARVE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Transition from WMM to RMM because of low thr= eshold", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "UNC_M_WMM_TO_RMM.VMSE_RETRY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the Write P= ending Queue is full. When the WPQ is full, the HA will not be able to iss= ue any additional write requests into the iMC. This count should be simila= r count in the CHA which tracks the number of cycles that the CHA has no WP= Q credits, just somewhat smaller to account for the credit return overhead.= ", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the Write P= ending Queue is not empty. This can then be used to calculate the average = queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).= The WPQ is used to schedule write out to the memory controller and to tra= ck the writes. Requests allocate into the WPQ soon after they enter the me= mory controller, and need credits for an entry in this buffer before being = sent from the CHA to the iMC. They deallocate after being issued to DRAM. = Write requests themselves are able to complete (from the perspective of th= e rest of the system) as soon they have posted to the iMC. This is not to = be confused with actually performing the write to DRAM. Therefore, the ave= rage latency for this queue is actually not useful for deconstruction inter= mediate write latencies.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS", "PerPkg": "1", @@ -1949,6 +2410,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_WPQ_OCCUPANCY", "PerPkg": "1", @@ -1957,1359 +2419,1701 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times a request hits in= the WPQ (write-pending queue). The iMC allows writes and reads to pass up= other writes to different addresses. Before a read or a write is issued, = it will first CAM the WPQ to see if there is a write pending to that addres= s. When reads hit, they are able to directly pull their data from the WPQ = instead of going to memory. Writes that hit will overwrite the existing da= ta. Partial writes that hit will not need to do underfill reads and will s= imply update their relevant sections.", "Unit": "iMC" }, { "BriefDescription": "Not getting the requested Major Mode", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_M_WRONG_MM", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 0; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M_WR_CAS_RANK0.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 1; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M_WR_CAS_RANK1.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 2; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M_WR_CAS_RANK2.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 3; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M_WR_CAS_RANK3.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 4; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "UNC_M_WR_CAS_RANK4.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 5; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "UNC_M_WR_CAS_RANK5.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 6; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBE", "EventName": "UNC_M_WR_CAS_RANK6.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; All Banks", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.ALLBANKS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 0", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK0", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 1", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 10", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK10", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 11", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK11", + "Experimental": "1", "PerPkg": "1", "UMask": "0xb", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 12", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK12", + "Experimental": "1", "PerPkg": "1", "UMask": "0xc", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 13", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK13", + "Experimental": "1", "PerPkg": "1", "UMask": "0xd", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 14", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK14", + "Experimental": "1", "PerPkg": "1", "UMask": "0xe", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 15", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK15", + "Experimental": "1", "PerPkg": "1", "UMask": "0xf", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 2", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 3", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 4", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 5", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x5", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 6", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK6", + "Experimental": "1", "PerPkg": "1", "UMask": "0x6", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 7", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK7", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 8", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK8", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank 9", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANK9", + "Experimental": "1", "PerPkg": "1", "UMask": "0x9", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 0 (Banks = 0-3)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x11", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 1 (Banks = 4-7)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x12", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 2 (Banks = 8-11)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x13", "Unit": "iMC" }, { "BriefDescription": "WR_CAS Access to Rank 7; Bank Group 3 (Banks = 12-15)", + "Counter": "0,1,2,3", "EventCode": "0xBF", "EventName": "UNC_M_WR_CAS_RANK7.BANKG3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x14", "Unit": "iMC" diff --git a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json b/to= ols/perf/pmu-events/arch/x86/skylakex/uncore-power.json index ceef46046488..809b86dde933 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/uncore-power.json @@ -1,147 +1,185 @@ [ { "BriefDescription": "pclk Cycles", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "The PCU runs off a fixed 1 GHz clock. This = event counts the number of pclk cycles measured while the counter was enabl= ed. The pclk, like the Memory Controller's dclk, counts at a constant rate= making it a good measure of actual wall time.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 0= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 1= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 2= ", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent in phase-shedding power state 3= ", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when thermal con= ditions are the upper limit on frequency. This is related to the THERMAL_T= HROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are abo= ve the thermal temperature. This event (STRONGEST_UPPER_LIMIT) is sampled = at the output of the algorithm that determines the actual frequency, while = THERMAL_THROTTLE looks at the input.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when power is th= e upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when IO P Limit = is preventing us from dropping the frequency lower. This algorithm monitor= s the needs to the IO subsystem on both local and remote sockets and will m= aintain a frequency high enough to maintain good IO BW. This is necessary = for when all the IA cores on a socket are idle but a user still would like = to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the system = is changing frequency. This can not be filtered by thread ID. One can als= o use it with the occupancy counter that monitors number of threads in C0 t= o estimate the performance impact that frequency transitions had on the sys= tem.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_MCP_PROCHOT_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "UNC_P_MCP_PROCHOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that the PCU has= triggered memory phase shedding. This is a mode that can be run in the iM= C physicals that saves power at the expense of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C0. This event can be used in conjunction with edge detect to coun= t C0 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C2E. This event can be used in conjunction with edge detect to cou= nt C2E entrances (or exits using invert). Residency events do not include = transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C3. This event can be used in conjunction with edge detect to coun= t C3 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles when the package= was in C6. This event can be used in conjunction with edge detect to coun= t C6 entrances (or exits using invert). Residency events do not include tr= ansition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State; C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0x40", @@ -149,8 +187,10 @@ }, { "BriefDescription": "Number of cores in C-State; C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0x80", @@ -158,8 +198,10 @@ }, { "BriefDescription": "Number of cores in C-State; C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "This is an occupancy event that tracks the n= umber of cores that are in the chosen C-State. It can be used by itself to= get the average number of cores in that C-state with thresholding to gener= ate histograms, or with other PCU events and occupancy triggering to captur= e other details.", "UMask": "0xc0", @@ -167,32 +209,40 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0xA", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that we are in e= xternal PROCHOT mode. This mode is triggered when a sensor off the die det= ermines that something off-die (like DRAM) is too hot and must throttle to = avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x9", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of cycles that we are in I= nternal PROCHOT mode. This mode is triggered when a sensor on the die dete= rmines that we are too hot and must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cycles spent performing core C sta= te transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" } diff --git a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json b/= tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json index 73feadaf7674..ad33fff57c03 100644 --- a/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/skylakex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause pag= e walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data loads that caused a page = walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB leve= ls, but the walk need not have completed.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a load. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data load= to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a load. EPT page walk duration are excluded in Skylake= .", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a load. EPT page walk duration are excluded in Skylak= e microarchitecture.", @@ -66,6 +74,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause pa= ge walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts demand data stores that caused a page= walk of any page size (4K/2M/4M/1G). This implies it missed in all TLB lev= els, but the walk need not have completed.", @@ -74,6 +83,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Stores that miss the DTLB (Data TLB) and hit= the STLB (2nd Level TLB).", @@ -82,6 +92,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store. EPT page walk duration are excluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 2M/4M page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data stores. This implies address translations missed in th= e DTLB and further levels of TLB. The page walk can end with or without a f= ault.", @@ -115,6 +129,7 @@ }, { "BriefDescription": "Page walk completed due to a demand data stor= e to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data stores. This implies address translations missed in the D= TLB and further levels of TLB. The page walk can end with or without a faul= t.", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for a store. EPT page walk duration are excluded in Skylak= e.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH that is busy= with a page walk for a store. EPT page walk duration are excluded in Skyla= ke microarchitecture.", @@ -131,6 +147,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a EPT (Extended Page Table) walk for any request type.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts cycles for each PMH (Page Miss Handle= r) that is busy with an EPT (Extended Page Table) walk for any request type= .", @@ -139,6 +156,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages,= includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of flushes of the big or s= mall ITLB pages. Counting include both TLB Flush (covering all sets) and TL= B Set Clear (set-specific).", @@ -147,6 +165,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page wal= ks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Counts page walks of any page size (4K/2M/4M= /1G) caused by a code fetch. This implies it missed in the ITLB and further= levels of TLB, but the walk need not have completed.", @@ -155,6 +174,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "100003", @@ -162,6 +182,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request. EPT page walk duration are e= xcluded in Skylake.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -171,6 +192,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -179,6 +201,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts completed page walks (1G page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -187,6 +210,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -195,6 +219,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -203,6 +228,7 @@ }, { "BriefDescription": "Counts 1 per cycle for each PMH that is busy = with a page walk for an instruction fetch request. EPT page walk duration a= re excluded in Skylake.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts 1 per cycle for each PMH (Page Miss H= andler) that is busy with a page walk for an instruction fetch request. EPT= page walk duration are excluded in Skylake microarchitecture.", @@ -211,6 +237,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -219,6 +246,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pg1-f201.google.com (mail-pg1-f201.google.com [209.85.215.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E37C1B583B for ; Thu, 20 Jun 2024 18:20:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Thu, 20 Jun 2024 11:20:33 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:47 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-34-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 33/37] perf vendor events: Add snowridgex counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update/remove events as per v1.23: https://github.com/intel/perfmon/commit/9debd874e1b2b0cca42b9ba2342cacaaace= 2f0ce Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/snowridgex/cache.json | 101 + .../arch/x86/snowridgex/counter.json | 47 + .../arch/x86/snowridgex/floating-point.json | 3 + .../arch/x86/snowridgex/frontend.json | 9 + .../arch/x86/snowridgex/memory.json | 40 + .../pmu-events/arch/x86/snowridgex/other.json | 61 + .../arch/x86/snowridgex/pipeline.json | 60 + .../arch/x86/snowridgex/uncore-cache.json | 1548 ++++++++++++++- .../x86/snowridgex/uncore-interconnect.json | 1403 +++++++++++++ .../arch/x86/snowridgex/uncore-io.json | 1743 +++++++++++++++++ .../arch/x86/snowridgex/uncore-memory.json | 103 + .../arch/x86/snowridgex/uncore-power.json | 51 + .../arch/x86/snowridgex/virtual-memory.json | 31 + 14 files changed, 5177 insertions(+), 25 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/snowridgex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index b5d40fa2a29f..f4adfc157197 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -31,7 +31,7 @@ GenuineIntel-6-AF,v1.04,sierraforest,core GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-55-[01234],v1.35,skylakex,core -GenuineIntel-6-86,v1.22,snowridgex,core +GenuineIntel-6-86,v1.23,snowridgex,core GenuineIntel-6-8[CD],v1.15,tigerlake,core GenuineIntel-6-2C,v5,westmereep-dp,core GenuineIntel-6-25,v4,westmereep-sp,core diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/cache.json index c6be60584522..7882dca9d5e1 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/cache.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of core requests (demand an= d L1 prefetchers) rejected by the L2 queue (L2Q) due to a full condition.", + "Counter": "0,1,2,3", "EventCode": "0x31", "EventName": "CORE_REJECT_L2Q.ANY", "PublicDescription": "Counts the number of (demand and L1 prefetch= ers) core requests rejected by the L2 queue (L2Q) due to a full or nearly f= ull condition, which likely indicates back pressure from L2Q. It also coun= ts requests that would have gone directly to the External Queue (XQ), but a= re rejected due to a full or nearly full condition, indicating back pressur= e from the IDI link. The L2Q may also reject transactions from a core to = ensure fairness between cores, or to delay a cores dirty eviction when the = address conflicts incoming external snoops. (Note that L2 prefetcher reque= sts that are dropped are not counted by this event). Counts on a per core = basis.", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of L1D cacheline (dirty) ev= ictions caused by load misses, stores, and prefetches.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "DL1.DIRTY_EVICTION", "PublicDescription": "Counts the number of L1D cacheline (dirty) e= victions caused by load misses, stores, and prefetches. Does not count evi= ctions or dirty writebacks caused by snoops. Does not count a replacement = unless a (dirty) line was written back.", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of demand and prefetch tran= sactions that the External Queue (XQ) rejects due to a full or near full co= ndition.", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "L2_REJECT_XQ.ANY", "PublicDescription": "Counts the number of demand and prefetch tra= nsactions that the External Queue (XQ) rejects due to a full or near full c= ondition which likely indicates back pressure from the IDI link. The XQ ma= y reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses= ) and WOB (L2 write-back victims).", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the total number of L2 Cache accesses.= Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.ALL", "PublicDescription": "Counts the total number of L2 Cache Accesses= , includes hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/= L2 Prefetches only. Counts on a per core basis.", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a hit. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.HIT", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a hit from a front door request only (does not include rejects = or recycles), Counts on a per core basis.", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that r= esulted in a miss. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.MISS", "PublicDescription": "Counts the number of L2 Cache accesses that = resulted in a miss from a front door request only (does not include rejects= or recycles). Counts on a per core basis.", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Counts the number of L2 Cache accesses that m= iss the L2 and get rejected. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_REQUEST.REJECTS", "PublicDescription": "Counts the number of L2 Cache accesses that = miss the L2 and get BBL reject short and long rejects (includes those coun= ted in L2_reject_XQ.any). Counts on a per core basis.", @@ -54,6 +61,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that miss in the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts the number of cacheable memory reques= ts that miss in the Last Level Cache (LLC). Requests include demand loads, = reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the= platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 = cache. Counts on a per core basis.", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of cacheable memory request= s that access the LLC. Counts on a per core basis.", + "Counter": "0,1,2,3", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "PublicDescription": "Counts the number of cacheable memory reques= ts that access the Last Level Cache (LLC). Requests include demand loads, r= eads for ownership (RFO), instruction fetches and L1 HW prefetches. If the = platform has an L3 cache, the LLC is the L3 cache, otherwise it is the L2 c= ache. Counts on a per core basis.", @@ -70,6 +79,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM o= r MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).", @@ -78,6 +88,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-D= RAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or translation lookaside buffer (TLB) miss = which hit in DRAM or MMIO (non-DRAM).", @@ -86,6 +97,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the L2 cache.", @@ -94,6 +106,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to an instruction cache or TLB miss which hit in the LLC or other co= re with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to an instruction cache or Translation Lookaside Buffer (TLB) miss = which hit in the Last Level Cache (LLC) or other core with HITE/F/M.", @@ -102,6 +115,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DR= AM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD", "SampleAfterValue": "200003", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT", "SampleAfterValue": "200003", @@ -116,6 +131,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT", "SampleAfterValue": "200003", @@ -123,6 +139,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a demand load which hit in the LLC or other core with HITE/F/M.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT", "PublicDescription": "Counts the number of cycles the core is stal= led due to a demand load which hit in the Last Level Cache (LLC) or other c= ore with HITE/F/M.", @@ -131,6 +148,7 @@ }, { "BriefDescription": "Counts the number of cycles the core is stall= ed due to a store buffer being full.", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "MEM_BOUND_STALLS.STORE_BUFFER_FULL", "SampleAfterValue": "200003", @@ -138,6 +156,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in DRAM.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT", @@ -147,6 +166,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache, in which a snoop was required and modified data was for= warded from another core or module.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.HITM", @@ -156,6 +176,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", @@ -165,6 +186,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L1 data cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", @@ -183,6 +206,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the L2 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", @@ -192,6 +216,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that h= it in the L3 cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", @@ -201,6 +226,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL", @@ -211,6 +237,7 @@ }, { "BriefDescription": "Counts the number of load uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", @@ -221,6 +248,7 @@ }, { "BriefDescription": "Counts the number of store uops retired.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.ALL_STORES", @@ -231,6 +259,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that p= erformed one or more locks.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", @@ -240,6 +269,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= were splits.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT", @@ -249,6 +279,7 @@ }, { "BriefDescription": "Counts the number of retired split load uops.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", @@ -258,6 +289,7 @@ }, { "BriefDescription": "Counts the number of retired split store uops= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", @@ -267,6 +299,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -276,6 +309,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and modified data was fo= rwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -285,6 +319,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, but no data was forwarde= d.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent, the snoop hit, and non-modified data wa= s forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -303,6 +339,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -312,6 +349,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by t= he L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -321,6 +359,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -330,6 +369,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -339,6 +379,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -348,6 +389,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -357,6 +399,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -366,6 +409,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -375,6 +419,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -384,6 +429,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -393,6 +439,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and modi= fied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -402,6 +449,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, but no d= ata was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -411,6 +459,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent, the snoop hit, and non-= modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FW= D", "MSRIndex": "0x1a6,0x1a7", @@ -420,6 +469,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -429,6 +479,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by the L3 cache where no snoop was needed to satisfy the reques= t.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -438,6 +489,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT", @@ -448,6 +500,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HITM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", @@ -458,6 +511,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_NO_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", @@ -468,6 +522,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", @@ -478,6 +533,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_MISS", @@ -488,6 +544,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_HIT.SNOOP_NOT_NEEDED", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", @@ -498,6 +555,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -507,6 +565,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and modified data was= forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -516,6 +575,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, but no data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -525,6 +585,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent, the snoop hit, and non-modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -534,6 +595,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -543,6 +605,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -552,6 +615,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -561,6 +625,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that were supplied by the = L3 cache where a snoop was sent, the snoop hit, and modified data was forwa= rded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -570,6 +635,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -579,6 +645,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -588,6 +655,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -597,6 +665,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -606,6 +675,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -615,6 +685,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -624,6 +695,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -633,6 +705,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -642,6 +715,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -651,6 +725,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -660,6 +735,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where a s= noop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -669,6 +745,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by the L3 cache where no = snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -678,6 +755,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -687,6 +765,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -696,6 +775,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, but no data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -705,6 +785,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent, the snoop hit, and non-modified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -714,6 +795,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where a snoop w= as sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -723,6 +805,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by the L3 cache where no snoop = was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -732,6 +815,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -741,6 +825,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -750,6 +835,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -759,6 +845,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -768,6 +855,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and modif= ied data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -777,6 +865,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, but no da= ta was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -786,6 +875,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent, the snoop hit, and non-m= odified data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -795,6 +885,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -804,6 +895,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by the L3 cache where no snoop was needed to satisfy the request= .", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -813,6 +905,7 @@ }, { "BriefDescription": "Counts streaming stores that were supplied by= the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -822,6 +915,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -831,6 +925,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and modified data= was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -840,6 +935,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, but no data was f= orwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_NO_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -849,6 +945,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent, the snoop hit, and non-modified = data was forwarded.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -858,6 +955,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where a snoop was sent but the snoop missed.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -867,6 +965,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by the L3 cache where no snoop was needed to satisfy the request.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_HIT.SNOOP_NOT_NEEDED", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +975,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were suppl= ied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -885,6 +985,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to instruction cache misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ICACHE", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/counter.json b/tools= /perf/pmu-events/arch/x86/snowridgex/counter.json new file mode 100644 index 000000000000..5ae30dc3c1ac --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/snowridgex/counter.json @@ -0,0 +1,47 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "3", + "CountersNumGeneric": "4" + }, + { + "Unit": "CHA", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IIO", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "IRP", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "iMC", + "CountersNumFixed": "1", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2M", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "M2PCIe", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "PCU", + "CountersNumFixed": "0", + "CountersNumGeneric": "4" + }, + { + "Unit": "UBOX", + "CountersNumFixed": 1, + "CountersNumGeneric": "2" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json = b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json index 88522244b760..79a4beba4b78 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cycles the floating poin= t divider is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.FPDIV", "PublicDescription": "Counts the number of cycles the floating poi= nt divider is busy. Does not imply a stall waiting for the divider.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of floating point operation= s retired that required microcode assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.FP_ASSIST", "PublicDescription": "Counts the number of floating point operatio= ns retired that required microcode assist, which is not a reflection of the= number of FP operations, instructions or uops.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of floating point divide uo= ps retired (x87 and SSE, including x87 sqrt).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.FPDIV", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/frontend.json index 5ba998e06592..6d131ed90242 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of BACLEARS due to al= l branch types including conditional and unconditional jumps, returns, and = indirect branches.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the total number of BACLEARS, which o= ccur when the Branch Target Buffer (BTB) prediction or lack thereof, was co= rrected by a later branch predictor in the frontend. Includes BACLEARS due= to all branch types including conditional and unconditional jumps, returns= , and indirect branches.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a condit= ional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.COND", "SampleAfterValue": "200003", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to an indir= ect branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.INDIRECT", "SampleAfterValue": "200003", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a return= branch.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.RETURN", "SampleAfterValue": "200003", @@ -30,6 +34,7 @@ }, { "BriefDescription": "Counts the number of BACLEARS due to a direct= , unconditional jump.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.UNCOND", "SampleAfterValue": "200003", @@ -37,6 +42,7 @@ }, { "BriefDescription": "Counts the number of times a decode restricti= on reduces the decode throughput due to wrong instruction length prediction= .", + "Counter": "0,1,2,3", "EventCode": "0xe9", "EventName": "DECODE_RESTRICTION.PREDECODE_WRONG", "SampleAfterValue": "200003", @@ -44,6 +50,7 @@ }, { "BriefDescription": "Counts the number of requests to the instruct= ion cache for one or more bytes of a cache line.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.ACCESSES", "PublicDescription": "Counts the total number of requests to the i= nstruction cache. The event only counts new cache line accesses, so that m= ultiple back to back fetches to the exact same cache line or byte chunk cou= nt as one. Specifically, the event counts when accesses from sequential co= de crosses the cache line boundary, or when a branch target is moved to a n= ew line or to a non-sequential byte chunk of the same line.", @@ -52,6 +59,7 @@ }, { "BriefDescription": "Counts the number of instruction cache hits.", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.HIT", "PublicDescription": "Counts the number of requests that hit in th= e instruction cache. The event only counts new cache line accesses, so tha= t multiple back to back fetches to the exact same cache line and byte chunk= count as one. Specifically, the event counts when accesses from sequentia= l code crosses the cache line boundary, or when a branch target is moved to= a new line or to a non-sequential byte chunk of the same line.", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Counts the number of instruction cache misses= .", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE.MISSES", "PublicDescription": "Counts the number of missed requests to the = instruction cache. The event only counts new cache line accesses, so that = multiple back to back fetches to the exact same cache line and byte chunk c= ount as one. Specifically, the event counts when accesses from sequential = code crosses the cache line boundary, or when a branch target is moved to a= new line or to a non-sequential byte chunk of the same line.", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json b/tools/= perf/pmu-events/arch/x86/snowridgex/memory.json index c02eb0e836ad..34306ec24e9b 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of machine clears due to me= mory ordering caused by a snoop from an external agent. Does not count inte= rnally generated machine clears such as those due to memory disambiguation.= ", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "SampleAfterValue": "20003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of misaligned load uops tha= t are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT", "PEBS": "1", @@ -16,6 +18,7 @@ }, { "BriefDescription": "Counts the number of misaligned store uops th= at are 4K page splits.", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT", "PEBS": "1", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts all code reads that were not supplied = by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -51,6 +57,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -69,6 +77,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -78,6 +87,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -87,6 +97,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -96,6 +107,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS", @@ -106,6 +118,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were not suppli= ed by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat were not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e not supplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Counts streaming stores that were not supplie= d by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were not su= pplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Counts uncached memory writes that were not s= upplied by the L3 cache.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.L3_MISS_LOCAL", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/other.json b/tools/p= erf/pmu-events/arch/x86/snowridgex/other.json index fefbc383b840..57613207f7ad 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/other.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.SELF_LOCKS", + "Counter": "0,1,2,3", "Deprecated": "1", "EdgeDetect": "1", "EventCode": "0x63", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock issued by other cores.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.BLOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock issued by other cores. Counts on a per c= ore basis.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.BLOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_OTHER_BLOCK", @@ -25,6 +28,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = BUS_LOCK.LOCK_CYCLES", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.CYCLES_SELF_BLOCK", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of unhalted cycles a core i= s blocked due to an accepted lock it issued.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "BUS_LOCK.LOCK_CYCLES", "PublicDescription": "Counts the number of unhalted cycles a core = is blocked due to an accepted lock it issued. Counts on a per core basis.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of bus locks a core issued = its self (e.g. lock to UC or Split Lock) and does not include cache locks.", + "Counter": "0,1,2,3", "EdgeDetect": "1", "EventCode": "0x63", "EventName": "BUS_LOCK.SELF_LOCKS", @@ -49,6 +55,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_DRAM_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_DRAM_HIT", @@ -57,6 +64,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_L2_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_L2_HIT", @@ -65,6 +73,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = MEM_BOUND_STALLS.LOAD_LLC_HIT", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "C0_STALLS.LOAD_LLC_HIT", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.MASKED", "PublicDescription": "Counts the number of core cycles during whic= h interrupts are masked (disabled). Increments by 1 each core cycle that EF= LAGS.IF is 0, regardless of whether interrupts are pending or not.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of core cycles during which= there are pending interrupts while interrupts are masked (disabled).", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.PENDING_AND_MASKED", "PublicDescription": "Counts the number of core cycles during whic= h there are pending interrupts while interrupts are masked (disabled). Incr= ements by 1 each core cycle that both EFLAGS.IF is 0 and an INTR is pending= (which means the APIC is telling the ROB to cause an INTR). This event doe= s not increment if EFLAGS.IF is 0 but all interrupt in the APICs Interrupt = Request Register (IRR) are inhibited by the PPR (thus either by ISRV or TPR= ) because in these cases the interrupts would be held up in the APIC and w= ould not be pended to the ROB. This event does count when an interrupt is o= nly inhibited by MOV/POP SS state machines or the STI state machine. These = extra inhibits only last for a single instructions and would not be importa= nt.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of hardware interrupts rece= ived by the processor.", + "Counter": "0,1,2,3", "EventCode": "0xcb", "EventName": "HW_INTERRUPTS.RECEIVED", "SampleAfterValue": "203", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Counts all code reads that have any type of r= esponse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -114,6 +128,7 @@ }, { "BriefDescription": "Counts all code reads that were supplied by D= RAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -123,6 +138,7 @@ }, { "BriefDescription": "Counts all code reads that have an outstandin= g request. Returns the number of cycles until the response is received (i.e= . XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.ALL_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -141,6 +158,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache and = L2 cache that have an outstanding request. Returns the number of cycles unt= il the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.COREWB_M.OUTSTANDING", "MSRIndex": "0x1a6", @@ -150,6 +168,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -159,6 +178,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -168,6 +188,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 inst= ruction cache prefetches that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -177,6 +198,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -186,6 +208,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -195,6 +218,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that we= re supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -204,6 +228,7 @@ }, { "BriefDescription": "Counts cacheable demand data reads, L1 data c= ache hardware prefetches and software prefetches (except PREFETCHW) that ha= ve an outstanding request. Returns the number of cycles until the response = is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -213,6 +238,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.ANY_RESPONSE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", @@ -223,6 +249,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.DRAM", @@ -233,6 +260,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", @@ -243,6 +271,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = OCR.DEMAND_DATA_AND_L1PF_RD.OUTSTANDING", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0XB7", "EventName": "OCR.DEMAND_DATA_RD.OUTSTANDING", @@ -253,6 +282,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have any type o= f response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +292,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +302,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that were supplied b= y DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +312,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) and s= oftware prefetches for exclusive ownership (PREFETCHW) that have an outstan= ding request. Returns the number of cycles until the response is received (= i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.DEMAND_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -289,6 +322,7 @@ }, { "BriefDescription": "Counts streaming stores which modify a full 6= 4 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.FULL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +332,7 @@ }, { "BriefDescription": "Counts L1 data cache hardware prefetches and = software prefetches (except PREFETCHW and PFRFO) that have any type of resp= onse.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +342,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +352,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -325,6 +362,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +372,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch code reads = (written to the L2 cache only) that have an outstanding request. Returns th= e number of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_CODE_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -343,6 +382,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +392,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +402,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch data reads = (written to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +412,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +422,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +432,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that were supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +442,7 @@ }, { "BriefDescription": "Counts L2 cache hardware prefetch RFOs (writt= en to the L2 cache only) that have an outstanding request. Returns the numb= er of cycles until the response is received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.HWPF_L2_RFO.OUTSTANDING", "MSRIndex": "0x1a6", @@ -406,6 +452,7 @@ }, { "BriefDescription": "Counts modified writebacks from L1 cache that= miss the L2 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L1WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +462,7 @@ }, { "BriefDescription": "Counts modified writeBacks from L2 cache that= miss the L3 cache that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.L2WB_M.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +472,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O ac= cesses, that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +482,7 @@ }, { "BriefDescription": "Counts streaming stores which modify only par= t of a 64 byte cacheline that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PARTIAL_STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +492,7 @@ }, { "BriefDescription": "Counts all hardware and software prefetches t= hat have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.PREFETCHES.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +502,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e any type of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +512,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +522,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that wer= e supplied by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +532,7 @@ }, { "BriefDescription": "Counts all data read, code read and RFO reque= sts including demands and prefetches to the core caches (L1 or L2) that hav= e an outstanding request. Returns the number of cycles until the response i= s received (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.READS_TO_CORE.OUTSTANDING", "MSRIndex": "0x1a6", @@ -487,6 +542,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +552,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have any ty= pe of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +562,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +572,7 @@ }, { "BriefDescription": "Counts uncached memory reads that were suppli= ed by DRAM.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +582,7 @@ }, { "BriefDescription": "Counts uncached memory reads that have an out= standing request. Returns the number of cycles until the response is receiv= ed (i.e. XQ to XQ latency).", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_RD.OUTSTANDING", "MSRIndex": "0x1a6", @@ -532,6 +592,7 @@ }, { "BriefDescription": "Counts uncached memory writes that have any t= ype of response.", + "Counter": "0,1,2,3", "EventCode": "0XB7", "EventName": "OCR.UC_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json b/tool= s/perf/pmu-events/arch/x86/snowridgex/pipeline.json index c483c0838e08..e4e7902c1162 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number of branch instruction= s retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts the number of near CALL branch instruc= tions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.CALL", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts the number of far branch instructions = retired, includes far jump, far call and return, and interrupt call and ret= urn.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts the number of near indirect CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.IND_CALL", "PEBS": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts the number of retired JCC (Jump on Con= ditional Code) branch instructions retired, includes both taken and not tak= en branches.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.JCC", "PEBS": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts the number of near indirect JMP and ne= ar indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts the number of near relative CALL branc= h instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.REL_CALL", "PEBS": "1", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts the number of near RET branch instruct= ions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.RETURN", "PEBS": "1", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Counts the number of taken JCC (Jump on Condi= tional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Counts the total number of mispredicted branc= h instructions retired for all branch types.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.IND_CALL", "PEBS": "1", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts the number of mispredicted JCC (Jump o= n Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.JCC", "PEBS": "1", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near indire= ct JMP and near indirect CALL branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NON_RETURN_IND", "PEBS": "1", @@ -105,6 +118,7 @@ }, { "BriefDescription": "Counts the number of mispredicted near RET br= anch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RETURN", "PEBS": "1", @@ -113,6 +127,7 @@ }, { "BriefDescription": "Counts the number of mispredicted taken JCC (= Jump on Conditional Code) branch instructions retired.", + "Counter": "0,1,2,3", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.TAKEN_JCC", "PEBS": "1", @@ -121,6 +136,7 @@ }, { "BriefDescription": "Counts the total number of BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0xe8", "EventName": "BTCLEAR.ANY", "PublicDescription": "Counts the total number of BTCLEARS which oc= curs when the Branch Target Buffer (BTB) predicts a taken branch.", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es. (Fixed event)", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.CORE", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses fixed counter 1.", "SampleAfterValue": "2000003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Counts the number of unhalted core clock cycl= es.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.CORE_P", "PublicDescription": "Counts the number of core cycles while the c= ore is not in a halt state. The core enters the halt state when it is runni= ng the HLT instruction. The core frequency may change from time to time. Fo= r this reason this event may have a changing ratio with regards to time. Th= is event uses a programmable general purpose performance counter.", @@ -142,6 +160,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", @@ -150,6 +169,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency. (Fixed event)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses fixed counter 2.", "SampleAfterValue": "2000003", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of unhalted reference clock= cycles at TSC frequency.", + "Counter": "0,1,2,3", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_TSC_P", "PublicDescription": "Counts the number of reference cycles that t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction. This event is not affected by core frequency ch= anges and increments at a fixed frequency that is also used for the Time St= amp Counter (TSC). This event uses a programmable general purpose performan= ce counter.", @@ -165,6 +186,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.ANY", @@ -172,6 +194,7 @@ }, { "BriefDescription": "Counts the number of cycles the integer divid= er is busy.", + "Counter": "0,1,2,3", "EventCode": "0xcd", "EventName": "CYCLES_DIV_BUSY.IDIV", "PublicDescription": "Counts the number of cycles the integer divi= der is busy. Does not imply a stall waiting for the divider.", @@ -180,6 +203,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed. (Fixed event)", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the total number of instructions that= retired. For instructions that consist of multiple uops, this event counts= the retirement of the last uop of the instruction. This event continues co= unting during hardware interrupts, traps, and inside interrupt handlers. Th= is event uses fixed counter 0.", @@ -188,6 +212,7 @@ }, { "BriefDescription": "Counts the total number of instructions retir= ed.", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -196,6 +221,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because it initially appears to be store forward blocked, but subseq= uently is shown not to be blocked based on 4K alias check.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.4K_ALIAS", "PEBS": "1", @@ -204,6 +230,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked for any of the following reasons: DTLB miss, address alias, store f= orward or data unknown (includes memory disambiguation blocks and ESP consu= ming load blocks).", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.ALL", "PEBS": "1", @@ -212,6 +239,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address exactly matches an older store whose data is not= ready.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DATA_UNKNOWN", "PEBS": "1", @@ -220,6 +248,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked because its address partially overlapped with an older store.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PEBS": "1", @@ -228,12 +257,14 @@ }, { "BriefDescription": "Counts the total number of machine clears for= any reason including, but not limited to, memory ordering, memory disambig= uation, SMC, and FP assist.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.ANY", "SampleAfterValue": "20003" }, { "BriefDescription": "Counts the number of machine clears due to me= mory ordering in which an internal load passes an older store within the sa= me CPU.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.DISAMBIGUATION", "SampleAfterValue": "20003", @@ -241,6 +272,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to a = page fault. Counts both I-Side and D-Side (Loads/Stores) page faults. A p= age fault occurs when either the page is not present, or an access violatio= n occurs.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.PAGE_FAULT", "SampleAfterValue": "20003", @@ -248,6 +280,7 @@ }, { "BriefDescription": "Counts the number of machine clears due to pr= ogram modifying data (self modifying code) within 1K of a recently fetched = code page.", + "Counter": "0,1,2,3", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20003", @@ -255,6 +288,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a misp= redicted jump or a machine clear.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.ALL", "PublicDescription": "Counts the total number of issue slots that = were not consumed by the backend because allocation is stalled due to a mis= predicted jump or a machine clear. Only issue slots wasted due to fast nuke= s such as memory ordering nukes are counted. Other nukes are not accounted = for. Counts all issue slots blocked during this recovery window including r= elevant microcode flows and while uops are not yet available in the instruc= tion queue (IQ) even if an FE_bound event occurs during this period. Also i= ncludes the issue slots that were consumed by the backend but were thrown a= way because they were younger than the mispredict or machine clear.", @@ -263,6 +297,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to fast nukes such as memory orde= ring and memory disambiguation machine clears.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.FASTNUKE", "SampleAfterValue": "1000003", @@ -270,6 +305,7 @@ }, { "BriefDescription": "Counts the total number of issue slots that w= ere not consumed by the backend because allocation is stalled due to a mach= ine clear (nuke) of any kind including memory ordering and memory disambigu= ation.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MACHINE_CLEARS", "SampleAfterValue": "1000003", @@ -277,6 +313,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to branch mispredicts.", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MISPREDICT", "SampleAfterValue": "1000003", @@ -284,6 +321,7 @@ }, { "BriefDescription": "This event is deprecated. Refer to new event = TOPDOWN_BAD_SPECULATION.FASTNUKE", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x73", "EventName": "TOPDOWN_BAD_SPECULATION.MONUKE", @@ -292,12 +330,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to backend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to certain allocation restriction= s.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS", "SampleAfterValue": "1000003", @@ -305,6 +345,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to memory reservation stalls in w= hich a scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -312,6 +353,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to IEC or FPC RAT stalls, which c= an be due to FIQ or IEC reservation stalls in which the integer, floating p= oint or SIMD scheduler is not able to accept uops.", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER", "SampleAfterValue": "1000003", @@ -319,6 +361,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the physical register file una= ble to accept an entry (marble stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REGISTER", "SampleAfterValue": "1000003", @@ -326,6 +369,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to the reorder buffer being full = (ROB stalls).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.REORDER_BUFFER", "SampleAfterValue": "1000003", @@ -333,6 +377,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not consumed by the backend due to scoreboards from the instructi= on queue (IQ), jump execution unit (JEU), or microcode sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.SERIALIZATION", "SampleAfterValue": "1000003", @@ -340,6 +385,7 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x74", "EventName": "TOPDOWN_BE_BOUND.STORE_BUFFER", @@ -348,12 +394,14 @@ }, { "BriefDescription": "Counts the total number of issue slots every = cycle that were not consumed by the backend due to frontend stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ALL", "SampleAfterValue": "1000003" }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BACLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_DETECT", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BACLEARS, which occurs when= the Branch Target Buffer (BTB) prediction or lack thereof, was corrected b= y a later branch predictor in the frontend. Includes BACLEARS due to all br= anch types including conditional and unconditional jumps, returns, and indi= rect branches.", @@ -362,6 +410,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to BTCLEARS.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.BRANCH_RESTEER", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to BTCLEARS, which occurs when= the Branch Target Buffer (BTB) predicts a taken branch.", @@ -370,6 +419,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to the microcode sequencer (MS)= .", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.CISC", "SampleAfterValue": "1000003", @@ -377,6 +427,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to decode stalls.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.DECODE", "SampleAfterValue": "1000003", @@ -384,6 +435,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to ITLB misses.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.ITLB", "PublicDescription": "Counts the number of issue slots every cycle= that were not delivered by the frontend due to Instruction Table Lookaside= Buffer (ITLB) misses.", @@ -392,6 +444,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to other common frontend stalls= not categorized.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.OTHER", "SampleAfterValue": "1000003", @@ -399,6 +452,7 @@ }, { "BriefDescription": "Counts the number of issue slots every cycle = that were not delivered by the frontend due to wrong predecodes.", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "TOPDOWN_FE_BOUND.PREDECODE", "SampleAfterValue": "1000003", @@ -406,6 +460,7 @@ }, { "BriefDescription": "Counts the total number of consumed retiremen= t slots.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "TOPDOWN_RETIRING.ALL", "PEBS": "1", @@ -413,6 +468,7 @@ }, { "BriefDescription": "Counts the number of uops issued by the front= end every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops issued by the fron= t end every cycle. When 4-uops are requested and only 2-uops are delivered,= the event counts 2. Uops_issued correlates to the number of ROB entries. = If uop takes 2 ROB slots it counts as 2 uops_issued.", @@ -420,6 +476,7 @@ }, { "BriefDescription": "Counts the total number of uops retired.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.ALL", "PEBS": "1", @@ -427,6 +484,7 @@ }, { "BriefDescription": "Counts the number of integer divide uops reti= red.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.IDIV", "PEBS": "1", @@ -435,6 +493,7 @@ }, { "BriefDescription": "Counts the number of uops that are from compl= ex flows issued by the micro-sequencer (MS).", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.MS", "PEBS": "1", @@ -444,6 +503,7 @@ }, { "BriefDescription": "Counts the number of x87 uops retired, includ= es those in MS flows.", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.X87", "PEBS": "1", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json index 4090e4da1bd0..7551fb91a9d7 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "MMIO reads. Derived from unc_cha_tor_inserts.= ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_READ", "Filter": "config1=3D0x40040e33", @@ -11,6 +12,7 @@ }, { "BriefDescription": "MMIO writes. Derived from unc_cha_tor_inserts= .ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.MMIO_WRITE", "Filter": "config1=3D0x40041e33", @@ -21,6 +23,7 @@ }, { "BriefDescription": "LLC misses - Uncacheable reads (from cpu) . D= erived from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_MISSES.UNCACHEABLE", "Filter": "config1=3D0x40e33", @@ -31,6 +34,7 @@ }, { "BriefDescription": "Streaming stores (full cache line). Derived f= rom unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_FULL", "Filter": "config1=3D0x41833", @@ -42,6 +46,7 @@ }, { "BriefDescription": "Streaming stores (partial cache line). Derive= d from unc_cha_tor_inserts.ia_miss", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "LLC_REFERENCES.STREAMING_PARTIAL", "Filter": "config1=3D0x41a33", @@ -53,8 +58,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -62,8 +69,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -71,8 +80,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -80,8 +91,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -89,8 +102,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -98,8 +113,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -107,8 +124,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -116,8 +135,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -125,8 +146,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -134,8 +157,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -143,8 +168,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_CHA_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -152,8 +179,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -161,8 +190,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -170,8 +201,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -179,8 +212,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -188,8 +223,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -197,8 +234,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -206,8 +245,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -215,8 +256,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -224,8 +267,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -233,8 +278,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -242,8 +289,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_CHA_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -251,8 +300,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -260,8 +311,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -269,8 +322,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -278,8 +333,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -287,8 +344,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -296,8 +355,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -305,8 +366,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -314,8 +377,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -323,8 +388,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -332,8 +399,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -341,8 +410,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_CHA_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -350,8 +421,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -359,8 +432,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -368,8 +443,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -377,8 +454,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -386,8 +465,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -395,8 +476,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -404,8 +487,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -413,8 +498,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -422,8 +509,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -431,8 +520,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -440,8 +531,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_CHA_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -449,8 +542,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -458,8 +553,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -467,8 +564,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -476,8 +575,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -485,8 +586,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -494,8 +597,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -503,8 +608,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -512,8 +619,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -521,8 +630,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -530,8 +641,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -539,8 +652,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_CHA_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -548,8 +663,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -557,8 +674,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -566,8 +685,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -575,8 +696,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -584,8 +707,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -593,8 +718,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -602,8 +729,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -611,8 +740,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -620,8 +751,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -629,8 +762,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -638,8 +773,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_CHA_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -647,8 +784,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -656,8 +795,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -665,8 +806,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -674,8 +817,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -683,8 +828,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -692,8 +839,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -701,8 +850,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -710,8 +861,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -719,8 +872,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -728,8 +883,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -737,8 +894,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_CHA_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -746,8 +905,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -755,8 +916,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -764,8 +927,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -773,8 +938,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -782,8 +949,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -791,8 +960,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -800,8 +971,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -809,8 +982,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -818,8 +993,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -827,8 +1004,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -836,8 +1015,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_CHA_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -845,8 +1026,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Intermediate bypass Taken= ", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.INTERMEDIATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Intermediate bypass Take= n : Counts the number of times when the CHA was able to bypass HA pipe on t= he way to iMC. This is a latency optimization for situations when there is= light loadings on the memory subsystem. This can be filtered by when the = bypass was taken and when it was not. : Filter for transactions that succee= ded in taking the intermediate bypass.", "UMask": "0x2", @@ -854,8 +1037,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Not Taken : Counts the n= umber of times when the CHA was able to bypass HA pipe on the way to iMC. = This is a latency optimization for situations when there is light loadings = on the memory subsystem. This can be filtered by when the bypass was taken= and when it was not. : Filter for transactions that could not take the byp= ass, and issues a read to memory. Note that transactions that did not take = the bypass but did not issue read to memory will not be counted.", "UMask": "0x4", @@ -863,8 +1048,10 @@ }, { "BriefDescription": "CHA to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x57", "EventName": "UNC_CHA_BYPASS_CHA_IMC.TAKEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Bypass : Taken : Counts the numbe= r of times when the CHA was able to bypass HA pipe on the way to iMC. This= is a latency optimization for situations when there is light loadings on t= he memory subsystem. This can be filtered by when the bypass was taken and= when it was not. : Filter for transactions that succeeded in taking the fu= ll bypass.", "UMask": "0x1", @@ -872,12 +1059,14 @@ }, { "BriefDescription": "Uncore cache clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_CHA_CLOCKTICKS", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_CHA_CMS_CLOCKTICKS", "PerPkg": "1", @@ -885,8 +1074,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Cycle with Mul= tiple Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Cycle with Mu= ltiple Snoops : Counts the number of transactions that trigger a configurab= le number of cross snoops. Cores are snooped if the transaction looks up t= he cache and determines that it is necessary based on the operation type an= d what CoreValid bits are set. For example, if 2 CV bits are set on a data= read, the cores must have the data in S state so it is not necessary to sn= oop them. However, if only 1 CV bit is set the core my have modified the d= ata. If the transaction was an RFO, it would need to invalidate the lines.= This event can be filtered based on who triggered the initial snoop(s).", "UMask": "0xf2", @@ -894,8 +1085,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Any Single Snoop", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.ANY_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Any Single Snoop = : Counts the number of transactions that trigger a configurable number of c= ross snoops. Cores are snooped if the transaction looks up the cache and d= etermines that it is necessary based on the operation type and what CoreVal= id bits are set. For example, if 2 CV bits are set on a data read, the cor= es must have the data in S state so it is not necessary to snoop them. How= ever, if only 1 CV bit is set the core my have modified the data. If the t= ransaction was an RFO, it would need to invalidate the lines. This event c= an be filtered based on who triggered the initial snoop(s).", "UMask": "0xf1", @@ -903,8 +1096,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Core Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Core Req= uests : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x42", @@ -912,8 +1107,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Core Reques= ts", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.CORE_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Core Reque= sts : Counts the number of transactions that trigger a configurable number = of cross snoops. Cores are snooped if the transaction looks up the cache a= nd determines that it is necessary based on the operation type and what Cor= eValid bits are set. For example, if 2 CV bits are set on a data read, the= cores must have the data in S state so it is not necessary to snoop them. = However, if only 1 CV bit is set the core my have modified the data. If t= he transaction was an RFO, it would need to invalidate the lines. This eve= nt can be filtered based on who triggered the initial snoop(s).", "UMask": "0x41", @@ -921,8 +1118,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple Eviction= : Counts the number of transactions that trigger a configurable number of = cross snoops. Cores are snooped if the transaction looks up the cache and = determines that it is necessary based on the operation type and what CoreVa= lid bits are set. For example, if 2 CV bits are set on a data read, the co= res must have the data in S state so it is not necessary to snoop them. Ho= wever, if only 1 CV bit is set the core my have modified the data. If the = transaction was an RFO, it would need to invalidate the lines. This event = can be filtered based on who triggered the initial snoop(s).", "UMask": "0x82", @@ -930,8 +1129,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single Eviction", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EVICT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single Eviction := Counts the number of transactions that trigger a configurable number of cr= oss snoops. Cores are snooped if the transaction looks up the cache and de= termines that it is necessary based on the operation type and what CoreVali= d bits are set. For example, if 2 CV bits are set on a data read, the core= s must have the data in S state so it is not necessary to snoop them. Howe= ver, if only 1 CV bit is set the core my have modified the data. If the tr= ansaction was an RFO, it would need to invalidate the lines. This event ca= n be filtered based on who triggered the initial snoop(s).", "UMask": "0x81", @@ -939,8 +1140,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Multiple External = Snoops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_GTONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Multiple External= Snoops : Counts the number of transactions that trigger a configurable num= ber of cross snoops. Cores are snooped if the transaction looks up the cac= he and determines that it is necessary based on the operation type and what= CoreValid bits are set. For example, if 2 CV bits are set on a data read,= the cores must have the data in S state so it is not necessary to snoop th= em. However, if only 1 CV bit is set the core my have modified the data. = If the transaction was an RFO, it would need to invalidate the lines. This= event can be filtered based on who triggered the initial snoop(s).", "UMask": "0x22", @@ -948,8 +1151,10 @@ }, { "BriefDescription": "Core Cross Snoops Issued : Single External Sn= oops", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_CHA_CORE_SNP.EXT_ONE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Core Cross Snoops Issued : Single External S= noops : Counts the number of transactions that trigger a configurable numbe= r of cross snoops. Cores are snooped if the transaction looks up the cache= and determines that it is necessary based on the operation type and what C= oreValid bits are set. For example, if 2 CV bits are set on a data read, t= he cores must have the data in S state so it is not necessary to snoop them= . However, if only 1 CV bit is set the core my have modified the data. If= the transaction was an RFO, it would need to invalidate the lines. This e= vent can be filtered based on who triggered the initial snoop(s).", "UMask": "0x21", @@ -957,104 +1162,130 @@ }, { "BriefDescription": "Counter 0 Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_CHA_COUNTER0_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counter 0 Occupancy : Since occupancy counts= can only be captured in the Cbo's 0 counter, this event allows a user to c= apture occupancy related information by filtering the Cb0 occupancy count c= aptured in Counter 0. The filtering available is found in the control reg= ister - threshold, invert and edge detect. E.g. setting threshold to 1 ca= n effectively monitor how many cycles the monitored queue has an entry.", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_SUPPRESS_NO_D2C", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_CHA_DIRECT_GO.HA_TOR_DEALLOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.EXTCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.FAST_GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.GO_PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.IDLE_DUE_SUPPRESS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.NOP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "Direct GO", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_CHA_DIRECT_GO_OPC.PULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1062,8 +1293,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1071,8 +1304,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1080,8 +1315,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1089,8 +1326,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1098,8 +1337,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_CHA_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1107,8 +1348,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1116,8 +1359,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_CHA_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1125,8 +1370,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1134,8 +1381,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1143,8 +1392,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1152,8 +1403,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_CHA_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1161,8 +1414,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1170,8 +1425,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1179,8 +1436,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1188,8 +1447,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_CHA_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1197,8 +1458,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1206,8 +1469,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1215,8 +1480,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1224,8 +1491,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_CHA_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1233,8 +1502,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1242,8 +1513,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1251,8 +1524,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1260,8 +1535,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_CHA_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1269,8 +1546,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1278,8 +1557,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_CHA_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1287,6 +1568,7 @@ }, { "BriefDescription": "Normal priority reads issued to the memory co= ntroller from the CHA", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.NORMAL", "PerPkg": "1", @@ -1296,8 +1578,10 @@ }, { "BriefDescription": "HA to iMC Reads Issued : ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x59", "EventName": "UNC_CHA_IMC_READS_COUNT.PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "HA to iMC Reads Issued : ISOCH : Count of th= e number of reads issued to any of the memory controller channels. This ca= n be filtered by the priority of the reads.", "UMask": "0x2", @@ -1305,6 +1589,7 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Full Lin= e Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL", "PerPkg": "1", @@ -1314,8 +1599,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Fu= ll Line", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.FULL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH F= ull Line : Counts the total number of full line writes issued from the HA i= nto the memory controller.", "UMask": "0x4", @@ -1323,8 +1610,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : Partial = Non-ISOCH", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : Partial= Non-ISOCH : Counts the total number of full line writes issued from the HA= into the memory controller.", "UMask": "0x2", @@ -1332,8 +1621,10 @@ }, { "BriefDescription": "CHA to iMC Full Line Writes Issued : ISOCH Pa= rtial", + "Counter": "0,1,2,3", "EventCode": "0x5B", "EventName": "UNC_CHA_IMC_WRITES_COUNT.PARTIAL_PRIORITY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA to iMC Full Line Writes Issued : ISOCH P= artial : Counts the total number of full line writes issued from the HA int= o the memory controller.", "UMask": "0x8", @@ -1341,8 +1632,10 @@ }, { "BriefDescription": "Cache and Snoop Filter Lookups; Any Request", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the number of times the LLC was acces= sed - this includes code, data, prefetches and hints coming from L2. This = has numerous filters available. Note the non-standard filtering equation. = This event will count requests that lookup the cache multiple times with m= ultiple increments. One must ALWAYS set umask bit 0 and select a state or = states to match. Otherwise, the event will count nothing. CHAFilter0[24:= 21,17] bits correspond to [FMESI] state.; Filters for any transaction origi= nating from the IPQ or IRQ. This does not include lookups originating from= the ISMQ.", "UMask": "0x1fffff", @@ -1350,25 +1643,31 @@ }, { "BriefDescription": "Cache Lookups : All Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.ANY_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Any local or remote transaction to the LLC, includi= ng prefetch.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.CODE_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bd0ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Code Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Reads : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bd0ff", @@ -1376,16 +1675,20 @@ }, { "BriefDescription": "Cache Lookups : CRd Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : CRd Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote CRd transactions to the LLC. This = includes CRd prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Code Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.CODE_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Code Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bd001", @@ -1393,23 +1696,28 @@ }, { "BriefDescription": "Cache Lookups : Local request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.COREPREF_OR_DMND_LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Local request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Any local transaction to the LLC, including prefe= tches from the Core", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_LLC_LOOKUP.DATA_READ", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1bc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache and Snoop Filter Lookups; Data Read Req= uest", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ", "PerPkg": "1", @@ -1419,25 +1727,31 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1fc1ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Data Read Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Request Filter : C= ounts the number of times the LLC was accessed - this includes code, data, = prefetches and hints coming from L2. This has numerous filters available. = Note the non-standard filtering equation. This event will count requests = that lookup the cache multiple times with multiple increments. One must AL= WAYS select a state or states (in the umask field) to match. Otherwise, th= e event will count nothing. : Read transactions.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Data Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DATA_READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Data Read Misses : Counts th= e number of times the LLC was accessed - this includes code, data, prefetch= es and hints coming from L2. This has numerous filters available. Note th= e non-standard filtering equation. This event will count requests that loo= kup the cache multiple times with multiple increments. One must ALWAYS sel= ect a state or states (in the umask field) to match. Otherwise, the event = will count nothing.", "UMask": "0x1bc101", @@ -1445,17 +1759,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.DMND_READ_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x841ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : E State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Exclusive State", "UMask": "0x20", @@ -1463,8 +1781,10 @@ }, { "BriefDescription": "Cache Lookups : F State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : F State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Forward State", "UMask": "0x80", @@ -1472,8 +1792,10 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_INV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS set umask bit = 0 and select a state or states to match. Otherwise, the event will count n= othing.", "UMask": "0x1a44ff", @@ -1481,16 +1803,20 @@ }, { "BriefDescription": "Cache Lookups : Flush or Invalidate Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.FLUSH_OR_INV_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Flush or Invalidate Filter := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : I State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : I State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Miss", "UMask": "0x1", @@ -1498,16 +1824,20 @@ }, { "BriefDescription": "Cache Lookups : Transactions homed locally Fi= lter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.LOCAL_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Transactions homed locally F= ilter : Counts the number of times the LLC was accessed - this includes cod= e, data, prefetches and hints coming from L2. This has numerous filters av= ailable. Note the non-standard filtering equation. This event will count = requests that lookup the cache multiple times with multiple increments. On= e must ALWAYS select a state or states (in the umask field) to match. Othe= rwise, the event will count nothing. : Transaction whose address resides in= the local MC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : M State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : M State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Modified State", "UMask": "0x40", @@ -1515,8 +1845,10 @@ }, { "BriefDescription": "Cache Lookups : All Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.MISS_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : All Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1fe001", @@ -1524,16 +1856,20 @@ }, { "BriefDescription": "Cache Lookups : Write Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.OTHER_REQ_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Request Filter : Count= s the number of times the LLC was accessed - this includes code, data, pref= etches and hints coming from L2. This has numerous filters available. Not= e the non-standard filtering equation. This event will count requests that= lookup the cache multiple times with multiple increments. One must ALWAYS= select a state or states (in the umask field) to match. Otherwise, the ev= ent will count nothing. : Writeback transactions to the LLC This includes = all write transactions -- both Cacheable and UC.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : Reads", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads : Counts the number of= times the LLC was accessed - this includes code, data, prefetches and hint= s coming from L2. This has numerous filters available. Note the non-stand= ard filtering equation. This event will count requests that lookup the cac= he multiple times with multiple increments. One must ALWAYS select a state= or states (in the umask field) to match. Otherwise, the event will count = nothing.", "UMask": "0x1bd9ff", @@ -1541,8 +1877,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Locally HOMed : Counts the number of times the LLC was accessed - this= includes code, data, prefetches and hints coming from L2. This has numero= us filters available. Note the non-standard filtering equation. This even= t will count requests that lookup the cache multiple times with multiple in= crements. One must ALWAYS select a state or states (in the umask field) to= match. Otherwise, the event will count nothing.", "UMask": "0x9d9ff", @@ -1550,8 +1888,10 @@ }, { "BriefDescription": "Cache Lookups : Locally Requested Reads that = are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_LOCAL_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally Requested Reads that= are Remotely HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0x11d9ff", @@ -1559,8 +1899,10 @@ }, { "BriefDescription": "Cache Lookups : Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Read Misses : Counts the num= ber of times the LLC was accessed - this includes code, data, prefetches an= d hints coming from L2. This has numerous filters available. Note the non= -standard filtering equation. This event will count requests that lookup t= he cache multiple times with multiple increments. One must ALWAYS select a= state or states (in the umask field) to match. Otherwise, the event will = count nothing.", "UMask": "0x1bd901", @@ -1568,8 +1910,10 @@ }, { "BriefDescription": "Cache Lookups : Locally HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Locally HOMed Read Misses : = Counts the number of times the LLC was accessed - this includes code, data,= prefetches and hints coming from L2. This has numerous filters available.= Note the non-standard filtering equation. This event will count requests= that lookup the cache multiple times with multiple increments. One must A= LWAYS select a state or states (in the umask field) to match. Otherwise, t= he event will count nothing.", "UMask": "0xbd901", @@ -1577,8 +1921,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely HOMed Read Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_MISS_REM_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely HOMed Read Misses := Counts the number of times the LLC was accessed - this includes code, data= , prefetches and hints coming from L2. This has numerous filters available= . Note the non-standard filtering equation. This event will count request= s that lookup the cache multiple times with multiple increments. One must = ALWAYS select a state or states (in the umask field) to match. Otherwise, = the event will count nothing.", "UMask": "0x13d901", @@ -1586,8 +1932,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely requested Read or Sn= oop Misses that are Remotely HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_OR_SNOOP_REMOTE_MISS_REM_HOM= ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely requested Read or S= noop Misses that are Remotely HOMed : Counts the number of times the LLC wa= s accessed - this includes code, data, prefetches and hints coming from L2.= This has numerous filters available. Note the non-standard filtering equ= ation. This event will count requests that lookup the cache multiple times= with multiple increments. One must ALWAYS select a state or states (in th= e umask field) to match. Otherwise, the event will count nothing.", "UMask": "0x161901", @@ -1595,8 +1943,10 @@ }, { "BriefDescription": "Cache Lookups : Remotely Requested Reads that= are Locally HOMed", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_REMOTE_LOC_HOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Remotely Requested Reads tha= t are Locally HOMed : Counts the number of times the LLC was accessed - thi= s includes code, data, prefetches and hints coming from L2. This has numer= ous filters available. Note the non-standard filtering equation. This eve= nt will count requests that lookup the cache multiple times with multiple i= ncrements. One must ALWAYS select a state or states (in the umask field) t= o match. Otherwise, the event will count nothing.", "UMask": "0xa19ff", @@ -1604,8 +1954,10 @@ }, { "BriefDescription": "Cache Lookups : Reads that Hit the Snoop Filt= er", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.READ_SF_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Reads that Hit the Snoop Fil= ter : Counts the number of times the LLC was accessed - this includes code,= data, prefetches and hints coming from L2. This has numerous filters avai= lable. Note the non-standard filtering equation. This event will count re= quests that lookup the cache multiple times with multiple increments. One = must ALWAYS select a state or states (in the umask field) to match. Otherw= ise, the event will count nothing.", "UMask": "0x1bd90e", @@ -1613,8 +1965,10 @@ }, { "BriefDescription": "Cache Lookups : RFO Requests", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Requests : Counts the nu= mber of times the LLC was accessed - this includes code, data, prefetches a= nd hints coming from L2. This has numerous filters available. Note the no= n-standard filtering equation. This event will count requests that lookup = the cache multiple times with multiple increments. One must ALWAYS set uma= sk bit 0 and select a state or states to match. Otherwise, the event will = count nothing. : Local or remote RFO transactions to the LLC. This include= s RFO prefetch.", "UMask": "0x1bc8ff", @@ -1622,16 +1976,20 @@ }, { "BriefDescription": "Cache Lookups : RFO Request Filter", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_F", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Request Filter : Counts = the number of times the LLC was accessed - this includes code, data, prefet= ches and hints coming from L2. This has numerous filters available. Note = the non-standard filtering equation. This event will count requests that l= ookup the cache multiple times with multiple increments. One must ALWAYS s= elect a state or states (in the umask field) to match. Otherwise, the even= t will count nothing. : Local or remote RFO transactions to the LLC. This = includes RFO prefetch.", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : RFO Misses", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : RFO Misses : Counts the numb= er of times the LLC was accessed - this includes code, data, prefetches and= hints coming from L2. This has numerous filters available. Note the non-= standard filtering equation. This event will count requests that lookup th= e cache multiple times with multiple increments. One must ALWAYS select a = state or states (in the umask field) to match. Otherwise, the event will c= ount nothing.", "UMask": "0x1bc801", @@ -1639,17 +1997,21 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.RFO_PREF_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x888ff", "Unit": "CHA" }, { "BriefDescription": "Cache Lookups : S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : S State : Counts the number = of times the LLC was accessed - this includes code, data, prefetches and hi= nts coming from L2. This has numerous filters available. Note the non-sta= ndard filtering equation. This event will count requests that lookup the c= ache multiple times with multiple increments. One must ALWAYS select a sta= te or states (in the umask field) to match. Otherwise, the event will coun= t nothing. : Hit Shared State", "UMask": "0x10", @@ -1657,8 +2019,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - E State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - E State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Exclusive State", "UMask": "0x4", @@ -1666,8 +2030,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - H State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_H", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - H State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit HitMe State", "UMask": "0x8", @@ -1675,8 +2041,10 @@ }, { "BriefDescription": "Cache Lookups : SnoopFilter - S State", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.SF_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : SnoopFilter - S State : Coun= ts the number of times the LLC was accessed - this includes code, data, pre= fetches and hints coming from L2. This has numerous filters available. No= te the non-standard filtering equation. This event will count requests tha= t lookup the cache multiple times with multiple increments. One must ALWAY= S select a state or states (in the umask field) to match. Otherwise, the e= vent will count nothing. : SF Hit Shared State", "UMask": "0x2", @@ -1684,8 +2052,10 @@ }, { "BriefDescription": "Cache Lookups : Filters Requests for those th= at write info into the cache", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITES_AND_OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cache Lookups : Write Requests : Counts the = number of times the LLC was accessed - this includes code, data, prefetches= and hints coming from L2. This has numerous filters available. Note the = non-standard filtering equation. This event will count requests that looku= p the cache multiple times with multiple increments. One must ALWAYS set u= mask bit 0 and select a state or states to match. Otherwise, the event wil= l count nothing. : Writeback transactions from L2 to the LLC This includes= all write transactions -- both Cacheable and UC.", "UMask": "0x1a42ff", @@ -1693,15 +2063,18 @@ }, { "BriefDescription": "This event is deprecated.", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x34", "EventName": "UNC_CHA_LLC_LOOKUP.WRITE_LOCAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x842ff", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : All Lines Victimized", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.ALL", "PerPkg": "1", @@ -1711,8 +2084,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in E state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.E_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in E state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x2", @@ -1720,8 +2095,10 @@ }, { "BriefDescription": "Lines Victimized : Local - All Lines", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - All Lines : Count= s the number of lines that were victimized on a fill. This can be filtered= by the state that the line was in.", "UMask": "0x200f", @@ -1729,8 +2106,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in E State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in E State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2002", @@ -1738,8 +2117,10 @@ }, { "BriefDescription": "Lines Victimized : Local - Lines in M State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in M State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2001", @@ -1747,16 +2128,20 @@ }, { "BriefDescription": "Lines Victimized : Local Only", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_ONLY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local Only : Counts the n= umber of lines that were victimized on a fill. This can be filtered by the= state that the line was in.", "Unit": "CHA" }, { "BriefDescription": "Lines Victimized : Local - Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.LOCAL_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Local - Lines in S State = : Counts the number of lines that were victimized on a fill. This can be f= iltered by the state that the line was in.", "UMask": "0x2004", @@ -1764,8 +2149,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in M state", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.M_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in M state : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x1", @@ -1773,8 +2160,10 @@ }, { "BriefDescription": "Lines Victimized : Lines in S State", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_CHA_LLC_VICTIMS.S_STATE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Lines Victimized : Lines in S State : Counts= the number of lines that were victimized on a fill. This can be filtered = by the state that the line was in.", "UMask": "0x4", @@ -1782,8 +2171,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Miss", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Miss : Miscellaneous= events in the Cbo.", "UMask": "0x20", @@ -1791,8 +2182,10 @@ }, { "BriefDescription": "Cbo Misc : CV0 Prefetch Victim", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.CV0_PREF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : CV0 Prefetch Victim : Miscellaneo= us events in the Cbo.", "UMask": "0x10", @@ -1800,8 +2193,10 @@ }, { "BriefDescription": "Number of times that an RFO hit in S state.", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RFO_HIT_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts when a RFO (the Read for Ownership is= sued before a write) request hit a cacheline in the S (Shared) state.", "UMask": "0x8", @@ -1809,8 +2204,10 @@ }, { "BriefDescription": "Cbo Misc : Silent Snoop Eviction", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.RSPI_WAS_FSE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Silent Snoop Eviction : Miscellan= eous events in the Cbo. : Counts the number of times when a Snoop hit in FS= E states and triggered a silent eviction. This is useful because this info= rmation is lost in the PRE encodings.", "UMask": "0x1", @@ -1818,8 +2215,10 @@ }, { "BriefDescription": "Cbo Misc : Write Combining Aliasing", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_CHA_MISC.WC_ALIASING", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cbo Misc : Write Combining Aliasing : Miscel= laneous events in the Cbo. : Counts the number of times that a USWC write (= WCIL(F)) transaction hit in the LLC in M state, triggering a WBMtoI followe= d by the USWC write. This occurs when there is WC aliasing.", "UMask": "0x2", @@ -1827,64 +2226,80 @@ }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_CHA_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ADEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.AKEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ALLRSFWAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.BLEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.FSF_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLOWSNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x4", @@ -1892,8 +2307,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_ALLWAYRSV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x10", @@ -1901,8 +2318,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_PAMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x2", @@ -1910,8 +2329,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.GOTRACK_WAYMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x8", @@ -1919,88 +2340,110 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.HACREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IDX_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IPQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ISMQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.IVEGRCREDIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.LLC_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.NOTALLOWSNOOP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_FSF_VIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.ONE_RSP_CON", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.PTL_INPIPE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x80", @@ -2008,8 +2451,10 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RMW_SETMATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "UMask": "0x1", @@ -2017,104 +2462,100 @@ }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.RRQ_SETMATCH_VICP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SETMATCHENTRYWSCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.SF_WAYS_RES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TOPA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.TORID_MATCH_GO_P", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_REQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_AD_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_NCS", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_RSP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "Pipe Rejects", - "EventCode": "0x42", - "EventName": "UNC_CHA_PIPE_REJECT.VN_BL_WB", - "PerPkg": "1", - "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", - "Unit": "CHA" - }, - { - "BriefDescription": "Pipe Rejects", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_CHA_PIPE_REJECT.WAY_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Pipe Rejects : More Miscellaneous events in = the Cbo.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC0 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 0 only.", "UMask": "0x1", @@ -2122,8 +2563,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC1 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 1 only.", "UMask": "0x2", @@ -2131,40 +2574,50 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC10 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC11 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC12 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC13 : Cou= nts the number of times when there are no credits available for sending rea= ds from the CHA into the iMC. In order to send reads into the memory contr= oller, the HA must first acquire a credit for the iMC's AD Ingress queue. := Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC2 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 2 only.", "UMask": "0x4", @@ -2172,8 +2625,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC3 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 3 only.", "UMask": "0x8", @@ -2181,8 +2636,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC4 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 4 only.", "UMask": "0x10", @@ -2190,8 +2647,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC5 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 5 only.", "UMask": "0x20", @@ -2199,8 +2658,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC6 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 6 only.", "UMask": "0x40", @@ -2208,8 +2669,10 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC7 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 7 only.", "UMask": "0x80", @@ -2217,24 +2680,30 @@ }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC8 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx READ Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_CHA_READ_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx READ Credits Empty : MC9 : Coun= ts the number of times when there are no credits available for sending read= s from the CHA into the iMC. In order to send reads into the memory contro= ller, the HA must first acquire a credit for the iMC's AD Ingress queue. : = Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "Local INVITOE requests (exclusive ownership o= f a cache line without receiving data) that miss the SF/LLC and remote INVI= TOE requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.INVITOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of requests coming f= rom a unit on this socket for exclusive ownership of a cache line without r= eceiving data (INVITOE) to the CHA.", "UMask": "0x30", @@ -2242,6 +2711,7 @@ }, { "BriefDescription": "Local read requests that miss the SF/LLC and = remote read requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.READS", "PerPkg": "1", @@ -2251,6 +2721,7 @@ }, { "BriefDescription": "Local write requests that miss the SF/LLC and= remote write requests sent to the CHA's home agent", + "Counter": "0,1,2,3", "EventCode": "0x50", "EventName": "UNC_CHA_REQUESTS.WRITES", "PerPkg": "1", @@ -2260,8 +2731,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -2269,8 +2742,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -2278,8 +2753,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -2287,8 +2764,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_CHA_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -2296,8 +2775,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -2305,8 +2786,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -2314,8 +2797,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -2323,8 +2808,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -2332,8 +2819,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_CHA_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -2341,95 +2830,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_CHA_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_CHA_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_CHA_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x1", @@ -2437,8 +2950,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : IRQ Rejected= ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.IRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : IRQ Rejecte= d : Counts number of allocations per cycle into the specified Ingress queue= .", "UMask": "0x2", @@ -2446,8 +2961,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x10", @@ -2455,8 +2972,10 @@ }, { "BriefDescription": "Ingress (from CMS) Allocations : PRQ", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_CHA_RxC_INSERTS.PRQ_REJ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Allocations : PRQ : Count= s number of allocations per cycle into the specified Ingress queue.", "UMask": "0x20", @@ -2464,8 +2983,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2473,8 +2994,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2482,8 +3005,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2491,8 +3016,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2500,8 +3027,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2509,8 +3038,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2518,8 +3049,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2527,8 +3060,10 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_CHA_RxC_IRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -2536,16 +3071,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the IRQ0 Reject counter was true", "UMask": "0x1", @@ -2553,16 +3092,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C or SF Way", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : L= LC or SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -2570,24 +3113,30 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Ingress (from CMS) Request Queue Rejects; Phy= Addr Match", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "CHA" }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -2595,16 +3144,20 @@ }, { "BriefDescription": "IRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_CHA_RxC_IRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2612,8 +3165,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2621,8 +3176,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -2630,8 +3187,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2639,8 +3198,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2648,8 +3209,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2657,8 +3220,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2666,8 +3231,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_CHA_RxC_ISMQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -2675,8 +3242,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD REQ on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2684,8 +3253,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : AD RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2693,8 +3264,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI AK Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject AK ring message", "UMask": "0x40", @@ -2702,8 +3275,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCB on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2711,8 +3286,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL NCS on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2720,8 +3297,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL RSP on VN0 : Numbe= r of times a transaction flowing through the ISMQ had to retry. Transactio= n pass through the ISMQ as responses for requests that already exist in the= Cbo. Some examples include: when data is returned or when snoop responses= come back from the cores. : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2729,8 +3308,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : BL WB on VN0 : Number= of times a transaction flowing through the ISMQ had to retry. Transaction= pass through the ISMQ as responses for requests that already exist in the = Cbo. Some examples include: when data is returned or when snoop responses = come back from the cores. : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2738,8 +3319,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_CHA_RxC_ISMQ0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 0 : Non UPI IV Request : = Number of times a transaction flowing through the ISMQ had to retry. Trans= action pass through the ISMQ as responses for requests that already exist i= n the Cbo. Some examples include: when data is returned or when snoop resp= onses come back from the cores. : Can't inject IV ring message", "UMask": "0x80", @@ -2747,8 +3330,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2756,8 +3341,10 @@ }, { "BriefDescription": "ISMQ Rejects - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_CHA_RxC_ISMQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Rejects - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2765,8 +3352,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : ANY0 : Number of time= s a transaction flowing through the ISMQ had to retry. Transaction pass th= rough the ISMQ as responses for requests that already exist in the Cbo. So= me examples include: when data is returned or when snoop responses come bac= k from the cores. : Any condition listed in the ISMQ0 Reject counter was tr= ue", "UMask": "0x1", @@ -2774,8 +3363,10 @@ }, { "BriefDescription": "ISMQ Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_CHA_RxC_ISMQ1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "ISMQ Retries - Set 1 : HA : Number of times = a transaction flowing through the ISMQ had to retry. Transaction pass thro= ugh the ISMQ as responses for requests that already exist in the Cbo. Some= examples include: when data is returned or when snoop responses come back = from the cores.", "UMask": "0x2", @@ -2783,8 +3374,10 @@ }, { "BriefDescription": "Ingress (from CMS) Occupancy : IRQ", + "Counter": "0", "EventCode": "0x11", "EventName": "UNC_CHA_RxC_OCCUPANCY.IRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Occupancy : IRQ : Counts = number of entries in the specified Ingress queue in each cycle.", "UMask": "0x1", @@ -2792,8 +3385,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD REQ on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a request", "UMask": "0x1", @@ -2801,8 +3396,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : AD RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : AD RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No AD VN0 credit for generat= ing a response", "UMask": "0x2", @@ -2810,8 +3407,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI AK Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject AK ring me= ssage", "UMask": "0x40", @@ -2819,8 +3418,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCB on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2828,8 +3429,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL NCS on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2837,8 +3440,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL RSP on VN0 : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : No BL VN0 credit for generat= ing a response", "UMask": "0x4", @@ -2846,8 +3451,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : BL WB on VN0 : Retry= Queue Inserts of Transactions that were already in another Retry Q (sub-ev= ents encode the reason for the next reject) : No BL VN0 credit for generati= ng a writeback", "UMask": "0x8", @@ -2855,8 +3462,10 @@ }, { "BriefDescription": "Other Retries - Set 0 : Non UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "UNC_CHA_RxC_OTHER0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 0 : Non UPI IV Request := Retry Queue Inserts of Transactions that were already in another Retry Q (= sub-events encode the reason for the next reject) : Can't inject IV ring me= ssage", "UMask": "0x80", @@ -2864,8 +3473,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Allow Snoop : Retry = Queue Inserts of Transactions that were already in another Retry Q (sub-eve= nts encode the reason for the next reject)", "UMask": "0x40", @@ -2873,8 +3484,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : ANY0 : Retry Queue I= nserts of Transactions that were already in another Retry Q (sub-events enc= ode the reason for the next reject) : Any condition listed in the Other0 Re= ject counter was true", "UMask": "0x1", @@ -2882,8 +3495,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : HA : Retry Queue Ins= erts of Transactions that were already in another Retry Q (sub-events encod= e the reason for the next reject)", "UMask": "0x2", @@ -2891,8 +3506,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC OR SF Way : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Way conflict with another re= quest that caused the reject", "UMask": "0x20", @@ -2900,8 +3517,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : LLC Victim : Retry Q= ueue Inserts of Transactions that were already in another Retry Q (sub-even= ts encode the reason for the next reject)", "UMask": "0x4", @@ -2909,8 +3528,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : PhyAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : PhyAddr Match : Retr= y Queue Inserts of Transactions that were already in another Retry Q (sub-e= vents encode the reason for the next reject) : Address match with an outsta= nding request that was rejected.", "UMask": "0x80", @@ -2918,8 +3539,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : SF Victim : Retry Qu= eue Inserts of Transactions that were already in another Retry Q (sub-event= s encode the reason for the next reject) : Requests did not generate Snoop = filter victim", "UMask": "0x8", @@ -2927,8 +3550,10 @@ }, { "BriefDescription": "Other Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_CHA_RxC_OTHER1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Other Retries - Set 1 : Victim : Retry Queue= Inserts of Transactions that were already in another Retry Q (sub-events e= ncode the reason for the next reject)", "UMask": "0x10", @@ -2936,8 +3561,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= REQ on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D REQ on VN0 : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -2945,8 +3572,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : AD= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : A= D RSP on VN0 : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -2954,8 +3583,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI AK Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI AK Request : Can't inject AK ring message", "UMask": "0x40", @@ -2963,8 +3594,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCB on VN0 : No BL VN0 credit for NCB", "UMask": "0x10", @@ -2972,8 +3605,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= NCS on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L NCS on VN0 : No BL VN0 credit for NCS", "UMask": "0x20", @@ -2981,8 +3616,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= RSP on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L RSP on VN0 : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -2990,8 +3627,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : BL= WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : B= L WB on VN0 : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -2999,8 +3638,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 0 : No= n UPI IV Request", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_CHA_RxC_PRQ0_REJECT.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 0 : N= on UPI IV Request : Can't inject IV ring message", "UMask": "0x80", @@ -3008,16 +3649,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Al= low Snoop", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : AN= Y0", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : A= NY0 : Any condition listed in the PRQ0 Reject counter was true", "UMask": "0x1", @@ -3025,16 +3670,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : HA= ", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.HA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C OR SF Way", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : L= LC OR SF Way : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3042,16 +3691,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : LL= C Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Ph= yAddr Match", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : P= hyAddr Match : Address match with an outstanding request that was rejected.= ", "UMask": "0x80", @@ -3059,8 +3712,10 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : SF= Victim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PRQ Requests (from CMS) Rejected - Set 1 : S= F Victim : Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3068,16 +3723,20 @@ }, { "BriefDescription": "PRQ Requests (from CMS) Rejected - Set 1 : Vi= ctim", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_CHA_RxC_PRQ1_REJECT.VICTIM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Request Queue Retries - Set 0 : AD REQ on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_REQ_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD REQ on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a request", "UMask": "0x1", @@ -3085,8 +3744,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : AD RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AD_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : AD RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No AD VN0 credit for generating a response", "UMask": "0x2", @@ -3094,8 +3755,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI AK Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.AK_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI AK R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject AK ring message", "UMask": "0x40", @@ -3103,8 +3766,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCB on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCB on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCB", "UMask": "0x10", @@ -3112,8 +3777,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL NCS on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_NCS_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL NCS on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for NCS", "UMask": "0x20", @@ -3121,8 +3788,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL RSP on VN0= ", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_RSP_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL RSP on VN= 0 : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : No BL VN0 credit for generating a response", "UMask": "0x4", @@ -3130,8 +3799,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : BL WB on VN0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.BL_WB_VN0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : BL WB on VN0= : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)= : No BL VN0 credit for generating a writeback", "UMask": "0x8", @@ -3139,8 +3810,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 0 : Non UPI IV Re= quest", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_CHA_RxC_REQ_Q0_RETRY.IV_NON_UPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 0 : Non UPI IV R= equest : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for= ISMQ) : Can't inject IV ring message", "UMask": "0x80", @@ -3148,8 +3821,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Allow Snoop", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ALLOW_SNP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Allow Snoop = : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x40", @@ -3157,8 +3832,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : ANY0", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.ANY0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : ANY0 : REQUE= STQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : Any c= ondition listed in the WBQ0 Reject counter was true", "UMask": "0x1", @@ -3166,8 +3843,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : HA", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.HA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : HA : REQUEST= Q includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x2", @@ -3175,8 +3854,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC OR SF Way= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC OR SF Wa= y : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Way conflict with another request that caused the reject", "UMask": "0x20", @@ -3184,8 +3865,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : LLC Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.LLC_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : LLC Victim := REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x4", @@ -3193,8 +3876,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : PhyAddr Match= ", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.PA_MATCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : PhyAddr Matc= h : REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ= ) : Address match with an outstanding request that was rejected.", "UMask": "0x80", @@ -3202,8 +3887,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : SF Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.SF_VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : SF Victim : = REQUESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ) : = Requests did not generate Snoop filter victim", "UMask": "0x8", @@ -3211,8 +3898,10 @@ }, { "BriefDescription": "Request Queue Retries - Set 1 : Victim", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_CHA_RxC_REQ_Q1_RETRY.VICTIM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Request Queue Retries - Set 1 : Victim : REQ= UESTQ includes: IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)", "UMask": "0x10", @@ -3220,8 +3909,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3229,8 +3920,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -3238,8 +3931,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -3247,8 +3942,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3256,8 +3953,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -3265,8 +3964,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_CHA_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -3274,8 +3975,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3283,8 +3986,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -3292,8 +3997,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -3301,8 +4008,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -3310,8 +4019,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -3319,8 +4030,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3328,8 +4041,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -3337,8 +4052,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -3346,8 +4063,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_CHA_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -3355,8 +4074,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3364,8 +4085,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -3373,8 +4096,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -3382,8 +4107,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -3391,8 +4118,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3400,8 +4129,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -3409,8 +4140,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -3418,8 +4151,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -3427,8 +4162,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_CHA_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -3436,16 +4173,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_CHA_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "CHA" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3453,8 +4194,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -3462,8 +4205,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -3471,8 +4216,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -3480,8 +4227,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -3489,8 +4238,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3498,8 +4249,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -3507,8 +4260,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -3516,8 +4271,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_CHA_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -3525,8 +4282,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3534,8 +4293,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -3543,8 +4304,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -3552,8 +4315,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -3561,8 +4326,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -3570,8 +4337,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3579,8 +4348,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -3588,8 +4359,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -3597,8 +4370,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_CHA_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -3606,6 +4381,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for E-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.E_STATE", "PerPkg": "1", @@ -3615,6 +4391,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for M-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.M_STATE", "PerPkg": "1", @@ -3624,6 +4401,7 @@ }, { "BriefDescription": "Snoop filter capacity evictions for S-state e= ntries.", + "Counter": "0,1,2,3", "EventCode": "0x3D", "EventName": "UNC_CHA_SF_EVICTION.S_STATE", "PerPkg": "1", @@ -3633,8 +4411,10 @@ }, { "BriefDescription": "Snoops Sent : All", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : All : Counts the number of sno= ops issued by the HA.", "UMask": "0x1", @@ -3642,8 +4422,10 @@ }, { "BriefDescription": "Snoops Sent : Broadcast snoops for Local Requ= ests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.BCST_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Broadcast snoops for Local Req= uests : Counts the number of snoops issued by the HA. : Counts the number o= f broadcast snoops issued by the HA responding to local requests", "UMask": "0x10", @@ -3651,8 +4433,10 @@ }, { "BriefDescription": "Snoops Sent : Directed snoops for Local Reque= sts", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.DIRECT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Directed snoops for Local Requ= ests : Counts the number of snoops issued by the HA. : Counts the number of= directed snoops issued by the HA responding to local requests", "UMask": "0x40", @@ -3660,8 +4444,10 @@ }, { "BriefDescription": "Snoops Sent : Snoops sent for Local Requests", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "UNC_CHA_SNOOPS_SENT.LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoops Sent : Snoops sent for Local Requests= : Counts the number of snoops issued by the HA. : Counts the number of bro= adcast or directed snoops issued by the HA responding to local requests", "UMask": "0x4", @@ -3669,8 +4455,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspCnflct", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPCNFLCT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspCnflct := Number of snoop responses received for a Local request : Filters for snoo= ps responses of RspConflict to local CA requests. This is returned when a = snoop finds an existing outstanding transaction in a remote caching agent w= hen it CAMs that caching agent. This triggers conflict resolution hardware= . This covers both RspCnflct and RspCnflctWbI.", "UMask": "0x40", @@ -3678,8 +4466,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspFwd : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspFwd to local CA requests. This snoop response is only poss= ible for RdCur when a snoop HITM/E in a remote caching agent and it directl= y forwards data to a requestor without changing the requestor's cache line = state.", "UMask": "0x80", @@ -3687,8 +4477,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*FWD*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPFWDWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*FWD*WB = : Number of snoop responses received for a Local request : Filters for a s= noop response of Rsp*Fwd*WB to local CA requests. This snoop response is o= nly used in 4s systems. It is used when a snoop HITM's in a remote caching= agent and it directly forwards data to a requestor, and simultaneously ret= urns data to the home to be written back to memory.", "UMask": "0x20", @@ -3696,8 +4488,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspI", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspI : Numb= er of snoop responses received for a Local request : Filters for snoops re= sponses of RspI to local CA requests. RspI is returned when the remote cac= he does not have the data, or when the remote cache silently evicts data (s= uch as when an RFO hits non-modified data).", "UMask": "0x1", @@ -3705,8 +4499,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspIFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPIFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspIFwd : N= umber of snoop responses received for a Local request : Filters for snoop = responses of RspIFwd to local CA requests. This is returned when a remote = caching agent forwards data and the requesting agent is able to acquire the= data in E or M states. This is commonly returned with RFO transactions. = It can be either a HitM or a HitFE.", "UMask": "0x4", @@ -3714,8 +4510,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspS", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspS : Numb= er of snoop responses received for a Local request : Filters for snoop res= ponses of RspS to local CA requests. RspS is returned when a remote cache = has data but is not forwarding it. It is a way to let the requesting socke= t know that it cannot allocate the data in E state. No data is sent with S= RspS.", "UMask": "0x2", @@ -3723,8 +4521,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : RspSFwd", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPSFWD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : RspSFwd : N= umber of snoop responses received for a Local request : Filters for a snoo= p response of RspSFwd to local CA requests. This is returned when a remote= caching agent forwards data but holds on to its currently copy. This is c= ommon for data and code reads that hit in a remote socket in E or F state.", "UMask": "0x8", @@ -3732,8 +4532,10 @@ }, { "BriefDescription": "Snoop Responses Received Local : Rsp*WB", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_CHA_SNOOP_RESP_LOCAL.RSPWB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Snoop Responses Received Local : Rsp*WB : Nu= mber of snoop responses received for a Local request : Filters for a snoop= response of RspIWB or RspSWB to local CA requests. This is returned when = a non-RFO request hits in M state. Data and Code Reads can return either R= spIWB or RspSWB depending on how the system has been configured. InvItoE t= ransactions will also return RspIWB because they must acquire ownership.", "UMask": "0x10", @@ -3741,56 +4543,70 @@ }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIData= M", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPDATAM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : MtoI RspIFwdM= ", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.MTOI_RSPIFWDM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : Pull Data Par= tial - Hit SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.PULLDATAPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t LLC", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITLLC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "CHA" }, { "BriefDescription": "Misc Snoop Responses Received : RspIFwdPtl Hi= t SF", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_CHA_SNOOP_RSP_MISC.RSPIFWDMPTL_HITSF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "CHA" }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3798,8 +4614,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3807,8 +4625,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3816,8 +4636,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3825,8 +4647,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3834,8 +4658,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3843,8 +4669,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3852,8 +4680,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3861,8 +4691,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3870,8 +4702,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3879,8 +4713,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3888,8 +4724,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3897,8 +4735,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3906,8 +4746,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3915,8 +4757,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3924,8 +4768,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3933,8 +4779,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3942,8 +4790,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3951,8 +4801,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3960,8 +4812,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3969,8 +4823,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3978,8 +4834,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3987,8 +4845,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3996,8 +4856,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4005,8 +4867,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4014,8 +4878,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4023,8 +4889,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4032,8 +4900,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -4041,8 +4911,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -4050,8 +4922,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -4059,8 +4933,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -4068,8 +4944,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_CHA_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -4077,8 +4955,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4086,8 +4966,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4095,8 +4977,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4104,8 +4988,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4113,8 +4999,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4122,8 +5010,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4131,8 +5021,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4140,8 +5032,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4149,8 +5043,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4158,8 +5054,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -4167,8 +5065,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -4176,8 +5076,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_CHA_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -4185,8 +5087,10 @@ }, { "BriefDescription": "TOR Inserts : All", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All : Counts the number of ent= ries successfully inserted into the TOR that match qualifications specified= by the subevent. Does not include addressless requests such as locks and= interrupts.", "UMask": "0xc001ffff", @@ -4194,24 +5098,30 @@ }, { "BriefDescription": "TOR Inserts : DDR4 Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DDR4 Access : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_CHA_TOR_INSERTS.DDR", + "Counter": "0,1,2,3", "Deprecated": "1", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.DDR4", + "Experimental": "1", "PerPkg": "1", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : SF/LLC Evictions", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : SF/LLC Evictions : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts. : TOR allocation occurred as a result of SF/LLC e= victions (came from the ISMQ)", "UMask": "0x2", @@ -4219,14 +5129,17 @@ }, { "BriefDescription": "TOR Inserts : Just Hits", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Hits : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All requests from iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA", "PerPkg": "1", @@ -4236,6 +5149,7 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSH", "PerPkg": "1", @@ -4245,8 +5159,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushOpts issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushOpts issued by iA Cores= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4254,6 +5170,7 @@ }, { "BriefDescription": "TOR Inserts : CRDs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD", "PerPkg": "1", @@ -4263,8 +5180,10 @@ }, { "BriefDescription": "TOR Inserts; CRd Pref from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts; Code read prefetch from local I= A that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4272,8 +5191,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk : Counts the number of entries successfully inserted into = the TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -4281,6 +5202,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT", "PerPkg": "1", @@ -4290,6 +5212,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -4299,6 +5222,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT", "PerPkg": "1", @@ -4308,6 +5232,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD", "PerPkg": "1", @@ -4317,6 +5242,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_CRD_PREF", "PerPkg": "1", @@ -4326,8 +5252,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to page walks that hit the LLC : Counts the number of entries successfull= y inserted into the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837fd01", @@ -4335,6 +5263,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opts issued by iA Cores tha= t hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -4344,6 +5273,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -4353,6 +5283,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Hi= t the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO", "PerPkg": "1", @@ -4362,6 +5293,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_HIT_RFO_PREF", "PerPkg": "1", @@ -4371,6 +5303,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from iA Cores that= Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS", "PerPkg": "1", @@ -4380,6 +5313,7 @@ }, { "BriefDescription": "TOR Inserts : CRds issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD", "PerPkg": "1", @@ -4389,6 +5323,7 @@ }, { "BriefDescription": "TOR Inserts : CRd_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_CRD_PREF", "PerPkg": "1", @@ -4398,8 +5333,10 @@ }, { "BriefDescription": "TOR Inserts : DRd PTEs issued by iA Cores tha= t Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : DRd PTEs issued by iA Cores du= e to a page walk that missed the LLC : Counts the number of entries success= fully inserted into the TOR that match qualifications specified by the sube= vent. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc837fe01", @@ -4407,6 +5344,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt issued by iA Cores that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -4416,6 +5354,7 @@ }, { "BriefDescription": "TOR Inserts : DRd_Opt_Prefs issued by iA Core= s that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_DRD_OPT_PREF", "PerPkg": "1", @@ -4425,6 +5364,7 @@ }, { "BriefDescription": "TOR Inserts; WCiLF misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_FULL_STREAMING_WR", "PerPkg": "1", @@ -4434,6 +5374,7 @@ }, { "BriefDescription": "TOR Inserts; WCiL misses from local IA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_PARTIAL_STREAMING_WR", "PerPkg": "1", @@ -4443,6 +5384,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores that Mi= ssed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO", "PerPkg": "1", @@ -4452,6 +5394,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores th= at Missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_RFO_PREF", "PerPkg": "1", @@ -4461,6 +5404,7 @@ }, { "BriefDescription": "TOR Inserts : UCRdFs issued by iA Cores that = Missed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_UCRDF", "PerPkg": "1", @@ -4470,6 +5414,7 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCIL", "PerPkg": "1", @@ -4479,6 +5424,7 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores that M= issed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WCILF", "PerPkg": "1", @@ -4488,6 +5434,7 @@ }, { "BriefDescription": "TOR Inserts : WiLs issued by iA Cores that Mi= ssed LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_MISS_WIL", "PerPkg": "1", @@ -4497,6 +5444,7 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO", "PerPkg": "1", @@ -4506,6 +5454,7 @@ }, { "BriefDescription": "TOR Inserts : RFO_Prefs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_RFO_PREF", "PerPkg": "1", @@ -4515,8 +5464,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoEs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc3fff01", @@ -4524,8 +5475,10 @@ }, { "BriefDescription": "TOR Inserts : WBEFtoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBEFTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbEFtoIs issued by iA Cores . (Non Modified= Write Backs) :Counts the number of entries successfully inserted into the= TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xcc37ff01", @@ -4533,8 +5486,10 @@ }, { "BriefDescription": "TOR Inserts : WBMtoEs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoEs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc2fff01", @@ -4542,8 +5497,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by an iA Cores. = Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbMtoIs issued by iA Cores . (Modified Writ= e Backs) :Counts the number of entries successfully inserted into the TOR = that match qualifications specified by the subevent. Does not include addr= essless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -4551,8 +5508,10 @@ }, { "BriefDescription": "TOR Inserts : WBStoIs issued by an IA Core. = Non Modified Write Backs", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WBSTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbStoIs issued by iA Cores . (Non Modified = Write Backs) :Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include = addressless requests such as locks and interrupts.", "UMask": "0xcc67ff01", @@ -4560,8 +5519,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLs issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLs issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc86fff01", @@ -4569,8 +5530,10 @@ }, { "BriefDescription": "TOR Inserts : WCiLF issued by iA Cores", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WCiLF issued by iA Cores : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts.", "UMask": "0xc867ff01", @@ -4578,6 +5541,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO", "PerPkg": "1", @@ -4587,8 +5551,10 @@ }, { "BriefDescription": "TOR Inserts : CLFlushes issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : CLFlushes issued by IO Devices= : Counts the number of entries successfully inserted into the TOR that mat= ch qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -4596,6 +5562,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT", "PerPkg": "1", @@ -4605,6 +5572,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= Hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOM", "PerPkg": "1", @@ -4614,6 +5582,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_ITOMCACHENEAR", "PerPkg": "1", @@ -4623,6 +5592,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_PCIRDCUR", "PerPkg": "1", @@ -4632,8 +5602,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = hit the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= hit the LLC : Counts the number of entries successfully inserted into the = TOR that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -4641,6 +5613,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOM", "PerPkg": "1", @@ -4650,6 +5623,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR", "PerPkg": "1", @@ -4659,6 +5633,7 @@ }, { "BriefDescription": "TOR Inserts : All requests from IO Devices th= at missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS", "PerPkg": "1", @@ -4668,6 +5643,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMs issued by IO Devices that= missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOM", "PerPkg": "1", @@ -4677,6 +5653,7 @@ }, { "BriefDescription": "TOR Inserts : ItoMCacheNears, indicating a pa= rtial write request, from IO Devices that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_ITOMCACHENEAR", "PerPkg": "1", @@ -4686,6 +5663,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices = that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -4695,8 +5673,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices that = missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices that= missed the LLC : Counts the number of entries successfully inserted into t= he TOR that match qualifications specified by the subevent. Does not incl= ude addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -4704,6 +5684,7 @@ }, { "BriefDescription": "TOR Inserts : PCIRdCurs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_PCIRDCUR", "PerPkg": "1", @@ -4713,8 +5694,10 @@ }, { "BriefDescription": "TOR Inserts : RFOs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : RFOs issued by IO Devices : Co= unts the number of entries successfully inserted into the TOR that match qu= alifications specified by the subevent. Does not include addressless requ= ests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -4722,8 +5705,10 @@ }, { "BriefDescription": "TOR Inserts : WbMtoIs issued by IO Devices", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : WbMtoIs issued by IO Devices := Counts the number of entries successfully inserted into the TOR that match= qualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -4731,8 +5716,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - iA : Counts the number o= f entries successfully inserted into the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lock= s and interrupts. : From an iA Core", "UMask": "0x1", @@ -4740,8 +5727,10 @@ }, { "BriefDescription": "TOR Inserts : IRQ - Non iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : IRQ - Non iA : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "UMask": "0x10", @@ -4749,24 +5738,30 @@ }, { "BriefDescription": "TOR Inserts : Just ISOC", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just ISOC : Counts the number = of entries successfully inserted into the TOR that match qualifications spe= cified by the subevent. Does not include addressless requests such as loc= ks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Local Targets", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Local Targets : Counts th= e number of entries successfully inserted into the TOR that match qualifica= tions specified by the subevent. Does not include addressless requests su= ch as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : All from Local iA and IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA and IO : Cou= nts the number of entries successfully inserted into the TOR that match qua= lifications specified by the subevent. Does not include addressless reque= sts such as locks and interrupts. : All locally initiated requests", "UMask": "0xc000ff05", @@ -4774,8 +5769,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local iA", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local iA : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally initiated requests from iA Cores", "UMask": "0xc000ff01", @@ -4783,8 +5780,10 @@ }, { "BriefDescription": "TOR Inserts : All from Local IO", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : All from Local IO : Counts the= number of entries successfully inserted into the TOR that match qualificat= ions specified by the subevent. Does not include addressless requests suc= h as locks and interrupts. : All locally generated IO traffic", "UMask": "0xc000ff04", @@ -4792,64 +5791,80 @@ }, { "BriefDescription": "TOR Inserts : Match the Opcode in b[29:19] of= the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the Opcode in b[29:19] o= f the extended umask field : Counts the number of entries successfully inse= rted into the TOR that match qualifications specified by the subevent. Do= es not include addressless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just Misses", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just Misses : Counts the numbe= r of entries successfully inserted into the TOR that match qualifications s= pecified by the subevent. Does not include addressless requests such as l= ocks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : MMCFG Access", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : MMCFG Access : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NearMem : Counts the numb= er of entries successfully inserted into the TOR that match qualifications = specified by the subevent. Does not include addressless requests such as = locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NonCoherent", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NonCoherent : Counts the = number of entries successfully inserted into the TOR that match qualificati= ons specified by the subevent. Does not include addressless requests such= as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Just NotNearMem", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Just NotNearMem : Counts the n= umber of entries successfully inserted into the TOR that match qualificatio= ns specified by the subevent. Does not include addressless requests such = as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : Match the PreMorphed Opcode in = b[29:19] of the extended umask field", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : Match the PreMorphed Opcode in= b[29:19] of the extended umask field : Counts the number of entries succes= sfully inserted into the TOR that match qualifications specified by the sub= event. Does not include addressless requests such as locks and interrupts= .", "Unit": "CHA" }, { "BriefDescription": "TOR Inserts : PRQ - IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - IOSF : Counts the number= of entries successfully inserted into the TOR that match qualifications sp= ecified by the subevent. Does not include addressless requests such as lo= cks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -4857,8 +5872,10 @@ }, { "BriefDescription": "TOR Inserts : PRQ - Non IOSF", + "Counter": "0,1,2,3", "EventCode": "0x35", "EventName": "UNC_CHA_TOR_INSERTS.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Inserts : PRQ - Non IOSF : Counts the nu= mber of entries successfully inserted into the TOR that match qualification= s specified by the subevent. Does not include addressless requests such a= s locks and interrupts.", "UMask": "0x20", @@ -4866,16 +5883,20 @@ }, { "BriefDescription": "TOR Occupancy : DDR4 Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.DDR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DDR4 Access : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : SF/LLC Evictions", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.EVICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : SF/LLC Evictions : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts. : TOR allocation occurred as a = result of SF/LLC evictions (came from the ISMQ)", "UMask": "0x2", @@ -4883,14 +5904,17 @@ }, { "BriefDescription": "TOR Occupancy : Just Hits", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Hits : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA", "PerPkg": "1", @@ -4900,8 +5924,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc8c7ff01", @@ -4909,8 +5935,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushOpts issued by iA Core= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CLFLUSHOPT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushOpts issued by iA Cor= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8d7ff01", @@ -4918,6 +5946,7 @@ }, { "BriefDescription": "TOR Occupancy : CRDs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD", "PerPkg": "1", @@ -4927,8 +5956,10 @@ }, { "BriefDescription": "TOR Occupancy; CRd Pref from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Code read prefetch from local= IA that misses in the snoop filter", "UMask": "0xc88fff01", @@ -4936,8 +5967,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc837ff01", @@ -4945,6 +5978,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT", "PerPkg": "1", @@ -4954,6 +5988,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_DRD_OPT_PREF", "PerPkg": "1", @@ -4963,6 +5998,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT", "PerPkg": "1", @@ -4972,8 +6008,10 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRds issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc80ffd01", @@ -4981,8 +6019,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc88ffd01", @@ -4990,8 +6030,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that hit the LLC : For each cycle, this event accumulates = the number of valid entries in the TOR that match qualifications specified = by the subevent. Does not include addressless requests such as locks an= d interrupts.", "UMask": "0xc837fd01", @@ -4999,6 +6041,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opts issued by iA Cores t= hat hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT", "PerPkg": "1", @@ -5008,6 +6051,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_DRD_OPT_PREF", "PerPkg": "1", @@ -5017,8 +6061,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by iA Cores that= Hit the LLC : For each cycle, this event accumulates the number of valid e= ntries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc807fd01", @@ -5026,8 +6072,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_HIT_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Hit the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc887fd01", @@ -5035,6 +6083,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from iA Cores th= at Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS", "PerPkg": "1", @@ -5044,6 +6093,7 @@ }, { "BriefDescription": "TOR Occupancy : CRds issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD", "PerPkg": "1", @@ -5053,8 +6103,10 @@ }, { "BriefDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_CRD_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CRd_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc88ffe01", @@ -5062,8 +6114,10 @@ }, { "BriefDescription": "TOR Occupancy : DRdPte issued by iA Cores due= to a page walk that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRDPTE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRdPte issued by iA Cores du= e to a page walk that missed the LLC : For each cycle, this event accumulat= es the number of valid entries in the TOR that match qualifications specifi= ed by the subevent. Does not include addressless requests such as locks= and interrupts.", "UMask": "0xc837fe01", @@ -5071,6 +6125,7 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt issued by iA Cores th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT", "PerPkg": "1", @@ -5080,8 +6135,10 @@ }, { "BriefDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA Co= res that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_OPT_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : DRd_Opt_Prefs issued by iA C= ores that missed the LLC : For each cycle, this event accumulates the numbe= r of valid entries in the TOR that match qualifications specified by the su= bevent. Does not include addressless requests such as locks and interru= pts.", "UMask": "0xc8a7fe01", @@ -5089,8 +6146,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiLF misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_FULL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc867fe01", @@ -5098,8 +6157,10 @@ }, { "BriefDescription": "TOR Occupancy; WCiL misses from local IA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_PARTIAL_STREAMING_WR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy; Data read from local IA that = misses in the snoop filter", "UMask": "0xc86ffe01", @@ -5107,6 +6168,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores that = Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO", "PerPkg": "1", @@ -5116,8 +6178,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores = that Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= that Missed the LLC : For each cycle, this event accumulates the number of= valid entries in the TOR that match qualifications specified by the subeve= nt. Does not include addressless requests such as locks and interrupts.= ", "UMask": "0xc887fe01", @@ -5125,8 +6189,10 @@ }, { "BriefDescription": "TOR Occupancy : UCRdFs issued by iA Cores tha= t Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_UCRDF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : UCRdFs issued by iA Cores th= at Missed LLC : For each cycle, this event accumulates the number of valid = entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc877de01", @@ -5134,8 +6200,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc86ffe01", @@ -5143,8 +6211,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores that= Missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores tha= t Missed the LLC : For each cycle, this event accumulates the number of val= id entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc867fe01", @@ -5152,8 +6222,10 @@ }, { "BriefDescription": "TOR Occupancy : WiLs issued by iA Cores that = Missed LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_MISS_WIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WiLs issued by iA Cores that= Missed LLC : For each cycle, this event accumulates the number of valid en= tries in the TOR that match qualifications specified by the subevent. D= oes not include addressless requests such as locks and interrupts.", "UMask": "0xc87fde01", @@ -5161,6 +6233,7 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO", "PerPkg": "1", @@ -5170,8 +6243,10 @@ }, { "BriefDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_RFO_PREF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFO_Prefs issued by iA Cores= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xc887ff01", @@ -5179,8 +6254,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by iA Cores := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc27ff01", @@ -5188,8 +6265,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLs issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCIL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLs issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc86fff01", @@ -5197,8 +6276,10 @@ }, { "BriefDescription": "TOR Occupancy : WCiLF issued by iA Cores", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IA_WCILF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WCiLF issued by iA Cores : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts.", "UMask": "0xc867ff01", @@ -5206,6 +6287,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO", "PerPkg": "1", @@ -5215,8 +6297,10 @@ }, { "BriefDescription": "TOR Occupancy : CLFlushes issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : CLFlushes issued by IO Devic= es : For each cycle, this event accumulates the number of valid entries in = the TOR that match qualifications specified by the subevent. Does not i= nclude addressless requests such as locks and interrupts.", "UMask": "0xc8c3ff04", @@ -5224,6 +6308,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT", "PerPkg": "1", @@ -5233,8 +6318,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at Hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat Hit the LLC : For each cycle, this event accumulates the number of vali= d entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fd04", @@ -5242,8 +6329,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that hit the LLC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "UMask": "0xcd43fd04", @@ -5251,8 +6340,10 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_PCIRDCUR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PCIRdCurs issued by IO Devic= es that hit the LLC : For each cycle, this event accumulates the number of = valid entries in the TOR that match qualifications specified by the subeven= t. Does not include addressless requests such as locks and interrupts.", "UMask": "0xc8f3fd04", @@ -5260,8 +6351,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t hit the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_HIT_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at hit the LLC : For each cycle, this event accumulates the number of valid= entries in the TOR that match qualifications specified by the subevent. = Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fd04", @@ -5269,8 +6362,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices := For each cycle, this event accumulates the number of valid entries in the = TOR that match qualifications specified by the subevent. Does not inclu= de addressless requests such as locks and interrupts.", "UMask": "0xcc43ff04", @@ -5278,8 +6373,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "UMask": "0xcd43ff04", @@ -5287,6 +6384,7 @@ }, { "BriefDescription": "TOR Occupancy : All requests from IO Devices = that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS", "PerPkg": "1", @@ -5296,8 +6394,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMs issued by IO Devices th= at missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMs issued by IO Devices t= hat missed the LLC : For each cycle, this event accumulates the number of v= alid entries in the TOR that match qualifications specified by the subevent= . Does not include addressless requests such as locks and interrupts.", "UMask": "0xcc43fe04", @@ -5305,8 +6405,10 @@ }, { "BriefDescription": "TOR Occupancy : ItoMCacheNears, indicating a = partial write request, from IO Devices that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_ITOMCACHENEAR", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : ItoMCacheNears, indicating a= partial write request, from IO Devices that missed the LLC : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0xcd43fe04", @@ -5314,6 +6416,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s that missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_PCIRDCUR", "PerPkg": "1", @@ -5323,8 +6426,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices tha= t missed the LLC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_MISS_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices th= at missed the LLC : For each cycle, this event accumulates the number of va= lid entries in the TOR that match qualifications specified by the subevent.= Does not include addressless requests such as locks and interrupts.", "UMask": "0xc803fe04", @@ -5332,6 +6437,7 @@ }, { "BriefDescription": "TOR Occupancy : PCIRdCurs issued by IO Device= s", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_PCIRDCUR", "PerPkg": "1", @@ -5341,8 +6447,10 @@ }, { "BriefDescription": "TOR Occupancy : RFOs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : RFOs issued by IO Devices : = For each cycle, this event accumulates the number of valid entries in the T= OR that match qualifications specified by the subevent. Does not includ= e addressless requests such as locks and interrupts.", "UMask": "0xc803ff04", @@ -5350,8 +6458,10 @@ }, { "BriefDescription": "TOR Occupancy : WbMtoIs issued by IO Devices", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IO_WBMTOI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : WbMtoIs issued by IO Devices= : For each cycle, this event accumulates the number of valid entries in th= e TOR that match qualifications specified by the subevent. Does not inc= lude addressless requests such as locks and interrupts.", "UMask": "0xcc23ff04", @@ -5359,8 +6469,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - iA : For each cycle, t= his event accumulates the number of valid entries in the TOR that match qua= lifications specified by the subevent. Does not include addressless req= uests such as locks and interrupts. : From an iA Core", "UMask": "0x1", @@ -5368,8 +6480,10 @@ }, { "BriefDescription": "TOR Occupancy : IRQ - Non iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.IRQ_NON_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : IRQ - Non iA : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "UMask": "0x10", @@ -5377,24 +6491,30 @@ }, { "BriefDescription": "TOR Occupancy : Just ISOC", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.ISOC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just ISOC : For each cycle, = this event accumulates the number of valid entries in the TOR that match qu= alifications specified by the subevent. Does not include addressless re= quests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Local Targets", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOCAL_TGT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Local Targets : For eac= h cycle, this event accumulates the number of valid entries in the TOR that= match qualifications specified by the subevent. Does not include addre= ssless requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : All from Local iA and IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA and IO : F= or each cycle, this event accumulates the number of valid entries in the TO= R that match qualifications specified by the subevent. Does not include= addressless requests such as locks and interrupts. : All locally initiated= requests", "UMask": "0xc000ff05", @@ -5402,8 +6522,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local iA", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IA", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local iA : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally initiated reques= ts from iA Cores", "UMask": "0xc000ff01", @@ -5411,8 +6533,10 @@ }, { "BriefDescription": "TOR Occupancy : All from Local IO", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.LOC_IO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : All from Local IO : For each= cycle, this event accumulates the number of valid entries in the TOR that = match qualifications specified by the subevent. Does not include addres= sless requests such as locks and interrupts. : All locally generated IO tra= ffic", "UMask": "0xc000ff04", @@ -5420,64 +6544,80 @@ }, { "BriefDescription": "TOR Occupancy : Match the Opcode in b[29:19] = of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MATCH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the Opcode in b[29:19]= of the extended umask field : For each cycle, this event accumulates the n= umber of valid entries in the TOR that match qualifications specified by th= e subevent. Does not include addressless requests such as locks and int= errupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just Misses", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just Misses : For each cycle= , this event accumulates the number of valid entries in the TOR that match = qualifications specified by the subevent. Does not include addressless = requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : MMCFG Access", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.MMCFG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : MMCFG Access : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NearMem : For each cycl= e, this event accumulates the number of valid entries in the TOR that match= qualifications specified by the subevent. Does not include addressless= requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NonCoherent", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NONCOH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NonCoherent : For each = cycle, this event accumulates the number of valid entries in the TOR that m= atch qualifications specified by the subevent. Does not include address= less requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Just NotNearMem", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.NOT_NEARMEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Just NotNearMem : For each c= ycle, this event accumulates the number of valid entries in the TOR that ma= tch qualifications specified by the subevent. Does not include addressl= ess requests such as locks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : Match the PreMorphed Opcode i= n b[29:19] of the extended umask field", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PREMORPH_OPC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : Match the PreMorphed Opcode = in b[29:19] of the extended umask field : For each cycle, this event accumu= lates the number of valid entries in the TOR that match qualifications spec= ified by the subevent. Does not include addressless requests such as lo= cks and interrupts.", "Unit": "CHA" }, { "BriefDescription": "TOR Occupancy : PRQ - IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - IOSF : For each cycle,= this event accumulates the number of valid entries in the TOR that match q= ualifications specified by the subevent. Does not include addressless r= equests such as locks and interrupts. : From a PCIe Device", "UMask": "0x4", @@ -5485,8 +6625,10 @@ }, { "BriefDescription": "TOR Occupancy : PRQ - Non IOSF", + "Counter": "0", "EventCode": "0x36", "EventName": "UNC_CHA_TOR_OCCUPANCY.PRQ_NON_IOSF", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "TOR Occupancy : PRQ - Non IOSF : For each cy= cle, this event accumulates the number of valid entries in the TOR that mat= ch qualifications specified by the subevent. Does not include addressle= ss requests such as locks and interrupts.", "UMask": "0x20", @@ -5494,8 +6636,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5503,8 +6647,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -5512,8 +6658,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -5521,8 +6669,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5530,8 +6680,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -5539,8 +6691,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_CHA_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -5548,8 +6702,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5557,8 +6713,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -5566,8 +6724,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -5575,8 +6735,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -5584,8 +6746,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -5593,8 +6757,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5602,8 +6768,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -5611,8 +6779,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -5620,8 +6790,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_CHA_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -5629,8 +6801,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5638,8 +6812,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -5647,8 +6823,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -5656,8 +6834,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -5665,8 +6845,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -5674,8 +6856,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5683,8 +6867,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -5692,8 +6878,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -5701,8 +6889,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -5710,8 +6900,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5719,8 +6911,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -5728,8 +6922,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -5737,8 +6933,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -5746,8 +6944,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -5755,8 +6955,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5764,8 +6966,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -5773,8 +6977,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -5782,8 +6988,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_CHA_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -5791,8 +6999,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5800,8 +7010,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -5809,8 +7021,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -5818,8 +7032,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -5827,8 +7043,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -5836,8 +7054,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -5845,8 +7065,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -5854,8 +7076,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -5863,8 +7087,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_CHA_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -5872,8 +7098,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -5881,8 +7109,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -5890,8 +7120,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -5899,8 +7131,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -5908,8 +7142,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -5917,8 +7153,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -5926,8 +7164,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -5935,8 +7175,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -5944,8 +7186,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_CHA_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -5953,8 +7197,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -5962,8 +7208,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -5971,8 +7219,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -5980,8 +7230,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -5989,8 +7241,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -5998,8 +7252,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6007,8 +7263,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -6016,8 +7274,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -6025,8 +7285,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_CHA_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -6034,8 +7296,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -6043,8 +7307,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -6052,8 +7318,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -6061,8 +7329,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -6070,8 +7340,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -6079,8 +7351,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -6088,8 +7362,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_CHA_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -6097,8 +7373,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -6106,8 +7384,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -6115,8 +7395,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -6124,8 +7406,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_CHA_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -6133,8 +7417,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -6142,8 +7428,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -6151,8 +7439,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -6160,8 +7450,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -6169,8 +7461,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -6178,8 +7472,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -6187,8 +7483,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_CHA_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -6196,8 +7494,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -6205,8 +7505,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_CHA_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -6214,8 +7516,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6223,8 +7527,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -6232,8 +7538,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6241,8 +7549,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6250,8 +7560,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -6259,8 +7571,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -6268,8 +7582,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -6277,8 +7593,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6286,8 +7604,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_CHA_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6295,8 +7615,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -6304,8 +7626,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -6313,8 +7637,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6322,8 +7648,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6331,8 +7659,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -6340,8 +7670,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -6349,8 +7681,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -6358,8 +7692,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -6367,8 +7703,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_CHA_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -6376,8 +7714,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6385,8 +7725,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -6394,8 +7736,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -6403,8 +7747,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6412,8 +7758,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -6421,8 +7769,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -6430,8 +7780,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_CHA_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -6439,8 +7791,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6448,8 +7802,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_CHA_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -6457,8 +7813,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -6466,8 +7824,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -6475,8 +7835,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -6484,8 +7846,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -6493,8 +7857,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -6502,8 +7868,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -6511,8 +7879,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_CHA_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -6520,8 +7890,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -6529,8 +7901,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_CHA_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -6538,8 +7912,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6547,8 +7923,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -6556,8 +7934,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -6565,8 +7945,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -6574,8 +7956,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -6583,8 +7967,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -6592,8 +7978,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -6601,8 +7989,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -6610,8 +8000,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_CHA_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -6619,8 +8011,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -6628,8 +8022,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -6637,8 +8033,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -6646,8 +8044,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -6655,8 +8055,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -6664,8 +8066,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -6673,8 +8077,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_CHA_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -6682,8 +8088,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -6691,8 +8099,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -6700,8 +8110,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_CHA_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -6709,8 +8121,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6718,8 +8132,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6727,8 +8143,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6736,8 +8154,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_CHA_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6745,8 +8165,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6754,8 +8176,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6763,8 +8187,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6772,8 +8198,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_CHA_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6781,8 +8209,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6790,8 +8220,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6799,8 +8231,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6808,8 +8242,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_CHA_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6817,8 +8253,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6826,8 +8264,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6835,8 +8275,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -6844,8 +8286,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_CHA_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -6853,8 +8297,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -6862,8 +8308,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_CHA_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -6871,8 +8319,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -6880,8 +8330,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -6889,8 +8341,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -6898,8 +8352,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_CHA_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -6907,8 +8363,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to LLC", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.LLC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to LLC : Counts the numb= er of times when the CHA was received WbPushMtoI : Counts the number of tim= es when the CHA was able to push WbPushMToI to LLC", "UMask": "0x1", @@ -6916,8 +8374,10 @@ }, { "BriefDescription": "WbPushMtoI : Pushed to Memory", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_CHA_WB_PUSH_MTOI.MEM", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "WbPushMtoI : Pushed to Memory : Counts the n= umber of times when the CHA was received WbPushMtoI : Counts the number of = times when the CHA was unable to push WbPushMToI to LLC (hence pushed it to= MEM)", "UMask": "0x2", @@ -6925,8 +8385,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC0", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC0 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 0 only.", "UMask": "0x1", @@ -6934,8 +8396,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC1", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC1 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 1 only.", "UMask": "0x2", @@ -6943,40 +8407,50 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC10", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC10 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 10 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC11", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC11", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC11 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 11 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC12", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC12", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC12 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 12 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC13", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC13", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC13 : Co= unts the number of times when there are no credits available for sending WR= ITEs from the CHA into the iMC. In order to send WRITEs into the memory co= ntroller, the HA must first acquire a credit for the iMC's BL Ingress queue= . : Filter for memory controller 13 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC2", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC2 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 2 only.", "UMask": "0x4", @@ -6984,8 +8458,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC3", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC3 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 3 only.", "UMask": "0x8", @@ -6993,8 +8469,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC4", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC4 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 4 only.", "UMask": "0x10", @@ -7002,8 +8480,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC5", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC5 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 5 only.", "UMask": "0x20", @@ -7011,8 +8491,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC6", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC6 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 6 only.", "UMask": "0x40", @@ -7020,8 +8502,10 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC7", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC7 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 7 only.", "UMask": "0x80", @@ -7029,24 +8513,30 @@ }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC8", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC8 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 8 only.", "Unit": "CHA" }, { "BriefDescription": "CHA iMC CHNx WRITE Credits Empty : MC9", + "Counter": "0,1,2,3", "EventCode": "0x5A", "EventName": "UNC_CHA_WRITE_NO_CREDITS.MC9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CHA iMC CHNx WRITE Credits Empty : MC9 : Cou= nts the number of times when there are no credits available for sending WRI= TEs from the CHA into the iMC. In order to send WRITEs into the memory con= troller, the HA must first acquire a credit for the iMC's BL Ingress queue.= : Filter for memory controller 9 only.", "Unit": "CHA" }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x8", @@ -7054,8 +8544,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 0?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP0_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 0?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x4", @@ -7063,8 +8555,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - Conflict", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_CONFLICT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - Conflict = : Number of XPT prefetches dropped due to AD CMS write port contention", "UMask": "0x80", @@ -7072,8 +8566,10 @@ }, { "BriefDescription": "XPT Prefetches : Dropped (on 1?) - No Credits= ", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.DROP1_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Dropped (on 1?) - No Credit= s : Number of XPT prefetches dropped due to lack of XPT AD egress credits", "UMask": "0x40", @@ -7081,8 +8577,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 0?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 0?) : Number of XP= T prefetches sent", "UMask": "0x1", @@ -7090,8 +8588,10 @@ }, { "BriefDescription": "XPT Prefetches : Sent (on 1?)", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_CHA_XPT_PREF.SENT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "XPT Prefetches : Sent (on 1?) : Number of XP= T prefetches sent", "UMask": "0x10", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.= json b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json index 7cc3635b118b..88ee90b8a2d9 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-interconnect.json @@ -1,8 +1,10 @@ [ { "BriefDescription": "Total Write Cache Occupancy : Any Source", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.ANY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Any Source : A= ccumulates the number of reads and writes that are outstanding in the uncor= e in each cycle. This is effectively the sum of the READ_OCCUPANCY and WRI= TE_OCCUPANCY events. : Tracks all requests from any source port.", "UMask": "0x1", @@ -10,8 +12,10 @@ }, { "BriefDescription": "Total Write Cache Occupancy : Snoops", + "Counter": "0,1", "EventCode": "0x0F", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.IV_Q", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Write Cache Occupancy : Snoops : Accum= ulates the number of reads and writes that are outstanding in the uncore in= each cycle. This is effectively the sum of the READ_OCCUPANCY and WRITE_O= CCUPANCY events.", "UMask": "0x2", @@ -19,6 +23,7 @@ }, { "BriefDescription": "Total IRP occupancy of inbound read and write= requests to coherent memory.", + "Counter": "0,1", "EventCode": "0x0f", "EventName": "UNC_I_CACHE_TOTAL_OCCUPANCY.MEM", "PerPkg": "1", @@ -28,6 +33,7 @@ }, { "BriefDescription": "Clockticks of the IO coherency tracker (IRP)", + "Counter": "0,1", "EventCode": "0x01", "EventName": "UNC_I_CLOCKTICKS", "PerPkg": "1", @@ -35,8 +41,10 @@ }, { "BriefDescription": "Coherent Ops : CLFlush", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.CLFLUSH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Coherent Ops : CLFlush : Counts the number o= f coherency related operations serviced by the IRP", "UMask": "0x80", @@ -44,6 +52,7 @@ }, { "BriefDescription": "PCIITOM request issued by the IRP unit to the= mesh with the intention of writing a full cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.PCITOM", "PerPkg": "1", @@ -53,8 +62,10 @@ }, { "BriefDescription": "RFO request issued by the IRP unit to the mes= h with the intention of writing a partial cacheline.", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.RFO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RFO request issued by the IRP unit to the me= sh with the intention of writing a partial cacheline to coherent memory. R= FO is a Read For Ownership command that requests ownership of the cacheline= and moves data from the mesh to IRP cache.", "UMask": "0x8", @@ -62,6 +73,7 @@ }, { "BriefDescription": "Coherent Ops : WbMtoI", + "Counter": "0,1", "EventCode": "0x10", "EventName": "UNC_I_COHERENT_OPS.WBMTOI", "PerPkg": "1", @@ -71,6 +83,7 @@ }, { "BriefDescription": "FAF RF full", + "Counter": "0,1", "EventCode": "0x17", "EventName": "UNC_I_FAF_FULL", "PerPkg": "1", @@ -78,6 +91,7 @@ }, { "BriefDescription": "Inbound read requests received by the IRP and= inserted into the FAF queue.", + "Counter": "0,1", "EventCode": "0x18", "EventName": "UNC_I_FAF_INSERTS", "PerPkg": "1", @@ -86,6 +100,7 @@ }, { "BriefDescription": "Occupancy of the IRP FAF queue.", + "Counter": "0,1", "EventCode": "0x19", "EventName": "UNC_I_FAF_OCCUPANCY", "PerPkg": "1", @@ -94,6 +109,7 @@ }, { "BriefDescription": "FAF allocation -- sent to ADQ", + "Counter": "0,1", "EventCode": "0x16", "EventName": "UNC_I_FAF_TRANSACTIONS", "PerPkg": "1", @@ -101,14 +117,17 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.EVICTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": ": All Inserts Inbound (p2p + faf + cset)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.INBOUND_INSERTS", "PerPkg": "1", @@ -117,78 +136,97 @@ }, { "BriefDescription": ": All Inserts Outbound (BL, AK, Snoops)", + "Counter": "0,1", "EventCode": "0x20", "EventName": "UNC_I_IRP_ALL.OUTBOUND_INSERTS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of At= omic Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.2ND_ATOMIC_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Re= ad Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_RD_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Wr= ite Transactions as Secondary", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.2ND_WR_INSERT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_REJ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Requests", + "Counter": "0,1", "EventCode": "0x1e", "EventName": "UNC_I_MISC0.FAST_REQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Fastpath Transfers = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.FAST_XFER", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Prefetch Ack Hints = From Primary to Secondary", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.PF_ACK_HINT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Counts Timeouts - Set 0 : Slow path fwpf didn= 't find prefetch", + "Counter": "0,1", "EventCode": "0x1E", "EventName": "UNC_I_MISC0.SLOWPATH_FWPF_NO_PRF", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "Misc Events - Set 1 : Lost Forward", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.LOST_FWD", "PerPkg": "1", @@ -198,8 +236,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Invalid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_INVLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Invalid : Sec= ondary received a transfer that did not have sufficient MESI state", "UMask": "0x20", @@ -207,8 +247,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Received Valid", + "Counter": "0,1", "EventCode": "0x1F", "EventName": "UNC_I_MISC1.SEC_RCVD_VLD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Received Valid : Secon= dary received a transfer that did have sufficient MESI state", "UMask": "0x40", @@ -216,8 +258,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of E Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_E", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of E Lin= e : Secondary received a transfer that did have sufficient MESI state", "UMask": "0x4", @@ -225,8 +269,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of I Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of I Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x1", @@ -234,8 +280,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of M Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_M", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of M Lin= e : Snoop took cacheline ownership before write from data was committed.", "UMask": "0x8", @@ -243,8 +291,10 @@ }, { "BriefDescription": "Misc Events - Set 1 : Slow Transfer of S Line= ", + "Counter": "0,1", "EventCode": "0x1f", "EventName": "UNC_I_MISC1.SLOW_S", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Misc Events - Set 1 : Slow Transfer of S Lin= e : Secondary received a transfer that did not have sufficient MESI state", "UMask": "0x2", @@ -252,88 +302,110 @@ }, { "BriefDescription": "P2P Requests", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_I_P2P_INSERTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Requests : P2P requests from the ITC", "Unit": "IRP" }, { "BriefDescription": "P2P Occupancy", + "Counter": "0,1", "EventCode": "0x15", "EventName": "UNC_I_P2P_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "P2P Occupancy : P2P B & S Queue Occupancy", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P completions", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.CMPL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if local and target = matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.LOC_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Message", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.MSG", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P reads", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : Match if remote only", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : match if remote and target= matches", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.REM_AND_TGT_MATCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "P2P Transactions : P2P Writes", + "Counter": "0,1", "EventCode": "0x13", "EventName": "UNC_I_P2P_TRANSACTIONS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Responses to snoops of any type that hit M, E= , S or I line in the IIO", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit M, E, S or I line in the IIO", "UMask": "0x7e", @@ -341,8 +413,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit E or= S line in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_ES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit E or S line in the IIO cache", "UMask": "0x74", @@ -350,8 +424,10 @@ }, { "BriefDescription": "Responses to snoops of any type that hit I li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_I", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that hit I line in the IIO cache", "UMask": "0x72", @@ -359,6 +435,7 @@ }, { "BriefDescription": "Responses to snoops of any type that hit M li= ne in the IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_HIT_M", "PerPkg": "1", @@ -368,8 +445,10 @@ }, { "BriefDescription": "Responses to snoops of any type that miss the= IIO cache", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.ALL_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Responses to snoops of any type (code, data,= invalidate) that miss the IIO cache", "UMask": "0x71", @@ -377,64 +456,80 @@ }, { "BriefDescription": "Snoop Responses : Hit E or S", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_ES", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit I", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_I", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Hit M", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.HIT_M", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : Miss", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.MISS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpCode", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPCODE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpData", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPDATA", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "IRP" }, { "BriefDescription": "Snoop Responses : SnpInv", + "Counter": "0,1", "EventCode": "0x12", "EventName": "UNC_I_SNOOP_RESP.SNPINV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "IRP" }, { "BriefDescription": "Inbound Transaction Count : Atomic", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.ATOMIC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Atomic : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks the number of atomic transactions", "UMask": "0x10", @@ -442,8 +537,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Other", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.OTHER", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Other : Counts t= he number of Inbound transactions from the IRP to the Uncore. This can be = filtered based on request type in addition to the source queue. Note the s= pecial filtering equation. We do OR-reduction on the request type. If the= SOURCE bit is set, then we also do AND qualification based on the source p= ortID. : Tracks the number of 'other' kinds of transactions.", "UMask": "0x20", @@ -451,8 +548,10 @@ }, { "BriefDescription": "Inbound Transaction Count : Writes", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WRITES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Inbound Transaction Count : Writes : Counts = the number of Inbound transactions from the IRP to the Uncore. This can be= filtered based on request type in addition to the source queue. Note the = special filtering equation. We do OR-reduction on the request type. If th= e SOURCE bit is set, then we also do AND qualification based on the source = portID. : Tracks only write requests. Each write request should have a pre= fetch, so there is no need to explicitly track these requests. For writes = that are tickled and have to retry, the counter will be incremented for eac= h retry.", "UMask": "0x2", @@ -460,6 +559,7 @@ }, { "BriefDescription": "Inbound write (fast path) requests received b= y the IRP.", + "Counter": "0,1", "EventCode": "0x11", "EventName": "UNC_I_TRANSACTIONS.WR_PREF", "PerPkg": "1", @@ -469,134 +569,170 @@ }, { "BriefDescription": "AK Egress Allocations", + "Counter": "0,1", "EventCode": "0x0B", "EventName": "UNC_I_TxC_AK_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x05", "EventName": "UNC_I_TxC_BL_DRS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Inserts", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_I_TxC_BL_DRS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL DRS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x08", "EventName": "UNC_I_TxC_BL_DRS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x06", "EventName": "UNC_I_TxC_BL_NCB_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Inserts", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_I_TxC_BL_NCB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCB Egress Occupancy", + "Counter": "0,1", "EventCode": "0x09", "EventName": "UNC_I_TxC_BL_NCB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Cycles Full", + "Counter": "0,1", "EventCode": "0x07", "EventName": "UNC_I_TxC_BL_NCS_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Inserts", + "Counter": "0,1", "EventCode": "0x04", "EventName": "UNC_I_TxC_BL_NCS_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "BL NCS Egress Occupancy", + "Counter": "0,1", "EventCode": "0x0A", "EventName": "UNC_I_TxC_BL_NCS_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "IRP" }, { "BriefDescription": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Counter": "0,1", "EventCode": "0x1C", "EventName": "UNC_I_TxR2_AD01_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Counts the number times when it is not pos= sible to issue a request to the M2PCIe because there are no Egress Credits = available on AD0, A1 or AD0&AD1 both. Stalls on both AD0 and AD1 will count= as 2", "Unit": "IRP" }, { "BriefDescription": "No AD0 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1A", "EventName": "UNC_I_TxR2_AD0_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD0 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD0 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No AD1 Egress Credits Stalls", + "Counter": "0,1", "EventCode": "0x1B", "EventName": "UNC_I_TxR2_AD1_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No AD1 Egress Credits Stalls : Counts the nu= mber times when it is not possible to issue a request to the M2PCIe because= there are no AD1 Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "No BL Egress Credit Stalls", + "Counter": "0,1", "EventCode": "0x1D", "EventName": "UNC_I_TxR2_BL_STALL_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "No BL Egress Credit Stalls : Counts the numb= er times when it is not possible to issue data to the R2PCIe because there = are no BL Egress Credits available.", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0D", "EventName": "UNC_I_TxS_DATA_INSERTS_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Read Requests", + "Counter": "0,1", "EventCode": "0x0E", "EventName": "UNC_I_TxS_DATA_INSERTS_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Read Requests : Counts the number o= f requests issued to the switch (towards the devices).", "Unit": "IRP" }, { "BriefDescription": "Outbound Request Queue Occupancy", + "Counter": "0,1", "EventCode": "0x0C", "EventName": "UNC_I_TxS_REQUEST_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Outbound Request Queue Occupancy : Accumulat= es the number of outstanding outbound requests from the IRP to the switch (= towards the devices). This can be used in conjunction with the allocations= event in order to calculate average latency of outbound requests.", "Unit": "IRP" }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -604,8 +740,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -613,8 +751,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -622,8 +762,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -631,8 +773,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -640,8 +784,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -649,8 +795,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -658,8 +806,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -667,8 +817,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -676,8 +828,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -685,8 +839,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2M_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -694,8 +850,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -703,8 +861,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -712,8 +872,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -721,8 +883,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -730,8 +894,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -739,8 +905,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -748,8 +916,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -757,8 +927,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -766,8 +938,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -775,8 +949,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -784,8 +960,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2M_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -793,8 +971,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -802,8 +982,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -811,8 +993,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -820,8 +1004,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -829,8 +1015,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -838,8 +1026,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -847,8 +1037,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -856,8 +1048,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -865,8 +1059,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -874,8 +1070,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -883,8 +1081,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2M_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -892,8 +1092,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -901,8 +1103,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -910,8 +1114,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -919,8 +1125,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -928,8 +1136,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -937,8 +1147,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -946,8 +1158,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -955,8 +1169,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8A", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -964,8 +1180,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -973,8 +1191,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -982,8 +1202,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8B", "EventName": "UNC_M2M_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -991,8 +1213,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1000,8 +1224,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1009,8 +1235,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1018,8 +1246,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1027,8 +1257,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1036,8 +1268,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1045,8 +1279,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1054,8 +1290,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1063,8 +1301,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1072,8 +1312,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1081,8 +1323,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2M_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1090,8 +1334,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1099,8 +1345,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1108,8 +1356,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1117,8 +1367,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1126,8 +1378,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1135,8 +1389,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1144,8 +1400,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1153,8 +1411,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1162,8 +1422,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1171,8 +1433,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1180,8 +1444,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2M_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1189,8 +1455,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1198,8 +1466,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1207,8 +1477,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -1216,8 +1488,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -1225,8 +1499,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -1234,8 +1510,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -1243,8 +1521,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -1252,8 +1532,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8C", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -1261,8 +1543,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -1270,8 +1554,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -1279,8 +1565,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8D", "EventName": "UNC_M2M_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -1288,8 +1576,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1297,8 +1587,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1306,8 +1598,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -1315,8 +1609,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -1324,8 +1620,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -1333,8 +1631,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -1342,8 +1642,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -1351,8 +1653,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -1360,8 +1664,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -1369,8 +1675,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -1378,8 +1686,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_M2M_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -1387,44 +1697,54 @@ }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M2M_BYPASS_M2M_EGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Not Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.NOT_TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC Bypass : Taken", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M2M_BYPASS_M2M_INGRESS.TAKEN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Clockticks of the mesh to memory (M2M)", + "Counter": "0,1,2,3", "EventName": "UNC_M2M_CLOCKTICKS", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2M_CMS_CLOCKTICKS", "PerPkg": "1", @@ -1432,29 +1752,37 @@ }, { "BriefDescription": "Cycles when direct to core mode, which bypass= es the CHA, was disabled", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_DIRSTATE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_M2M_DIRECT2CORE_NOT_TAKEN_NOTFORKED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number of reads in which direct to core trans= action was overridden", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2M_DIRECT2CORE_TXN_OVERRIDE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -1462,8 +1790,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -1471,8 +1801,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -1480,8 +1812,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -1489,8 +1823,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -1498,8 +1834,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xAF", "EventName": "UNC_M2M_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -1507,8 +1845,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -1516,8 +1856,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xBA", "EventName": "UNC_M2M_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -1525,8 +1867,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1534,8 +1878,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1543,8 +1889,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1552,8 +1900,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB6", "EventName": "UNC_M2M_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1561,8 +1911,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1570,8 +1922,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1579,8 +1933,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1588,8 +1944,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xBB", "EventName": "UNC_M2M_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1597,8 +1955,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1606,8 +1966,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1615,8 +1977,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1624,8 +1988,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB7", "EventName": "UNC_M2M_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1633,8 +1999,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -1642,8 +2010,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -1651,8 +2021,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -1660,8 +2032,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "UNC_M2M_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -1669,8 +2043,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -1678,8 +2054,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xB9", "EventName": "UNC_M2M_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -1687,463 +2065,581 @@ }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x704", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x104", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x140", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x102", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h0", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH0_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x101", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : All, regardless of = priority. - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x204", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x240", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= Ch1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x202", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - C= h1", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.CH1_NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x201", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : From TGR - All Chan= nels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x740", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Critical Priority -= All Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x702", "Unit": "M2M" }, { "BriefDescription": "M2M Reads Issued to iMC : Normal Priority - A= ll Channels", + "Counter": "0,1,2,3", "EventCode": "0x37", "EventName": "UNC_M2M_IMC_READS.NORMAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x701", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - All C= hannels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c10", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x410", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x401", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x404", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x402", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 0", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH0_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x408", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : All Writes - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x810", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x801", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x804", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - Ch1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x802", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Ch= 1", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.CH1_PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x808", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : From TGR - All Cha= nnels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FROM_TGR", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Full Line Non-ISOC= H - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c01", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Full Line - = All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.FULL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c04", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Non-Inclusive Miss= - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.NI_MISS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : Partial Non-ISOCH = - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c02", "Unit": "M2M" }, { "BriefDescription": "M2M Writes Issued to iMC : ISOCH Partial - Al= l Channels", + "Counter": "0,1,2,3", "EventCode": "0x38", "EventName": "UNC_M2M_IMC_WRITES.PARTIAL_ISOCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1c08", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts", + "Counter": "0,1,2,3", "EventCode": "0x64", "EventName": "UNC_M2M_MIRR_WRQ_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x65", "EventName": "UNC_M2M_MIRR_WRQ_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "UNC_M2M_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : MC Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Number Packet Header Matches : Mesh Match", + "Counter": "0,1,2,3", "EventCode": "0x4C", "EventName": "UNC_M2M_PKT_MATCH.MESH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_CIS_DROPS", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_M2M_PREFCAM_CIS_DROPS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6B", "EventName": "UNC_M2M_PREFCAM_CYCLES_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "UNC_M2M_PREFCAM_CYCLES_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH0_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA0_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_HITA1_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_MISS_INVAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Deallocs", + "Counter": "0,1,2,3", "EventCode": "0x6E", "EventName": "UNC_M2M_PREFCAM_DEALLOCS.CH1_RSP_PDRESET", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6F", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6f", "EventName": "UNC_M2M_PREFCAM_DEMAND_DROPS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 0", "UMask": "0x1", @@ -2151,16 +2647,20 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI- Ch 1", "UMask": "0x4", @@ -2168,8 +2668,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - Ch 2", "UMask": "0x10", @@ -2177,8 +2679,10 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT & = UPI- All Channels", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Merged with CAMed Prefetches : XPT &= UPI - All Channels", "UMask": "0x15", @@ -2186,24 +2690,30 @@ }, { "BriefDescription": "Demands Merged with CAMed Prefetches : XPT - = All Channels", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_M2M_PREFCAM_DEMAND_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH0_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 0", "UMask": "0x1", @@ -2211,16 +2721,20 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH1_XPTUPI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Demands Not Merged with CAMed Prefetches : X= PT & UPI- Ch 1", "UMask": "0x4", @@ -2228,305 +2742,383 @@ }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - Ch 2", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.CH2_XPTUPI", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T & UPI - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPTUPI_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Demands Not Merged with CAMed Prefetches : XP= T - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_M2M_PREFCAM_DEMAND_NO_MERGE.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch0 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x70", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH0.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.ERRORBLK_RxC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.NOT_PF_SAD_REGION", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_AD_CRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_FULL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.PF_SECURE_DROP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.RPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.STOP_B2B", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.WPQ_PROXY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2M" }, { "BriefDescription": "Data Prefetches Dropped Ch1 - Reasons", + "Counter": "0,1,2,3", "EventCode": "0x71", "EventName": "UNC_M2M_PREFCAM_DROP_REASONS_CH1.XPT_THRESH", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 0", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH0_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - Ch 1", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.CH1_XPT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Inserts : XPT - All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6D", "EventName": "UNC_M2M_PREFCAM_INSERTS.XPT_ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x15", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : All Channels", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Prefetch CAM Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x6A", "EventName": "UNC_M2M_PREFCAM_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": ": All Channels", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.ALLCH", + "Experimental": "1", "PerPkg": "1", "UMask": "0x7", "Unit": "M2M" }, { "BriefDescription": ": Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": ": Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_M2M_PREFCAM_RESP_MISS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "UNC_M2M_PREFCAM_RxC_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.1LM_POSTED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.CIS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Counter": "0,1,2,3", "EventCode": "0x7A", "EventName": "UNC_M2M_PREFCAM_RxC_DEALLOCS.SQUASHED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_M2M_PREFCAM_RxC_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_PREFCAM_RxC_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -2534,8 +3126,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -2543,8 +3137,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -2552,8 +3148,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xAC", "EventName": "UNC_M2M_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -2561,8 +3159,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -2570,8 +3170,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -2579,8 +3181,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -2588,8 +3192,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -2597,8 +3203,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAA", "EventName": "UNC_M2M_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -2606,197 +3214,249 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xAD", "EventName": "UNC_M2M_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xAB", "EventName": "UNC_M2M_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2M_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Regular : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M2M_RPQ_NO_REG_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M to iMC RPQ Cycles w/Credits - Special : C= hannel 1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2M_RPQ_NO_SPEC_CRD.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M2M_RxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "UNC_M2M_RxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2M_RxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M2M_RxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Ingress (from CMS) Occupancy - Prefetches", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_M2M_RxC_AD_PREF_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "UNC_M2M_RxC_AK_WR_CMP", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "UNC_M2M_RxC_BL_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "UNC_M2M_RxC_BL_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_M2M_RxC_BL_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "BL Ingress (from CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_M2M_RxC_BL_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2804,8 +3464,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -2813,8 +3475,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -2822,8 +3486,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2831,8 +3497,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -2840,8 +3508,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "UNC_M2M_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -2849,8 +3519,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2858,8 +3530,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -2867,8 +3541,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -2876,8 +3552,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -2885,8 +3563,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -2894,8 +3574,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2903,8 +3585,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -2912,8 +3596,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -2921,8 +3607,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xE2", "EventName": "UNC_M2M_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -2930,8 +3618,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -2939,8 +3629,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -2948,8 +3640,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -2957,8 +3651,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -2966,8 +3662,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -2975,8 +3673,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -2984,8 +3684,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -2993,8 +3695,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -3002,8 +3706,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xE3", "EventName": "UNC_M2M_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -3011,16 +3717,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2M_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2M" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3028,8 +3738,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -3037,8 +3749,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -3046,8 +3760,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -3055,8 +3771,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -3064,8 +3782,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3073,8 +3793,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -3082,8 +3804,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -3091,8 +3815,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xE1", "EventName": "UNC_M2M_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -3100,8 +3826,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -3109,8 +3837,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -3118,8 +3848,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -3127,8 +3859,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -3136,8 +3870,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -3145,8 +3881,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -3154,8 +3892,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -3163,8 +3903,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -3172,8 +3914,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "UNC_M2M_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -3181,8 +3925,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3190,8 +3936,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3199,8 +3947,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3208,8 +3958,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3217,8 +3969,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3226,8 +3980,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3235,8 +3991,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3244,8 +4002,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3253,8 +4013,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3262,8 +4024,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3271,8 +4035,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3280,8 +4046,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3289,8 +4057,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3298,8 +4068,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3307,8 +4079,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3316,8 +4090,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3325,8 +4101,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3334,8 +4112,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3343,8 +4123,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3352,8 +4134,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3361,8 +4145,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3370,8 +4156,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3379,8 +4167,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3388,8 +4178,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3397,8 +4189,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3406,8 +4200,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3415,8 +4211,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3424,8 +4222,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -3433,8 +4233,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -3442,8 +4244,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -3451,8 +4255,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -3460,8 +4266,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xD6", "EventName": "UNC_M2M_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -3469,8 +4277,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3478,8 +4288,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3487,8 +4299,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3496,8 +4310,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3505,8 +4321,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3514,8 +4332,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD3", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3523,8 +4343,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3532,8 +4354,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3541,8 +4365,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3550,8 +4376,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -3559,8 +4387,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -3568,8 +4398,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xD7", "EventName": "UNC_M2M_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -3577,573 +4409,719 @@ }, { "BriefDescription": "Number AD Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2M_TGR_AD_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Number BL Ingress Credits", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_M2M_TGR_BL_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2M_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_M2M_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2M_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2M_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credit Acquired", + "Counter": "0,1,2,3", "EventCode": "0x0d", "EventName": "UNC_M2M_TxC_AD_CREDITS_ACQUIRED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Credits Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0e", "EventName": "UNC_M2M_TxC_AD_CREDIT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x0c", "EventName": "UNC_M2M_TxC_AD_CYCLES_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x0b", "EventName": "UNC_M2M_TxC_AD_CYCLES_NE", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_M2M_TxC_AD_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AD Egress (to CMS) Credits", + "Counter": "0,1,2,3", "EventCode": "0x0f", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AD Egress (to CMS) Cre= dits", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2M_TxC_AD_NO_CREDIT_STALLED", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AD Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_M2M_TxC_AD_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : CRD Transa= ctions to Cbo", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.CRD_CBO", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Outbound Ring Transactions on AK : NDR Transa= ctions", + "Counter": "0,1,2,3", "EventCode": "0x39", "EventName": "UNC_M2M_TxC_AK.NDR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AKC Credits", + "Counter": "0,1,2,3", "EventCode": "0x5F", "EventName": "UNC_M2M_TxC_AKC_CREDITS", + "Experimental": "1", "PerPkg": "1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1D", "EventName": "UNC_M2M_TxC_AK_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.RDCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x88", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCMP1", + "Experimental": "1", "PerPkg": "1", "UMask": "0xa0", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Full", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "UNC_M2M_TxC_AK_CYCLES_FULL.WRCRD1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x90", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "UNC_M2M_TxC_AK_CYCLES_NE.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.PREF_RD_CAM_HIT", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Allocations", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2M_TxC_AK_INSERTS.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No AK Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1F", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No AK Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M2M_TxC_AK_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : All", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.RDCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCMP", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "AK Egress (to CMS) Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M2M_TxC_AK_OCCUPANCY.WRCRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Cache", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CACHE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Outbound DRS Ring Transactions to Cache : Dat= a to Core", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2M_TxC_BL.DRS_CORE", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Credit Acquired : Common M= esh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2M_TxC_BL_CREDITS_ACQUIRED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : All", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Near Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Full : Common Mesh Stop - = Far Side", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2M_TxC_BL_CYCLES_FULL.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : All", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Not Empty : Common Mesh St= op - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2M_TxC_BL_CYCLES_NE.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x3", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "BL Egress (to CMS) Allocations : Common Mesh = Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2M_TxC_BL_INSERTS.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles with No BL Egress (to CMS) Credits : C= ommon Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1B", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_CYCLES.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Near Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Cycles Stalled with No BL Egress (to CMS) Cre= dits : Common Mesh Stop - Far Side", + "Counter": "0,1,2,3", "EventCode": "0x1C", "EventName": "UNC_M2M_TxC_BL_NO_CREDIT_STALLED.CMS1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4151,8 +5129,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -4160,8 +5140,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -4169,8 +5151,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4178,8 +5162,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -4187,8 +5173,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "UNC_M2M_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -4196,8 +5184,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4205,8 +5195,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -4214,8 +5206,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -4223,8 +5217,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -4232,8 +5228,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -4241,8 +5239,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4250,8 +5250,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -4259,8 +5261,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -4268,8 +5272,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "UNC_M2M_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -4277,8 +5283,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4286,8 +5294,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -4295,8 +5305,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -4304,8 +5316,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -4313,8 +5327,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -4322,8 +5338,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4331,8 +5349,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -4340,8 +5360,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -4349,8 +5371,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -4358,8 +5382,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4367,8 +5393,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -4376,8 +5404,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -4385,8 +5415,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -4394,8 +5426,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -4403,8 +5437,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4412,8 +5448,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -4421,8 +5459,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -4430,8 +5470,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xA3", "EventName": "UNC_M2M_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -4439,8 +5481,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4448,8 +5492,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -4457,8 +5503,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -4466,8 +5514,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -4475,8 +5525,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -4484,8 +5536,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4493,8 +5547,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -4502,8 +5558,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -4511,8 +5569,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xA1", "EventName": "UNC_M2M_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -4520,8 +5580,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -4529,8 +5591,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -4538,8 +5602,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -4547,8 +5613,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -4556,8 +5624,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -4565,8 +5635,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -4574,8 +5646,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -4583,8 +5657,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -4592,8 +5668,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xA4", "EventName": "UNC_M2M_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -4601,8 +5679,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -4610,8 +5690,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -4619,8 +5701,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -4628,8 +5712,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -4637,8 +5723,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -4646,8 +5734,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -4655,8 +5745,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -4664,8 +5756,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -4673,8 +5767,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M2M_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -4682,8 +5778,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -4691,8 +5789,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -4700,8 +5800,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -4709,8 +5811,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -4718,8 +5822,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -4727,8 +5833,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -4736,8 +5844,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xA5", "EventName": "UNC_M2M_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -4745,8 +5855,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -4754,8 +5866,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -4763,8 +5877,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -4772,8 +5888,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9C", "EventName": "UNC_M2M_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -4781,8 +5899,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -4790,8 +5910,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -4799,8 +5921,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -4808,8 +5932,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -4817,8 +5943,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -4826,8 +5954,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -4835,8 +5965,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9D", "EventName": "UNC_M2M_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -4844,8 +5976,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -4853,8 +5987,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9E", "EventName": "UNC_M2M_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -4862,8 +5998,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -4871,8 +6009,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -4880,8 +6020,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4889,8 +6031,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -4898,8 +6042,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -4907,8 +6053,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -4916,8 +6064,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -4925,8 +6075,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -4934,8 +6086,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2M_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4943,8 +6097,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -4952,8 +6108,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -4961,8 +6119,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -4970,8 +6130,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -4979,8 +6141,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -4988,8 +6152,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -4997,8 +6163,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -5006,8 +6174,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -5015,8 +6185,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2M_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -5024,8 +6196,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5033,8 +6207,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -5042,8 +6218,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -5051,8 +6229,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5060,8 +6240,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -5069,8 +6251,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -5078,8 +6262,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2M_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -5087,8 +6273,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5096,8 +6284,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2M_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -5105,8 +6295,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5114,8 +6306,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -5123,8 +6317,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5132,8 +6328,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -5141,8 +6339,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -5150,8 +6350,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -5159,8 +6361,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2M_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -5168,8 +6372,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -5177,8 +6383,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2M_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -5186,8 +6394,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5195,8 +6405,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -5204,8 +6416,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -5213,8 +6427,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -5222,8 +6438,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -5231,8 +6449,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -5240,8 +6460,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -5249,8 +6471,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -5258,8 +6482,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2M_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -5267,8 +6493,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -5276,8 +6504,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -5285,8 +6515,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -5294,8 +6526,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -5303,8 +6537,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -5312,8 +6548,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -5321,8 +6559,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9A", "EventName": "UNC_M2M_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -5330,8 +6570,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -5339,8 +6581,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -5348,8 +6592,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9B", "EventName": "UNC_M2M_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -5357,8 +6603,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5366,8 +6614,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5375,8 +6625,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5384,8 +6636,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "UNC_M2M_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5393,8 +6647,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5402,8 +6658,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5411,8 +6669,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5420,8 +6680,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "UNC_M2M_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5429,8 +6691,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5438,8 +6702,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5447,8 +6713,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5456,8 +6724,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UNC_M2M_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5465,8 +6735,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5474,8 +6746,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5483,8 +6757,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -5492,8 +6768,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "UNC_M2M_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -5501,8 +6779,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -5510,8 +6790,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xB3", "EventName": "UNC_M2M_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -5519,8 +6801,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5528,8 +6812,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5537,8 +6823,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5546,8 +6834,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xB5", "EventName": "UNC_M2M_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5555,254 +6845,317 @@ }, { "BriefDescription": "WPQ Flush : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "WPQ Flush : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x58", "EventName": "UNC_M2M_WPQ_FLUSH.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Regular : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4D", "EventName": "UNC_M2M_WPQ_NO_REG_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 0", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 1", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "M2M->iMC WPQ Cycles w/Credits - Special : Cha= nnel 2", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "UNC_M2M_WPQ_NO_SPEC_CRD.CHN2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Full : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4A", "EventName": "UNC_M2M_WR_TRACKER_FULL.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UNC_M2M_WR_TRACKER_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x4B", "EventName": "UNC_M2M_WR_TRACKER_NE.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 0", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Non-Posted Occupancy : Channel = 1", + "Counter": "0,1,2,3", "EventCode": "0x62", "EventName": "UNC_M2M_WR_TRACKER_NONPOSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy : Mirror", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_NONTGR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "UNC_M2M_WR_TRACKER_OCCUPANCY.MIRR_PWR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Inserts : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5E", "EventName": "UNC_M2M_WR_TRACKER_POSTED_INSERTS.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 0", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2M" }, { "BriefDescription": "Write Tracker Posted Occupancy : Channel 1", + "Counter": "0,1,2,3", "EventCode": "0x5D", "EventName": "UNC_M2M_WR_TRACKER_POSTED_OCCUPANCY.CH1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2M" }, { "BriefDescription": "Clockticks in the UBOX using a dedicated 48-b= it Fixed Counter", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_U_CLOCKTICKS", "PerPkg": "1", @@ -5810,16 +7163,20 @@ }, { "BriefDescription": "Message Received : Doorbell", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.DOORBELL_RCVD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "Message Received : Interrupt", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.INT_PRIO", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : Interrupt : Interrupts", "UMask": "0x10", @@ -5827,8 +7184,10 @@ }, { "BriefDescription": "Message Received : IPI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.IPI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : IPI : Inter Processor Int= errupts", "UMask": "0x4", @@ -5836,8 +7195,10 @@ }, { "BriefDescription": "Message Received : MSI", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.MSI_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : MSI : Message Signaled In= terrupts - interrupts sent by devices (including PCIe via IOxAPIC) (Socket = Mode only)", "UMask": "0x2", @@ -5845,8 +7206,10 @@ }, { "BriefDescription": "Message Received : VLW", + "Counter": "0,1", "EventCode": "0x42", "EventName": "UNC_U_EVENT_MSG.VLW_RCVD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Message Received : VLW : Virtual Logical Wir= e (legacy) message were received from Uncore.", "UMask": "0x1", @@ -5854,128 +7217,160 @@ }, { "BriefDescription": "IDI Lock/SplitLock Cycles", + "Counter": "0,1", "EventCode": "0x44", "EventName": "UNC_U_LOCK_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IDI Lock/SplitLock Cycles : Number of times = an IDI Lock/SplitLock sequence was started", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.RxC_CYCLES_NE_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Counter": "0,1", "EventCode": "0x4D", "EventName": "UNC_U_M2U_MISC1.TxC_CYCLES_CRD_OVF_CBO_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.RxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_CRD_OVF_VN0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_EMPTY_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "UNC_U_M2U_MISC2.TxC_CYCLES_FULL_BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Counter": "0,1", "EventCode": "0x4F", "EventName": "UNC_U_M2U_MISC3.TxC_CYCLES_FULL_AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "Cycles PHOLD Assert to Ack : Assert to ACK", + "Counter": "0,1", "EventCode": "0x45", "EventName": "UNC_U_PHOLD_CYCLES.ASSERT_TO_ACK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles PHOLD Assert to Ack : Assert to ACK := PHOLD cycles.", "UMask": "0x1", @@ -5983,32 +7378,40 @@ }, { "BriefDescription": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.PFTCH_BUF_EMPTY", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDRAND", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDRAND", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "UBOX" }, { "BriefDescription": "UNC_U_RACU_DRNG.RDSEED", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "UNC_U_RACU_DRNG.RDSEED", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "UBOX" }, { "BriefDescription": "RACU Request", + "Counter": "0,1", "EventCode": "0x46", "EventName": "UNC_U_RACU_REQUESTS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "RACU Request : Number outstanding register r= equests within message channel tracker", "Unit": "UBOX" diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json b/too= ls/perf/pmu-events/arch/x86/snowridgex/uncore-io.json index de156e499f56..dff3c5a9f0d7 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-io.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "PCI Express bandwidth reading at IIO. Derived= from unc_iio_data_req_of_cpu.mem_read.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_READ", "FCMask": "0x07", @@ -16,6 +17,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO. Derived= from unc_iio_data_req_of_cpu.mem_write.part0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "LLC_MISSES.PCIE_WRITE", "FCMask": "0x07", @@ -31,70 +33,87 @@ }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART0_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART1_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x21", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART2_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x22", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART3_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x23", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART4_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x24", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "6", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART5_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x25", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "7", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART6_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x26", "Unit": "iio_free_running" }, { "BriefDescription": "Free running counter that increments for ever= y 32 bytes of data sent from the IO agent to the SOC", + "Counter": "8", "EventCode": "0xff", "EventName": "UNC_IIO_BANDWIDTH_IN.PART7_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x27", "Unit": "iio_free_running" }, { "BriefDescription": "Clockticks of the integrated IO (IIO) traffic= controller", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_IIO_CLOCKTICKS", "PerPkg": "1", @@ -102,6 +121,7 @@ }, { "BriefDescription": "Free running counter that increments for IIO = clocktick", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_IIO_CLOCKTICKS_FREERUN", "PerPkg": "1", @@ -111,8 +131,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts : All Ports", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PortMask": "0xFF", @@ -121,6 +143,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0-7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -132,6 +155,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 0", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART0", "FCMask": "0x04", @@ -143,6 +167,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 1", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART1", "FCMask": "0x04", @@ -154,6 +179,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 2", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART2", "FCMask": "0x04", @@ -165,6 +191,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 3", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART3", "FCMask": "0x04", @@ -176,6 +203,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 4", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART4", "FCMask": "0x04", @@ -187,6 +215,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 5", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART5", "FCMask": "0x04", @@ -198,6 +227,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 6", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART6", "FCMask": "0x04", @@ -209,6 +239,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Inserts of completions= with data: Part 7", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_COMP_BUF_INSERTS.CMPD.PART7", "FCMask": "0x04", @@ -220,8 +251,10 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xD5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL", + "Experimental": "1", "FCMask": "0x04", "PerPkg": "1", "PublicDescription": "PCIe Completion Buffer Occupancy : Part 0-7", @@ -230,6 +263,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0-7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.ALL_PARTS", "FCMask": "0x04", @@ -240,6 +274,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 0", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART0", "FCMask": "0x04", @@ -250,6 +285,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 1", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART1", "FCMask": "0x04", @@ -260,6 +296,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 2", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART2", "FCMask": "0x04", @@ -270,6 +307,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 3", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART3", "FCMask": "0x04", @@ -280,6 +318,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 4", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART4", "FCMask": "0x04", @@ -290,6 +329,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 5", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART5", "FCMask": "0x04", @@ -300,6 +340,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 6", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART6", "FCMask": "0x04", @@ -310,6 +351,7 @@ }, { "BriefDescription": "PCIe Completion Buffer Occupancy of completio= ns with data : Part 7", + "Counter": "2,3", "EventCode": "0xd5", "EventName": "UNC_IIO_COMP_BUF_OCCUPANCY.CMPD.PART7", "FCMask": "0x04", @@ -320,8 +362,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -331,8 +375,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -342,8 +388,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -353,8 +401,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -364,8 +414,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -375,8 +427,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -386,8 +440,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -397,8 +453,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -408,8 +466,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -419,8 +479,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -430,8 +492,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -441,8 +505,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -452,8 +518,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -463,8 +531,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -474,8 +544,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -485,8 +557,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -496,8 +570,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -507,8 +583,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -518,8 +596,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -529,8 +609,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's PCICFG space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -540,8 +622,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -551,8 +635,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -562,8 +648,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -573,8 +661,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -584,8 +674,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -595,8 +687,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -606,8 +700,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -617,8 +713,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -628,8 +726,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -639,8 +739,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reading from= Card's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -650,8 +752,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -661,8 +765,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -672,8 +778,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -683,8 +791,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -694,8 +804,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -705,8 +817,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -716,8 +830,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -727,8 +843,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -738,8 +856,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -749,8 +869,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's IO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -760,8 +882,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -771,8 +895,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -782,6 +908,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -793,6 +920,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -804,6 +932,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -815,6 +944,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -826,6 +956,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -837,6 +968,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -848,6 +980,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -859,6 +992,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core reporting co= mpletion of Card read from Core DRAM", + "Counter": "2,3", "EventCode": "0xc0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -870,8 +1004,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -881,8 +1017,10 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -892,6 +1030,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -903,6 +1042,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -914,6 +1054,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -925,6 +1066,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -936,6 +1078,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -947,6 +1090,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -958,6 +1102,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -969,6 +1114,7 @@ }, { "BriefDescription": "Data requested by the CPU : Core writing to C= ard's MMIO space", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -980,8 +1126,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -991,8 +1139,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1002,8 +1152,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1013,8 +1165,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1024,8 +1178,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1035,8 +1191,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1046,8 +1204,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1057,8 +1217,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1068,8 +1230,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1079,8 +1243,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) reading from this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1090,8 +1256,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1101,8 +1269,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1112,8 +1282,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1123,8 +1295,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1134,8 +1308,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1145,8 +1321,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1156,8 +1334,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1167,8 +1347,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1178,8 +1360,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1189,8 +1373,10 @@ }, { "BriefDescription": "Data requested by the CPU : Another card (dif= ferent IIO stack) writing to this card.", + "Counter": "2,3", "EventCode": "0xC0", "EventName": "UNC_IIO_DATA_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1200,8 +1386,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1211,8 +1399,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1222,8 +1412,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1233,8 +1425,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1244,8 +1438,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1255,8 +1451,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1266,8 +1464,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1277,8 +1477,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1288,8 +1490,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1299,8 +1503,10 @@ }, { "BriefDescription": "Data requested of the CPU : Atomic requests t= argeting DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1310,8 +1516,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1321,8 +1529,10 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1332,6 +1542,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -1343,6 +1554,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -1354,6 +1566,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -1365,6 +1578,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -1376,6 +1590,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -1387,6 +1602,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -1398,6 +1614,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -1409,6 +1626,7 @@ }, { "BriefDescription": "Data requested of the CPU : CmpD - device sen= ding completion to CPU request", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -1420,8 +1638,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1431,8 +1651,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1442,6 +1664,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -1453,6 +1676,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -1464,6 +1688,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -1475,6 +1700,7 @@ }, { "BriefDescription": "PCI Express bandwidth reading at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -1486,6 +1712,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -1497,6 +1724,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -1508,6 +1736,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -1519,6 +1748,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card read= ing from DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -1530,8 +1760,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1541,8 +1773,10 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1552,6 +1786,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 0", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -1563,6 +1798,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 1", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -1574,6 +1810,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 2", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -1585,6 +1822,7 @@ }, { "BriefDescription": "PCI Express bandwidth writing at IIO, part 3", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -1596,6 +1834,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -1607,6 +1846,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -1618,6 +1858,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -1629,6 +1870,7 @@ }, { "BriefDescription": "Four byte data request of the CPU : Card writ= ing to DRAM", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -1640,8 +1882,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1651,8 +1895,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1662,8 +1908,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1673,8 +1921,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1684,8 +1934,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1695,8 +1947,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1706,8 +1960,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1717,8 +1973,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1728,8 +1986,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1739,8 +1999,10 @@ }, { "BriefDescription": "Data requested of the CPU : Messages", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1750,8 +2012,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1761,8 +2025,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1772,8 +2038,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1783,8 +2051,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1794,8 +2064,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1805,8 +2077,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1816,8 +2090,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1827,8 +2103,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1838,8 +2116,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1849,8 +2129,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card reading from= another Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1860,8 +2142,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -1871,8 +2155,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -1882,8 +2168,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -1893,8 +2181,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -1904,8 +2194,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -1915,8 +2207,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -1926,8 +2220,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -1937,8 +2233,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -1948,8 +2246,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -1959,8 +2259,10 @@ }, { "BriefDescription": "Data requested of the CPU : Card writing to a= nother Card (same or different stack)", + "Counter": "0,1", "EventCode": "0x83", "EventName": "UNC_IIO_DATA_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -1970,8 +2272,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Passing data = to be written", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1981,8 +2285,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing final= read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -1992,8 +2298,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Processing re= sponse from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2003,8 +2311,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Issuing to IO= MMU", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2014,8 +2324,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Request Owner= ship", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2025,8 +2337,10 @@ }, { "BriefDescription": "Incoming arbitration requests : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_IIO_INBOUND_ARB_REQ.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2036,8 +2350,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Passi= ng data to be written", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2047,8 +2363,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng final read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2058,8 +2376,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Proce= ssing response from IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2069,8 +2389,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Issui= ng to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2080,8 +2402,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Reque= st Ownership", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2091,8 +2415,10 @@ }, { "BriefDescription": "Incoming arbitration requests granted : Writi= ng line", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_IIO_INBOUND_ARB_WON.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2102,8 +2428,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 1G Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 1G Page : Counts if a tran= saction to a 1G page, on its first lookup, hits the IOTLB.", "UMask": "0x10", @@ -2111,8 +2439,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 2M Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 2M Page : Counts if a tran= saction to a 2M page, on its first lookup, hits the IOTLB.", "UMask": "0x8", @@ -2120,8 +2450,10 @@ }, { "BriefDescription": ": IOTLB Hits to a 4K Page", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Hits to a 4K Page : Counts if a tran= saction to a 4K page, on its first lookup, hits the IOTLB.", "UMask": "0x4", @@ -2129,8 +2461,10 @@ }, { "BriefDescription": ": IOTLB lookups all", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.ALL_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups all : Some transactions have= to look up IOTLB multiple times. Counts every time a request looks up IOT= LB.", "UMask": "0x2", @@ -2138,8 +2472,10 @@ }, { "BriefDescription": ": Context cache hits", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache hits : Counts each time a fi= rst look up of the transaction hits the RCC.", "UMask": "0x80", @@ -2147,8 +2483,10 @@ }, { "BriefDescription": ": Context cache lookups", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.CTXT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache lookups : Counts each time a= transaction looks up root context cache.", "UMask": "0x40", @@ -2156,8 +2494,10 @@ }, { "BriefDescription": ": IOTLB lookups first", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.FIRST_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB lookups first : Some transactions ha= ve to look up IOTLB multiple times. Counts the first time a request looks = up IOTLB.", "UMask": "0x1", @@ -2165,8 +2505,10 @@ }, { "BriefDescription": ": IOTLB Fills (same as IOTLB miss)", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_IIO_IOMMU0.MISSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOTLB Fills (same as IOTLB miss) : When a = transaction misses IOTLB, it does a page walk to look up memory and bring i= n the relevant page translation. Counts when this page translation is writt= en to IOTLB.", "UMask": "0x20", @@ -2174,8 +2516,10 @@ }, { "BriefDescription": ": Cycles PWT full", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.CYC_PWT_FULL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Cycles PWT full : Counts cycles the IOMMU = has reached its maximum limit for outstanding page walks.", "UMask": "0x80", @@ -2183,8 +2527,10 @@ }, { "BriefDescription": ": IOMMU memory access", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.NUM_MEM_ACCESSES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": IOMMU memory access : IOMMU sends out memo= ry fetches when it misses the cache look up which is indicated by this sign= al. M2IOSF only uses low priority channel", "UMask": "0x40", @@ -2192,8 +2538,10 @@ }, { "BriefDescription": ": PWC Hit to a 1G page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_1G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 1G page : Counts each time a = transaction's first look up hits the SLPWC at the 1G level", "UMask": "0x8", @@ -2201,8 +2549,10 @@ }, { "BriefDescription": ": PWC Hit to a 2M page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_2M_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 2M page : Counts each time a = transaction's first look up hits the SLPWC at the 2M level", "UMask": "0x4", @@ -2210,8 +2560,10 @@ }, { "BriefDescription": ": PWC Hit to a 4K page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_4K_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWC Hit to a 4K page : Counts each time a = transaction's first look up hits the SLPWC at the 4K level", "UMask": "0x2", @@ -2219,8 +2571,10 @@ }, { "BriefDescription": ": PWT Hit to a 256T page", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_512G_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PWT Hit to a 256T page : Counts each time = a transaction's first look up hits the SLPWC at the 512G level", "UMask": "0x10", @@ -2228,8 +2582,10 @@ }, { "BriefDescription": ": PageWalk cache fill", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWC_CACHE_FILLS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache fill : When a transaction m= isses SLPWC, it does a page walk to look up memory and bring in the relevan= t page translation. When this page translation is written to SLPWC, ObsPwcF= illValid_nnnH is asserted.", "UMask": "0x20", @@ -2237,8 +2593,10 @@ }, { "BriefDescription": ": PageWalk cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_IIO_IOMMU1.PWT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": PageWalk cache lookup : Counts each time a= transaction looks up second level page walk cache.", "UMask": "0x1", @@ -2246,8 +2604,10 @@ }, { "BriefDescription": ": Interrupt Entry cache hit", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_HITS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache hit : Counts each ti= me a transaction's first look up hits the IEC.", "UMask": "0x80", @@ -2255,8 +2615,10 @@ }, { "BriefDescription": ": Interrupt Entry cache lookup", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.INT_CACHE_LOOKUPS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Interrupt Entry cache lookup : Counts the = number of transaction looks up that interrupt remapping cache.", "UMask": "0x40", @@ -2264,8 +2626,10 @@ }, { "BriefDescription": ": Device-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DEVICE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Device-selective Context cache invalidatio= n cycles : Counts number of Device selective context cache invalidation eve= nts", "UMask": "0x20", @@ -2273,8 +2637,10 @@ }, { "BriefDescription": ": Domain-selective Context cache invalidation= cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective Context cache invalidatio= n cycles : Counts number of Domain selective context cache invalidation eve= nts", "UMask": "0x10", @@ -2282,8 +2648,10 @@ }, { "BriefDescription": ": Context cache global invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_CTXT_CACHE_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Context cache global invalidation cycles := Counts number of Context Cache global invalidation events", "UMask": "0x8", @@ -2291,8 +2659,10 @@ }, { "BriefDescription": ": Domain-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_DOMAIN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Domain-selective IOTLB invalidation cycles= : Counts number of Domain selective invalidation events", "UMask": "0x2", @@ -2300,8 +2670,10 @@ }, { "BriefDescription": ": Global IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_GBL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Global IOTLB invalidation cycles : Indicat= es that IOMMU is doing global invalidation.", "UMask": "0x1", @@ -2309,8 +2681,10 @@ }, { "BriefDescription": ": Page-selective IOTLB invalidation cycles", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_IIO_IOMMU3.NUM_INVAL_PAGE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": ": Page-selective IOTLB invalidation cycles := Counts number of Page-selective within Domain Invalidation events", "UMask": "0x4", @@ -2318,8 +2692,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = : Asserted if all bits specified by mask match", "UMask": "0x1", @@ -2327,8 +2703,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x8", @@ -2336,8 +2714,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : Non-PCIE bus = and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x4", @@ -2345,8 +2725,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : PCIE bus : As= serted if all bits specified by mask match", "UMask": "0x2", @@ -2354,8 +2736,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and PCIE bus : Asserted if all bits specified by mask match", "UMask": "0x10", @@ -2363,8 +2747,10 @@ }, { "BriefDescription": "AND Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x02", "EventName": "UNC_IIO_MASK_MATCH_AND.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "AND Mask/match for debug bus : !(Non-PCIE bu= s) and !(PCIE bus) : Asserted if all bits specified by mask match", "UMask": "0x20", @@ -2372,8 +2758,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus := Asserted if any bits specified by mask match", "UMask": "0x1", @@ -2381,8 +2769,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x8", @@ -2390,8 +2780,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : Non-PCIE bus an= d !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : Non-PCIE bus a= nd !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x4", @@ -2399,8 +2791,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : PCIE bus : Ass= erted if any bits specified by mask match", "UMask": "0x2", @@ -2408,8 +2802,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and PCIE bus", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and PCIE bus : Asserted if any bits specified by mask match", "UMask": "0x10", @@ -2417,8 +2813,10 @@ }, { "BriefDescription": "OR Mask/match for debug bus : !(Non-PCIE bus)= and !(PCIE bus)", + "Counter": "0,1", "EventCode": "0x03", "EventName": "UNC_IIO_MASK_MATCH_OR.NOT_BUS0_NOT_BUS1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "OR Mask/match for debug bus : !(Non-PCIE bus= ) and !(PCIE bus) : Asserted if any bits specified by mask match", "UMask": "0x20", @@ -2426,15 +2824,19 @@ }, { "BriefDescription": "Counting disabled", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_IIO_NOTHING", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Occupancy of outbound request queue : To devi= ce", + "Counter": "2,3", "EventCode": "0xC5", "EventName": "UNC_IIO_NUM_OUSTANDING_REQ_FROM_CPU.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2444,8 +2846,10 @@ }, { "BriefDescription": ": Passing data to be written", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2455,8 +2859,10 @@ }, { "BriefDescription": ": Issuing final read or write of line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2465,8 +2871,10 @@ }, { "BriefDescription": ": Processing response from IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2475,8 +2883,10 @@ }, { "BriefDescription": ": Issuing to IOMMU", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2485,8 +2895,10 @@ }, { "BriefDescription": ": Request Ownership", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2496,8 +2908,10 @@ }, { "BriefDescription": ": Writing line", + "Counter": "2,3", "EventCode": "0x88", "EventName": "UNC_IIO_NUM_OUTSTANDING_REQ_OF_CPU.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2507,8 +2921,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = From ITC", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.ITC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2518,8 +2934,10 @@ }, { "BriefDescription": "Number requests sent to PCIe from main die : = Completion allocations", + "Counter": "0,1,2,3", "EventCode": "0xc2", "EventName": "UNC_IIO_NUM_REQ_FROM_CPU.PREALLOC", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2528,8 +2946,10 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = Drop request", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.ALL.DROP", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2539,6 +2959,7 @@ }, { "BriefDescription": "Number requests PCIe makes of the main die : = All", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_IIO_NUM_REQ_OF_CPU.COMMIT.ALL", "FCMask": "0x07", @@ -2550,8 +2971,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Abort= ", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.ABORT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2560,8 +2983,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Confi= ned P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.CONFINED_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2570,8 +2995,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Local= P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.LOC_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2580,8 +3007,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Multi= -cast", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MCAST", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2590,8 +3019,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Memor= y", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MEM", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2600,8 +3031,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : MsgB", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.MSGB", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2610,8 +3043,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Remot= e P2P", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.REM_P2P", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2620,8 +3055,10 @@ }, { "BriefDescription": "Num requests sent by PCIe - by target : Ubox", + "Counter": "0,1,2,3", "EventCode": "0x8E", "EventName": "UNC_IIO_NUM_REQ_OF_CPU_BY_TGT.UBOX", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2630,15 +3067,19 @@ }, { "BriefDescription": "ITC address map 1", + "Counter": "0,1,2,3", "EventCode": "0x8F", "EventName": "UNC_IIO_NUM_TGT_MATCHED_REQ_OF_CPU", + "Experimental": "1", "PerPkg": "1", "Unit": "IIO" }, { "BriefDescription": "Outbound cacheline requests issued : 64B requ= ests issued to device", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "UNC_IIO_OUTBOUND_CL_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2648,8 +3089,10 @@ }, { "BriefDescription": "Outbound TLP (transaction layer packet) reque= sts issued : To device", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UNC_IIO_OUTBOUND_TLP_REQS_ISSUED.TO_IO", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2659,16 +3102,20 @@ }, { "BriefDescription": "PWT occupancy", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_IIO_PWT_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "PWT occupancy : Indicates how many page walk= s are outstanding at any point in time.", "Unit": "IIO" }, { "BriefDescription": "PCIe Request - cacheline complete : Passing d= ata to be written", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2678,8 +3125,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Issuing f= inal read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2689,8 +3138,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Request O= wnership", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2700,8 +3151,10 @@ }, { "BriefDescription": "PCIe Request - cacheline complete : Writing l= ine", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_IIO_REQ_FROM_PCIE_CL_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2711,8 +3164,10 @@ }, { "BriefDescription": "PCIe Request complete : Passing data to be wr= itten", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2722,8 +3177,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing final read or= write of line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2733,8 +3190,10 @@ }, { "BriefDescription": "PCIe Request complete : Processing response f= rom IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_HIT", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2744,8 +3203,10 @@ }, { "BriefDescription": "PCIe Request complete : Issuing to IOMMU", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.IOMMU_REQ", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2755,8 +3216,10 @@ }, { "BriefDescription": "PCIe Request complete : Request Ownership", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2766,8 +3229,10 @@ }, { "BriefDescription": "PCIe Request complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_IIO_REQ_FROM_PCIE_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2777,8 +3242,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Passing data t= o be written", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.DATA", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2788,8 +3255,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Issuing final = read or write of line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.FINAL_RD_WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2799,8 +3268,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Request Owners= hip", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.REQ_OWN", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2810,8 +3281,10 @@ }, { "BriefDescription": "PCIe Request - pass complete : Writing line", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_IIO_REQ_FROM_PCIE_PASS_CMPL.WR", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0xFF", @@ -2821,16 +3294,20 @@ }, { "BriefDescription": "Symbol Times on Link", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_IIO_SYMBOL_TIMES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Symbol Times on Link : Gen1 - increment once= every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1n= S", "Unit": "IIO" }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2840,8 +3317,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2851,8 +3330,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2862,8 +3343,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2873,8 +3356,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2884,8 +3369,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -2895,8 +3382,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -2906,8 +3395,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -2917,8 +3408,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -2928,8 +3421,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -2939,8 +3434,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -2950,8 +3447,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -2961,8 +3460,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -2972,8 +3473,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -2983,8 +3486,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -2994,8 +3499,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3005,8 +3512,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3016,8 +3525,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3027,8 +3538,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3038,8 +3551,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's PCICFG space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.CFG_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3049,8 +3564,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3060,8 +3577,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3071,8 +3590,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3082,8 +3603,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3093,8 +3616,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3104,8 +3629,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3115,8 +3642,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3126,8 +3655,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3137,8 +3668,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3148,8 +3681,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3159,8 +3694,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3170,8 +3707,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3181,8 +3720,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3192,8 +3733,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3203,8 +3746,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3214,8 +3759,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3225,8 +3772,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3236,8 +3785,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3247,8 +3798,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3258,8 +3811,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's IO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.IO_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3269,8 +3824,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3280,8 +3837,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3291,6 +3850,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3302,6 +3862,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3313,6 +3874,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3324,6 +3886,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3335,6 +3898,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3346,6 +3910,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -3357,6 +3922,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -3368,6 +3934,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re reading from Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -3379,8 +3946,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3390,8 +3959,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3401,6 +3972,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -3412,6 +3984,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -3423,6 +3996,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -3434,6 +4008,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -3445,6 +4020,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -3456,6 +4032,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -3467,6 +4044,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -3478,6 +4056,7 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : Co= re writing to Card's MMIO space", + "Counter": "0,1,2,3", "EventCode": "0xc1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -3489,8 +4068,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3500,8 +4081,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3511,8 +4094,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3522,8 +4107,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3533,8 +4120,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3544,8 +4133,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3555,8 +4146,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3566,8 +4159,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3577,8 +4172,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3588,8 +4185,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) reading from this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3599,8 +4198,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3610,8 +4211,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3621,8 +4224,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3632,8 +4237,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3643,8 +4250,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3654,8 +4263,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3665,8 +4276,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3676,8 +4289,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3687,8 +4302,10 @@ }, { "BriefDescription": "Number Transactions requested by the CPU : An= other card (different IIO stack) writing to this card.", + "Counter": "0,1,2,3", "EventCode": "0xC1", "EventName": "UNC_IIO_TXN_REQ_BY_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3698,8 +4315,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3709,8 +4328,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3720,8 +4341,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -3731,8 +4354,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -3742,8 +4367,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -3753,8 +4380,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -3764,8 +4393,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -3775,8 +4406,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -3786,8 +4419,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -3797,8 +4432,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : At= omic requests targeting DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.ATOMIC.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -3808,8 +4445,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3819,8 +4458,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3830,6 +4471,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART0", "FCMask": "0x07", @@ -3841,6 +4483,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART1", "FCMask": "0x07", @@ -3852,6 +4495,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART2", "FCMask": "0x07", @@ -3863,6 +4507,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART3", "FCMask": "0x07", @@ -3874,6 +4519,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART4", "FCMask": "0x07", @@ -3885,6 +4531,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART5", "FCMask": "0x07", @@ -3896,6 +4543,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART6", "FCMask": "0x07", @@ -3907,6 +4555,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Cm= pD - device sending completion to CPU request", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.CMPD.PART7", "FCMask": "0x07", @@ -3918,8 +4567,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -3929,8 +4580,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -3940,6 +4593,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART0", "FCMask": "0x07", @@ -3951,6 +4605,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART1", "FCMask": "0x07", @@ -3962,6 +4617,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART2", "FCMask": "0x07", @@ -3973,6 +4629,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART3", "FCMask": "0x07", @@ -3984,6 +4641,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART4", "FCMask": "0x07", @@ -3995,6 +4653,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART5", "FCMask": "0x07", @@ -4006,6 +4665,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART6", "FCMask": "0x07", @@ -4017,6 +4677,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_READ.PART7", "FCMask": "0x07", @@ -4028,8 +4689,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4039,8 +4702,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4050,6 +4715,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART0", "FCMask": "0x07", @@ -4061,6 +4727,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART1", "FCMask": "0x07", @@ -4072,6 +4739,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART2", "FCMask": "0x07", @@ -4083,6 +4751,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART3", "FCMask": "0x07", @@ -4094,6 +4763,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART4", "FCMask": "0x07", @@ -4105,6 +4775,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART5", "FCMask": "0x07", @@ -4116,6 +4787,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART6", "FCMask": "0x07", @@ -4127,6 +4799,7 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to DRAM", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MEM_WRITE.PART7", "FCMask": "0x07", @@ -4138,8 +4811,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4149,8 +4824,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4160,8 +4837,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4171,8 +4850,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4182,8 +4863,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4193,8 +4876,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4204,8 +4889,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4215,8 +4902,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4226,8 +4915,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4237,8 +4928,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Me= ssages", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.MSG.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4248,8 +4941,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4259,8 +4954,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4270,8 +4967,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4281,8 +4980,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4292,8 +4993,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4303,8 +5006,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4314,8 +5019,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4325,8 +5032,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4336,8 +5045,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4347,8 +5058,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd reading from another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_READ.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4358,8 +5071,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x100", @@ -4369,8 +5084,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.IOMMU1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x200", @@ -4380,8 +5097,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART0", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x01", @@ -4391,8 +5110,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART1", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x02", @@ -4402,8 +5123,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART2", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x04", @@ -4413,8 +5136,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART3", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x08", @@ -4424,8 +5149,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART4", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x10", @@ -4435,8 +5162,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART5", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x20", @@ -4446,8 +5175,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART6", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x40", @@ -4457,8 +5188,10 @@ }, { "BriefDescription": "Number Transactions requested of the CPU : Ca= rd writing to another Card (same or different stack)", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_IIO_TXN_REQ_OF_CPU.PEER_WRITE.PART7", + "Experimental": "1", "FCMask": "0x07", "PerPkg": "1", "PortMask": "0x80", @@ -4468,8 +5201,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4477,8 +5212,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4486,8 +5223,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4495,8 +5234,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4504,8 +5245,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4513,8 +5256,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4522,8 +5267,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4531,8 +5278,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4540,8 +5289,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4549,8 +5300,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4558,8 +5311,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M2P_AG0_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4567,8 +5322,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4576,8 +5333,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4585,8 +5344,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4594,8 +5355,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4603,8 +5366,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4612,8 +5377,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4621,8 +5388,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4630,8 +5399,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4639,8 +5410,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4648,8 +5421,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4657,8 +5432,10 @@ }, { "BriefDescription": "CMS Agent0 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M2P_AG0_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4666,8 +5443,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4675,8 +5454,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4684,8 +5465,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4693,8 +5476,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4702,8 +5487,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4711,8 +5498,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4720,8 +5509,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4729,8 +5520,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4738,8 +5531,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4747,8 +5542,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4756,8 +5553,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "UNC_M2P_AG0_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 0 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4765,8 +5564,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4774,8 +5575,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4783,8 +5586,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4792,8 +5597,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4801,8 +5608,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -4810,8 +5619,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -4819,8 +5630,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -4828,8 +5641,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8a", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -4837,8 +5652,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 0 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -4846,8 +5663,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4855,8 +5674,10 @@ }, { "BriefDescription": "CMS Agent0 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8b", "EventName": "UNC_M2P_AG0_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent0 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 0 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4864,8 +5685,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4873,8 +5696,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4882,8 +5707,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -4891,8 +5718,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -4900,8 +5729,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -4909,8 +5740,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -4918,8 +5751,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 6", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 6 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -4927,8 +5762,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 7", + "Counter": "0,1,2,3", "EventCode": "0x84", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 7 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -4936,8 +5773,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -4945,8 +5784,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -4954,8 +5795,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M2P_AG1_AD_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 AD credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -4963,8 +5806,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -4972,8 +5817,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -4981,8 +5828,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -4990,8 +5839,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -4999,8 +5850,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -5008,8 +5861,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -5017,8 +5872,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -5026,8 +5883,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5035,8 +5894,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 AD credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5044,8 +5905,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5053,8 +5916,10 @@ }, { "BriefDescription": "CMS Agent1 AD Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "UNC_M2P_AG1_AD_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 AD Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 AD credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5062,8 +5927,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 0", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 0 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5071,8 +5938,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 1", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 1 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5080,8 +5949,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 2", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 2 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x4", @@ -5089,8 +5960,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 3", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 3 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x8", @@ -5098,8 +5971,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x10", @@ -5107,8 +5982,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x20", @@ -5116,8 +5993,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 4", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 4 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x40", @@ -5125,8 +6004,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 5", + "Counter": "0,1,2,3", "EventCode": "0x8c", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 5 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x80", @@ -5134,8 +6015,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 10", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 10 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tr= ansgress.", "UMask": "0x4", @@ -5143,8 +6026,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 8", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 8 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x1", @@ -5152,8 +6037,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Acquired : For Transgre= ss 9", + "Counter": "0,1,2,3", "EventCode": "0x8d", "EventName": "UNC_M2P_AG1_BL_CRD_ACQUIRED1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Acquired : For Transgr= ess 9 : Number of CMS Agent 1 BL credits acquired in a given cycle, per tra= nsgress.", "UMask": "0x2", @@ -5161,8 +6048,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 0", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 0 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5170,8 +6059,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 1", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 1 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5179,8 +6070,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 2", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 2 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x4", @@ -5188,8 +6081,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 3", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 3 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x8", @@ -5197,8 +6092,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 4", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 4 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x10", @@ -5206,8 +6103,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 5", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 5 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x20", @@ -5215,8 +6114,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 6", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 6 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x40", @@ -5224,8 +6125,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 7", + "Counter": "0,1,2,3", "EventCode": "0x8e", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 7 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x80", @@ -5233,8 +6136,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 10", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 10 : Number of CMS Agent 1 BL credits in use in a given cycle, per tra= nsgress", "UMask": "0x4", @@ -5242,8 +6147,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 8", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 8 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x1", @@ -5251,8 +6158,10 @@ }, { "BriefDescription": "CMS Agent1 BL Credits Occupancy : For Transgr= ess 9", + "Counter": "0,1,2,3", "EventCode": "0x8f", "EventName": "UNC_M2P_AG1_BL_CRD_OCCUPANCY1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Agent1 BL Credits Occupancy : For Transg= ress 9 : Number of CMS Agent 1 BL credits in use in a given cycle, per tran= sgress", "UMask": "0x2", @@ -5260,6 +6169,7 @@ }, { "BriefDescription": "Clockticks of the mesh to PCI (M2P)", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M2P_CLOCKTICKS", "PerPkg": "1", @@ -5267,6 +6177,7 @@ }, { "BriefDescription": "CMS Clockticks", + "Counter": "0,1,2,3", "EventCode": "0xc0", "EventName": "UNC_M2P_CMS_CLOCKTICKS", "PerPkg": "1", @@ -5274,8 +6185,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Local", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_LOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Local : Count= s the number of cycles either the local or incoming distress signals are as= serted. : Dynamic Prefetch Throttle triggered by this tile", "UMask": "0x4", @@ -5283,8 +6196,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Remote", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_NONLOCAL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Remote : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : Dynamic Prefetch Throttle received by this tile", "UMask": "0x8", @@ -5292,8 +6207,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - IV", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - IV = : Counts the number of cycles either the local or incoming distress signals= are asserted. : DPT occurred while regular IVs were received, causing DPT = to be stalled", "UMask": "0x40", @@ -5301,8 +6218,10 @@ }, { "BriefDescription": "Distress signal asserted : DPT Stalled - No = Credit", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.DPT_STALL_NOCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : DPT Stalled - No= Credit : Counts the number of cycles either the local or incoming distress= signals are asserted. : DPT occurred while credit not available causing DP= T to be stalled", "UMask": "0x80", @@ -5310,8 +6229,10 @@ }, { "BriefDescription": "Distress signal asserted : Horizontal", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.HORZ", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Horizontal : Coun= ts the number of cycles either the local or incoming distress signals are a= sserted. : If TGR egress is full, then agents will throttle outgoing AD IDI= transactions", "UMask": "0x2", @@ -5319,8 +6240,10 @@ }, { "BriefDescription": "Distress signal asserted : Vertical", + "Counter": "0,1,2,3", "EventCode": "0xaf", "EventName": "UNC_M2P_DISTRESS_ASSERTED.VERT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Distress signal asserted : Vertical : Counts= the number of cycles either the local or incoming distress signals are ass= erted. : If IRQ egress is full, then agents will throttle outgoing AD IDI t= ransactions", "UMask": "0x1", @@ -5328,8 +6251,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Down", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Down : Counts number of cycles IV was blocked in the TGR Egress due to S= NP/GO Ordering requirements", "UMask": "0x4", @@ -5337,8 +6262,10 @@ }, { "BriefDescription": "Egress Blocking due to Ordering requirements = : Up", + "Counter": "0,1,2,3", "EventCode": "0xba", "EventName": "UNC_M2P_EGRESS_ORDERING.IV_SNOOPGO_UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress Blocking due to Ordering requirements= : Up : Counts number of cycles IV was blocked in the TGR Egress due to SNP= /GO Ordering requirements", "UMask": "0x1", @@ -5346,8 +6273,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5355,8 +6284,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AD ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop. We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5364,8 +6295,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AD ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop. We really have two rings -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5373,8 +6306,10 @@ }, { "BriefDescription": "Horizontal AD Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb6", "EventName": "UNC_M2P_HORZ_RING_AD_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AD Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AD ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop. We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5382,8 +6317,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5391,8 +6328,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AKC ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings in JKT -- a clockwise ring and a counter-c= lockwise ring. On the left side of the ring, the UP direction is on the cl= ockwise ring and DN is on the counter-clockwise ring. On the right side of= the ring, this is reversed. The first half of the CBos are on the left si= de of the ring, and the 2nd half are on the right side of the ring. In oth= er words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as C= Bo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5400,8 +6339,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AKC ring is being used at = this ring stop. This includes when packets are passing by and when packets= are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings in JKT -- a clockwise ring and a counter= -clockwise ring. On the left side of the ring, the UP direction is on the = clockwise ring and DN is on the counter-clockwise ring. On the right side = of the ring, this is reversed. The first half of the CBos are on the left = side of the ring, and the 2nd half are on the right side of the ring. In o= ther words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as= CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5409,8 +6350,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xbb", "EventName": "UNC_M2P_HORZ_RING_AKC_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AKC ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings in JKT -- a clockwise ring and a counter-= clockwise ring. On the left side of the ring, the UP direction is on the c= lockwise ring and DN is on the counter-clockwise ring. On the right side o= f the ring, this is reversed. The first half of the CBos are on the left s= ide of the ring, and the 2nd half are on the right side of the ring. In ot= her words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as = CBo 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5418,8 +6361,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Even : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5427,8 +6372,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Left and Odd : C= ounts the number of cycles that the Horizontal AK ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the rin= g stop.We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5436,8 +6383,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Even := Counts the number of cycles that the Horizontal AK ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5445,8 +6394,10 @@ }, { "BriefDescription": "Horizontal AK Ring In Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb7", "EventName": "UNC_M2P_HORZ_RING_AK_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal AK Ring In Use : Right and Odd : = Counts the number of cycles that the Horizontal AK ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5454,8 +6405,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Even : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -5463,8 +6416,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Left and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.LEFT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Left and Odd : C= ounts the number of cycles that the Horizontal BL ring is being used at thi= s ring stop. This includes when packets are passing by and when packets ar= e being sunk, but does not include when packets are being sent from the ri= ng stop.We really have two rings -- a clockwise ring and a counter-clockwis= e ring. On the left side of the ring, the UP direction is on the clockwise= ring and DN is on the counter-clockwise ring. On the right side of the ri= ng, this is reversed. The first half of the CBos are on the left side of t= he ring, and the 2nd half are on the right side of the ring. In other word= s (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP= AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -5472,8 +6427,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Even", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Even := Counts the number of cycles that the Horizontal BL ring is being used at t= his ring stop. This includes when packets are passing by and when packets = are being sunk, but does not include when packets are being sent from the = ring stop.We really have two rings -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -5481,8 +6438,10 @@ }, { "BriefDescription": "Horizontal BL Ring in Use : Right and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb8", "EventName": "UNC_M2P_HORZ_RING_BL_IN_USE.RIGHT_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal BL Ring in Use : Right and Odd : = Counts the number of cycles that the Horizontal BL ring is being used at th= is ring stop. This includes when packets are passing by and when packets a= re being sunk, but does not include when packets are being sent from the r= ing stop.We really have two rings -- a clockwise ring and a counter-clockwi= se ring. On the left side of the ring, the UP direction is on the clockwis= e ring and DN is on the counter-clockwise ring. On the right side of the r= ing, this is reversed. The first half of the CBos are on the left side of = the ring, and the 2nd half are on the right side of the ring. In other wor= ds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 U= P AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -5490,8 +6449,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Left", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.LEFT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Left : Counts th= e number of cycles that the Horizontal IV ring is being used at this ring s= top. This includes when packets are passing by and when packets are being = sunk, but does not include when packets are being sent from the ring stop. = There is only 1 IV ring. Therefore, if one wants to monitor the Even ring= , they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, th= ey should select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -5499,8 +6460,10 @@ }, { "BriefDescription": "Horizontal IV Ring in Use : Right", + "Counter": "0,1,2,3", "EventCode": "0xb9", "EventName": "UNC_M2P_HORZ_RING_IV_IN_USE.RIGHT", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Horizontal IV Ring in Use : Right : Counts t= he number of cycles that the Horizontal IV ring is being used at this ring = stop. This includes when packets are passing by and when packets are being= sunk, but does not include when packets are being sent from the ring stop.= There is only 1 IV ring. Therefore, if one wants to monitor the Even rin= g, they should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, t= hey should select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -5508,8 +6471,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x1", @@ -5517,8 +6482,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : DRS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : DRS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the DRS message class.", "UMask": "0x2", @@ -5526,8 +6493,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x4", @@ -5535,8 +6504,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCB", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCB : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCB message class.", "UMask": "0x8", @@ -5544,8 +6515,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credits f= or transfer through CMS Port 0 to the IIO for the NCS message class.", "UMask": "0x10", @@ -5553,8 +6526,10 @@ }, { "BriefDescription": "M2PCIe IIO Credit Acquired : NCS", + "Counter": "0,1,2,3", "EventCode": "0x33", "EventName": "UNC_M2P_IIO_CREDITS_ACQUIRED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credit Acquired : NCS : Counts th= e number of credits that are acquired in the M2PCIe agent for sending trans= actions into the IIO on either NCB or NCS are in use. Transactions from th= e BL ring going into the IIO Agent must first acquire a credit. These cred= its are for either the NCB or NCS message classes. NCB, or non-coherent by= pass messages are used to transmit data without coherency (and are common).= NCS is used for reads to PCIe (and should be used sparingly). : Credit fo= r transfer through CMS Port 0s to the IIO for the NCS message class.", "UMask": "0x20", @@ -5562,8 +6537,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.DRS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : DRS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the DRS message class.", "UMask": "0x8", @@ -5571,8 +6548,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCB = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCB message class.", "UMask": "0x10", @@ -5580,8 +6559,10 @@ }, { "BriefDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS", + "Counter": "0,1,2,3", "EventCode": "0x34", "EventName": "UNC_M2P_IIO_CREDITS_REJECT.NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Failed to Acquire a Credit : NCS = : Counts the number of times that a request pending in the BL Ingress attem= pted to acquire either a NCB or NCS credit to transmit into the IIO, but wa= s rejected because no credits were available. NCB, or non-coherent bypass = messages are used to transmit data without coherency (and are common). NCS= is used for reads to PCIe (and should be used sparingly). : Credits to the= IIO for the NCS message class.", "UMask": "0x20", @@ -5589,8 +6570,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x1", @@ -5598,8 +6581,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.DRS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : DRS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the DRS me= ssage class.", "UMask": "0x2", @@ -5607,8 +6592,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x4", @@ -5616,8 +6603,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCB_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCB to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCB me= ssage class.", "UMask": "0x8", @@ -5625,8 +6614,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 0= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 0 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credits for transfer through CMS Port 0 to the IIO for the NCS me= ssage class.", "UMask": "0x10", @@ -5634,8 +6625,10 @@ }, { "BriefDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port 1= ", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "UNC_M2P_IIO_CREDITS_USED.NCS_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "M2PCIe IIO Credits in Use : NCS to CMS Port = 1 : Counts the number of cycles when one or more credits in the M2PCIe agen= t for sending transactions into the IIO on either NCB or NCS are in use. T= ransactions from the BL ring going into the IIO Agent must first acquire a = credit. These credits are for either the NCB or NCS message classes. NCB,= or non-coherent bypass messages are used to transmit data without coherenc= y (and are common). NCS is used for reads to PCIe (and should be used spar= ingly). : Credit for transfer through CMS Port 0s to the IIO for the NCS me= ssage class.", "UMask": "0x20", @@ -5643,648 +6636,810 @@ }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 0 : M2IOSF= 3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Dedicated P2P Credit Taken - 1 : M2IOSF= 5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M2P_LOCAL_DED_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 0 : M2= IOSF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_0.MS2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Dedicated Credits Returned - 1 : M2= IOSF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x1a", "EventName": "UNC_M2P_LOCAL_P2P_DED_RETURNED_1.MS2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M2P_LOCAL_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent3", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_3", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent4", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_4", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Returned to credit ri= ng : Agent5", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_RETURNED.AGENT_5", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF0 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF1 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF2 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 0 : M2IOSF3 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x40", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF4 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCB", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Local Shared P2P Credit Taken - 1 : M2IOSF5 -= NCS", + "Counter": "0,1,2,3", "EventCode": "0x41", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_TAKEN_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF0 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF0_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF1 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF1_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF2 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF2_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x40", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 0 : M2IO= SF3 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_0.M2IOSF3_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x80", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF4 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF4_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCB", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Waiting on Local Shared P2P Credit - 1 : M2IO= SF5 - NCS", + "Counter": "0,1,2,3", "EventCode": "0x4b", "EventName": "UNC_M2P_LOCAL_SHAR_P2P_CRD_WAIT_1.M2IOSF5_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI0", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Miscellaneous Events (mostly from MS2IDI) : N= umber of cycles MBE is high for MS2IDI1", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "UNC_M2P_MISC_EXTERNAL.MBE_INST1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : All", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Local NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCB", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "P2P Credit Occupancy : Remote NCS", + "Counter": "0,1", "EventCode": "0x14", "EventName": "UNC_M2P_P2P_CRD_OCCUPANCY.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Dedicated Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M2P_P2P_DED_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : All", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Local NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.LOCAL_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCB", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCB", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Shared Credits Received : Remote NCS", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M2P_P2P_SHAR_RECEIVED.REMOTE_NCS", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote P2P Shared Credits Returned : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M2P_REMOTE_P2P_SHAR_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent0", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_0", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent1", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Remote Shared P2P Credit Returned to credit r= ing : Agent2", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M2P_REMOTE_SHAR_P2P_CRD_RETURNED.AGENT_2", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AD", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AD : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x1", @@ -6292,8 +7447,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : AK", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : AK : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x2", @@ -6301,8 +7458,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : BL", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : BL : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x4", @@ -6310,8 +7469,10 @@ }, { "BriefDescription": "Messages that bounced on the Horizontal Ring.= : IV", + "Counter": "0,1,2,3", "EventCode": "0xac", "EventName": "UNC_M2P_RING_BOUNCES_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Horizontal Ring= . : IV : Number of cycles incoming messages from the Horizontal ring that w= ere bounced, by ring type.", "UMask": "0x8", @@ -6319,8 +7480,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := AD", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : AD : Number of cycles incoming messages from the Vertical ring that were = bounced, by ring type.", "UMask": "0x1", @@ -6328,8 +7491,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Acknowledgements to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Acknowledgements to core : Number of cycles incoming messages from the Ve= rtical ring that were bounced, by ring type.", "UMask": "0x2", @@ -6337,8 +7502,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Number of cycles incoming messages from the Vertical ring that were bounc= ed, by ring type.", "UMask": "0x10", @@ -6346,8 +7513,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Data Responses to core", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.BL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Data Responses to core : Number of cycles incoming messages from the Vert= ical ring that were bounced, by ring type.", "UMask": "0x4", @@ -6355,8 +7524,10 @@ }, { "BriefDescription": "Messages that bounced on the Vertical Ring. := Snoops of processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xaa", "EventName": "UNC_M2P_RING_BOUNCES_VERT.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Messages that bounced on the Vertical Ring. = : Snoops of processor's cache. : Number of cycles incoming messages from th= e Vertical ring that were bounced, by ring type.", "UMask": "0x8", @@ -6364,95 +7535,119 @@ }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : AK", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : Acknowle= dgements to Agent 1", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.AK_AG1", + "Experimental": "1", "PerPkg": "1", "UMask": "0x20", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : BL", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Horizontal Ring : IV", + "Counter": "0,1,2,3", "EventCode": "0xad", "EventName": "UNC_M2P_RING_SINK_STARVED_HORZ.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : AD", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Acknowledg= ements to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AK", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.AKC", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Data Respo= nses to core", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.BL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "M2PCIe" }, { "BriefDescription": "Sink Starvation on Vertical Ring : Snoops of = processor's cache.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "UNC_M2P_RING_SINK_STARVED_VERT.IV", + "Experimental": "1", "PerPkg": "1", "UMask": "0x8", "Unit": "M2PCIe" }, { "BriefDescription": "Source Throttle", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "UNC_M2P_RING_SRC_THRTL", + "Experimental": "1", "PerPkg": "1", "Unit": "M2PCIe" }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x80", @@ -6460,8 +7655,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x1", @@ -6469,8 +7666,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x2", @@ -6478,8 +7677,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x4", @@ -6487,8 +7688,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x20", @@ -6496,8 +7699,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Cycles Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M2P_RxC_CYCLES_NE.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Cycles Not Empty : = Counts the number of cycles when the M2PCIe Ingress is not empty.", "UMask": "0x40", @@ -6505,8 +7710,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x80", @@ -6514,8 +7721,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_IDI", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x1", @@ -6523,8 +7732,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x2", @@ -6532,8 +7743,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.CHA_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x4", @@ -6541,8 +7754,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCB", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x20", @@ -6550,8 +7765,10 @@ }, { "BriefDescription": "Ingress (from CMS) Queue Inserts", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M2P_RxC_INSERTS.IIO_NCS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Ingress (from CMS) Queue Inserts : Counts th= e number of entries inserted into the M2PCIe Ingress Queue. This can be us= ed in conjunction with the M2PCIe Ingress Occupancy Accumulator event in or= der to calculate average queue latency.", "UMask": "0x40", @@ -6559,8 +7776,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6568,8 +7787,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x10", @@ -6577,8 +7798,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x1", @@ -6586,8 +7809,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, because a message from the other queue has h= igher priority : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6595,8 +7820,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, because a message from the other queue = has higher priority", "UMask": "0x40", @@ -6604,8 +7831,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe5", "EventName": "UNC_M2P_RxR_BUSY_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, because a message from the other queu= e has higher priority", "UMask": "0x4", @@ -6613,8 +7842,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6622,8 +7853,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x10", @@ -6631,8 +7864,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AD - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x1", @@ -6640,8 +7875,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AK", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AK : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x2", @@ -6649,8 +7886,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : AKC - Uncredited= : Number of packets bypassing the CMS Ingress", "UMask": "0x80", @@ -6658,8 +7897,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - All : Numbe= r of packets bypassing the CMS Ingress : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6667,8 +7908,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Credited : = Number of packets bypassing the CMS Ingress", "UMask": "0x40", @@ -6676,8 +7919,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : BL - Uncredited = : Number of packets bypassing the CMS Ingress", "UMask": "0x4", @@ -6685,8 +7930,10 @@ }, { "BriefDescription": "Transgress Ingress Bypass : IV", + "Counter": "0,1,2,3", "EventCode": "0xe2", "EventName": "UNC_M2P_RxR_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Bypass : IV : Number of p= ackets bypassing the CMS Ingress", "UMask": "0x8", @@ -6694,8 +7941,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6703,8 +7952,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x10", @@ -6712,8 +7963,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AD - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x1", @@ -6721,8 +7974,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : AK", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : AK : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x2", @@ -6730,8 +7985,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - All := Counts cycles under injection starvation mode. This starvation is trigger= ed when the CMS Ingress cannot send a transaction onto the mesh for a long = period of time. In this case, the Ingress is unable to forward to the Egre= ss due to a lack of credit. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6739,8 +7996,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Credi= ted : Counts cycles under injection starvation mode. This starvation is tr= iggered when the CMS Ingress cannot send a transaction onto the mesh for a = long period of time. In this case, the Ingress is unable to forward to the= Egress due to a lack of credit.", "UMask": "0x40", @@ -6748,8 +8007,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : BL - Uncre= dited : Counts cycles under injection starvation mode. This starvation is = triggered when the CMS Ingress cannot send a transaction onto the mesh for = a long period of time. In this case, the Ingress is unable to forward to t= he Egress due to a lack of credit.", "UMask": "0x4", @@ -6757,8 +8018,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IFV - Credi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IFV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IFV - Cred= ited : Counts cycles under injection starvation mode. This starvation is t= riggered when the CMS Ingress cannot send a transaction onto the mesh for a= long period of time. In this case, the Ingress is unable to forward to th= e Egress due to a lack of credit.", "UMask": "0x80", @@ -6766,8 +8029,10 @@ }, { "BriefDescription": "Transgress Injection Starvation : IV", + "Counter": "0,1,2,3", "EventCode": "0xe3", "EventName": "UNC_M2P_RxR_CRD_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : IV : Count= s cycles under injection starvation mode. This starvation is triggered whe= n the CMS Ingress cannot send a transaction onto the mesh for a long period= of time. In this case, the Ingress is unable to forward to the Egress due= to a lack of credit.", "UMask": "0x8", @@ -6775,16 +8040,20 @@ }, { "BriefDescription": "Transgress Injection Starvation", + "Counter": "0,1,2,3", "EventCode": "0xe4", "EventName": "UNC_M2P_RxR_CRD_STARVED_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Injection Starvation : Counts cyc= les under injection starvation mode. This starvation is triggered when the= CMS Ingress cannot send a transaction onto the mesh for a long period of t= ime. In this case, the Ingress is unable to forward to the Egress due to a= lack of credit.", "Unit": "M2PCIe" }, { "BriefDescription": "Transgress Ingress Allocations : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6792,8 +8061,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x10", @@ -6801,8 +8072,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AD - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AD - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x1", @@ -6810,8 +8083,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AK", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AK : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x2", @@ -6819,8 +8094,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : AKC - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : AKC - Uncre= dited : Number of allocations into the CMS Ingress The Ingress is used to = queue up requests received from the mesh", "UMask": "0x80", @@ -6828,8 +8105,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - All : = Number of allocations into the CMS Ingress The Ingress is used to queue up= requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6837,8 +8116,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Credite= d", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Credit= ed : Number of allocations into the CMS Ingress The Ingress is used to que= ue up requests received from the mesh", "UMask": "0x40", @@ -6846,8 +8127,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : BL - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : BL - Uncred= ited : Number of allocations into the CMS Ingress The Ingress is used to q= ueue up requests received from the mesh", "UMask": "0x4", @@ -6855,8 +8138,10 @@ }, { "BriefDescription": "Transgress Ingress Allocations : IV", + "Counter": "0,1,2,3", "EventCode": "0xe1", "EventName": "UNC_M2P_RxR_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Allocations : IV : Number= of allocations into the CMS Ingress The Ingress is used to queue up reque= sts received from the mesh", "UMask": "0x8", @@ -6864,8 +8149,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -6873,8 +8160,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x10", @@ -6882,8 +8171,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AD - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AD - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x1", @@ -6891,8 +8182,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AK : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x2", @@ -6900,8 +8193,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : AKC - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : AKC - Uncredi= ted : Occupancy event for the Ingress buffers in the CMS The Ingress is us= ed to queue up requests received from the mesh", "UMask": "0x80", @@ -6909,8 +8204,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - All : Oc= cupancy event for the Ingress buffers in the CMS The Ingress is used to qu= eue up requests received from the mesh : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -6918,8 +8215,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Credited= : Occupancy event for the Ingress buffers in the CMS The Ingress is used = to queue up requests received from the mesh", "UMask": "0x20", @@ -6927,8 +8226,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : BL - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : BL - Uncredit= ed : Occupancy event for the Ingress buffers in the CMS The Ingress is use= d to queue up requests received from the mesh", "UMask": "0x4", @@ -6936,8 +8237,10 @@ }, { "BriefDescription": "Transgress Ingress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xe0", "EventName": "UNC_M2P_RxR_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Transgress Ingress Occupancy : IV : Occupanc= y event for the Ingress buffers in the CMS The Ingress is used to queue up= requests received from the mesh", "UMask": "0x8", @@ -6945,8 +8248,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -6954,8 +8259,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -6963,8 +8270,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -6972,8 +8281,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -6981,8 +8292,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -6990,8 +8303,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -6999,8 +8314,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7008,8 +8325,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd0", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7017,8 +8336,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7026,8 +8347,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7035,8 +8358,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7044,8 +8369,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7053,8 +8380,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7062,8 +8391,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7071,8 +8402,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7080,8 +8413,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd2", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_AD_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7089,8 +8424,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7098,8 +8435,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7107,8 +8446,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7116,8 +8457,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7125,8 +8468,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7134,8 +8479,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7143,8 +8490,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7152,8 +8501,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd4", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG0.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7161,8 +8512,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 0", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 0 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7170,8 +8523,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 1", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 1 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7179,8 +8534,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 2", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 2 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7188,8 +8545,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 3", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 3 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x8", @@ -7197,8 +8556,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 4", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR4", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 4 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x10", @@ -7206,8 +8567,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 5", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR5", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 5 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x20", @@ -7215,8 +8578,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 6", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 6 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x40", @@ -7224,8 +8589,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 7", + "Counter": "0,1,2,3", "EventCode": "0xd6", "EventName": "UNC_M2P_STALL0_NO_TxR_HORZ_CRD_BL_AG1.TGR7", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 7 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x80", @@ -7233,8 +8600,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7242,8 +8611,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7251,8 +8622,10 @@ }, { "BriefDescription": "Stall on No AD Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd1", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG0.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7260,8 +8633,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the AD Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7269,8 +8644,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7278,8 +8655,10 @@ }, { "BriefDescription": "Stall on No AD Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd3", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_AD_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No AD Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the AD Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7287,8 +8666,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 0 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7296,8 +8677,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7305,8 +8688,10 @@ }, { "BriefDescription": "Stall on No BL Agent0 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd5", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG0_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent0 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 0 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7314,8 +8699,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 10", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR10", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 10 : Number of cycles the BL Agent 1 Egress Buffer is stalled= waiting for a TGR credit to become available, per transgress.", "UMask": "0x4", @@ -7323,8 +8710,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 8", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR8", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 8 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x1", @@ -7332,8 +8721,10 @@ }, { "BriefDescription": "Stall on No BL Agent1 Transgress Credits : Fo= r Transgress 9", + "Counter": "0,1,2,3", "EventCode": "0xd7", "EventName": "UNC_M2P_STALL1_NO_TxR_HORZ_CRD_BL_AG1_1.TGR9", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Stall on No BL Agent1 Transgress Credits : F= or Transgress 9 : Number of cycles the BL Agent 1 Egress Buffer is stalled = waiting for a TGR credit to become available, per transgress.", "UMask": "0x2", @@ -7341,16 +8732,20 @@ }, { "BriefDescription": "UNC_M2P_TxC_CREDITS.PRQ", + "Counter": "0,1", "EventCode": "0x2d", "EventName": "UNC_M2P_TxC_CREDITS.PRQ", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "M2PCIe" }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x1", @@ -7358,8 +8753,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x10", @@ -7367,8 +8764,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x2", @@ -7376,8 +8775,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x20", @@ -7385,8 +8786,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x4", @@ -7394,8 +8797,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Full", + "Counter": "0,1,2,3", "EventCode": "0x25", "EventName": "UNC_M2P_TxC_CYCLES_FULL.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Full : Counts the num= ber of cycles when the M2PCIe Egress is full. This tracks messages for one= of the two CMS ports that are used by the M2PCIe agent.", "UMask": "0x40", @@ -7403,8 +8808,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x1", @@ -7412,8 +8819,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x10", @@ -7421,8 +8830,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x2", @@ -7430,8 +8841,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.AK_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x20", @@ -7439,8 +8852,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x4", @@ -7448,8 +8863,10 @@ }, { "BriefDescription": "Egress (to CMS) Cycles Not Empty", + "Counter": "0,1", "EventCode": "0x23", "EventName": "UNC_M2P_TxC_CYCLES_NE.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Cycles Not Empty : Counts th= e number of cycles when the M2PCIe Egress is not empty. This tracks messag= es for one of the two CMS ports that are used by the M2PCIe agent. This ca= n be used in conjunction with the M2PCIe Ingress Occupancy Accumulator even= t in order to calculate average queue occupancy. Multiple egress buffers c= an be tracked at a given time using multiple counters.", "UMask": "0x40", @@ -7457,8 +8874,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x1", @@ -7466,8 +8885,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x10", @@ -7475,8 +8896,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x8", @@ -7484,8 +8907,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.AK_CRD_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x80", @@ -7493,8 +8918,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x4", @@ -7502,8 +8929,10 @@ }, { "BriefDescription": "Egress (to CMS) Ingress", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M2P_TxC_INSERTS.BL_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Egress (to CMS) Ingress : Counts the number = of number of messages inserted into the the M2PCIe Egress queue. This tra= cks messages for one of the two CMS ports that are used by the M2PCIe agent= . This can be used in conjunction with the M2PCIe Ingress Occupancy Accumu= lator event in order to calculate average queue occupancy.", "UMask": "0x40", @@ -7511,8 +8940,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7520,8 +8951,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x10", @@ -7529,8 +8962,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : AD - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x1", @@ -7538,8 +8973,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - All : Number = of packets using the Horizontal Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7547,8 +8984,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Credited : Nu= mber of packets using the Horizontal Anti-Deadlock Slot, broken down by rin= g type and CMS Agent.", "UMask": "0x40", @@ -7556,8 +8995,10 @@ }, { "BriefDescription": "CMS Horizontal ADS Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa6", "EventName": "UNC_M2P_TxR_HORZ_ADS_USED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal ADS Used : BL - Uncredited : = Number of packets using the Horizontal Anti-Deadlock Slot, broken down by r= ing type and CMS Agent.", "UMask": "0x4", @@ -7565,8 +9006,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7574,8 +9017,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -7583,8 +9028,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AD - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x1", @@ -7592,8 +9039,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AK", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AK : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x2", @@ -7601,8 +9050,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : AKC - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : AKC - Uncredite= d : Number of packets bypassing the Horizontal Egress, broken down by ring = type and CMS Agent.", "UMask": "0x80", @@ -7610,8 +9061,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - All : Numb= er of packets bypassing the Horizontal Egress, broken down by ring type and= CMS Agent. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7619,8 +9072,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Credited := Number of packets bypassing the Horizontal Egress, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -7628,8 +9083,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : BL - Uncredited= : Number of packets bypassing the Horizontal Egress, broken down by ring t= ype and CMS Agent.", "UMask": "0x4", @@ -7637,8 +9094,10 @@ }, { "BriefDescription": "CMS Horizontal Bypass Used : IV", + "Counter": "0,1,2,3", "EventCode": "0xa7", "EventName": "UNC_M2P_TxR_HORZ_BYPASS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Bypass Used : IV : Number of = packets bypassing the Horizontal Egress, broken down by ring type and CMS A= gent.", "UMask": "0x8", @@ -7646,8 +9105,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7655,8 +9116,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x10", @@ -7664,8 +9127,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AD - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x1", @@ -7673,8 +9138,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AK : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x2", @@ -7682,8 +9149,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop a= re Full. The egress is used to queue up requests destined for the Horizont= al Ring on the Mesh.", "UMask": "0x80", @@ -7691,8 +9160,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - All : Cycles the Transgress buffers in the Common Mesh Stop are Full.= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7700,8 +9171,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop are = Full. The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x40", @@ -7709,8 +9182,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := BL - Uncredited : Cycles the Transgress buffers in the Common Mesh Stop ar= e Full. The egress is used to queue up requests destined for the Horizonta= l Ring on the Mesh.", "UMask": "0x4", @@ -7718,8 +9193,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Full : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa2", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_FULL.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Full := IV : Cycles the Transgress buffers in the Common Mesh Stop are Full. The = egress is used to queue up requests destined for the Horizontal Ring on the= Mesh.", "UMask": "0x8", @@ -7727,8 +9204,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7736,8 +9215,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x10", @@ -7745,8 +9226,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AD - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x1", @@ -7754,8 +9237,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AK", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AK : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x2", @@ -7763,8 +9248,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : AKC - Uncredited : Cycles the Transgress buffers in the Common Mesh S= top are Not-Empty. The egress is used to queue up requests destined for th= e Horizontal Ring on the Mesh.", "UMask": "0x80", @@ -7772,8 +9259,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - All : Cycles the Transgress buffers in the Common Mesh Stop are = Not-Empty. The egress is used to queue up requests destined for the Horizo= ntal Ring on the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7781,8 +9270,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Credited : Cycles the Transgress buffers in the Common Mesh Stop= are Not-Empty. The egress is used to queue up requests destined for the H= orizontal Ring on the Mesh.", "UMask": "0x40", @@ -7790,8 +9281,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : BL - Uncredited : Cycles the Transgress buffers in the Common Mesh St= op are Not-Empty. The egress is used to queue up requests destined for the= Horizontal Ring on the Mesh.", "UMask": "0x4", @@ -7799,8 +9292,10 @@ }, { "BriefDescription": "Cycles CMS Horizontal Egress Queue is Not Emp= ty : IV", + "Counter": "0,1,2,3", "EventCode": "0xa3", "EventName": "UNC_M2P_TxR_HORZ_CYCLES_NE.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Horizontal Egress Queue is Not Em= pty : IV : Cycles the Transgress buffers in the Common Mesh Stop are Not-Em= pty. The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x8", @@ -7808,8 +9303,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7817,8 +9314,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x10", @@ -7826,8 +9325,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AD - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AD - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x1", @@ -7835,8 +9336,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AK", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AK : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x2", @@ -7844,8 +9347,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : AKC - Uncredi= ted", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : AKC - Uncred= ited : Number of allocations into the Transgress buffers in the Common Mesh= Stop The egress is used to queue up requests destined for the Horizontal = Ring on the Mesh.", "UMask": "0x80", @@ -7853,8 +9358,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - All : N= umber of allocations into the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -7862,8 +9369,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Credited= ", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Credite= d : Number of allocations into the Transgress buffers in the Common Mesh St= op The egress is used to queue up requests destined for the Horizontal Rin= g on the Mesh.", "UMask": "0x40", @@ -7871,8 +9380,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : BL - Uncredit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : BL - Uncredi= ted : Number of allocations into the Transgress buffers in the Common Mesh = Stop The egress is used to queue up requests destined for the Horizontal R= ing on the Mesh.", "UMask": "0x4", @@ -7880,8 +9391,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Inserts : IV", + "Counter": "0,1,2,3", "EventCode": "0xa1", "EventName": "UNC_M2P_TxR_HORZ_INSERTS.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Inserts : IV : Number = of allocations into the Transgress buffers in the Common Mesh Stop The egr= ess is used to queue up requests destined for the Horizontal Ring on the Me= sh.", "UMask": "0x8", @@ -7889,8 +9402,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x11", @@ -7898,8 +9413,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x10", @@ -7907,8 +9424,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AD - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AD - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x1", @@ -7916,8 +9435,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AK", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AK : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x2", @@ -7925,8 +9446,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : AKC - Uncredite= d", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : AKC - Uncredit= ed : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x80", @@ -7934,8 +9457,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - All : Cou= nts number of Egress packets NACK'ed on to the Horizontal Ring : All =3D=3D= Credited + Uncredited", "UMask": "0x44", @@ -7943,8 +9468,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Credited", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Credited = : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x40", @@ -7952,8 +9479,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : BL - Uncredited= ", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : BL - Uncredite= d : Counts number of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x4", @@ -7961,8 +9490,10 @@ }, { "BriefDescription": "CMS Horizontal Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0xa4", "EventName": "UNC_M2P_TxR_HORZ_NACK.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress NACKs : IV : Counts nu= mber of Egress packets NACK'ed on to the Horizontal Ring", "UMask": "0x8", @@ -7970,8 +9501,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x11", @@ -7979,8 +9512,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x10", @@ -7988,8 +9523,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AD - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AD - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x1", @@ -7997,8 +9534,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AK", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AK : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x2", @@ -8006,8 +9545,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : AKC - Uncre= dited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : AKC - Uncr= edited : Occupancy event for the Transgress buffers in the Common Mesh Stop= The egress is used to queue up requests destined for the Horizontal Ring = on the Mesh.", "UMask": "0x80", @@ -8015,8 +9556,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - All := Occupancy event for the Transgress buffers in the Common Mesh Stop The eg= ress is used to queue up requests destined for the Horizontal Ring on the M= esh. : All =3D=3D Credited + Uncredited", "UMask": "0x44", @@ -8024,8 +9567,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Credit= ed", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_CRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Credi= ted : Occupancy event for the Transgress buffers in the Common Mesh Stop T= he egress is used to queue up requests destined for the Horizontal Ring on = the Mesh.", "UMask": "0x40", @@ -8033,8 +9578,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : BL - Uncred= ited", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : BL - Uncre= dited : Occupancy event for the Transgress buffers in the Common Mesh Stop = The egress is used to queue up requests destined for the Horizontal Ring o= n the Mesh.", "UMask": "0x4", @@ -8042,8 +9589,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Occupancy : IV", + "Counter": "0,1,2,3", "EventCode": "0xa0", "EventName": "UNC_M2P_TxR_HORZ_OCCUPANCY.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Occupancy : IV : Occup= ancy event for the Transgress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Horizontal Ring on the Mesh.", "UMask": "0x8", @@ -8051,8 +9600,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x1", @@ -8060,8 +9611,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AD - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AD_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AD - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x1", @@ -8069,8 +9622,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AK", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AK", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AK : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x2", @@ -8078,8 +9633,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = AKC - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.AKC_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := AKC - Uncredited : Counts injection starvation. This starvation is trigge= red when the CMS Transgress buffer cannot send a transaction onto the Horiz= ontal ring for a long period of time.", "UMask": "0x80", @@ -8087,8 +9644,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - All", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - All : Counts injection starvation. This starvation is triggered when= the CMS Transgress buffer cannot send a transaction onto the Horizontal ri= ng for a long period of time. : All =3D=3D Credited + Uncredited", "UMask": "0x4", @@ -8096,8 +9655,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = BL - Uncredited", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.BL_UNCRD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := BL - Uncredited : Counts injection starvation. This starvation is trigger= ed when the CMS Transgress buffer cannot send a transaction onto the Horizo= ntal ring for a long period of time.", "UMask": "0x4", @@ -8105,8 +9666,10 @@ }, { "BriefDescription": "CMS Horizontal Egress Injection Starvation : = IV", + "Counter": "0,1,2,3", "EventCode": "0xa5", "EventName": "UNC_M2P_TxR_HORZ_STARVED.IV", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Horizontal Egress Injection Starvation := IV : Counts injection starvation. This starvation is triggered when the C= MS Transgress buffer cannot send a transaction onto the Horizontal ring for= a long period of time.", "UMask": "0x8", @@ -8114,8 +9677,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x1", @@ -8123,8 +9688,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x10", @@ -8132,8 +9699,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x4", @@ -8141,8 +9710,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9c", "EventName": "UNC_M2P_TxR_VERT_ADS_USED.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets using the Vertical Anti-Deadlock Slot, broken down by ring typ= e and CMS Agent.", "UMask": "0x40", @@ -8150,8 +9721,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x1", @@ -8159,8 +9732,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AD - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x10", @@ -8168,8 +9743,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x2", @@ -8177,8 +9754,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AK - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x20", @@ -8186,8 +9765,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 0 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x4", @@ -8195,8 +9776,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : BL - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x40", @@ -8204,8 +9787,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : IV - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9d", "EventName": "UNC_M2P_TxR_VERT_BYPASS.IV_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : IV - Agent 1 : Numbe= r of packets bypassing the Vertical Egress, broken down by ring type and CM= S Agent.", "UMask": "0x8", @@ -8213,8 +9798,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 0 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x1", @@ -8222,8 +9809,10 @@ }, { "BriefDescription": "CMS Vertical ADS Used : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9e", "EventName": "UNC_M2P_TxR_VERT_BYPASS_1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical ADS Used : AKC - Agent 1 : Numb= er of packets bypassing the Vertical Egress, broken down by ring type and C= MS Agent.", "UMask": "0x2", @@ -8231,8 +9820,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some ex= ample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8240,8 +9831,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= D - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AD ring. This is= commonly used for outbound requests.", "UMask": "0x10", @@ -8249,8 +9842,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the AK ring. This is= commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8258,8 +9853,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= K - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8267,8 +9864,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the BL ring. This is= commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8276,8 +9875,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : B= L - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 1 destined for the BL ring. This is= commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8285,8 +9886,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : IV= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x94", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : I= V - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. T= he Egress is used to queue up requests destined for the Vertical Ring on th= e Mesh. : Ring transactions from Agent 0 destined for the IV ring. This is= commonly used for snoops to the cores.", "UMask": "0x8", @@ -8294,8 +9897,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AD ring. Some e= xample include outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8303,8 +9908,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Full : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x95", "EventName": "UNC_M2P_TxR_VERT_CYCLES_FULL1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Full : A= KC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Full. = The Egress is used to queue up requests destined for the Vertical Ring on t= he Mesh. : Ring transactions from Agent 0 destined for the AK ring. This i= s commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8312,8 +9919,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. S= ome example include outbound requests, snoop requests, and snoop responses.= ", "UMask": "0x1", @@ -8321,8 +9930,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AD - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AD ring. T= his is commonly used for outbound requests.", "UMask": "0x10", @@ -8330,8 +9941,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. T= his is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8339,8 +9952,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AK - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8348,8 +9963,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the BL ring. T= his is commonly used to send data from the cache to various destinations.", "UMask": "0x4", @@ -8357,8 +9974,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : BL - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 1 destined for the BL ring. T= his is commonly used for transferring writeback data to the cache.", "UMask": "0x40", @@ -8366,8 +9985,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x96", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : IV - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Emp= ty. The Egress is used to queue up requests destined for the Vertical Ring= on the Mesh. : Ring transactions from Agent 0 destined for the IV ring. T= his is commonly used for snoops to the cores.", "UMask": "0x8", @@ -8375,8 +9996,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 0 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AD ring. = Some example include outbound requests, snoop requests, and snoop responses= .", "UMask": "0x1", @@ -8384,8 +10007,10 @@ }, { "BriefDescription": "Cycles CMS Vertical Egress Queue Is Not Empty= : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x97", "EventName": "UNC_M2P_TxR_VERT_CYCLES_NE1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles CMS Vertical Egress Queue Is Not Empt= y : AKC - Agent 1 : Number of cycles the Common Mesh Stop Egress was Not Em= pty. The Egress is used to queue up requests destined for the Vertical Rin= g on the Mesh. : Ring transactions from Agent 0 destined for the AK ring. = This is commonly used for credit returns and GO responses.", "UMask": "0x2", @@ -8393,8 +10018,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AD ring. Some example include ou= tbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8402,8 +10029,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AD - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AD ring. This is commonly used f= or outbound requests.", "UMask": "0x10", @@ -8411,8 +10040,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the AK ring. This is commonly used f= or credit returns and GO responses.", "UMask": "0x2", @@ -8420,8 +10051,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AK - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8429,8 +10062,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the BL ring. This is commonly used t= o send data from the cache to various destinations.", "UMask": "0x4", @@ -8438,8 +10073,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : BL - Agent 1 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 1 destined for the BL ring. This is commonly used f= or transferring writeback data to the cache.", "UMask": "0x40", @@ -8447,8 +10084,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x92", "EventName": "UNC_M2P_TxR_VERT_INSERTS0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : IV - Agent 0 := Number of allocations into the Common Mesh Stop Egress. The Egress is use= d to queue up requests destined for the Vertical Ring on the Mesh. : Ring t= ransactions from Agent 0 destined for the IV ring. This is commonly used f= or snoops to the cores.", "UMask": "0x8", @@ -8456,8 +10095,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 0 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AD ring. Some example include o= utbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8465,8 +10106,10 @@ }, { "BriefDescription": "CMS Vert Egress Allocations : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x93", "EventName": "UNC_M2P_TxR_VERT_INSERTS1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Allocations : AKC - Agent 1 = : Number of allocations into the Common Mesh Stop Egress. The Egress is us= ed to queue up requests destined for the Vertical Ring on the Mesh. : Ring = transactions from Agent 0 destined for the AK ring. This is commonly used = for credit returns and GO responses.", "UMask": "0x2", @@ -8474,8 +10117,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8483,8 +10128,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AD - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x10", @@ -8492,8 +10139,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8501,8 +10150,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AK - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x20", @@ -8510,8 +10161,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 0 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x4", @@ -8519,8 +10172,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : BL - Agent 1 : C= ounts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x40", @@ -8528,8 +10183,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : IV", + "Counter": "0,1,2,3", "EventCode": "0x98", "EventName": "UNC_M2P_TxR_VERT_NACK0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : IV : Counts numb= er of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x8", @@ -8537,8 +10194,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 0 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x1", @@ -8546,8 +10205,10 @@ }, { "BriefDescription": "CMS Vertical Egress NACKs : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x99", "EventName": "UNC_M2P_TxR_VERT_NACK1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress NACKs : AKC - Agent 1 : = Counts number of Egress packets NACK'ed on to the Vertical Ring", "UMask": "0x2", @@ -8555,8 +10216,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AD ring. Some example inclu= de outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8564,8 +10227,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AD - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AD - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AD ring. This is commonly u= sed for outbound requests.", "UMask": "0x10", @@ -8573,8 +10238,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the AK ring. This is commonly u= sed for credit returns and GO responses.", "UMask": "0x2", @@ -8582,8 +10249,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AK - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AK - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the AK ring.", "UMask": "0x20", @@ -8591,8 +10260,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the BL ring. This is commonly u= sed to send data from the cache to various destinations.", "UMask": "0x4", @@ -8600,8 +10271,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : BL - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : BL - Agent 1 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 1 destined for the BL ring. This is commonly u= sed for transferring writeback data to the cache.", "UMask": "0x40", @@ -8609,8 +10282,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : IV - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x90", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : IV - Agent 0 : O= ccupancy event for the Egress buffers in the Common Mesh Stop The egress i= s used to queue up requests destined for the Vertical Ring on the Mesh. : R= ing transactions from Agent 0 destined for the IV ring. This is commonly u= sed for snoops to the cores.", "UMask": "0x8", @@ -8618,8 +10293,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 0 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AD ring. Some example incl= ude outbound requests, snoop requests, and snoop responses.", "UMask": "0x1", @@ -8627,8 +10304,10 @@ }, { "BriefDescription": "CMS Vert Egress Occupancy : AKC - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x91", "EventName": "UNC_M2P_TxR_VERT_OCCUPANCY1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vert Egress Occupancy : AKC - Agent 1 : = Occupancy event for the Egress buffers in the Common Mesh Stop The egress = is used to queue up requests destined for the Vertical Ring on the Mesh. : = Ring transactions from Agent 0 destined for the AK ring. This is commonly = used for credit returns and GO responses.", "UMask": "0x2", @@ -8636,8 +10315,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x1", @@ -8645,8 +10326,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AD= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AD_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= D - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x10", @@ -8654,8 +10337,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x2", @@ -8663,8 +10348,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.AK_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= K - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x20", @@ -8672,8 +10359,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 0 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x4", @@ -8681,8 +10370,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : BL= - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.BL_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : B= L - Agent 1 : Counts injection starvation. This starvation is triggered wh= en the CMS Egress cannot send a transaction onto the Vertical ring for a lo= ng period of time.", "UMask": "0x40", @@ -8690,8 +10381,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : IV= ", + "Counter": "0,1,2,3", "EventCode": "0x9a", "EventName": "UNC_M2P_TxR_VERT_STARVED0.IV_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : I= V : Counts injection starvation. This starvation is triggered when the CMS= Egress cannot send a transaction onto the Vertical ring for a long period = of time.", "UMask": "0x8", @@ -8699,8 +10392,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x1", @@ -8708,8 +10403,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 1", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.AKC_AG1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 1 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x2", @@ -8717,8 +10414,10 @@ }, { "BriefDescription": "CMS Vertical Egress Injection Starvation : AK= C - Agent 0", + "Counter": "0,1,2,3", "EventCode": "0x9b", "EventName": "UNC_M2P_TxR_VERT_STARVED1.TGC", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CMS Vertical Egress Injection Starvation : A= KC - Agent 0 : Counts injection starvation. This starvation is triggered w= hen the CMS Egress cannot send a transaction onto the Vertical ring for a l= ong period of time.", "UMask": "0x4", @@ -8726,8 +10425,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AD ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top. We really have two rings -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8735,8 +10436,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AD ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op. We really have two rings -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8744,8 +10447,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AD ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p. We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8753,8 +10458,10 @@ }, { "BriefDescription": "Vertical AD Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "UNC_M2P_VERT_RING_AD_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AD Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AD ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= . We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8762,8 +10469,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical AKC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8771,8 +10480,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical AKC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8780,8 +10491,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical AKC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8789,8 +10502,10 @@ }, { "BriefDescription": "Vertical AKC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb4", "EventName": "UNC_M2P_VERT_RING_AKC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AKC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical AKC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8798,8 +10513,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Even : Co= unts the number of cycles that the Vertical AK ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in -- a clockwise ring and a counter-clockwise= ring. On the left side of the ring, the UP direction is on the clockwise = ring and DN is on the counter-clockwise ring. On the right side of the rin= g, this is reversed. The first half of the CBos are on the left side of th= e ring, and the 2nd half are on the right side of the ring. In other words= (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP = AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8807,8 +10524,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Down and Odd : Cou= nts the number of cycles that the Vertical AK ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in -- a clockwise ring and a counter-clockwise = ring. On the left side of the ring, the UP direction is on the clockwise r= ing and DN is on the counter-clockwise ring. On the right side of the ring= , this is reversed. The first half of the CBos are on the left side of the= ring, and the 2nd half are on the right side of the ring. In other words = (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP A= D because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8816,8 +10535,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Even : Coun= ts the number of cycles that the Vertical AK ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings in -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8825,8 +10546,10 @@ }, { "BriefDescription": "Vertical AK Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb1", "EventName": "UNC_M2P_VERT_RING_AK_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical AK Ring In Use : Up and Odd : Count= s the number of cycles that the Vertical AK ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring stop= .We really have two rings in -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x2", @@ -8834,8 +10557,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Even : Co= unts the number of cycles that the Vertical BL ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring = stop.We really have two rings -- a clockwise ring and a counter-clockwise r= ing. On the left side of the ring, the UP direction is on the clockwise ri= ng and DN is on the counter-clockwise ring. On the right side of the ring,= this is reversed. The first half of the CBos are on the left side of the = ring, and the 2nd half are on the right side of the ring. In other words (= for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD= because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8843,8 +10568,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Down and Odd : Cou= nts the number of cycles that the Vertical BL ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings -- a clockwise ring and a counter-clockwise ri= ng. On the left side of the ring, the UP direction is on the clockwise rin= g and DN is on the counter-clockwise ring. On the right side of the ring, = this is reversed. The first half of the CBos are on the left side of the r= ing, and the 2nd half are on the right side of the ring. In other words (f= or example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD = because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8852,8 +10579,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Even : Coun= ts the number of cycles that the Vertical BL ring is being used at this rin= g stop. This includes when packets are passing by and when packets are bei= ng sunk, but does not include when packets are being sent from the ring st= op.We really have two rings -- a clockwise ring and a counter-clockwise rin= g. On the left side of the ring, the UP direction is on the clockwise ring= and DN is on the counter-clockwise ring. On the right side of the ring, t= his is reversed. The first half of the CBos are on the left side of the ri= ng, and the 2nd half are on the right side of the ring. In other words (fo= r example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD b= ecause they are on opposite sides of the ring.", "UMask": "0x1", @@ -8861,8 +10590,10 @@ }, { "BriefDescription": "Vertical BL Ring in Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb2", "EventName": "UNC_M2P_VERT_RING_BL_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical BL Ring in Use : Up and Odd : Count= s the number of cycles that the Vertical BL ring is being used at this ring= stop. This includes when packets are passing by and when packets are bein= g sunk, but does not include when packets are being sent from the ring sto= p.We really have two rings -- a clockwise ring and a counter-clockwise ring= . On the left side of the ring, the UP direction is on the clockwise ring = and DN is on the counter-clockwise ring. On the right side of the ring, th= is is reversed. The first half of the CBos are on the left side of the rin= g, and the 2nd half are on the right side of the ring. In other words (for= example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD be= cause they are on opposite sides of the ring.", "UMask": "0x2", @@ -8870,8 +10601,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Down", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.DN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Down : Counts the = number of cycles that the Vertical IV ring is being used at this ring stop.= This includes when packets are passing by and when packets are being sunk= , but does not include when packets are being sent from the ring stop. The= re is only 1 IV ring. Therefore, if one wants to monitor the Even ring, th= ey should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they s= hould select both UP_ODD and DN_ODD.", "UMask": "0x4", @@ -8879,8 +10612,10 @@ }, { "BriefDescription": "Vertical IV Ring in Use : Up", + "Counter": "0,1,2,3", "EventCode": "0xb3", "EventName": "UNC_M2P_VERT_RING_IV_IN_USE.UP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical IV Ring in Use : Up : Counts the nu= mber of cycles that the Vertical IV ring is being used at this ring stop. = This includes when packets are passing by and when packets are being sunk, = but does not include when packets are being sent from the ring stop. There= is only 1 IV ring. Therefore, if one wants to monitor the Even ring, they= should select both UP_EVEN and DN_EVEN. To monitor the Odd ring, they sho= uld select both UP_ODD and DN_ODD.", "UMask": "0x1", @@ -8888,8 +10623,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Even : C= ounts the number of cycles that the Vertical TGC ring is being used at this= ring stop. This includes when packets are passing by and when packets are= being sunk, but does not include when packets are being sent from the ring= stop.We really have two rings in JKT -- a clockwise ring and a counter-clo= ckwise ring. On the left side of the ring, the UP direction is on the cloc= kwise ring and DN is on the counter-clockwise ring. On the right side of t= he ring, this is reversed. The first half of the CBos are on the left side= of the ring, and the 2nd half are on the right side of the ring. In other= words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo= 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x4", @@ -8897,8 +10634,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Down and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.DN_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Down and Odd : Co= unts the number of cycles that the Vertical TGC ring is being used at this = ring stop. This includes when packets are passing by and when packets are = being sunk, but does not include when packets are being sent from the ring = stop.We really have two rings in JKT -- a clockwise ring and a counter-cloc= kwise ring. On the left side of the ring, the UP direction is on the clock= wise ring and DN is on the counter-clockwise ring. On the right side of th= e ring, this is reversed. The first half of the CBos are on the left side = of the ring, and the 2nd half are on the right side of the ring. In other = words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo = 2 UP AD because they are on opposite sides of the ring.", "UMask": "0x8", @@ -8906,8 +10645,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Even", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_EVEN", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Even : Cou= nts the number of cycles that the Vertical TGC ring is being used at this r= ing stop. This includes when packets are passing by and when packets are b= eing sunk, but does not include when packets are being sent from the ring s= top.We really have two rings in JKT -- a clockwise ring and a counter-clock= wise ring. On the left side of the ring, the UP direction is on the clockw= ise ring and DN is on the counter-clockwise ring. On the right side of the= ring, this is reversed. The first half of the CBos are on the left side o= f the ring, and the 2nd half are on the right side of the ring. In other w= ords (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2= UP AD because they are on opposite sides of the ring.", "UMask": "0x1", @@ -8915,8 +10656,10 @@ }, { "BriefDescription": "Vertical TGC Ring In Use : Up and Odd", + "Counter": "0,1,2,3", "EventCode": "0xb5", "EventName": "UNC_M2P_VERT_RING_TGC_IN_USE.UP_ODD", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Vertical TGC Ring In Use : Up and Odd : Coun= ts the number of cycles that the Vertical TGC ring is being used at this ri= ng stop. This includes when packets are passing by and when packets are be= ing sunk, but does not include when packets are being sent from the ring st= op.We really have two rings in JKT -- a clockwise ring and a counter-clockw= ise ring. On the left side of the ring, the UP direction is on the clockwi= se ring and DN is on the counter-clockwise ring. On the right side of the = ring, this is reversed. The first half of the CBos are on the left side of= the ring, and the 2nd half are on the right side of the ring. In other wo= rds (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 = UP AD because they are on opposite sides of the ring.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json b= /tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json index b80911d498dd..2f6907cba7f6 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "read requests to memory controller. Derived f= rom unc_m_cas_count.rd", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_READ", "PerPkg": "1", @@ -11,6 +12,7 @@ }, { "BriefDescription": "write requests to memory controller. Derived = from unc_m_cas_count.wr", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "LLC_MISSES.MEM_WRITE", "PerPkg": "1", @@ -21,6 +23,7 @@ }, { "BriefDescription": "DRAM Activate Count : All Activates", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.ALL", "PerPkg": "1", @@ -30,8 +33,10 @@ }, { "BriefDescription": "DRAM Activate Count : Activate due to Bypass", + "Counter": "0,1,2,3", "EventCode": "0x01", "EventName": "UNC_M_ACT_COUNT.BYP", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Activate Count : Activate due to Bypass= : Counts the number of DRAM Activate commands sent on this channel. Activ= ate commands are issued to open up a page on the DRAM devices so that it ca= n be read or written to with a CAS. One can calculate the number of Page M= isses by subtracting the number of Page Miss precharges from the number of = Activates.", "UMask": "0x8", @@ -39,6 +44,7 @@ }, { "BriefDescription": "All DRAM CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.ALL", "PerPkg": "1", @@ -48,6 +54,7 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (including = underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD", "PerPkg": "1", @@ -57,8 +64,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CA= S commands w/auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total= number or DRAM Read CAS commands issued on this channel. This includes bo= th regular RD CAS commands as well as those with explicit Precharge. AutoP= re is only used in systems that are using closed page policy. We do not fi= lter based on major mode, as RD_CAS is not issued during WMM (with the exce= ption of underfills).", "UMask": "0x2", @@ -66,8 +75,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_C= AS and WR_CAS Commands", "UMask": "0x8", @@ -75,8 +86,10 @@ }, { "BriefDescription": "All DRAM read CAS commands issued (does not i= nclude underfills)", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_REG", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total number of DRAM Read CAS com= mands issued on this channel. This includes both regular RD CAS commands a= s well as those with implicit Precharge. We do not filter based on major = mode, as RD_CAS is not issued during WMM (with the exception of underfills)= .", "UMask": "0x1", @@ -84,8 +97,10 @@ }, { "BriefDescription": "DRAM underfill read CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Counts the total of DRAM Read CAS commands i= ssued due to an underfill", "UMask": "0x4", @@ -93,6 +108,7 @@ }, { "BriefDescription": "All DRAM write CAS commands issued", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR", "PerPkg": "1", @@ -102,8 +118,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/o auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_NONPRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x10", @@ -111,8 +129,10 @@ }, { "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CA= S commands w/ auto-pre", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_M_CAS_COUNT.WR_PRE", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_C= AS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands", "UMask": "0x20", @@ -120,6 +140,7 @@ }, { "BriefDescription": "Memory controller clock ticks", + "Counter": "0,1,2,3", "EventName": "UNC_M_CLOCKTICKS", "PerPkg": "1", "PublicDescription": "Clockticks of the integrated memory controll= er (IMC)", @@ -127,22 +148,27 @@ }, { "BriefDescription": "Free running counter that increments for the = Memory Controller", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_M_CLOCKTICKS_FREERUN", + "Experimental": "1", "PerPkg": "1", "UMask": "0x10", "Unit": "imc_free_running" }, { "BriefDescription": "DRAM Precharge All Commands", + "Counter": "0,1,2,3", "EventCode": "0x44", "EventName": "UNC_M_DRAM_PRE_ALL", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge All Commands : Counts the num= ber of times that the precharge all command was sent.", "Unit": "iMC" }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.HIGH", "PerPkg": "1", @@ -152,6 +178,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC", "PerPkg": "1", @@ -161,6 +188,7 @@ }, { "BriefDescription": "Number of DRAM Refreshes Issued", + "Counter": "0,1,2,3", "EventCode": "0x45", "EventName": "UNC_M_DRAM_REFRESH.PANIC", "PerPkg": "1", @@ -170,6 +198,7 @@ }, { "BriefDescription": "Half clockticks for IMC", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_M_HCLOCKTICKS", "PerPkg": "1", @@ -177,39 +206,49 @@ }, { "BriefDescription": "UNC_M_PARITY_ERRORS", + "Counter": "0,1,2,3", "EventCode": "0x2c", "EventName": "UNC_M_PARITY_ERRORS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.RD", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.TOTAL", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.TOTAL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x4", "Unit": "iMC" }, { "BriefDescription": "UNC_M_PCLS.WR", + "Counter": "0,1,2,3", "EventCode": "0xA0", "EventName": "UNC_M_PCLS.WR", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "iMC" }, { "BriefDescription": "Cycles where DRAM ranks are in power down (CK= E) mode", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "UNC_M_POWER_CHANNEL_PPD", + "Experimental": "1", "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100", "MetricName": "power_channel_ppd", "PerPkg": "1", @@ -218,8 +257,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x1", @@ -227,8 +268,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x2", @@ -236,8 +279,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x4", @@ -245,8 +290,10 @@ }, { "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID", + "Counter": "0,1,2,3", "EventCode": "0x47", "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of = cycles spent in CKE ON mode. The filter allows you to select a rank to mon= itor. If multiple ranks are in CKE ON mode at one time, the counter will O= NLY increment by one rather than doing accumulation. Multiple counters wil= l need to be used to track multiple ranks simultaneously. There is no dist= inction between the different CKE modes (APD, PPDS, PPDF). This can be det= ermined based on the system programming. These events should commonly be u= sed with Invert to get the number of cycles in power saving mode. Edge Det= ect is also useful here. Make sure that you do NOT use Invert with Edge De= tect (this just confuses the system and is not necessary).", "UMask": "0x8", @@ -254,8 +301,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -263,8 +312,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x86", "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -272,8 +323,10 @@ }, { "BriefDescription": "Cycles Memory is in self refresh power mode", + "Counter": "0,1,2,3", "EventCode": "0x43", "EventName": "UNC_M_POWER_SELF_REFRESH", + "Experimental": "1", "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100= ", "MetricName": "power_self_refresh", "PerPkg": "1", @@ -282,8 +335,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1. : T= hermal throttling is performed per DIMM. We support 3 DIMMs per channel. = This ID allows us to filter by ID.", "UMask": "0x1", @@ -291,8 +346,10 @@ }, { "BriefDescription": "Throttle Cycles for Rank 0", + "Counter": "0,1,2,3", "EventCode": "0x46", "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Throttle Cycles for Rank 0 : Counts the numb= er of cycles while the iMC is being throttled by either thermal constraints= or by the PCU throttling. It is not possible to distinguish between the t= wo. This can be filtered by rank. If multiple ranks are selected and are = being throttled at the same time, the counter will only increment by 1.", "UMask": "0x2", @@ -300,6 +357,7 @@ }, { "BriefDescription": "DRAM Precharge commands.", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.ALL", "PerPkg": "1", @@ -309,8 +367,10 @@ }, { "BriefDescription": "Pre-charges due to page misses", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PAGE_MISS", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "DRAM Precharge commands. : Precharge due to = page miss : Counts the number of DRAM Precharge commands sent on this chann= el. : Pages Misses are due to precharges from bank scheduler (rd/wr request= s)", "UMask": "0xc", @@ -318,6 +378,7 @@ }, { "BriefDescription": "DRAM Precharge commands. : Precharge due to p= age table", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.PGT", "PerPkg": "1", @@ -327,6 +388,7 @@ }, { "BriefDescription": "Pre-charge for reads", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.RD", "PerPkg": "1", @@ -336,6 +398,7 @@ }, { "BriefDescription": "Pre-charge for writes", + "Counter": "0,1,2,3", "EventCode": "0x02", "EventName": "UNC_M_PRE_COUNT.WR", "PerPkg": "1", @@ -345,52 +408,66 @@ }, { "BriefDescription": "Read Data Buffer Full", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "UNC_M_RDB_FULL", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Inserts", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "UNC_M_RDB_INSERTS", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "UNC_M_RDB_NOT_EMPTY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Data Buffer Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x1A", "EventName": "UNC_M_RDB_OCCUPANCY", + "Experimental": "1", "PerPkg": "1", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x15", "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Full Cycles : Counts the = number of cycles when the Read Pending Queue is full. When the RPQ is full= , the HA will not be able to issue any additional read requests into the iM= C. This count should be similar count in the HA which tracks the number of= cycles that the HA has no RPQ credits, just somewhat smaller to account fo= r the credit return overhead. We generally do not expect to see RPQ become= full except for potentially during Write Major Mode or while running with = slow DRAM. This event only tracks non-ISOC queue entries.", "Unit": "iMC" }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x1", @@ -398,8 +475,10 @@ }, { "BriefDescription": "Read Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x11", "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Read Pending Queue Not Empty : Counts the nu= mber of cycles that the Read Pending Queue is not empty. This can then be = used to calculate the average occupancy (in conjunction with the Read Pendi= ng Queue Occupancy count). The RPQ is used to schedule reads out to the me= mory controller and to track the requests. Requests allocate into the RPQ = soon after they enter the memory controller, and need credits for an entry = in this buffer before being sent from the HA to the iMC. They deallocate a= fter the CAS command has been issued to memory. This filter is to be used = in conjunction with the occupancy filter so that one can correctly track th= e average occupancies for schedulable entries and scheduled requests.", "UMask": "0x2", @@ -407,6 +486,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH0", "PerPkg": "1", @@ -416,6 +496,7 @@ }, { "BriefDescription": "Read Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "UNC_M_RPQ_INSERTS.PCH1", "PerPkg": "1", @@ -425,6 +506,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -433,6 +515,7 @@ }, { "BriefDescription": "Read Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -441,24 +524,30 @@ }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x22", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Full Cycles", + "Counter": "0,1,2,3", "EventCode": "0x16", "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Full Cycles : Counts the= number of cycles when the Write Pending Queue is full. When the WPQ is fu= ll, the HA will not be able to issue any additional write requests into the= iMC. This count should be similar count in the CHA which tracks the numbe= r of cycles that the CHA has no WPQ credits, just somewhat smaller to accou= nt for the credit return overhead.", "Unit": "iMC" }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x1", @@ -466,8 +555,10 @@ }, { "BriefDescription": "Write Pending Queue Not Empty", + "Counter": "0,1,2,3", "EventCode": "0x21", "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue Not Empty : Counts the n= umber of cycles that the Write Pending Queue is not empty. This can then b= e used to calculate the average queue occupancy (in conjunction with the WP= Q Occupancy Accumulation count). The WPQ is used to schedule write out to = the memory controller and to track the writes. Requests allocate into the = WPQ soon after they enter the memory controller, and need credits for an en= try in this buffer before being sent from the CHA to the iMC. They dealloc= ate after being issued to DRAM. Write requests themselves are able to comp= lete (from the perspective of the rest of the system) as soon they have pos= ted to the iMC. This is not to be confused with actually performing the wr= ite to DRAM. Therefore, the average latency for this queue is actually not= useful for deconstruction intermediate write latencies.", "UMask": "0x2", @@ -475,6 +566,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH0", "PerPkg": "1", @@ -484,6 +576,7 @@ }, { "BriefDescription": "Write Pending Queue Allocations", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "UNC_M_WPQ_INSERTS.PCH1", "PerPkg": "1", @@ -493,6 +586,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0", "PerPkg": "1", @@ -501,6 +595,7 @@ }, { "BriefDescription": "Write Pending Queue Occupancy", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1", "PerPkg": "1", @@ -509,8 +604,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -518,8 +615,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x23", "EventName": "UNC_M_WPQ_READ_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", @@ -527,8 +626,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x1", @@ -536,8 +637,10 @@ }, { "BriefDescription": "Write Pending Queue CAM Match", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Write Pending Queue CAM Match : Counts the n= umber of times a request hits in the WPQ (write-pending queue). The iMC al= lows writes and reads to pass up other writes to different addresses. Befo= re a read or a write is issued, it will first CAM the WPQ to see if there i= s a write pending to that address. When reads hit, they are able to direct= ly pull their data from the WPQ instead of going to memory. Writes that hi= t will overwrite the existing data. Partial writes that hit will not need = to do underfill reads and will simply update their relevant sections.", "UMask": "0x2", diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json b/= tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json index dcf268467db9..1d59c9b65b3f 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/uncore-power.json @@ -1,153 +1,192 @@ [ { "BriefDescription": "Clockticks of the power control unit (PCU)", + "Counter": "0,1,2,3", "EventName": "UNC_P_CLOCKTICKS", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_CORE_TRANSITION_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "UNC_P_CORE_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "UNC_P_DEMOTIONS", + "Counter": "0,1,2,3", "EventCode": "0x30", "EventName": "UNC_P_DEMOTIONS", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 0 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x75", "EventName": "UNC_P_FIVR_PS_PS0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 0 Cycles : Cycles spent in phase-= shedding power state 0", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 1 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x76", "EventName": "UNC_P_FIVR_PS_PS1_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 1 Cycles : Cycles spent in phase-= shedding power state 1", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 2 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x77", "EventName": "UNC_P_FIVR_PS_PS2_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 2 Cycles : Cycles spent in phase-= shedding power state 2", "Unit": "PCU" }, { "BriefDescription": "Phase Shed 3 Cycles", + "Counter": "0,1,2,3", "EventCode": "0x78", "EventName": "UNC_P_FIVR_PS_PS3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Phase Shed 3 Cycles : Cycles spent in phase-= shedding power state 3", "Unit": "PCU" }, { "BriefDescription": "AVX256 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "UNC_P_FREQ_CLIP_AVX256", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "AVX512 Frequency Clipping", + "Counter": "0,1,2,3", "EventCode": "0x4a", "EventName": "UNC_P_FREQ_CLIP_AVX512", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Thermal Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x04", "EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Thermal Strongest Upper Limit Cycles : Numbe= r of cycles any frequency is reduced due to a thermal limit. Count only if= throttling is occurring.", "Unit": "PCU" }, { "BriefDescription": "Power Strongest Upper Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x05", "EventName": "UNC_P_FREQ_MAX_POWER_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Power Strongest Upper Limit Cycles : Counts = the number of cycles when power is the upper limit on frequency.", "Unit": "PCU" }, { "BriefDescription": "IO P Limit Strongest Lower Limit Cycles", + "Counter": "0,1,2,3", "EventCode": "0x73", "EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "IO P Limit Strongest Lower Limit Cycles : Co= unts the number of cycles when IO P Limit is preventing us from dropping th= e frequency lower. This algorithm monitors the needs to the IO subsystem o= n both local and remote sockets and will maintain a frequency high enough t= o maintain good IO BW. This is necessary for when all the IA cores on a so= cket are idle but a user still would like to maintain high IO Bandwidth.", "Unit": "PCU" }, { "BriefDescription": "Cycles spent changing Frequency", + "Counter": "0,1,2,3", "EventCode": "0x74", "EventName": "UNC_P_FREQ_TRANS_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Cycles spent changing Frequency : Counts the= number of cycles when the system is changing frequency. This can not be f= iltered by thread ID. One can also use it with the occupancy counter that = monitors number of threads in C0 to estimate the performance impact that fr= equency transitions had on the system.", "Unit": "PCU" }, { "BriefDescription": "Memory Phase Shedding Cycles", + "Counter": "0,1,2,3", "EventCode": "0x2F", "EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Memory Phase Shedding Cycles : Counts the nu= mber of cycles that the PCU has triggered memory phase shedding. This is a= mode that can be run in the iMC physicals that saves power at the expense = of additional latency.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C0", + "Counter": "0,1,2,3", "EventCode": "0x2A", "EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C0 : Counts the = number of cycles when the package was in C0. This event can be used in con= junction with edge detect to count C0 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C2E", + "Counter": "0,1,2,3", "EventCode": "0x2B", "EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C2E : Counts the= number of cycles when the package was in C2E. This event can be used in c= onjunction with edge detect to count C2E entrances (or exits using invert).= Residency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C3", + "Counter": "0,1,2,3", "EventCode": "0x2C", "EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C3 : Counts the = number of cycles when the package was in C3. This event can be used in con= junction with edge detect to count C3 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "Package C State Residency - C6", + "Counter": "0,1,2,3", "EventCode": "0x2D", "EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Package C State Residency - C6 : Counts the = number of cycles when the package was in C6. This event can be used in con= junction with edge detect to count C6 entrances (or exits using invert). R= esidency events do not include transition times.", "Unit": "PCU" }, { "BriefDescription": "UNC_P_PMAX_THROTTLED_CYCLES", + "Counter": "0,1,2,3", "EventCode": "0x06", "EventName": "UNC_P_PMAX_THROTTLED_CYCLES", + "Experimental": "1", "PerPkg": "1", "Unit": "PCU" }, { "BriefDescription": "Number of cores in C-State : C0 and C1", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C0 and C1 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0x40", @@ -155,8 +194,10 @@ }, { "BriefDescription": "Number of cores in C-State : C3", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C3 : This is an= occupancy event that tracks the number of cores that are in the chosen C-S= tate. It can be used by itself to get the average number of cores in that = C-state with thresholding to generate histograms, or with other PCU events = and occupancy triggering to capture other details.", "UMask": "0x80", @@ -164,8 +205,10 @@ }, { "BriefDescription": "Number of cores in C-State : C6 and C7", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Number of cores in C-State : C6 and C7 : Thi= s is an occupancy event that tracks the number of cores that are in the cho= sen C-State. It can be used by itself to get the average number of cores i= n that C-state with thresholding to generate histograms, or with other PCU = events and occupancy triggering to capture other details.", "UMask": "0xc0", @@ -173,32 +216,40 @@ }, { "BriefDescription": "External Prochot", + "Counter": "0,1,2,3", "EventCode": "0x0A", "EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "External Prochot : Counts the number of cycl= es that we are in external PROCHOT mode. This mode is triggered when a sen= sor off the die determines that something off-die (like DRAM) is too hot an= d must throttle to avoid damaging the chip.", "Unit": "PCU" }, { "BriefDescription": "Internal Prochot", + "Counter": "0,1,2,3", "EventCode": "0x09", "EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Internal Prochot : Counts the number of cycl= es that we are in Internal PROCHOT mode. This mode is triggered when a sen= sor on the die determines that we are too hot and must throttle to avoid da= maging the chip.", "Unit": "PCU" }, { "BriefDescription": "Total Core C State Transition Cycles", + "Counter": "0,1,2,3", "EventCode": "0x72", "EventName": "UNC_P_TOTAL_TRANSITION_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "Total Core C State Transition Cycles : Numbe= r of cycles spent performing core C state transitions across all cores.", "Unit": "PCU" }, { "BriefDescription": "VR Hot", + "Counter": "0,1,2,3", "EventCode": "0x42", "EventName": "UNC_P_VR_HOT_CYCLES", + "Experimental": "1", "PerPkg": "1", "PublicDescription": "VR Hot : Number of cycles that a CPU SVID VR= is hot. Does not cover DRAM VRs", "Unit": "PCU" diff --git a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json index cabe29e70e79..f9a6caed8776 100644 --- a/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/snowridgex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of page walks due to loads = that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "200003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to a demand load that did not start a page walk. A= ccount for all page sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "200003", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to any page si= ze. Includes page walks that page fault.", @@ -23,6 +26,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 1GB pages. = Includes page walks that page fault.", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pa= ges. Includes page walks that page fault.", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to load DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to loads (including SW prefetches) whose address translations missed in a= ll Translation Lookaside Buffer (TLB) levels and were mapped to 4K pages. I= ncludes page walks that page fault.", @@ -47,6 +53,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for demand loads every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for demand loads every cycle. A page walk i= s outstanding from start till PMH becomes idle again (ready to serve next w= alk). Includes EPT-walk intervals.", @@ -55,6 +62,7 @@ }, { "BriefDescription": "Counts the number of page walks due to stores= that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -62,6 +70,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to stores that did not start a page walk. Account = for all pages sizes. Will result in a DTLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -69,6 +78,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to any page size. Includes page walks = that page fault.", @@ -77,6 +87,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 1G pages. Includes page walks that = page fault.", @@ -85,6 +96,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 2M or 4M pages. Includes page walks= that page fault.", @@ -93,6 +105,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to store DTLB misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to stores whose address translations missed in all Translation Lookaside = Buffer (TLB) levels and were mapped to 4K pages. Includes page walks that = page fault.", @@ -101,6 +114,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for stores every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for stores every cycle. A page walk is outs= tanding from start till PMH becomes idle again (ready to serve next walk). = Includes EPT-walk intervals.", @@ -109,6 +123,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_HIT", "PublicDescription": "Counts the number of Extended Page Directory= Entry hits. The Extended Page Directory cache is used by Virtual Machine = operating systems while the guest operating systems use the standard TLB ca= ches.", @@ -117,6 +132,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDE_MISS", "PublicDescription": "Counts the number Extended Page Directory En= try misses. The Extended Page Directory cache is used by Virtual Machine o= perating systems while the guest operating systems use the standard TLB cac= hes.", @@ -125,6 +141,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry hits.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_HIT", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry hits. The Extended Page Directory cache is used by Virtual Mac= hine operating systems while the guest operating systems use the standard T= LB caches.", @@ -133,6 +150,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Directory = Pointer Entry misses.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.EPDPE_MISS", "PublicDescription": "Counts the number Extended Page Directory Po= inter Entry misses. The Extended Page Directory cache is used by Virtual M= achine operating systems while the guest operating systems use the standard= TLB caches.", @@ -141,6 +159,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding f= or an Extended Page table walk including GTLB hits per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an Extended Page table walk including GTLB hits per cycle. The Extende= d Page Directory cache is used by Virtual Machine operating systems while t= he guest operating systems use the standard TLB caches.", @@ -149,6 +168,7 @@ }, { "BriefDescription": "Counts the number of times there was an ITLB = miss and a new translation was filled into the ITLB.", + "Counter": "0,1,2,3", "EventCode": "0x81", "EventName": "ITLB.FILLS", "PublicDescription": "Counts the number of times the machine was u= nable to find a translation in the Instruction Translation Lookaside Buffer= (ITLB) and a new translation was filled into the ITLB. The event is specul= ative in nature, but will not count translations (page walks) that are begu= n and not finished, or translations that are finished but not filled into t= he ITLB.", @@ -157,6 +177,7 @@ }, { "BriefDescription": "Counts the number of page walks due to an ins= truction fetch that miss the PDE (Page Directory Entry) cache.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.PDE_CACHE_MISS", "SampleAfterValue": "2000003", @@ -164,6 +185,7 @@ }, { "BriefDescription": "Counts the number of first level TLB misses b= ut second level hits due to an instruction fetch that did not start a page = walk. Account for all pages sizes. Will result in an ITLB write from STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "SampleAfterValue": "2000003", @@ -171,6 +193,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to any page size.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to any page size. Include= s page walks that page fault.", @@ -179,6 +202,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 1G page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 1G pages. Includes pag= e walks that page fault.", @@ -187,6 +211,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 2M or 4M page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 2M or 4M pages. Includ= es page walks that page fault.", @@ -195,6 +220,7 @@ }, { "BriefDescription": "Counts the number of page walks completed due= to instruction fetch misses to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts the number of page walks completed du= e to instruction fetches whose address translations missed in all Translati= on Lookaside Buffer (TLB) levels and were mapped to 4K pages. Includes pag= e walks that page fault.", @@ -203,6 +229,7 @@ }, { "BriefDescription": "Counts the number of page walks outstanding i= n the page miss handler (PMH) for instruction fetches every cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = in the page miss handler (PMH) for instruction fetches every cycle. A page= walk is outstanding from start till PMH becomes idle again (ready to serve= next walk).", @@ -211,6 +238,7 @@ }, { "BriefDescription": "Counts the number of retired loads that are b= locked due to a first level TLB miss.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.DTLB_MISS", "PEBS": "1", @@ -219,6 +247,7 @@ }, { "BriefDescription": "Counts the number of memory uops retired that= missed in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS", @@ -228,6 +257,7 @@ }, { "BriefDescription": "Counts the number of load uops retired that m= iss in the second Level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Counts the number of store uops retired that = miss in the second level TLB.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pf1-f201.google.com (mail-pf1-f201.google.com [209.85.210.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6A621BBBE0 for ; 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Thu, 20 Jun 2024 11:20:36 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:48 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-35-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 34/37] perf vendor events: Add/update tigerlake events/metrics From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update events from v1.15 to v1.16. Update TMA metrics from v4.7 to v4.8. Bring in the event updates v1.16: https://github.com/intel/perfmon/commit/43f3b8d6f82f3174bd3bffe8587e2179f08= 6d2ce The TMA 4.8 information was added in: https://github.com/intel/perfmon/commit/59194d4d90ca50a3fcb2de0d82b9f6fc0c9= a5736 Add counter information. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +- .../pmu-events/arch/x86/tigerlake/cache.json | 73 +++++++ .../arch/x86/tigerlake/counter.json | 17 ++ .../arch/x86/tigerlake/floating-point.json | 13 ++ .../arch/x86/tigerlake/frontend.json | 41 +++- .../pmu-events/arch/x86/tigerlake/memory.json | 24 +++ .../arch/x86/tigerlake/metricgroups.json | 13 ++ .../pmu-events/arch/x86/tigerlake/other.json | 4 + .../arch/x86/tigerlake/pipeline.json | 95 +++++++++ .../arch/x86/tigerlake/tgl-metrics.json | 198 +++++++++++------- .../x86/tigerlake/uncore-interconnect.json | 19 ++ .../arch/x86/tigerlake/uncore-memory.json | 6 + .../arch/x86/tigerlake/uncore-other.json | 1 + .../arch/x86/tigerlake/virtual-memory.json | 20 ++ 14 files changed, 446 insertions(+), 80 deletions(-) create mode 100644 tools/perf/pmu-events/arch/x86/tigerlake/counter.json diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-ev= ents/arch/x86/mapfile.csv index f4adfc157197..d503aa7e3594 100644 --- a/tools/perf/pmu-events/arch/x86/mapfile.csv +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv @@ -32,7 +32,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core GenuineIntel-6-55-[01234],v1.35,skylakex,core GenuineIntel-6-86,v1.23,snowridgex,core -GenuineIntel-6-8[CD],v1.15,tigerlake,core +GenuineIntel-6-8[CD],v1.16,tigerlake,core GenuineIntel-6-2C,v5,westmereep-dp,core GenuineIntel-6-25,v4,westmereep-sp,core GenuineIntel-6-2F,v4,westmereex,core diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json b/tools/pe= rf/pmu-events/arch/x86/tigerlake/cache.json index c54fb65d3259..f4144a1110be 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/cache.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the number of cache lines replaced in = L1 data cache.", + "Counter": "0,1,2,3", "EventCode": "0x51", "EventName": "L1D.REPLACEMENT", "PublicDescription": "Counts L1D data line replacements including = opportunistic replacements, and replacements that require stall-for-replace= or block-for-replace.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.FB_FULL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D Fill Buffer (FB) unavailability. Demand requests include= cacheable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of phases a demand request has waited = due to L1D Fill Buffer (FB) unavailability.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x48", @@ -27,6 +30,7 @@ }, { "BriefDescription": "Number of cycles a demand request has waited = due to L1D due to lack of L2 resources.", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.L2_STALL", "PublicDescription": "Counts number of cycles a demand request has= waited due to L1D due to lack of L2 resources. Demand requests include cac= heable/uncacheable demand load, store, lock or SW prefetch accesses.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Number of L1D misses that are outstanding", + "Counter": "0,1,2,3", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING", "PublicDescription": "Counts number of L1D misses that are outstan= ding in each cycle, that is each cycle the number of Fill Buffers (FB) outs= tanding required by Demand Reads. FB either is held by demand loads, or it = is held by non-demand loads and gets hit at least once by demand. The valid= outstanding interval is defined until the FB deallocation by one of the fo= llowing ways: from FB allocation, if FB is allocated by demand from the dem= and Hit FB, if it is allocated by hardware or software prefetch. Note: In t= he L1D, a Demand Read contains cacheable or noncacheable demand loads, incl= uding ones causing cache-line splits and reads due to page walks resulted f= rom any request type.", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Cycles with L1D load Misses outstanding.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x48", "EventName": "L1D_PEND_MISS.PENDING_CYCLES", @@ -52,6 +58,7 @@ }, { "BriefDescription": "L2 cache lines filling L2", + "Counter": "0,1,2,3", "EventCode": "0xf1", "EventName": "L2_LINES_IN.ALL", "PublicDescription": "Counts the number of L2 cache lines filling = the L2. Counting does not cover rejects.", @@ -60,6 +67,7 @@ }, { "BriefDescription": "Modified cache lines that are evicted by L2 c= ache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xf2", "EventName": "L2_LINES_OUT.NON_SILENT", "PublicDescription": "Counts the number of lines that are evicted = by L2 cache when triggered by an L2 cache fill. Those lines are in Modified= state. Modified lines are written back to L3", @@ -68,6 +76,7 @@ }, { "BriefDescription": "Non-modified cache lines that are silently dr= opped by L2 cache when triggered by an L2 cache fill.", + "Counter": "0,1,2,3", "EventCode": "0xf2", "EventName": "L2_LINES_OUT.SILENT", "PublicDescription": "Counts the number of lines that are silently= dropped by L2 cache when triggered by an L2 cache fill. These lines are ty= pically in Shared or Exclusive state. A non-threaded event.", @@ -76,6 +85,7 @@ }, { "BriefDescription": "L2 code requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_CODE_RD", "PublicDescription": "Counts the total number of L2 code requests.= ", @@ -84,6 +94,7 @@ }, { "BriefDescription": "Demand Data Read access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "PublicDescription": "Counts Demand Data Read requests accessing t= he L2 cache. These requests may hit or miss L2 cache. True-miss exclude mis= ses that were merged with ongoing L2 misses. An access is counted once.", @@ -92,6 +103,7 @@ }, { "BriefDescription": "RFO requests to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.ALL_RFO", "PublicDescription": "Counts the total number of RFO (read for own= ership) requests to L2 cache. L2 RFO requests include both L1D demand RFO m= isses as well as L1D RFO prefetches.", @@ -100,6 +112,7 @@ }, { "BriefDescription": "L2 cache hits when fetching instructions, cod= e reads.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT", "PublicDescription": "Counts L2 cache hits when fetching instructi= ons, code reads.", @@ -108,6 +121,7 @@ }, { "BriefDescription": "L2 cache misses when fetching instructions", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.CODE_RD_MISS", "PublicDescription": "Counts L2 cache misses when fetching instruc= tions.", @@ -116,6 +130,7 @@ }, { "BriefDescription": "Demand Data Read requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "PublicDescription": "Counts the number of demand Data Read reques= ts initiated by load instructions that hit L2 cache.", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Demand Data Read miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "PublicDescription": "Counts demand Data Read requests with true-m= iss in the L2 cache. True-miss excludes misses that were merged with ongoin= g L2 misses. An access is counted once.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Read requests with true-miss in L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "PublicDescription": "Counts read requests of any type with true-m= iss in the L2 cache. True-miss excludes L2 misses that were merged with ong= oing L2 misses.", @@ -140,6 +157,7 @@ }, { "BriefDescription": "All accesses to L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "PublicDescription": "Counts all requests that were hit or true mi= sses in L2 cache. True-miss excludes misses that were merged with ongoing L= 2 misses.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "RFO requests that hit L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that hit L2 cache.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "RFO requests that miss L2 cache", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "PublicDescription": "Counts the RFO (Read-for-Ownership) requests= that miss L2 cache.", @@ -164,6 +184,7 @@ }, { "BriefDescription": "SW prefetch requests that hit L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_HIT", "PublicDescription": "Counts Software prefetch requests that hit t= he L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when = FB is not full.", @@ -172,6 +193,7 @@ }, { "BriefDescription": "SW prefetch requests that miss L2 cache.", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.SWPF_MISS", "PublicDescription": "Counts Software prefetch requests that miss = the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when= FB is not full.", @@ -180,6 +202,7 @@ }, { "BriefDescription": "L2 writebacks that access L2 cache", + "Counter": "0,1,2,3", "EventCode": "0xf0", "EventName": "L2_TRANS.L2_WB", "PublicDescription": "Counts L2 writebacks that access L2 cache.", @@ -188,6 +211,7 @@ }, { "BriefDescription": "Cycles when L1D is locked", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", "PublicDescription": "This event counts the number of cycles when = the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LO= CK_DURATION).", @@ -196,6 +220,7 @@ }, { "BriefDescription": "Core-originated cacheable requests that misse= d L3 (Except hardware prefetches to the L3)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x2e", "EventName": "LONGEST_LAT_CACHE.MISS", "PublicDescription": "Counts core-originated cacheable requests th= at miss the L3 cache (Longest Latency cache). Requests include data and cod= e reads, Reads-for-Ownership (RFOs), speculative accesses and hardware pref= etches to the L1 and L2. It does not include hardware prefetches to the L3= , and may not count other types of requests to the L3.", @@ -204,6 +229,7 @@ }, { "BriefDescription": "Retired load instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_LOADS", @@ -214,6 +240,7 @@ }, { "BriefDescription": "Retired store instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ALL_STORES", @@ -224,6 +251,7 @@ }, { "BriefDescription": "All retired memory instructions.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.ANY", @@ -234,6 +262,7 @@ }, { "BriefDescription": "Retired load instructions with locked access.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.LOCK_LOADS", @@ -244,6 +273,7 @@ }, { "BriefDescription": "Retired load instructions that split across a= cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_LOADS", @@ -254,6 +284,7 @@ }, { "BriefDescription": "Retired store instructions that split across = a cacheline boundary.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.SPLIT_STORES", @@ -264,6 +295,7 @@ }, { "BriefDescription": "Retired load instructions that miss the STLB.= ", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS", @@ -274,6 +306,7 @@ }, { "BriefDescription": "Retired store instructions that miss the STLB= .", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd0", "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES", @@ -284,6 +317,7 @@ }, { "BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_= W_FWD) in another on-pkg core which forwarded the data back due to a retire= d load instruction.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD", @@ -294,6 +328,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were L3 hit and cross-core snoop missed in on-pkg core cache.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS", @@ -304,6 +339,7 @@ }, { "BriefDescription": "Retired load instructions whose data sources = were hits in L3 without snoops required", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE", @@ -314,6 +350,7 @@ }, { "BriefDescription": "Snoop hit without forwarding in another on-pk= g core due to a retired load instruction, data was supplied by the L3.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd2", "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD", @@ -324,6 +361,7 @@ }, { "BriefDescription": "Retired instructions with at least 1 uncachea= ble load or lock.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd4", "EventName": "MEM_LOAD_MISC_RETIRED.UC", @@ -334,6 +372,7 @@ }, { "BriefDescription": "Number of completed demand load requests that= missed the L1, but hit the FB(fill buffer), because a preceding miss to th= e same cacheline initiated the line to be brought into L1, but data is not = yet ready in L1.", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.FB_HIT", @@ -344,6 +383,7 @@ }, { "BriefDescription": "Retired load instructions with L1 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_HIT", @@ -354,6 +394,7 @@ }, { "BriefDescription": "Retired load instructions missed L1 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L1_MISS", @@ -364,6 +405,7 @@ }, { "BriefDescription": "Retired load instructions with L2 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_HIT", @@ -374,6 +416,7 @@ }, { "BriefDescription": "Retired load instructions missed L2 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L2_MISS", @@ -384,6 +427,7 @@ }, { "BriefDescription": "Retired load instructions with L3 cache hits = as data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_HIT", @@ -394,6 +438,7 @@ }, { "BriefDescription": "Retired load instructions missed L3 cache as = data sources", + "Counter": "0,1,2,3", "Data_LA": "1", "EventCode": "0xd1", "EventName": "MEM_LOAD_RETIRED.L3_MISS", @@ -404,6 +449,7 @@ }, { "BriefDescription": "Counts demand data reads that hit a cacheline= in the L3 where a snoop hit in another cores caches, data forwarding is re= quired as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -413,6 +459,7 @@ }, { "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) reque= sts and software prefetches for exclusive ownership (PREFETCHW) that hit a = cacheline in the L3 where a snoop hit in another cores caches, data forward= ing is required as the data is modified.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -431,6 +479,7 @@ }, { "BriefDescription": "Demand and prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "PublicDescription": "Counts the demand and prefetch data reads. A= ll Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 p= refetchers). Counting also covers reads due to page walks resulted from any= request type.", @@ -439,6 +488,7 @@ }, { "BriefDescription": "Any memory transaction that reached the SQ.", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS", "PublicDescription": "Counts memory transactions reached the super= queue including requests initiated by the core, all L3 prefetches, page wa= lks, etc..", @@ -447,6 +497,7 @@ }, { "BriefDescription": "Demand Data Read requests sent to uncore", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "PublicDescription": "Counts the Demand Data Read requests sent to= uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determi= ne average latency in the uncore.", @@ -455,6 +506,7 @@ }, { "BriefDescription": "Demand RFO requests including regular RFOs, l= ocks, ItoM", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "PublicDescription": "Counts the demand RFO (read for ownership) r= equests including regular RFOs, locks, ItoM.", @@ -463,6 +515,7 @@ }, { "BriefDescription": "Offcore outstanding cacheable Core Data Read = transactions in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", "PublicDescription": "Counts the number of offcore outstanding cac= heable Core Data Read transactions in the super queue every cycle. A transa= ction is considered to be in the Offcore outstanding state between L2 miss = and transaction completion sent to requestor (SQ de-allocation). See corres= ponding Umask under OFFCORE_REQUESTS.", @@ -471,6 +524,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding cacheable Cor= e Data Read transactions are present in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", @@ -480,6 +534,7 @@ }, { "BriefDescription": "Cycles when offcore outstanding Demand Data R= ead transactions are present in SuperQueue (SQ), queue to uncore", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA= _RD", @@ -489,6 +544,7 @@ }, { "BriefDescription": "Cycles with offcore outstanding demand rfo re= ads transactions in SuperQueue (SQ), queue to uncore.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", @@ -498,6 +554,7 @@ }, { "BriefDescription": "Demand Data Read transactions pending for off= -core. Highly correlated.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", "PublicDescription": "Counts the number of off-core outstanding De= mand Data Read transactions every cycle. A transaction is considered to be = in the Off-core outstanding state between L2 cache miss and data-return to = the core.", @@ -506,6 +563,7 @@ }, { "BriefDescription": "Cycles with at least 6 offcore outstanding De= mand Data Read transactions in uncore queue.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", @@ -514,6 +572,7 @@ }, { "BriefDescription": "Store Read transactions pending for off-core.= Highly correlated.", + "Counter": "0,1,2,3", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", "PublicDescription": "Counts the number of off-core outstanding re= ad-for-ownership (RFO) store transactions every cycle. An RFO transaction i= s considered to be in the Off-core outstanding state between L2 cache miss = and transaction completion.", @@ -522,6 +581,7 @@ }, { "BriefDescription": "Counts bus locks, accounts for cache line spl= it locks and UC locks.", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.BUS_LOCK", "PublicDescription": "Counts the more expensive bus lock needed to= enforce cache coherency for certain memory accesses that need to be done a= tomically. Can be created by issuing an atomic instruction (via the LOCK p= refix) which causes a cache line split or accesses uncacheable memory.", @@ -530,14 +590,24 @@ }, { "BriefDescription": "Cycles the superQ cannot take any more entrie= s.", + "Counter": "0,1,2,3", "EventCode": "0xf4", "EventName": "SQ_MISC.SQ_FULL", "PublicDescription": "Counts the cycles for which the thread is ac= tive and the superQ cannot take any more entries.", "SampleAfterValue": "100003", "UMask": "0x4" }, + { + "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, = PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.", + "Counter": "0,1,2,3", + "EventCode": "0x32", + "EventName": "SW_PREFETCH_ACCESS.ANY", + "SampleAfterValue": "100003", + "UMask": "0xf" + }, { "BriefDescription": "Number of PREFETCHNTA instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.NTA", "PublicDescription": "Counts the number of PREFETCHNTA instruction= s executed.", @@ -546,6 +616,7 @@ }, { "BriefDescription": "Number of PREFETCHW instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.PREFETCHW", "PublicDescription": "Counts the number of PREFETCHW instructions = executed.", @@ -554,6 +625,7 @@ }, { "BriefDescription": "Number of PREFETCHT0 instructions executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T0", "PublicDescription": "Counts the number of PREFETCHT0 instructions= executed.", @@ -562,6 +634,7 @@ }, { "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructio= ns executed.", + "Counter": "0,1,2,3", "EventCode": "0x32", "EventName": "SW_PREFETCH_ACCESS.T1_T2", "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT= 2 instructions executed.", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/counter.json b/tools/= perf/pmu-events/arch/x86/tigerlake/counter.json new file mode 100644 index 000000000000..5a350072522a --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/tigerlake/counter.json @@ -0,0 +1,17 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "8" + }, + { + "Unit": "ARB", + "CountersNumFixed": "0", + "CountersNumGeneric": "2" + }, + { + "Unit": "CLOCK", + "CountersNumFixed": 1, + "CountersNumGeneric": "0" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json b= /tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json index 63b5b56d1ed0..0b04972d0b17 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts all microcode FP assists.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.FP", "PublicDescription": "Counts all microcode Floating Point assists.= ", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 128-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 2 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice = as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 2 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as the= y perform 2 calculations per element. The DAZ and FTZ flags in the MXCSR re= gister need to be set when using these events.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single precision floating-point instructions retired; some instructions w= ill count twice as noted below. Each count represents 4 computation operat= ions, one for each element. Applies to SSE* and AVX* packed single precisi= on floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT = DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they pe= rform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 4 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perf= orm 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 4 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 = calculations per element. The DAZ and FTZ flags in the MXCSR register need = to be set when using these events.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 256-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed single = precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN= MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed single precis= ion floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX S= QRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count tw= ice as they perform 2 calculations per element. The DAZ and FTZ flags in th= e MXCSR register need to be set when using these events.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 128-bit packe= d single and 256-bit packed double precision FP instructions retired; some = instructions will count twice as noted below. Each count represents 2 or/a= nd 4 computation operations, 1 for each element. Applies to SSE* and AVX* = packed single precision and packed double precision FP instructions: ADD SU= B HADD HSUB SUBADD MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DP= P and FM(N)ADD/SUB count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.4_FLOPS", "PublicDescription": "Number of SSE/AVX computational 128-bit pack= ed single precision and 256-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 2 or/and 4 computation operations, one for each element. = Applies to SSE* and AVX* packed single precision floating-point and packed= double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL= DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB ins= tructions count twice as they perform 2 calculations per element. The DAZ a= nd FTZ flags in the MXCSR register need to be set when using these events.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed double precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 8 computation= operations, one for each element. Applies to SSE* and AVX* packed double = precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14= RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform = 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_DOUBLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed double precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 8 computation opera= tions, one for each element. Applies to SSE* and AVX* packed double precis= ion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP14= FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calc= ulations per element. The DAZ and FTZ flags in the MXCSR register need to b= e set when using these events.", @@ -57,6 +64,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational 512-bi= t packed single precision floating-point instructions retired; some instruc= tions will count twice as noted below. Each count represents 16 computatio= n operations, one for each element. Applies to SSE* and AVX* packed single= precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT1= 4 RCP14 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform= 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.512B_PACKED_SINGLE", "PublicDescription": "Number of SSE/AVX computational 512-bit pack= ed single precision floating-point instructions retired; some instructions = will count twice as noted below. Each count represents 16 computation oper= ations, one for each element. Applies to SSE* and AVX* packed single preci= sion floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT14 RCP1= 4 FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 cal= culations per element. The DAZ and FTZ flags in the MXCSR register need to = be set when using these events.", @@ -65,6 +73,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational 256-bit packe= d single precision and 512-bit packed double precision FP instructions ret= ired; some instructions will count twice as noted below. Each count repres= ents 8 computation operations, 1 for each element. Applies to SSE* and AVX= * packed single precision and double precision FP instructions: ADD SUB HAD= D HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14 RCP RCP14 DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB count twice as they perform 2 calculations per elem= ent.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.8_FLOPS", "PublicDescription": "Number of SSE/AVX computational 256-bit pack= ed single precision and 512-bit packed double precision floating-point ins= tructions retired; some instructions will count twice as noted below. Each= count represents 8 computation operations, one for each element. Applies = to SSE* and AVX* packed single precision and double precision floating-poin= t instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RSQRT14= RCP RCP14 DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice= as they perform 2 calculations per element. The DAZ and FTZ flags in the M= XCSR register need to be set when using these events.", @@ -73,6 +82,7 @@ }, { "BriefDescription": "Number of SSE/AVX computational scalar floati= ng-point instructions retired; some instructions will count twice as noted = below. Applies to SSE* and AVX* scalar, double and single precision floati= ng-point: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 RANGE SQRT DPP FM(N)ADD/SUB= . DPP and FM(N)ADD/SUB instructions count twice as they perform multiple c= alculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision and double precision floating-point instructions retired; some = instructions will count twice as noted below. Each count represents 1 comp= utational operation. Applies to SSE* and AVX* scalar single precision float= ing-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB= . FM(N)ADD/SUB instructions count twice as they perform 2 calculations per= element. The DAZ and FTZ flags in the MXCSR register need to be set when u= sing these events.", @@ -81,6 +91,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= double precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar double precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructi= ons count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE", "PublicDescription": "Number of SSE/AVX computational scalar doubl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar double precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions co= unt twice as they perform 2 calculations per element. The DAZ and FTZ flags= in the MXCSR register need to be set when using these events.", @@ -89,6 +100,7 @@ }, { "BriefDescription": "Counts number of SSE/AVX computational scalar= single precision floating-point instructions retired; some instructions wi= ll count twice as noted below. Each count represents 1 computational opera= tion. Applies to SSE* and AVX* scalar single precision floating-point instr= uctions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB= instructions count twice as they perform 2 calculations per element.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "PublicDescription": "Number of SSE/AVX computational scalar singl= e precision floating-point instructions retired; some instructions will cou= nt twice as noted below. Each count represents 1 computational operation. = Applies to SSE* and AVX* scalar single precision floating-point instruction= s: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instr= uctions count twice as they perform 2 calculations per element. The DAZ and= FTZ flags in the MXCSR register need to be set when using these events.", @@ -97,6 +109,7 @@ }, { "BriefDescription": "Number of any Vector retired FP arithmetic in= structions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc7", "EventName": "FP_ARITH_INST_RETIRED.VECTOR", "SampleAfterValue": "1000003", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json b/tools= /perf/pmu-events/arch/x86/tigerlake/frontend.json index d7b972452c0e..13c052d0f470 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts the total number when the front end is= resteered, mainly when the BPU cannot provide a correct prediction and thi= s is corrected by other branch handling mechanisms at the front end.", + "Counter": "0,1,2,3", "EventCode": "0xe6", "EventName": "BACLEARS.ANY", "PublicDescription": "Counts the number of times the front-end is = resteered when it finds a branch instruction in a fetch line. This occurs f= or the first time a branch instruction is fetched or when the branch is not= tracked by the BPU (Branch Prediction Unit) anymore.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to ILD_STALL.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "DECODE.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to ILD_STALL.LCP]", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transition= s count.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xab", @@ -27,6 +30,7 @@ }, { "BriefDescription": "DSB-to-MITE switch true penalty cycles.", + "Counter": "0,1,2,3", "EventCode": "0xab", "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES", "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache th= at holds translations of previously fetched instructions that were decoded = by the legacy x86 decode pipeline (MITE). This event counts fetch penalty c= ycles when a transition occurs from DSB to MITE.", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Retired Instructions who experienced DSB miss= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS", "MSRIndex": "0x3F7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Retired Instructions who experienced a critic= al DSB miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.DSB_MISS", "MSRIndex": "0x3F7", @@ -57,6 +63,7 @@ }, { "BriefDescription": "Retired Instructions who experienced iTLB tru= e miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.ITLB_MISS", "MSRIndex": "0x3F7", @@ -68,6 +75,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L1 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L1I_MISS", "MSRIndex": "0x3F7", @@ -79,6 +87,7 @@ }, { "BriefDescription": "Retired Instructions who experienced Instruct= ion L2 Cache true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.L2_MISS", "MSRIndex": "0x3F7", @@ -90,6 +99,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 1 cycle", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_1", "MSRIndex": "0x3F7", @@ -101,6 +111,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 128 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_128", "MSRIndex": "0x3F7", @@ -112,6 +123,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 16 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_16", "MSRIndex": "0x3F7", @@ -123,6 +135,7 @@ }, { "BriefDescription": "Retired instructions after front-end starvati= on of at least 2 cycles", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2", "MSRIndex": "0x3F7", @@ -134,6 +147,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 256 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_256", "MSRIndex": "0x3F7", @@ -145,6 +159,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end had at least 1 bubble-slot for a period of 2= cycles which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1", "MSRIndex": "0x3F7", @@ -156,6 +171,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 32 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_32", "MSRIndex": "0x3F7", @@ -167,6 +183,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 4 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_4", "MSRIndex": "0x3F7", @@ -178,6 +195,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 512 cycles= which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_512", "MSRIndex": "0x3F7", @@ -189,6 +207,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 64 cycles = which was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_64", "MSRIndex": "0x3F7", @@ -200,6 +219,7 @@ }, { "BriefDescription": "Retired instructions that are fetched after a= n interval where the front-end delivered no uops for a period of 8 cycles w= hich was not interrupted by a back-end stall.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.LATENCY_GE_8", "MSRIndex": "0x3F7", @@ -211,6 +231,7 @@ }, { "BriefDescription": "Retired Instructions who experienced STLB (2n= d level TLB) true miss.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc6", "EventName": "FRONTEND_RETIRED.STLB_MISS", "MSRIndex": "0x3F7", @@ -222,6 +243,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_16B.IFDATA_STALL", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]", @@ -230,6 +252,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that hit in the= instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_HIT", "PublicDescription": "Counts instruction fetch tag lookups that hi= t in the instruction cache (L1I). Counts at 64-byte cache-line granularity.= Accounts for both cacheable and uncacheable accesses.", @@ -238,6 +261,7 @@ }, { "BriefDescription": "Instruction fetch tag lookups that miss in th= e instruction cache (L1I). Counts at 64-byte cache-line granularity.", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_MISS", "PublicDescription": "Counts instruction fetch tag lookups that mi= ss in the instruction cache (L1I). Counts at 64-byte cache-line granularity= . Accounts for both cacheable and uncacheable accesses.", @@ -246,6 +270,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_64B.IFTAG_STALL", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.ST= ALLS]", @@ -254,6 +279,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "ICACHE_DATA.STALLS", "PublicDescription": "Counts cycles where a code line fetch is sta= lled due to an L1 instruction cache miss. The legacy decode pipeline works = at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]", @@ -262,6 +288,7 @@ }, { "BriefDescription": "Cycles where a code fetch is stalled due to L= 1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STAL= L]", + "Counter": "0,1,2,3", "EventCode": "0x83", "EventName": "ICACHE_TAG.STALLS", "PublicDescription": "Counts cycles where a code fetch is stalled = due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IF= TAG_STALL]", @@ -270,6 +297,7 @@ }, { "BriefDescription": "Cycles Decode Stream Buffer (DSB) is deliveri= ng any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_ANY", @@ -279,15 +307,17 @@ }, { "BriefDescription": "Cycles DSB is delivering optimal number of Uo= ps", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.DSB_CYCLES_OK", - "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the M= ITE (legacy decode pipeline) path. During these cycles uops are not being d= elivered from the Decode Stream Buffer (DSB).", + "PublicDescription": "Counts the number of cycles where optimal nu= mber of uops was delivered to the Instruction Decode Queue (IDQ) from the D= SB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the I= DQ.", "SampleAfterValue": "2000003", "UMask": "0x8" }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from the Decode Stream Buffer (DSB) path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.DSB_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.", @@ -296,6 +326,7 @@ }, { "BriefDescription": "Cycles MITE is delivering any Uop", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_ANY", @@ -305,6 +336,7 @@ }, { "BriefDescription": "Cycles MITE is delivering optimal number of U= ops", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0x79", "EventName": "IDQ.MITE_CYCLES_OK", @@ -314,6 +346,7 @@ }, { "BriefDescription": "Uops delivered to Instruction Decode Queue (I= DQ) from MITE path", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MITE_UOPS", "PublicDescription": "Counts the number of uops delivered to Instr= uction Decode Queue (IDQ) from the MITE path. This also means that uops are= not being delivered from the Decode Stream Buffer (DSB).", @@ -322,6 +355,7 @@ }, { "BriefDescription": "Cycles when uops are being delivered to IDQ w= hile MS is busy", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x79", "EventName": "IDQ.MS_CYCLES_ANY", @@ -331,6 +365,7 @@ }, { "BriefDescription": "Number of switches from DSB or MITE to the MS= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x79", @@ -341,6 +376,7 @@ }, { "BriefDescription": "Uops delivered to IDQ while MS is busy", + "Counter": "0,1,2,3", "EventCode": "0x79", "EventName": "IDQ.MS_UOPS", "PublicDescription": "Counts the total number of uops delivered by= the Microcode Sequencer (MS). Any instruction over 4 uops will be delivere= d by the MS. Some instructions such as transcendentals may additionally gen= erate uops from the MS.", @@ -349,6 +385,7 @@ }, { "BriefDescription": "Uops not delivered by IDQ when backend of the= machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "PublicDescription": "Counts the number of uops not delivered to b= y the Instruction Decode Queue (IDQ) to the back-end of the pipeline when t= here was no back-end stalls. This event counts for one SMT thread in a give= n cycle.", @@ -357,6 +394,7 @@ }, { "BriefDescription": "Cycles when no uops are not delivered by the = IDQ when backend of the machine is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", @@ -366,6 +404,7 @@ }, { "BriefDescription": "Cycles when optimal number of uops was delive= red to the back-end when the back-end is not stalled", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x9c", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json b/tools/p= erf/pmu-events/arch/x86/tigerlake/memory.json index 8848fcbcc35c..a125cefa100f 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/memory.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Execution stalls while L3 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "6", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L3_MISS", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Number of machine clears due to memory orderi= ng conflicts.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "PublicDescription": "Counts the number of Machine Clears detected= dye to memory ordering. Memory Ordering Machine Clears may apply when a me= mory read may not conform to the memory ordering rules of the x86 architect= ure", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 128 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", @@ -29,6 +32,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 16 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", @@ -41,6 +45,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 256 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", @@ -53,6 +58,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 32 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", @@ -65,6 +71,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 4 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4", @@ -77,6 +84,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 512 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", @@ -89,6 +97,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 64 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", @@ -101,6 +110,7 @@ }, { "BriefDescription": "Counts randomly selected loads when the laten= cy from first dispatch to completion is greater than 8 cycles.", + "Counter": "0,1,2,3,4,5,6,7", "Data_LA": "1", "EventCode": "0xcd", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", @@ -113,6 +123,7 @@ }, { "BriefDescription": "Demand Data Read requests who miss L3 cache", + "Counter": "0,1,2,3", "EventCode": "0xb0", "EventName": "OFFCORE_REQUESTS.L3_MISS_DEMAND_DATA_RD", "PublicDescription": "Demand Data Read requests who miss L3 cache.= ", @@ -121,14 +132,17 @@ }, { "BriefDescription": "Number of times an RTM execution aborted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED", + "PEBS": "1", "PublicDescription": "Counts the number of times RTM abort was tri= ggered.", "SampleAfterValue": "100003", "UMask": "0x4" }, { "BriefDescription": "Number of times an RTM execution aborted due = to none of the previous 4 categories (e.g. interrupt)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_EVENTS", "PublicDescription": "Counts the number of times an RTM execution = aborted due to none of the previous 4 categories (e.g. interrupt).", @@ -137,6 +151,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to various memory events (e.g. read/write capacity and conflicts)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEM", "PublicDescription": "Counts the number of times an RTM execution = aborted due to various memory events (e.g. read/write capacity and conflict= s).", @@ -145,6 +160,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to incompatible memory type", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_MEMTYPE", "PublicDescription": "Counts the number of times an RTM execution = aborted due to incompatible memory type.", @@ -153,6 +169,7 @@ }, { "BriefDescription": "Number of times an RTM execution aborted due = to HLE-unfriendly instructions", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.ABORTED_UNFRIENDLY", "PublicDescription": "Counts the number of times an RTM execution = aborted due to HLE-unfriendly instructions.", @@ -161,6 +178,7 @@ }, { "BriefDescription": "Number of times an RTM execution successfully= committed", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.COMMIT", "PublicDescription": "Counts the number of times RTM commit succee= ded.", @@ -169,6 +187,7 @@ }, { "BriefDescription": "Number of times an RTM execution started.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc9", "EventName": "RTM_RETIRED.START", "PublicDescription": "Counts the number of times we entered an RTM= region. Does not count nested transactions.", @@ -177,6 +196,7 @@ }, { "BriefDescription": "Counts the number of times a class of instruc= tions that may cause a transactional abort was executed inside a transactio= nal region", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC2", "PublicDescription": "Counts Unfriendly TSX abort triggered by a v= zeroupper instruction.", @@ -185,6 +205,7 @@ }, { "BriefDescription": "Number of times an instruction execution caus= ed the transactional nest count supported to be exceeded", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5d", "EventName": "TX_EXEC.MISC3", "PublicDescription": "Counts Unfriendly TSX abort triggered by a n= est count that is too deep.", @@ -193,6 +214,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional reads", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_READ", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional reads", @@ -201,6 +223,7 @@ }, { "BriefDescription": "Speculatively counts the number of TSX aborts= due to a data capacity limitation for transactional writes.", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "PublicDescription": "Speculatively counts the number of Transacti= onal Synchronization Extensions (TSX) aborts due to a data capacity limitat= ion for transactional writes.", @@ -209,6 +232,7 @@ }, { "BriefDescription": "Number of times a transactional abort was sig= naled due to a data conflict on a transactionally accessed address", + "Counter": "0,1,2,3", "EventCode": "0x54", "EventName": "TX_MEM.ABORT_CONFLICT", "PublicDescription": "Counts the number of times a TSX line had a = cache conflict.", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/metricgroups.json b/t= ools/perf/pmu-events/arch/x86/tigerlake/metricgroups.json index 5452a1448ded..3a88260194d1 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/metricgroups.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/metricgroups.json @@ -5,7 +5,20 @@ "BigFootprint": "Grouping from Top-down Microarchitecture Analysis Met= rics spreadsheet", "BrMispredicts": "Grouping from Top-down Microarchitecture Analysis Me= trics spreadsheet", "Branches": "Grouping from Top-down Microarchitecture Analysis Metrics= spreadsheet", + "BvBC": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvBO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvCB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvFB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvIO": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvML": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMP": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMS": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvMT": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvOB": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", + "BvUW": "Grouping from Top-down Microarchitecture Analysis Metrics spr= eadsheet", "CacheHits": "Grouping from Top-down Microarchitecture Analysis Metric= s spreadsheet", + "CacheMisses": "Grouping from Top-down Microarchitecture Analysis Metr= ics spreadsheet", "CodeGen": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Compute": "Grouping from Top-down Microarchitecture Analysis Metrics = spreadsheet", "Cor": "Grouping from Top-down Microarchitecture Analysis Metrics spre= adsheet", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/other.json b/tools/pe= rf/pmu-events/arch/x86/tigerlake/other.json index 117b18abcaaf..a22b626c14c9 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for baseline license level 0. This includes non-AVX = codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was runnin= g with power-delivery for license level 1. This includes high current AVX = 256-bit instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a m= anner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with = power-delivery for license level 2 (introduced in Skylake Server microarchi= tecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of= response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json b/tools= /perf/pmu-events/arch/x86/tigerlake/pipeline.json index 4f85d53edec2..09b53b0722a9 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles when divide unit is busy executing div= ide or square root operations.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x14", "EventName": "ARITH.DIVIDER_ACTIVE", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Number of occurrences where a microcode assis= t is invoked by hardware.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc1", "EventName": "ASSISTS.ANY", "PublicDescription": "Counts the number of occurrences where a mic= rocode assist is invoked by hardware Examples include AD (page Access Dirty= ), FP and AVX related assists.", @@ -18,6 +20,7 @@ }, { "BriefDescription": "All branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Conditional branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND", "PEBS": "1", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Not taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Taken conditional branch instructions retired= .", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.COND_TAKEN", "PEBS": "1", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Far branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.FAR_BRANCH", "PEBS": "1", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Indirect near branch instructions retired (ex= cluding returns)", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.INDIRECT", "PEBS": "1", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Direct and indirect near call instructions re= tired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Return instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_RETURN", "PEBS": "1", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Taken branch instructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc4", "EventName": "BR_INST_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -98,6 +109,7 @@ }, { "BriefDescription": "All mispredicted branch instructions retired.= ", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Mispredicted conditional branch instructions = retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND", "PEBS": "1", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Mispredicted non-taken conditional branch ins= tructions retired.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_NTAKEN", "PEBS": "1", @@ -124,6 +138,7 @@ }, { "BriefDescription": "number of branch instructions retired that we= re mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.COND_TAKEN", "PEBS": "1", @@ -133,6 +148,7 @@ }, { "BriefDescription": "All miss-predicted indirect branch instructio= ns retired (excluding RETs. TSX aborts is considered indirect branch).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT", "PEBS": "1", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Mispredicted indirect CALL instructions retir= ed.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.INDIRECT_CALL", "PEBS": "1", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Number of near branch instructions retired th= at were mispredicted and taken.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.NEAR_TAKEN", "PEBS": "1", @@ -160,6 +178,7 @@ }, { "BriefDescription": "This event counts the number of mispredicted = ret instructions retired. Non PEBS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc5", "EventName": "BR_MISP_RETIRED.RET", "PEBS": "1", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Cycle counts are evenly distributed between a= ctive threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xec", "EventName": "CPU_CLK_UNHALTED.DISTRIBUTED", "PublicDescription": "This event distributes cycle counts between = active hyperthreads, i.e., those in C0. A hyperthread becomes inactive whe= n it executes the HLT or MWAIT instructions. If all other hyperthreads are= inactive (or disabled or do not exist), all counts are attributed to this = hyperthread. To obtain the full count when the Core is active, sum the coun= ts from each hyperthread.", @@ -177,6 +197,7 @@ }, { "BriefDescription": "Core crystal clock cycles when this thread is= unhalted and the other thread is halted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE", "PublicDescription": "Counts Core crystal clock cycles when curren= t thread is unhalted and the other thread is halted.", @@ -185,6 +206,7 @@ }, { "BriefDescription": "Core crystal clock cycles. Cycle counts are e= venly distributed between active threads in the Core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_DISTRIBUTED", "PublicDescription": "This event distributes Core crystal clock cy= cle counts between active hyperthreads, i.e., those in C0 sleep-state. A hy= perthread becomes inactive when it executes the HLT or MWAIT instructions. = If one thread is active in a core, all counts are attributed to this hypert= hread. To obtain the full count when the Core is active, sum the counts fro= m each hyperthread.", @@ -193,6 +215,7 @@ }, { "BriefDescription": "Reference cycles when the core is not in halt= state.", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.REF_TSC", "PublicDescription": "Counts the number of reference cycles when t= he core is not in a halt state. The core enters the halt state when it is r= unning the HLT instruction or the MWAIT instruction. This event is not affe= cted by core frequency changes (for example, P states, TM2 transitions) but= has the same incrementing frequency as the time stamp counter. This event = can approximate elapsed time while the core was not in a halt state. This e= vent has a constant ratio with the CPU_CLK_UNHALTED.REF_XCLK event. It is c= ounted on a dedicated fixed counter, leaving the eight programmable counter= s available for other events. Note: On all current platforms this event sto= ps counting during 'throttling (TM)' states duty off periods the processor = is 'halted'. The counter update is done at a lower clock rate then the cor= e clock the overflow status bit for this counter may appear 'sticky'. Afte= r the counter has overflowed and software clears the overflow status bit an= d resets the counter to less than MAX. The reset value to the counter is no= t clocked immediately so the overflow status bit will flip 'high (1)' and g= enerate another PMI (if enabled) after which the reset value gets clocked i= nto the counter. Therefore, software will get the interrupt, read the overf= low status bit '1 for bit 34 while the counter value is less than MAX. Soft= ware should ignore this case.", "SampleAfterValue": "2000003", @@ -200,6 +223,7 @@ }, { "BriefDescription": "Core crystal clock cycles when the thread is = unhalted.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.REF_XCLK", "PublicDescription": "Counts core crystal clock cycles when the th= read is unhalted.", @@ -208,6 +232,7 @@ }, { "BriefDescription": "Core cycles when the thread is not in halt st= ate", + "Counter": "Fixed counter 1", "EventName": "CPU_CLK_UNHALTED.THREAD", "PublicDescription": "Counts the number of core cycles while the t= hread is not in a halt state. The thread enters the halt state when it is r= unning the HLT instruction. This event is a component in many key event rat= ios. The core frequency may change from time to time due to transitions ass= ociated with Enhanced Intel SpeedStep Technology or TM2. For this reason th= is event may have a changing ratio with regards to time. When the core freq= uency is constant, this event can approximate elapsed time while the core w= as not in the halt state. It is counted on a dedicated fixed counter, leavi= ng the eight programmable counters available for other events.", "SampleAfterValue": "2000003", @@ -215,6 +240,7 @@ }, { "BriefDescription": "Thread cycles when thread is not in halt stat= e", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x3c", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "PublicDescription": "This is an architectural event that counts t= he number of thread cycles while the thread is not in a halt state. The thr= ead enters the halt state when it is running the HLT instruction. The core = frequency may change from time to time due to power or thermal throttling. = For this reason, this event may have a changing ratio with regards to wall = clock time.", @@ -222,6 +248,7 @@ }, { "BriefDescription": "Cycles while L1 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "8", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L1D_MISS", @@ -230,6 +257,7 @@ }, { "BriefDescription": "Cycles while L2 cache miss demand load is out= standing.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_L2_MISS", @@ -238,6 +266,7 @@ }, { "BriefDescription": "Cycles while memory subsystem has an outstand= ing load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "16", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.CYCLES_MEM_ANY", @@ -246,6 +275,7 @@ }, { "BriefDescription": "Execution stalls while L1 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "12", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L1D_MISS", @@ -254,6 +284,7 @@ }, { "BriefDescription": "Execution stalls while L2 cache miss demand l= oad is outstanding.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_L2_MISS", @@ -262,6 +293,7 @@ }, { "BriefDescription": "Execution stalls while memory subsystem has a= n outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "20", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_MEM_ANY", @@ -270,6 +302,7 @@ }, { "BriefDescription": "Total execution stalls.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xa3", "EventName": "CYCLE_ACTIVITY.STALLS_TOTAL", @@ -278,6 +311,7 @@ }, { "BriefDescription": "Cycles total of 1 uop is executed on all port= s and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.1_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 1 uop = was executed on all ports and Reservation Station (RS) was not empty.", @@ -286,6 +320,7 @@ }, { "BriefDescription": "Cycles total of 2 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.2_PORTS_UTIL", "PublicDescription": "Counts cycles during which a total of 2 uops= were executed on all ports and Reservation Station (RS) was not empty.", @@ -294,6 +329,7 @@ }, { "BriefDescription": "Cycles total of 3 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.3_PORTS_UTIL", "PublicDescription": "Cycles total of 3 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -302,6 +338,7 @@ }, { "BriefDescription": "Cycles total of 4 uops are executed on all po= rts and Reservation Station was not empty.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.4_PORTS_UTIL", "PublicDescription": "Cycles total of 4 uops are executed on all p= orts and Reservation Station (RS) was not empty.", @@ -310,6 +347,7 @@ }, { "BriefDescription": "Cycles when the memory subsystem has an outst= anding load. Increments by 4 for every such cycle.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "5", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_LOADS", @@ -319,6 +357,7 @@ }, { "BriefDescription": "Cycles where the Store Buffer was full and no= loads caused an execution stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.BOUND_ON_STORES", @@ -328,6 +367,7 @@ }, { "BriefDescription": "Cycles no uop executed while RS was not empty= , the SB was not full and there was no outstanding load.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa6", "EventName": "EXE_ACTIVITY.EXE_BOUND_0_PORTS", "PublicDescription": "Number of cycles total of 0 uops executed on= all ports, Reservation Station (RS) was not empty, the Store Buffer (SB) w= as not full and there was no outstanding load.", @@ -336,6 +376,7 @@ }, { "BriefDescription": "Stalls caused by changing prefix length of th= e instruction. [This event is alias to DECODE.LCP]", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "PublicDescription": "Counts cycles that the Instruction Length de= coder (ILD) stalls occurred due to dynamically changing prefix length of th= e decoded instruction (by operand size prefix instruction 0x66, address siz= e prefix instruction 0x67 or REX.W for Intel64). Count is proportional to t= he number of prefixes in a 16B-line. This may result in a three-cycle penal= ty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is= alias to DECODE.LCP]", @@ -344,6 +385,7 @@ }, { "BriefDescription": "Instruction decoders utilized in a cycle", + "Counter": "0,1,2,3", "EventCode": "0x55", "EventName": "INST_DECODED.DECODERS", "PublicDescription": "Number of decoders utilized in a cycle when = the MITE (legacy decode pipeline) fetches instructions.", @@ -352,6 +394,7 @@ }, { "BriefDescription": "Number of instructions retired. Fixed Counter= - architectural event", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.ANY", "PEBS": "1", "PublicDescription": "Counts the number of X86 instructions retire= d - an Architectural PerfMon event. Counting continues during hardware inte= rrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is co= unted by a designated fixed counter freeing up programmable counters to cou= nt other events. INST_RETIRED.ANY_P is counted by a programmable counter.", @@ -360,6 +403,7 @@ }, { "BriefDescription": "Number of instructions retired. General Count= er - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -368,6 +412,7 @@ }, { "BriefDescription": "Retired NOP instructions.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc0", "EventName": "INST_RETIRED.NOP", "PEBS": "1", @@ -377,6 +422,7 @@ }, { "BriefDescription": "Precise instruction retired event with a redu= ced effect of PEBS shadow in IP distribution", + "Counter": "Fixed counter 0", "EventName": "INST_RETIRED.PREC_DIST", "PEBS": "1", "PublicDescription": "A version of INST_RETIRED that allows for a = more unbiased distribution of samples across instructions retired. It utili= zes the Precise Distribution of Instructions Retired (PDIR) feature to miti= gate some bias in how retired instructions get sampled. Use on Fixed Counte= r 0.", @@ -385,6 +431,7 @@ }, { "BriefDescription": "Cycles the Backend cluster is recovering afte= r a miss-speculation or a Store Buffer or Load Buffer drain stall.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0d", "EventName": "INT_MISC.ALL_RECOVERY_CYCLES", @@ -394,6 +441,7 @@ }, { "BriefDescription": "Clears speculative count", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x0d", @@ -404,6 +452,7 @@ }, { "BriefDescription": "Counts cycles after recovery from a branch mi= sprediction or machine clear till the first uop is issued from the resteere= d path.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.CLEAR_RESTEER_CYCLES", "PublicDescription": "Cycles after recovery from a branch mispredi= ction or machine clear till the first uop is issued from the resteered path= .", @@ -412,6 +461,7 @@ }, { "BriefDescription": "Core cycles the allocator was stalled due to = recovery from earlier clear event for this thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.RECOVERY_CYCLES", "PublicDescription": "Counts core cycles when the Resource allocat= or was stalled due to recovery from an earlier branch misprediction or mach= ine clear event.", @@ -420,6 +470,7 @@ }, { "BriefDescription": "TMA slots where uops got dropped", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0d", "EventName": "INT_MISC.UOP_DROPPING", "PublicDescription": "Estimated number of Top-down Microarchitectu= re Analysis slots that got dropped due to non front-end reasons", @@ -428,6 +479,7 @@ }, { "BriefDescription": "The number of times that split load operation= s are temporarily blocked because all resources for handling the split acce= sses are in use.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.NO_SR", "PublicDescription": "Counts the number of times that split load o= perations are temporarily blocked because all resources for handling the sp= lit accesses are in use.", @@ -436,6 +488,7 @@ }, { "BriefDescription": "Loads blocked due to overlapping with a prece= ding store that cannot be forwarded.", + "Counter": "0,1,2,3", "EventCode": "0x03", "EventName": "LD_BLOCKS.STORE_FORWARD", "PublicDescription": "Counts the number of times where store forwa= rding was prevented for a load operation. The most common case is a load bl= ocked due to the address of memory access (partially) overlapping with a pr= eceding uncompleted store. Note: See the table of not supported store forwa= rds in the Optimization Guide.", @@ -444,6 +497,7 @@ }, { "BriefDescription": "False dependencies in MOB due to partial comp= are on address.", + "Counter": "0,1,2,3", "EventCode": "0x07", "EventName": "LD_BLOCKS_PARTIAL.ADDRESS_ALIAS", "PublicDescription": "Counts the number of times a load got blocke= d due to false dependencies in MOB due to partial compare on address.", @@ -452,6 +506,7 @@ }, { "BriefDescription": "Counts the number of demand load dispatches t= hat hit L1D fill buffer (FB) allocated for software prefetch.", + "Counter": "0,1,2,3", "EventCode": "0x4c", "EventName": "LOAD_HIT_PREFETCH.SWPF", "PublicDescription": "Counts all not software-prefetch load dispat= ches that hit the fill buffer (FB) allocated for the software prefetch. It = can also be incremented by some lock instructions. So it should only be use= d with profiling so that the locks can be excluded by ASM (Assembly File) i= nspection of the nearby instructions.", @@ -460,6 +515,7 @@ }, { "BriefDescription": "Cycles Uops delivered by the LSD, but didn't = come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xa8", "EventName": "LSD.CYCLES_ACTIVE", @@ -469,6 +525,7 @@ }, { "BriefDescription": "Cycles optimal number of Uops delivered by th= e LSD, but did not come from the decoder.", + "Counter": "0,1,2,3", "CounterMask": "5", "EventCode": "0xa8", "EventName": "LSD.CYCLES_OK", @@ -478,6 +535,7 @@ }, { "BriefDescription": "Number of Uops delivered by the LSD.", + "Counter": "0,1,2,3", "EventCode": "0xa8", "EventName": "LSD.UOPS", "PublicDescription": "Counts the number of uops delivered to the b= ack-end by the LSD(Loop Stream Detector).", @@ -486,6 +544,7 @@ }, { "BriefDescription": "Number of machine clears (nukes) of any type.= ", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xc3", @@ -496,6 +555,7 @@ }, { "BriefDescription": "Self-modifying code (SMC) detected.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc3", "EventName": "MACHINE_CLEARS.SMC", "PublicDescription": "Counts self-modifying code (SMC) detected, w= hich causes a machine clear.", @@ -504,6 +564,7 @@ }, { "BriefDescription": "Increments whenever there is an update to the= LBR array.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.LBR_INSERTS", "PublicDescription": "Increments when an entry is added to the Las= t Branch Record (LBR) array (or removed from the array in case of RETURNs i= n call stack mode). The event requires LBR enable via IA32_DEBUGCTL MSR and= branch type selection via MSR_LBR_SELECT.", @@ -512,6 +573,7 @@ }, { "BriefDescription": "Number of retired PAUSE instructions. This ev= ent is not supported on first SKL and KBL products.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xcc", "EventName": "MISC_RETIRED.PAUSE_INST", "PublicDescription": "Counts number of retired PAUSE instructions.= This event is not supported on first SKL and KBL products.", @@ -520,6 +582,7 @@ }, { "BriefDescription": "Cycles stalled due to no store buffers availa= ble. (not including draining form sync).", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SB", "PublicDescription": "Counts allocation stall cycles caused by the= store buffer (SB) being full. This counts cycles that the pipeline back-en= d blocked uop delivery from the front-end.", @@ -528,6 +591,7 @@ }, { "BriefDescription": "Counts cycles where the pipeline is stalled d= ue to serializing operations.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa2", "EventName": "RESOURCE_STALLS.SCOREBOARD", "SampleAfterValue": "100003", @@ -535,6 +599,7 @@ }, { "BriefDescription": "Cycles when Reservation Station (RS) is empty= for the thread", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x5e", "EventName": "RS_EVENTS.EMPTY_CYCLES", "PublicDescription": "Counts cycles during which the reservation s= tation (RS) is empty for this logical processor. This is usually caused whe= n the front-end pipeline runs into starvation periods (e.g. branch mispredi= ctions or i-cache misses)", @@ -543,6 +608,7 @@ }, { "BriefDescription": "Counts end of periods where the Reservation S= tation (RS) was empty.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5e", @@ -554,6 +620,7 @@ }, { "BriefDescription": "TMA slots where no uops were being issued due= to lack of back-end resources.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS", "PublicDescription": "Counts the number of Top-down Microarchitect= ure Analysis (TMA) method's slots where no micro-operations were being iss= ued from front-end to back-end of the machine due to lack of back-end resou= rces.", @@ -562,6 +629,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. Fixed counter - architectural event", + "Counter": "Fixed counter 3", "EventName": "TOPDOWN.SLOTS", "PublicDescription": "Number of available slots for an unhalted lo= gical processor. The event increments by machine-width of the narrowest pip= eline as employed by the Top-down Microarchitecture Analysis method (TMA). = The count is distributed among unhalted logical processors (hyper-threads) = who share the same physical core. Software can use this event as the denomi= nator for the top-level metrics of the TMA method. This architectural event= is counted on a designated fixed counter (Fixed Counter 3).", "SampleAfterValue": "10000003", @@ -569,6 +637,7 @@ }, { "BriefDescription": "TMA slots available for an unhalted logical p= rocessor. General counter - architectural event", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa4", "EventName": "TOPDOWN.SLOTS_P", "PublicDescription": "Counts the number of available slots for an = unhalted logical processor. The event increments by machine-width of the na= rrowest pipeline as employed by the Top-down Microarchitecture Analysis met= hod. The count is distributed among unhalted logical processors (hyper-thre= ads) who share the same physical core.", @@ -577,6 +646,7 @@ }, { "BriefDescription": "Number of uops decoded out of instructions ex= clusively fetched by decoder 0", + "Counter": "0,1,2,3", "EventCode": "0x56", "EventName": "UOPS_DECODED.DEC0", "PublicDescription": "Uops exclusively fetched by decoder 0", @@ -585,6 +655,7 @@ }, { "BriefDescription": "Number of uops executed on port 0", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_0", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 0.", @@ -593,6 +664,7 @@ }, { "BriefDescription": "Number of uops executed on port 1", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_1", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 1.", @@ -601,6 +673,7 @@ }, { "BriefDescription": "Number of uops executed on port 2 and 3", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_2_3", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 2 and 3.", @@ -609,6 +682,7 @@ }, { "BriefDescription": "Number of uops executed on port 4 and 9", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_4_9", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 5 and 9.", @@ -617,6 +691,7 @@ }, { "BriefDescription": "Number of uops executed on port 5", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_5", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 5.", @@ -625,6 +700,7 @@ }, { "BriefDescription": "Number of uops executed on port 6", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_6", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o port 6.", @@ -633,6 +709,7 @@ }, { "BriefDescription": "Number of uops executed on port 7 and 8", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xa1", "EventName": "UOPS_DISPATCHED.PORT_7_8", "PublicDescription": "Counts, on the per-thread basis, cycles duri= ng which at least one uop is dispatched from the Reservation Station (RS) t= o ports 7 and 8.", @@ -641,6 +718,7 @@ }, { "BriefDescription": "Number of uops executed on the core.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE", "PublicDescription": "Counts the number of uops executed from any = thread.", @@ -649,6 +727,7 @@ }, { "BriefDescription": "Cycles at least 1 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_1", @@ -658,6 +737,7 @@ }, { "BriefDescription": "Cycles at least 2 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_2", @@ -667,6 +747,7 @@ }, { "BriefDescription": "Cycles at least 3 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_3", @@ -676,6 +757,7 @@ }, { "BriefDescription": "Cycles at least 4 micro-op is executed from a= ny thread on physical core.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CORE_CYCLES_GE_4", @@ -685,6 +767,7 @@ }, { "BriefDescription": "Cycles where at least 1 uop was executed per-= thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_1", @@ -694,6 +777,7 @@ }, { "BriefDescription": "Cycles where at least 2 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "2", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_2", @@ -703,6 +787,7 @@ }, { "BriefDescription": "Cycles where at least 3 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "3", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_3", @@ -712,6 +797,7 @@ }, { "BriefDescription": "Cycles where at least 4 uops were executed pe= r-thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "4", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.CYCLES_GE_4", @@ -721,6 +807,7 @@ }, { "BriefDescription": "Counts number of cycles no uops were dispatch= ed to be executed on this thread.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.STALL_CYCLES", @@ -731,6 +818,7 @@ }, { "BriefDescription": "Counts the number of uops to be executed per-= thread each cycle.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.THREAD", "SampleAfterValue": "2000003", @@ -738,6 +826,7 @@ }, { "BriefDescription": "Counts the number of x87 uops dispatched.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xb1", "EventName": "UOPS_EXECUTED.X87", "PublicDescription": "Counts the number of x87 uops executed.", @@ -746,6 +835,7 @@ }, { "BriefDescription": "Uops that RAT issues to RS", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.ANY", "PublicDescription": "Counts the number of uops that the Resource = Allocation Table (RAT) issues to the Reservation Station (RS).", @@ -754,6 +844,7 @@ }, { "BriefDescription": "Cycles when RAT does not issue Uops to RS for= the thread", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -764,6 +855,7 @@ }, { "BriefDescription": "Uops inserted at issue-stage in order to pres= erve upper bits of vector registers.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0x0e", "EventName": "UOPS_ISSUED.VECTOR_WIDTH_MISMATCH", "PublicDescription": "Counts the number of Blend Uops issued by th= e Resource Allocation Table (RAT) to the reservation station (RS) in order = to preserve upper bits of vector registers. Starting with the Skylake micro= architecture, these Blend uops are needed since every Intel SSE instruction= executed in Dirty Upper State needs to preserve bits 128-255 of the destin= ation register. For more information, refer to Mixing Intel AVX and Intel S= SE Code section of the Optimization Guide.", @@ -772,6 +864,7 @@ }, { "BriefDescription": "Retirement slots used.", + "Counter": "0,1,2,3,4,5,6,7", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.SLOTS", "PublicDescription": "Counts the retirement slots used each cycle.= ", @@ -780,6 +873,7 @@ }, { "BriefDescription": "Cycles without actually retired uops.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "1", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -790,6 +884,7 @@ }, { "BriefDescription": "Cycles with less than 10 actually retired uop= s.", + "Counter": "0,1,2,3,4,5,6,7", "CounterMask": "10", "EventCode": "0xc2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json b/to= ols/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json index 8ae4f2474b25..c45c6b4a380d 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/tgl-metrics.json @@ -104,7 +104,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU retired uops delivered by the Microcode_Sequencer as a result of Assists= ", "MetricExpr": "34 * ASSISTS.ANY / tma_info_thread_slots", - "MetricGroup": "TopdownL4;tma_L4_group;tma_microcode_sequencer_gro= up", + "MetricGroup": "BvIO;TopdownL4;tma_L4_group;tma_microcode_sequence= r_group", "MetricName": "tma_assists", "MetricThreshold": "tma_assists > 0.1 & (tma_microcode_sequencer >= 0.05 & tma_heavy_operations > 0.1)", "PublicDescription": "This metric estimates fraction of slots the = CPU retired uops delivered by the Microcode_Sequencer as a result of Assist= s. Assists are long sequences of uops that are required in certain corner-c= ases for operations that cannot be handled natively by the execution pipeli= ne. For example; when working with very small floating point values (so-cal= led Denormals); the FP units are not set up to perform these operations nat= ively. Instead; a sequence of instructions to perform the computation on th= e Denormals is injected into the pipeline. Since these microcode sequences = might be dozens of uops long; Assists can be extremely deleterious to perfo= rmance and they can be avoided in many cases. Sample with: ASSISTS.ANY", @@ -114,7 +114,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere no uops are being delivered due to a lack of required resources for acc= epting new uops in the Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-be\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 5 * INT_MIS= C.CLEARS_COUNT / tma_info_thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvOB;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_backend_bound", "MetricThreshold": "tma_backend_bound > 0.2", "MetricgroupNoGroup": "TopdownL1;Default", @@ -135,7 +135,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring branch instructions.", "MetricExpr": "tma_light_operations * BR_INST_RETIRED.ALL_BRANCHES= / (tma_retiring * tma_info_thread_slots)", - "MetricGroup": "Branches;Pipeline;TopdownL3;tma_L3_group;tma_light= _operations_group", + "MetricGroup": "Branches;BvBO;Pipeline;TopdownL3;tma_L3_group;tma_= light_operations_group", "MetricName": "tma_branch_instructions", "MetricThreshold": "tma_branch_instructions > 0.1 & tma_light_oper= ations > 0.6", "ScaleUnit": "100%" @@ -143,7 +143,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Branch Misprediction", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * tma_bad_speculation", - "MetricGroup": "BadSpec;BrMispredicts;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueBM", "MetricName": "tma_branch_mispredicts", "MetricThreshold": "tma_branch_mispredicts > 0.1 & tma_bad_specula= tion > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -181,7 +181,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to contested acces= ses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "(49 * tma_info_system_core_frequency * (MEM_LOAD_L3= _HIT_RETIRED.XSNP_FWD * (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND= _DATA_RD.L3_HIT.SNOOP_HITM + OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))= ) + 48 * tma_info_system_core_frequency * MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS= ) * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info= _thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_l3_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_l3_bound_group", "MetricName": "tma_contested_accesses", "MetricThreshold": "tma_contested_accesses > 0.05 & (tma_l3_bound = > 0.05 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to contested acce= sses. Contested accesses occur when data written by one Logical Processor a= re read by another Logical Processor on a different Physical Core. Examples= of contested accesses include synchronizations such as locks; true data sh= aring such as modified locked variables; and false sharing. Sample with: ME= M_LOAD_L3_HIT_RETIRED.XSNP_FWD;MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS. Related m= etrics: tma_data_sharing, tma_false_sharing, tma_machine_clears, tma_remote= _cache", @@ -201,7 +201,7 @@ "BriefDescription": "This metric estimates fraction of cycles whil= e the memory subsystem was handling synchronizations due to data-sharing ac= cesses", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "48 * tma_info_system_core_frequency * (MEM_LOAD_L3_= HIT_RETIRED.XSNP_NO_FWD + MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD * (1 - OCR.DEMAN= D_DATA_RD.L3_HIT.SNOOP_HITM / (OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM + OCR.D= EMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD))) * (1 + MEM_LOAD_RETIRED.FB_HIT /= MEM_LOAD_RETIRED.L1_MISS / 2) / tma_info_thread_clks", - "MetricGroup": "Offcore;Snoop;TopdownL4;tma_L4_group;tma_issueSync= xn;tma_l3_bound_group", + "MetricGroup": "BvMS;Offcore;Snoop;TopdownL4;tma_L4_group;tma_issu= eSyncxn;tma_l3_bound_group", "MetricName": "tma_data_sharing", "MetricThreshold": "tma_data_sharing > 0.05 & (tma_l3_bound > 0.05= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whi= le the memory subsystem was handling synchronizations due to data-sharing a= ccesses. Data shared by multiple Logical Processors (even just read shared)= may cause increased access latency due to cache coherency. Excessive data = sharing can drastically harm multithreaded performance. Sample with: MEM_LO= AD_L3_HIT_RETIRED.XSNP_NO_FWD. Related metrics: tma_contested_accesses, tma= _false_sharing, tma_machine_clears, tma_remote_cache", @@ -219,7 +219,7 @@ { "BriefDescription": "This metric represents fraction of cycles whe= re the Divider unit was active", "MetricExpr": "ARITH.DIVIDER_ACTIVE / tma_info_thread_clks", - "MetricGroup": "TopdownL3;tma_L3_group;tma_core_bound_group", + "MetricGroup": "BvCB;TopdownL3;tma_L3_group;tma_core_bound_group", "MetricName": "tma_divider", "MetricThreshold": "tma_divider > 0.2 & (tma_core_bound > 0.1 & tm= a_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles wh= ere the Divider unit was active. Divide and square root instructions are pe= rformed by the Divider unit and can take considerably longer latency than i= nteger or Floating Point addition; subtraction; or multiplication. Sample w= ith: ARITH.DIVIDER_ACTIVE", @@ -250,13 +250,13 @@ "MetricGroup": "DSBmiss;FetchLat;TopdownL3;tma_L3_group;tma_fetch_= latency_group;tma_issueFB", "MetricName": "tma_dsb_switches", "MetricThreshold": "tma_dsb_switches > 0.05 & (tma_fetch_latency >= 0.1 & tma_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_mis= ses, tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to switches from DSB to MITE pipelines. The DSB (deco= ded i-cache) is a Uop Cache where the front-end directly delivers Uops (mic= ro operations) avoiding heavy x86 decoding. The DSB pipeline has shorter la= tency and delivered higher bandwidth than the MITE (legacy instruction deco= de pipeline). Switching between the two pipelines can cause penalties hence= this metric measures the exposed penalty. Sample with: FRONTEND_RETIRED.DS= B_MISS_PS. Related metrics: tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_ban= dwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { "BriefDescription": "This metric roughly estimates the fraction of= cycles where the Data TLB (DTLB) was missed by load accesses", "MetricExpr": "min(7 * cpu@DTLB_LOAD_MISSES.STLB_HIT\\,cmask\\=3D1= @ + DTLB_LOAD_MISSES.WALK_ACTIVE, max(CYCLE_ACTIVITY.CYCLES_MEM_ANY - CYCLE= _ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= l1_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_l1_bound_group", "MetricName": "tma_dtlb_load", "MetricThreshold": "tma_dtlb_load > 0.1 & (tma_l1_bound > 0.1 & (t= ma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles where the Data TLB (DTLB) was missed by load accesses. TLBs (Trans= lation Look-aside Buffers) are processor caches for recently used entries o= ut of the Page Tables that are used to map virtual- to physical-addresses b= y the operating system. This metric approximates the potential delay of dem= and loads missing the first-level data TLB (assuming worst case scenario wi= th back to back misses to different pages). This includes hitting in the se= cond-level TLB (STLB) as well as performing a hardware page walk on an STLB= miss. Sample with: MEM_INST_RETIRED.STLB_MISS_LOADS_PS. Related metrics: t= ma_dtlb_store, tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_me= mory_synchronization", @@ -265,7 +265,7 @@ { "BriefDescription": "This metric roughly estimates the fraction of= cycles spent handling first-level data TLB store misses", "MetricExpr": "(7 * cpu@DTLB_STORE_MISSES.STLB_HIT\\,cmask\\=3D1@ = + DTLB_STORE_MISSES.WALK_ACTIVE) / tma_info_core_core_clks", - "MetricGroup": "MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB;tma_= store_bound_group", + "MetricGroup": "BvMT;MemoryTLB;TopdownL4;tma_L4_group;tma_issueTLB= ;tma_store_bound_group", "MetricName": "tma_dtlb_store", "MetricThreshold": "tma_dtlb_store > 0.05 & (tma_store_bound > 0.2= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates the fraction o= f cycles spent handling first-level data TLB store misses. As with ordinar= y data caching; focus on improving data locality and reducing working-set s= ize to reduce DTLB overhead. Additionally; consider using profile-guided o= ptimization (PGO) to collocate frequently-used data on the same page. Try = using larger page sizes for large amounts of frequently-used data. Sample w= ith: MEM_INST_RETIRED.STLB_MISS_STORES_PS. Related metrics: tma_dtlb_load, = tma_info_bottleneck_memory_data_tlbs, tma_info_bottleneck_memory_synchroniz= ation", @@ -274,7 +274,7 @@ { "BriefDescription": "This metric roughly estimates how often CPU w= as handling synchronizations due to False Sharing", "MetricExpr": "54 * tma_info_system_core_frequency * OCR.DEMAND_RF= O.L3_HIT.SNOOP_HITM / tma_info_thread_clks", - "MetricGroup": "DataSharing;Offcore;Snoop;TopdownL4;tma_L4_group;t= ma_issueSyncxn;tma_store_bound_group", + "MetricGroup": "BvMS;DataSharing;Offcore;Snoop;TopdownL4;tma_L4_gr= oup;tma_issueSyncxn;tma_store_bound_group", "MetricName": "tma_false_sharing", "MetricThreshold": "tma_false_sharing > 0.05 & (tma_store_bound > = 0.2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric roughly estimates how often CPU = was handling synchronizations due to False Sharing. False Sharing is a mult= ithreading hiccup; where multiple Logical Processors contend on different d= ata-elements mapped into the same cache line. Sample with: OCR.DEMAND_RFO.L= 3_HIT.SNOOP_HITM. Related metrics: tma_contested_accesses, tma_data_sharing= , tma_machine_clears, tma_remote_cache", @@ -283,7 +283,7 @@ { "BriefDescription": "This metric does a *rough estimation* of how = often L1D Fill Buffer unavailability limited additional L1D miss memory acc= ess requests to proceed", "MetricExpr": "L1D_PEND_MISS.FB_FULL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;tma_is= sueSL;tma_issueSmSt;tma_l1_bound_group", + "MetricGroup": "BvMS;MemoryBW;TopdownL4;tma_L4_group;tma_issueBW;t= ma_issueSL;tma_issueSmSt;tma_l1_bound_group", "MetricName": "tma_fb_full", "MetricThreshold": "tma_fb_full > 0.3", "PublicDescription": "This metric does a *rough estimation* of how= often L1D Fill Buffer unavailability limited additional L1D miss memory ac= cess requests to proceed. The higher the metric value; the deeper the memor= y hierarchy level the misses are satisfied from (metric values >1 are valid= ). Often it hints on approaching bandwidth limits (to L2 cache; L3 cache or= external memory). Related metrics: tma_info_bottleneck_cache_memory_bandwi= dth, tma_info_system_dram_bw_use, tma_mem_bandwidth, tma_sq_full, tma_store= _latency, tma_streaming_stores", @@ -296,7 +296,7 @@ "MetricName": "tma_fetch_bandwidth", "MetricThreshold": "tma_fetch_bandwidth > 0.2", "MetricgroupNoGroup": "TopdownL2", - "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_= info_inst_mix_iptb, tma_lcp", + "PublicDescription": "This metric represents fraction of slots the= CPU was stalled due to Frontend bandwidth issues. For example; inefficien= cies at the instruction decoders; or restrictions for caching in the DSB (d= ecoded uops cache) are categorized under Fetch Bandwidth. In such cases; th= e Frontend typically delivers suboptimal amount of uops to the Backend. Sam= ple with: FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1_PS;FRONTEND_RETIRED.LA= TENCY_GE_1_PS;FRONTEND_RETIRED.LATENCY_GE_2_PS. Related metrics: tma_dsb_sw= itches, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp", "ScaleUnit": "100%" }, { @@ -338,7 +338,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) scalar uops fraction the CPU has retired", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.SCALAR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_scalar", "MetricThreshold": "tma_fp_scalar > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -347,7 +347,7 @@ }, { "BriefDescription": "This metric approximates arithmetic floating-= point (FP) vector uops fraction the CPU has retired aggregated across all v= ector widths", - "MetricExpr": "cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umas= k\\=3D0xfc@ / (tma_retiring * tma_info_thread_slots)", + "MetricExpr": "FP_ARITH_INST_RETIRED.VECTOR / (tma_retiring * tma_= info_thread_slots)", "MetricGroup": "Compute;Flops;TopdownL4;tma_L4_group;tma_fp_arith_= group;tma_issue2P", "MetricName": "tma_fp_vector", "MetricThreshold": "tma_fp_vector > 0.1 & (tma_fp_arith > 0.2 & tm= a_light_operations > 0.6)", @@ -385,7 +385,7 @@ "BriefDescription": "This category represents fraction of slots wh= ere the processor's Frontend undersupplies its Backend", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-fe\\-bound / (topdown\\-fe\\-bound + topd= own\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) - INT_MISC.UO= P_DROPPING / tma_info_thread_slots", - "MetricGroup": "Default;PGO;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvFB;BvIO;Default;PGO;TmaL1;TopdownL1;tma_L1_group= ", "MetricName": "tma_frontend_bound", "MetricThreshold": "tma_frontend_bound > 0.15", "MetricgroupNoGroup": "TopdownL1;Default", @@ -405,7 +405,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to instruction cache misses", "MetricExpr": "ICACHE_DATA.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;IcMiss;TopdownL3;tma_L3_grou= p;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;IcMiss;TopdownL3;tma_L3= _group;tma_fetch_latency_group", "MetricName": "tma_icache_misses", "MetricThreshold": "tma_icache_misses > 0.05 & (tma_fetch_latency = > 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to instruction cache misses. Sample with: FRONTEND_RE= TIRED.L2_MISS_PS;FRONTEND_RETIRED.L1I_MISS_PS", @@ -468,6 +468,14 @@ "MetricName": "tma_info_botlnk_l0_core_bound_likely", "MetricThreshold": "tma_info_botlnk_l0_core_bound_likely > 0.5" }, + { + "BriefDescription": "Total pipeline cost of DSB (uop cache) hits -= subset of the Instruction_Fetch_BW Bottleneck", + "MetricExpr": "100 * (tma_frontend_bound * (tma_fetch_bandwidth / = (tma_fetch_bandwidth + tma_fetch_latency)) * (tma_dsb / (tma_dsb + tma_lsd = + tma_mite)))", + "MetricGroup": "DSB;FetchBW;tma_issueFB", + "MetricName": "tma_info_botlnk_l2_dsb_bandwidth", + "MetricThreshold": "tma_info_botlnk_l2_dsb_bandwidth > 10", + "PublicDescription": "Total pipeline cost of DSB (uop cache) hits = - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb_s= witches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_front= end_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" + }, { "BriefDescription": "Total pipeline cost of DSB (uop cache) misses= - subset of the Instruction_Fetch_BW Bottleneck", "MetricConstraint": "NO_GROUP_EVENTS", @@ -475,7 +483,7 @@ "MetricGroup": "DSBmiss;Fed;tma_issueFB", "MetricName": "tma_info_botlnk_l2_dsb_misses", "MetricThreshold": "tma_info_botlnk_l2_dsb_misses > 10", - "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_frontend_dsb_coverage, tma_info_in= st_mix_iptb, tma_lcp" + "PublicDescription": "Total pipeline cost of DSB (uop cache) misse= s - subset of the Instruction_Fetch_BW Bottleneck. Related metrics: tma_dsb= _switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_= frontend_dsb_coverage, tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Total pipeline cost of Instruction Cache miss= es - subset of the Big_Code Bottleneck", @@ -486,40 +494,34 @@ "MetricThreshold": "tma_info_botlnk_l2_ic_misses > 5", "PublicDescription": "Total pipeline cost of Instruction Cache mis= ses - subset of the Big_Code Bottleneck. Related metrics: " }, - { - "BriefDescription": "Total pipeline cost of \"useful operations\" = - the baseline operations not covered by Branching_Overhead nor Irregular_O= verhead.", - "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + BR_INST_RETIRED.NEAR_CALL) / tma_info_thread_slots - tma_microcode_seque= ncer / (tma_few_uops_instructions + tma_microcode_sequencer) * (tma_assists= / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Ret", - "MetricName": "tma_info_bottleneck_base_non_br", - "MetricThreshold": "tma_info_bottleneck_base_non_br > 20" - }, { "BriefDescription": "Total pipeline cost of instruction fetch rela= ted bottlenecks by large code footprint programs (i-side cache; TLB and BTB= misses)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * tma_fetch_latency * (tma_itlb_misses + tma_ic= ache_misses + tma_unknown_branches) / (tma_branch_resteers + tma_dsb_switch= es + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches)", - "MetricGroup": "BigFootprint;Fed;Frontend;IcMiss;MemoryTLB", + "MetricGroup": "BigFootprint;BvBC;Fed;Frontend;IcMiss;MemoryTLB", "MetricName": "tma_info_bottleneck_big_code", "MetricThreshold": "tma_info_bottleneck_big_code > 20" }, { - "BriefDescription": "Total pipeline cost of branch related instruc= tions (used for program control-flow including function calls)", - "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + BR_INST_RETI= RED.NEAR_CALL) / tma_info_thread_slots)", - "MetricGroup": "Ret", + "BriefDescription": "Total pipeline cost of instructions used for = program control-flow - a subset of the Retiring category in TMA", + "MetricExpr": "100 * ((BR_INST_RETIRED.ALL_BRANCHES + 2 * BR_INST_= RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slots)", + "MetricGroup": "BvBO;Ret", "MetricName": "tma_info_bottleneck_branching_overhead", - "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5" + "MetricThreshold": "tma_info_bottleneck_branching_overhead > 5", + "PublicDescription": "Total pipeline cost of instructions used for= program control-flow - a subset of the Retiring category in TMA. Examples = include function calls; loops and alignments. (A lower bound)" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Bandwidth related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_lock_latency + tma_split_loads + tma_store_fwd_blk)))", - "MetricGroup": "Mem;MemoryBW;Offcore;tma_issueBW", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_bandwidth / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_b= ound * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_= l3_bound + tma_store_bound)) * (tma_sq_full / (tma_contested_accesses + tma= _data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound * (tm= a_l1_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound += tma_store_bound)) * (tma_fb_full / (tma_4k_aliasing + tma_dtlb_load + tma_= fb_full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_sto= re_fwd_blk)))", + "MetricGroup": "BvMB;Mem;MemoryBW;Offcore;tma_issueBW", "MetricName": "tma_info_bottleneck_cache_memory_bandwidth", "MetricThreshold": "tma_info_bottleneck_cache_memory_bandwidth > 2= 0", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Bandwidth related bottlenecks. Related metrics: tma_fb_full, tma_info_= system_dram_bw_use, tma_mem_bandwidth, tma_sq_full" }, { "BriefDescription": "Total pipeline cost of external Memory- or Ca= che-Latency related bottlenecks", - "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryLat;Offcore;tma_issueLat", + "MetricExpr": "100 * (tma_memory_bound * (tma_dram_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) *= (tma_mem_latency / (tma_mem_bandwidth + tma_mem_latency)) + tma_memory_bou= nd * (tma_l3_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3= _bound + tma_store_bound)) * (tma_l3_hit_latency / (tma_contested_accesses = + tma_data_sharing + tma_l3_hit_latency + tma_sq_full)) + tma_memory_bound = * tma_l2_bound / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bou= nd + tma_store_bound) + tma_memory_bound * (tma_store_bound / (tma_dram_bou= nd + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_= store_latency / (tma_dtlb_store + tma_false_sharing + tma_split_stores + tm= a_store_latency + tma_streaming_stores)) + tma_memory_bound * (tma_l1_bound= / (tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store= _bound)) * (tma_l1_hit_latency / (tma_4k_aliasing + tma_dtlb_load + tma_fb_= full + tma_l1_hit_latency + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)))", + "MetricGroup": "BvML;Mem;MemoryLat;Offcore;tma_issueLat", "MetricName": "tma_info_bottleneck_cache_memory_latency", "MetricThreshold": "tma_info_bottleneck_cache_memory_latency > 20", "PublicDescription": "Total pipeline cost of external Memory- or C= ache-Latency related bottlenecks. Related metrics: tma_l3_hit_latency, tma_= mem_latency" @@ -527,23 +529,23 @@ { "BriefDescription": "Total pipeline cost when the execution is com= pute-bound - an estimation", "MetricExpr": "100 * (tma_core_bound * tma_divider / (tma_divider = + tma_ports_utilization + tma_serializing_operation) + tma_core_bound * (tm= a_ports_utilization / (tma_divider + tma_ports_utilization + tma_serializin= g_operation)) * (tma_ports_utilized_3m / (tma_ports_utilized_0 + tma_ports_= utilized_1 + tma_ports_utilized_2 + tma_ports_utilized_3m)))", - "MetricGroup": "Cor;tma_issueComp", + "MetricGroup": "BvCB;Cor;tma_issueComp", "MetricName": "tma_info_bottleneck_compute_bound_est", "MetricThreshold": "tma_info_bottleneck_compute_bound_est > 20", "PublicDescription": "Total pipeline cost when the execution is co= mpute-bound - an estimation. Covers Core Bound when High ILP as well as whe= n long-latency execution units are busy. Related metrics: " }, { - "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks", + "BriefDescription": "Total pipeline cost of instruction fetch band= width related bottlenecks (when the front-end could not sustain operations = delivery to the back-end)", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (tma_frontend_bound - (1 - 10 * tma_microcode= _sequencer * tma_other_mispredicts / tma_branch_mispredicts) * tma_fetch_la= tency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switches = + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches) - tma_mi= crocode_sequencer / (tma_few_uops_instructions + tma_microcode_sequencer) *= (tma_assists / tma_microcode_sequencer) * tma_fetch_latency * (tma_ms_swit= ches + tma_branch_resteers * (tma_clears_resteers + tma_mispredicts_resteer= s * (10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_misp= redicts)) / (tma_clears_resteers + tma_mispredicts_resteers + tma_unknown_b= ranches)) / (tma_branch_resteers + tma_dsb_switches + tma_icache_misses + t= ma_itlb_misses + tma_lcp + tma_ms_switches)) - tma_info_bottleneck_big_code= ", - "MetricGroup": "Fed;FetchBW;Frontend", + "MetricGroup": "BvFB;Fed;FetchBW;Frontend", "MetricName": "tma_info_bottleneck_instruction_fetch_bw", "MetricThreshold": "tma_info_bottleneck_instruction_fetch_bw > 20" }, { "BriefDescription": "Total pipeline cost of irregular execution (e= .g", "MetricExpr": "100 * (tma_microcode_sequencer / (tma_few_uops_inst= ructions + tma_microcode_sequencer) * (tma_assists / tma_microcode_sequence= r) * tma_fetch_latency * (tma_ms_switches + tma_branch_resteers * (tma_clea= rs_resteers + tma_mispredicts_resteers * (10 * tma_microcode_sequencer * tm= a_other_mispredicts / tma_branch_mispredicts)) / (tma_clears_resteers + tma= _mispredicts_resteers + tma_unknown_branches)) / (tma_branch_resteers + tma= _dsb_switches + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_swit= ches) + 10 * tma_microcode_sequencer * tma_other_mispredicts / tma_branch_m= ispredicts * tma_branch_mispredicts + tma_machine_clears * tma_other_nukes = / tma_other_nukes + tma_core_bound * (tma_serializing_operation + tma_core_= bound * RS_EVENTS.EMPTY_CYCLES / tma_info_thread_clks * tma_ports_utilized_= 0) / (tma_divider + tma_ports_utilization + tma_serializing_operation) + tm= a_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_sequence= r) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", - "MetricGroup": "Bad;Cor;Ret;tma_issueMS", + "MetricGroup": "Bad;BvIO;Cor;Ret;tma_issueMS", "MetricName": "tma_info_bottleneck_irregular_overhead", "MetricThreshold": "tma_info_bottleneck_irregular_overhead > 10", "PublicDescription": "Total pipeline cost of irregular execution (= e.g. FP-assists in HPC, Wait time with work imbalance multithreaded workloa= ds, overhead in system services or virtualized environments). Related metri= cs: tma_microcode_sequencer, tma_ms_switches" @@ -551,8 +553,8 @@ { "BriefDescription": "Total pipeline cost of Memory Address Transla= tion related bottlenecks (data-side TLBs)", "MetricConstraint": "NO_GROUP_EVENTS", - "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_lock_latency + tma_split_loads + tma_store_= fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma_dram_bound + tma_l1_= bound + tma_l2_bound + tma_l3_bound + tma_store_bound)) * (tma_dtlb_store /= (tma_dtlb_store + tma_false_sharing + tma_split_stores + tma_store_latency= + tma_streaming_stores)))", - "MetricGroup": "Mem;MemoryTLB;Offcore;tma_issueTLB", + "MetricExpr": "100 * (tma_memory_bound * (tma_l1_bound / max(tma_m= emory_bound, tma_dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + = tma_store_bound)) * (tma_dtlb_load / max(tma_l1_bound, tma_4k_aliasing + tm= a_dtlb_load + tma_fb_full + tma_l1_hit_latency + tma_lock_latency + tma_spl= it_loads + tma_store_fwd_blk)) + tma_memory_bound * (tma_store_bound / (tma= _dram_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound)= ) * (tma_dtlb_store / (tma_dtlb_store + tma_false_sharing + tma_split_store= s + tma_store_latency + tma_streaming_stores)))", + "MetricGroup": "BvMT;Mem;MemoryTLB;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_data_tlbs", "MetricThreshold": "tma_info_bottleneck_memory_data_tlbs > 20", "PublicDescription": "Total pipeline cost of Memory Address Transl= ation related bottlenecks (data-side TLBs). Related metrics: tma_dtlb_load,= tma_dtlb_store, tma_info_bottleneck_memory_synchronization" @@ -560,7 +562,7 @@ { "BriefDescription": "Total pipeline cost of Memory Synchronization= related bottlenecks (data transfers and coherency updates across processor= s)", "MetricExpr": "100 * (tma_memory_bound * (tma_l3_bound / (tma_dram= _bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * (t= ma_contested_accesses + tma_data_sharing) / (tma_contested_accesses + tma_d= ata_sharing + tma_l3_hit_latency + tma_sq_full) + tma_store_bound / (tma_dr= am_bound + tma_l1_bound + tma_l2_bound + tma_l3_bound + tma_store_bound) * = tma_false_sharing / (tma_dtlb_store + tma_false_sharing + tma_split_stores = + tma_store_latency + tma_streaming_stores - tma_store_latency)) + tma_mach= ine_clears * (1 - tma_other_nukes / tma_other_nukes))", - "MetricGroup": "Mem;Offcore;tma_issueTLB", + "MetricGroup": "BvMS;Mem;Offcore;tma_issueTLB", "MetricName": "tma_info_bottleneck_memory_synchronization", "MetricThreshold": "tma_info_bottleneck_memory_synchronization > 1= 0", "PublicDescription": "Total pipeline cost of Memory Synchronizatio= n related bottlenecks (data transfers and coherency updates across processo= rs). Related metrics: tma_dtlb_load, tma_dtlb_store, tma_info_bottleneck_me= mory_data_tlbs" @@ -569,18 +571,25 @@ "BriefDescription": "Total pipeline cost of Branch Misprediction r= elated bottlenecks", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "100 * (1 - 10 * tma_microcode_sequencer * tma_other= _mispredicts / tma_branch_mispredicts) * (tma_branch_mispredicts + tma_fetc= h_latency * tma_mispredicts_resteers / (tma_branch_resteers + tma_dsb_switc= hes + tma_icache_misses + tma_itlb_misses + tma_lcp + tma_ms_switches))", - "MetricGroup": "Bad;BadSpec;BrMispredicts;tma_issueBM", + "MetricGroup": "Bad;BadSpec;BrMispredicts;BvMP;tma_issueBM", "MetricName": "tma_info_bottleneck_mispredictions", "MetricThreshold": "tma_info_bottleneck_mispredictions > 20", "PublicDescription": "Total pipeline cost of Branch Misprediction = related bottlenecks. Related metrics: tma_branch_mispredicts, tma_info_bad_= spec_branch_misprediction_cost, tma_mispredicts_resteers" }, { - "BriefDescription": "Total pipeline cost of remaining bottlenecks = (apart from those listed in the Info.Bottlenecks metrics class)", - "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_base_non_br)", - "MetricGroup": "Cor;Offcore", + "BriefDescription": "Total pipeline cost of remaining bottlenecks = in the back-end", + "MetricExpr": "100 - (tma_info_bottleneck_big_code + tma_info_bott= leneck_instruction_fetch_bw + tma_info_bottleneck_mispredictions + tma_info= _bottleneck_cache_memory_bandwidth + tma_info_bottleneck_cache_memory_laten= cy + tma_info_bottleneck_memory_data_tlbs + tma_info_bottleneck_memory_sync= hronization + tma_info_bottleneck_compute_bound_est + tma_info_bottleneck_i= rregular_overhead + tma_info_bottleneck_branching_overhead + tma_info_bottl= eneck_useful_work)", + "MetricGroup": "BvOB;Cor;Offcore", "MetricName": "tma_info_bottleneck_other_bottlenecks", "MetricThreshold": "tma_info_bottleneck_other_bottlenecks > 20", - "PublicDescription": "Total pipeline cost of remaining bottlenecks= (apart from those listed in the Info.Bottlenecks metrics class). Examples = include data-dependencies (Core Bound when Low ILP) and other unlisted memo= ry-related stalls." + "PublicDescription": "Total pipeline cost of remaining bottlenecks= in the back-end. Examples include data-dependencies (Core Bound when Low I= LP) and other unlisted memory-related stalls." + }, + { + "BriefDescription": "Total pipeline cost of \"useful operations\" = - the portion of Retiring category not covered by Branching_Overhead nor Ir= regular_Overhead.", + "MetricExpr": "100 * (tma_retiring - (BR_INST_RETIRED.ALL_BRANCHES= + 2 * BR_INST_RETIRED.NEAR_CALL + INST_RETIRED.NOP) / tma_info_thread_slot= s - tma_microcode_sequencer / (tma_few_uops_instructions + tma_microcode_se= quencer) * (tma_assists / tma_microcode_sequencer) * tma_heavy_operations)", + "MetricGroup": "BvUW;Ret", + "MetricName": "tma_info_bottleneck_useful_work", + "MetricThreshold": "tma_info_bottleneck_useful_work > 20" }, { "BriefDescription": "Fraction of branches that are CALL or RET", @@ -638,7 +647,7 @@ }, { "BriefDescription": "Actual per-core usage of the Floating Point n= on-X87 execution units (regardless of precision or vector-width)", - "MetricExpr": "(cpu@FP_ARITH_INST_RETIRED.SCALAR_SINGLE\\,umask\\= =3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\,umask\\=3D0xfc@) = / (2 * tma_info_core_core_clks)", + "MetricExpr": "(FP_ARITH_INST_RETIRED.SCALAR + FP_ARITH_INST_RETIR= ED.VECTOR) / (2 * tma_info_core_core_clks)", "MetricGroup": "Cor;Flops;HPC", "MetricName": "tma_info_core_fp_arith_utilization", "PublicDescription": "Actual per-core usage of the Floating Point = non-X87 execution units (regardless of precision or vector-width). Values >= 1 are possible due to ([BDW+] Fused-Multiply Add (FMA) counting - common; = [ADL+] use all of ADD/MUL/FMA in Scalar or 128/256-bit vectors - less commo= n)." @@ -655,7 +664,7 @@ "MetricGroup": "DSB;Fed;FetchBW;tma_issueFB", "MetricName": "tma_info_frontend_dsb_coverage", "MetricThreshold": "tma_info_frontend_dsb_coverage < 0.7 & tma_inf= o_thread_ipc / 5 > 0.35", - "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_inst_mix_iptb, tma_lcp" + "PublicDescription": "Fraction of Uops delivered by the DSB (aka D= ecoded ICache; or Uop Cache). Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_inst_mix_iptb, tma_lcp" }, { "BriefDescription": "Average number of cycles of a switch from the= DSB fetch-unit to MITE fetch unit - see DSB_Switches tree node for details= .", @@ -721,7 +730,7 @@ }, { "BriefDescription": "Instructions per FP Arithmetic instruction (l= ower number means higher occurrence rate)", - "MetricExpr": "INST_RETIRED.ANY / (cpu@FP_ARITH_INST_RETIRED.SCALA= R_SINGLE\\,umask\\=3D0x03@ + cpu@FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE\\= ,umask\\=3D0xfc@)", + "MetricExpr": "INST_RETIRED.ANY / (FP_ARITH_INST_RETIRED.SCALAR + = FP_ARITH_INST_RETIRED.VECTOR)", "MetricGroup": "Flops;InsType", "MetricName": "tma_info_inst_mix_iparith", "MetricThreshold": "tma_info_inst_mix_iparith < 10", @@ -816,12 +825,12 @@ "MetricThreshold": "tma_info_inst_mix_ipswpf < 100" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Instructions per taken branch", "MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO;tma_issueFB", "MetricName": "tma_info_inst_mix_iptb", "MetricThreshold": "tma_info_inst_mix_iptb < 11", - "PublicDescription": "Instruction per taken branch. Related metric= s: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_misses, tm= a_info_frontend_dsb_coverage, tma_lcp" + "PublicDescription": "Instructions per taken branch. Related metri= cs: tma_dsb_switches, tma_fetch_bandwidth, tma_info_botlnk_l2_dsb_bandwidth= , tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, tma_lcp" }, { "BriefDescription": "Average per-core data fill bandwidth to the L= 1 data cache [GB / sec]", @@ -854,7 +863,7 @@ "MetricName": "tma_info_memory_fb_hpki" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L1 data cache [GB / sec]", "MetricExpr": "64 * L1D.REPLACEMENT / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l1d_cache_fill_bw" @@ -872,7 +881,7 @@ "MetricName": "tma_info_memory_l1mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L2 cache [GB / sec]", "MetricExpr": "64 * L2_LINES_IN.ALL / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l2_cache_fill_bw" @@ -908,13 +917,19 @@ "MetricName": "tma_info_memory_l2mpki_load" }, { - "BriefDescription": "", + "BriefDescription": "Offcore requests (L2 cache miss) per kilo ins= truction for demand RFOs", + "MetricExpr": "1e3 * L2_RQSTS.RFO_MISS / INST_RETIRED.ANY", + "MetricGroup": "CacheMisses;Offcore", + "MetricName": "tma_info_memory_l2mpki_rfo" + }, + { + "BriefDescription": "Average per-thread data access bandwidth to t= he L3 cache [GB / sec]", "MetricExpr": "64 * OFFCORE_REQUESTS.ALL_REQUESTS / 1e9 / duration= _time", "MetricGroup": "Mem;MemoryBW;Offcore", "MetricName": "tma_info_memory_l3_cache_access_bw" }, { - "BriefDescription": "", + "BriefDescription": "Average per-thread data fill bandwidth to the= L3 cache [GB / sec]", "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1e9 / duration_time", "MetricGroup": "Mem;MemoryBW", "MetricName": "tma_info_memory_l3_cache_fill_bw" @@ -1000,11 +1015,29 @@ "MetricName": "tma_info_memory_tlb_store_stlb_mpki" }, { - "BriefDescription": "", + "BriefDescription": "Instruction-Level-Parallelism (average number= of uops executed when there is execution) per core", "MetricExpr": "UOPS_EXECUTED.THREAD / (UOPS_EXECUTED.CORE_CYCLES_G= E_1 / 2 if #SMT_on else cpu@UOPS_EXECUTED.THREAD\\,cmask\\=3D1@)", "MetricGroup": "Cor;Pipeline;PortsUtil;SMT", "MetricName": "tma_info_pipeline_execute" }, + { + "BriefDescription": "Average number of uops fetched from DSB per c= ycle", + "MetricExpr": "IDQ.DSB_UOPS / IDQ.DSB_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_dsb" + }, + { + "BriefDescription": "Average number of uops fetched from LSD per c= ycle", + "MetricExpr": "LSD.UOPS / LSD.CYCLES_ACTIVE", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_lsd" + }, + { + "BriefDescription": "Average number of uops fetched from MITE per = cycle", + "MetricExpr": "IDQ.MITE_UOPS / IDQ.MITE_CYCLES_ANY", + "MetricGroup": "Fed;FetchBW", + "MetricName": "tma_info_pipeline_fetch_mite" + }, { "BriefDescription": "Instructions per a microcode Assist invocatio= n", "MetricExpr": "INST_RETIRED.ANY / ASSISTS.ANY", @@ -1027,13 +1060,13 @@ }, { "BriefDescription": "Average CPU Utilization (percentage)", - "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", + "MetricExpr": "tma_info_system_cpus_utilized / #num_cpus_online", "MetricGroup": "HPC;Summary", "MetricName": "tma_info_system_cpu_utilization" }, { "BriefDescription": "Average number of utilized CPUs", - "MetricExpr": "#num_cpus_online * tma_info_system_cpu_utilization", + "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / TSC", "MetricGroup": "Summary", "MetricName": "tma_info_system_cpus_utilized" }, @@ -1171,7 +1204,7 @@ "MetricThreshold": "tma_info_thread_uoppi > 1.05" }, { - "BriefDescription": "Instruction per taken branch", + "BriefDescription": "Uops per taken branch", "MetricExpr": "tma_retiring * tma_info_thread_slots / BR_INST_RETI= RED.NEAR_TAKEN", "MetricGroup": "Branches;Fed;FetchBW", "MetricName": "tma_info_thread_uptb", @@ -1180,7 +1213,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Instruction TLB (ITLB) misses", "MetricExpr": "ICACHE_TAG.STALLS / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;MemoryTLB;TopdownL3;tma_L3_g= roup;tma_fetch_latency_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;MemoryTLB;TopdownL3;tma= _L3_group;tma_fetch_latency_group", "MetricName": "tma_itlb_misses", "MetricThreshold": "tma_itlb_misses > 0.05 & (tma_fetch_latency > = 0.1 & tma_frontend_bound > 0.15)", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Instruction TLB (ITLB) misses. Sample with: FRONTE= ND_RETIRED.STLB_MISS_PS;FRONTEND_RETIRED.ITLB_MISS_PS", @@ -1195,11 +1228,20 @@ "PublicDescription": "This metric estimates how often the CPU was = stalled without loads missing the L1 data cache. The L1 data cache typical= ly has the shortest latency. However; in certain cases like loads blocked = on older stores; a load might suffer due to high latency even though it is = being satisfied by the L1. Another example is loads who miss in the TLB. Th= ese cases are characterized by execution unit stalls; while some non-comple= ted demand load lives in the machine without having that demand load missin= g the L1 cache. Sample with: MEM_LOAD_RETIRED.L1_HIT_PS;MEM_LOAD_RETIRED.FB= _HIT_PS. Related metrics: tma_clears_resteers, tma_machine_clears, tma_micr= ocode_sequencer, tma_ms_switches, tma_ports_utilized_1", "ScaleUnit": "100%" }, + { + "BriefDescription": "This metric roughly estimates fraction of cyc= les with demand load accesses that hit the L1 cache", + "MetricExpr": "min(2 * (MEM_INST_RETIRED.ALL_LOADS - MEM_LOAD_RETI= RED.FB_HIT - MEM_LOAD_RETIRED.L1_MISS) * 20 / 100, max(CYCLE_ACTIVITY.CYCLE= S_MEM_ANY - CYCLE_ACTIVITY.CYCLES_L1D_MISS, 0)) / tma_info_thread_clks", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_l1_bound= _group", + "MetricName": "tma_l1_hit_latency", + "MetricThreshold": "tma_l1_hit_latency > 0.1 & (tma_l1_bound > 0.1= & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", + "PublicDescription": "This metric roughly estimates fraction of cy= cles with demand load accesses that hit the L1 cache. The short latency of = the L1 data cache may be exposed in pointer-chasing memory access patterns = as an example. Sample with: MEM_LOAD_RETIRED.L1_HIT", + "ScaleUnit": "100%" + }, { "BriefDescription": "This metric estimates how often the CPU was s= talled due to L2 cache accesses by loads", "MetricConstraint": "NO_GROUP_EVENTS", "MetricExpr": "MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_RETIRED.FB_= HIT / MEM_LOAD_RETIRED.L1_MISS) / (MEM_LOAD_RETIRED.L2_HIT * (1 + MEM_LOAD_= RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS) + L1D_PEND_MISS.FB_FULL_PERIODS)= * ((CYCLE_ACTIVITY.STALLS_L1D_MISS - CYCLE_ACTIVITY.STALLS_L2_MISS) / tma_= info_thread_clks)", - "MetricGroup": "CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_L3_gr= oup;tma_memory_bound_group", + "MetricGroup": "BvML;CacheHits;MemoryBound;TmaL3mem;TopdownL3;tma_= L3_group;tma_memory_bound_group", "MetricName": "tma_l2_bound", "MetricThreshold": "tma_l2_bound > 0.05 & (tma_memory_bound > 0.2 = & tma_backend_bound > 0.2)", "PublicDescription": "This metric estimates how often the CPU was = stalled due to L2 cache accesses by loads. Avoiding cache misses (i.e. L1 = misses/L2 hits) can improve the latency and increase performance. Sample wi= th: MEM_LOAD_RETIRED.L2_HIT_PS", @@ -1218,7 +1260,7 @@ { "BriefDescription": "This metric estimates fraction of cycles with= demand load accesses that hit the L3 cache under unloaded scenarios (possi= bly L3 latency limited)", "MetricExpr": "17.5 * tma_info_system_core_frequency * (MEM_LOAD_R= ETIRED.L3_HIT * (1 + MEM_LOAD_RETIRED.FB_HIT / MEM_LOAD_RETIRED.L1_MISS / 2= )) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;TopdownL4;tma_L4_group;tma_issueLat;tma_= l3_bound_group", + "MetricGroup": "BvML;MemoryLat;TopdownL4;tma_L4_group;tma_issueLat= ;tma_l3_bound_group", "MetricName": "tma_l3_hit_latency", "MetricThreshold": "tma_l3_hit_latency > 0.1 & (tma_l3_bound > 0.0= 5 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles wit= h demand load accesses that hit the L3 cache under unloaded scenarios (poss= ibly L3 latency limited). Avoiding private cache misses (i.e. L2 misses/L3= hits) will improve the latency; reduce contention with sibling physical co= res and increase performance. Note the value of this node may overlap with= its siblings. Sample with: MEM_LOAD_RETIRED.L3_HIT_PS. Related metrics: tm= a_info_bottleneck_cache_memory_latency, tma_mem_latency", @@ -1230,7 +1272,7 @@ "MetricGroup": "FetchLat;TopdownL3;tma_L3_group;tma_fetch_latency_= group;tma_issueFB", "MetricName": "tma_lcp", "MetricThreshold": "tma_lcp > 0.05 & (tma_fetch_latency > 0.1 & tm= a_frontend_bound > 0.15)", - "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_misses, tma_info_frontend_dsb_coverage, t= ma_info_inst_mix_iptb", + "PublicDescription": "This metric represents fraction of cycles CP= U was stalled due to Length Changing Prefixes (LCPs). Using proper compiler= flags or Intel Compiler by default will certainly avoid this. #Link: Optim= ization Guide about LCP BKMs. Related metrics: tma_dsb_switches, tma_fetch_= bandwidth, tma_info_botlnk_l2_dsb_bandwidth, tma_info_botlnk_l2_dsb_misses,= tma_info_frontend_dsb_coverage, tma_info_inst_mix_iptb", "ScaleUnit": "100%" }, { @@ -1275,7 +1317,7 @@ "MetricGroup": "Offcore;TopdownL4;tma_L4_group;tma_issueRFO;tma_l1= _bound_group", "MetricName": "tma_lock_latency", "MetricThreshold": "tma_lock_latency > 0.2 & (tma_l1_bound > 0.1 &= (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", - "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS_PS. Related metrics: tma_store_latency", + "PublicDescription": "This metric represents fraction of cycles th= e CPU spent handling cache misses due to lock operations. Due to the microa= rchitecture handling of locks; they are classified as L1_Bound regardless o= f what memory source satisfied them. Sample with: MEM_INST_RETIRED.LOCK_LOA= DS. Related metrics: tma_store_latency", "ScaleUnit": "100%" }, { @@ -1290,7 +1332,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Machine Clears", "MetricExpr": "max(0, tma_bad_speculation - tma_branch_mispredicts= )", - "MetricGroup": "BadSpec;MachineClears;TmaL2;TopdownL2;tma_L2_group= ;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", + "MetricGroup": "BadSpec;BvMS;MachineClears;TmaL2;TopdownL2;tma_L2_= group;tma_bad_speculation_group;tma_issueMC;tma_issueSyncxn", "MetricName": "tma_machine_clears", "MetricThreshold": "tma_machine_clears > 0.1 & tma_bad_speculation= > 0.15", "MetricgroupNoGroup": "TopdownL2", @@ -1300,7 +1342,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the core's performance was likely hurt due to approaching bandwidth limit= s of external memory - DRAM ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, cpu@OFFCORE_REQUESTS_O= UTSTANDING.ALL_DATA_RD\\,cmask\\=3D4@) / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_dram_b= ound_group;tma_issueBW", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_d= ram_bound_group;tma_issueBW", "MetricName": "tma_mem_bandwidth", "MetricThreshold": "tma_mem_bandwidth > 0.2 & (tma_dram_bound > 0.= 1 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the core's performance was likely hurt due to approaching bandwidth limi= ts of external memory - DRAM ([SPR-HBM] and/or HBM). The underlying heuris= tic assumes that a similar off-core traffic is generated by all IA cores. T= his metric does not aggregate non-data-read requests by this logical proces= sor; requests from other IA Logical Processors/Physical Cores/sockets; or o= ther non-IA devices like GPU; hence the maximum external memory bandwidth l= imits may or may not be approached when this metric is flagged (see Uncore = counters for that). Related metrics: tma_fb_full, tma_info_bottleneck_cache= _memory_bandwidth, tma_info_system_dram_bw_use, tma_sq_full", @@ -1309,7 +1351,7 @@ { "BriefDescription": "This metric estimates fraction of cycles wher= e the performance was likely hurt due to latency from external memory - DRA= M ([SPR-HBM] and/or HBM)", "MetricExpr": "min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUESTS_OUTST= ANDING.CYCLES_WITH_DATA_RD) / tma_info_thread_clks - tma_mem_bandwidth", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_dram_= bound_group;tma_issueLat", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= dram_bound_group;tma_issueLat", "MetricName": "tma_mem_latency", "MetricThreshold": "tma_mem_latency > 0.1 & (tma_dram_bound > 0.1 = & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles whe= re the performance was likely hurt due to latency from external memory - DR= AM ([SPR-HBM] and/or HBM). This metric does not aggregate requests from ot= her Logical Processors/Physical Cores/sockets (see Uncore counters for that= ). Related metrics: tma_info_bottleneck_cache_memory_latency, tma_l3_hit_la= tency", @@ -1346,7 +1388,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to Branch Resteers as a result of Branch Misprediction= at execution stage", "MetricExpr": "BR_MISP_RETIRED.ALL_BRANCHES / (BR_MISP_RETIRED.ALL= _BRANCHES + MACHINE_CLEARS.COUNT) * INT_MISC.CLEAR_RESTEER_CYCLES / tma_inf= o_thread_clks", - "MetricGroup": "BadSpec;BrMispredicts;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group;tma_issueBM", + "MetricGroup": "BadSpec;BrMispredicts;BvMP;TopdownL4;tma_L4_group;= tma_branch_resteers_group;tma_issueBM", "MetricName": "tma_mispredicts_resteers", "MetricThreshold": "tma_mispredicts_resteers > 0.05 & (tma_branch_= resteers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to Branch Resteers as a result of Branch Mispredictio= n at execution stage. Sample with: INT_MISC.CLEAR_RESTEER_CYCLES. Related m= etrics: tma_branch_mispredicts, tma_info_bad_spec_branch_misprediction_cost= , tma_info_bottleneck_mispredictions", @@ -1390,7 +1432,7 @@ { "BriefDescription": "This metric represents fraction of slots wher= e the CPU was retiring NOP (no op) instructions", "MetricExpr": "tma_light_operations * INST_RETIRED.NOP / (tma_reti= ring * tma_info_thread_slots)", - "MetricGroup": "Pipeline;TopdownL4;tma_L4_group;tma_other_light_op= s_group", + "MetricGroup": "BvBO;Pipeline;TopdownL4;tma_L4_group;tma_other_lig= ht_ops_group", "MetricName": "tma_nop_instructions", "MetricThreshold": "tma_nop_instructions > 0.1 & (tma_other_light_= ops > 0.3 & tma_light_operations > 0.6)", "PublicDescription": "This metric represents fraction of slots whe= re the CPU was retiring NOP (no op) instructions. Compilers often use NOPs = for certain address alignments - e.g. start address of a function or loop b= ody. Sample with: INST_RETIRED.NOP", @@ -1409,7 +1451,7 @@ { "BriefDescription": "This metric estimates fraction of slots the C= PU was stalled due to other cases of misprediction (non-retired x86 branche= s or other types).", "MetricExpr": "max(tma_branch_mispredicts * (1 - BR_MISP_RETIRED.A= LL_BRANCHES / (INT_MISC.CLEARS_COUNT - MACHINE_CLEARS.COUNT)), 0.0001)", - "MetricGroup": "BrMispredicts;TopdownL3;tma_L3_group;tma_branch_mi= spredicts_group", + "MetricGroup": "BrMispredicts;BvIO;TopdownL3;tma_L3_group;tma_bran= ch_mispredicts_group", "MetricName": "tma_other_mispredicts", "MetricThreshold": "tma_other_mispredicts > 0.05 & (tma_branch_mis= predicts > 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1417,7 +1459,7 @@ { "BriefDescription": "This metric represents fraction of slots the = CPU has wasted due to Nukes (Machine Clears) not related to memory ordering= .", "MetricExpr": "max(tma_machine_clears * (1 - MACHINE_CLEARS.MEMORY= _ORDERING / MACHINE_CLEARS.COUNT), 0.0001)", - "MetricGroup": "Machine_Clears;TopdownL3;tma_L3_group;tma_machine_= clears_group", + "MetricGroup": "BvIO;Machine_Clears;TopdownL3;tma_L3_group;tma_mac= hine_clears_group", "MetricName": "tma_other_nukes", "MetricThreshold": "tma_other_nukes > 0.05 & (tma_machine_clears >= 0.1 & tma_bad_speculation > 0.15)", "ScaleUnit": "100%" @@ -1469,7 +1511,7 @@ }, { "BriefDescription": "This metric represents fraction of cycles CPU= executed no uops on any execution port (Logical Processor cycles since ICL= , Physical Core cycles otherwise)", - "MetricExpr": "(cpu@EXE_ACTIVITY.3_PORTS_UTIL\\,umask\\=3D0x80@ + = tma_core_bound * RS_EVENTS.EMPTY_CYCLES) / tma_info_thread_clks * (CYCLE_AC= TIVITY.STALLS_TOTAL - CYCLE_ACTIVITY.STALLS_MEM_ANY) / tma_info_thread_clks= ", + "MetricExpr": "EXE_ACTIVITY.EXE_BOUND_0_PORTS / tma_info_thread_cl= ks", "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", "MetricName": "tma_ports_utilized_0", "MetricThreshold": "tma_ports_utilized_0 > 0.2 & (tma_ports_utiliz= ation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", @@ -1497,7 +1539,7 @@ { "BriefDescription": "This metric represents fraction of cycles CPU= executed total of 3 or more uops per cycle on all execution ports (Logical= Processor cycles since ICL, Physical Core cycles otherwise)", "MetricExpr": "UOPS_EXECUTED.CYCLES_GE_3 / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL4;tma_L4_group;tma_ports_utiliza= tion_group", + "MetricGroup": "BvCB;PortsUtil;TopdownL4;tma_L4_group;tma_ports_ut= ilization_group", "MetricName": "tma_ports_utilized_3m", "MetricThreshold": "tma_ports_utilized_3m > 0.4 & (tma_ports_utili= zation > 0.15 & (tma_core_bound > 0.1 & tma_backend_bound > 0.2))", "PublicDescription": "This metric represents fraction of cycles CP= U executed total of 3 or more uops per cycle on all execution ports (Logica= l Processor cycles since ICL, Physical Core cycles otherwise). Sample with:= UOPS_EXECUTED.CYCLES_GE_3", @@ -1507,7 +1549,7 @@ "BriefDescription": "This category represents fraction of slots ut= ilized by useful work i.e. issued uops that eventually get retired", "DefaultMetricgroupName": "TopdownL1", "MetricExpr": "topdown\\-retiring / (topdown\\-fe\\-bound + topdow= n\\-bad\\-spec + topdown\\-retiring + topdown\\-be\\-bound) + 0 * tma_info_= thread_slots", - "MetricGroup": "Default;TmaL1;TopdownL1;tma_L1_group", + "MetricGroup": "BvUW;Default;TmaL1;TopdownL1;tma_L1_group", "MetricName": "tma_retiring", "MetricThreshold": "tma_retiring > 0.7 | tma_heavy_operations > 0.= 1", "MetricgroupNoGroup": "TopdownL1;Default", @@ -1517,7 +1559,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU issue-pipeline was stalled due to serializing operations", "MetricExpr": "RESOURCE_STALLS.SCOREBOARD / tma_info_thread_clks", - "MetricGroup": "PortsUtil;TopdownL3;tma_L3_group;tma_core_bound_gr= oup;tma_issueSO", + "MetricGroup": "BvIO;PortsUtil;TopdownL3;tma_L3_group;tma_core_bou= nd_group;tma_issueSO", "MetricName": "tma_serializing_operation", "MetricThreshold": "tma_serializing_operation > 0.1 & (tma_core_bo= und > 0.1 & tma_backend_bound > 0.2)", "PublicDescription": "This metric represents fraction of cycles th= e CPU issue-pipeline was stalled due to serializing operations. Instruction= s like CPUID; WRMSR or LFENCE serialize the out-of-order execution which ma= y limit performance. Sample with: RESOURCE_STALLS.SCOREBOARD. Related metri= cs: tma_ms_switches", @@ -1554,7 +1596,7 @@ { "BriefDescription": "This metric measures fraction of cycles where= the Super Queue (SQ) was full taking into account all request-types and bo= th hardware SMT threads (Logical Processors)", "MetricExpr": "L1D_PEND_MISS.L2_STALL / tma_info_thread_clks", - "MetricGroup": "MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_issueB= W;tma_l3_bound_group", + "MetricGroup": "BvMS;MemoryBW;Offcore;TopdownL4;tma_L4_group;tma_i= ssueBW;tma_l3_bound_group", "MetricName": "tma_sq_full", "MetricThreshold": "tma_sq_full > 0.3 & (tma_l3_bound > 0.05 & (tm= a_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric measures fraction of cycles wher= e the Super Queue (SQ) was full taking into account all request-types and b= oth hardware SMT threads (Logical Processors). Related metrics: tma_fb_full= , tma_info_bottleneck_cache_memory_bandwidth, tma_info_system_dram_bw_use, = tma_mem_bandwidth", @@ -1582,7 +1624,7 @@ { "BriefDescription": "This metric estimates fraction of cycles the = CPU spent handling L1D store misses", "MetricExpr": "(L2_RQSTS.RFO_HIT * 10 * (1 - MEM_INST_RETIRED.LOCK= _LOADS / MEM_INST_RETIRED.ALL_STORES) + (1 - MEM_INST_RETIRED.LOCK_LOADS / = MEM_INST_RETIRED.ALL_STORES) * min(CPU_CLK_UNHALTED.THREAD, OFFCORE_REQUEST= S_OUTSTANDING.CYCLES_WITH_DEMAND_RFO)) / tma_info_thread_clks", - "MetricGroup": "MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_issue= RFO;tma_issueSL;tma_store_bound_group", + "MetricGroup": "BvML;MemoryLat;Offcore;TopdownL4;tma_L4_group;tma_= issueRFO;tma_issueSL;tma_store_bound_group", "MetricName": "tma_store_latency", "MetricThreshold": "tma_store_latency > 0.1 & (tma_store_bound > 0= .2 & (tma_memory_bound > 0.2 & tma_backend_bound > 0.2))", "PublicDescription": "This metric estimates fraction of cycles the= CPU spent handling L1D store misses. Store accesses usually less impact ou= t-of-order core performance; however; holding resources for longer time can= lead into undesired implications (e.g. contention on L1D fill-buffer entri= es - see FB_Full). Related metrics: tma_fb_full, tma_lock_latency", @@ -1625,7 +1667,7 @@ { "BriefDescription": "This metric represents fraction of cycles the= CPU was stalled due to new branch address clears", "MetricExpr": "10 * BACLEARS.ANY / tma_info_thread_clks", - "MetricGroup": "BigFootprint;FetchLat;TopdownL4;tma_L4_group;tma_b= ranch_resteers_group", + "MetricGroup": "BigFootprint;BvBC;FetchLat;TopdownL4;tma_L4_group;= tma_branch_resteers_group", "MetricName": "tma_unknown_branches", "MetricThreshold": "tma_unknown_branches > 0.05 & (tma_branch_rest= eers > 0.05 & (tma_fetch_latency > 0.1 & tma_frontend_bound > 0.15))", "PublicDescription": "This metric represents fraction of cycles th= e CPU was stalled due to new branch address clears. These are fetched branc= hes the Branch Prediction Unit was unable to recognize (e.g. first time the= branch is fetched or hitting BTB capacity limit) hence called Unknown Bran= ches. Sample with: BACLEARS.ANY", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.j= son b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json index 48f23acc76c0..1500bf109c99 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-interconnect.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "UNC_ARB_COH_TRK_REQUESTS.ALL", + "Counter": "0,1", "EventCode": "0x84", "EventName": "UNC_ARB_COH_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -9,56 +10,69 @@ }, { "BriefDescription": "Each cycle counts number of any coherent requ= est at memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle counts number of coherent reads pe= nding on data return from memory controller that were issued by any core.", + "Counter": "0", "EventCode": "0x85", "EventName": "UNC_ARB_DAT_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_REQ_TRK_REQUEST.DRD", + "Counter": "0,1", "Deprecated": "1", "EventCode": "0x81", "EventName": "UNC_ARB_DAT_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "This event is deprecated. Refer to new event = UNC_ARB_DAT_OCCUPANCY.ALL", + "Counter": "0", "Deprecated": "1", "EventCode": "0x85", "EventName": "UNC_ARB_IFA_OCCUPANCY.ALL", + "Experimental": "1", "PerPkg": "1", "UMask": "0x1", "Unit": "ARB" }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_T= RK_OCCUPANCY.RD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_REQ_TRK_OCCUPANCY.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_TRK_REQUESTS.RD]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_REQ_TRK_REQUEST.DRD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "Each cycle count number of all outgoing valid= entries in ReqTrk. Such entry is defined as valid from it's allocation in = ReqTrk till deallocation. Accounts for Coherent and non-coherent traffic.", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.ALL", "PerPkg": "1", @@ -67,14 +81,17 @@ }, { "BriefDescription": "Each cycle count number of 'valid' coherent D= ata Read entries . Such entry is defined as valid when it is allocated till= deallocation. Doesn't include prefetches [This event is alias to UNC_ARB_R= EQ_TRK_OCCUPANCY.DRD]", + "Counter": "0", "EventCode": "0x80", "EventName": "UNC_ARB_TRK_OCCUPANCY.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" }, { "BriefDescription": "UNC_ARB_TRK_REQUESTS.ALL", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.ALL", "PerPkg": "1", @@ -83,8 +100,10 @@ }, { "BriefDescription": "Number of all coherent Data Read entries. Doe= sn't include prefetches [This event is alias to UNC_ARB_REQ_TRK_REQUEST.DRD= ]", + "Counter": "0,1", "EventCode": "0x81", "EventName": "UNC_ARB_TRK_REQUESTS.RD", + "Experimental": "1", "PerPkg": "1", "UMask": "0x2", "Unit": "ARB" diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json b/= tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json index 99fb5259fd25..ea213045cbca 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "Counter": "1", "EventCode": "0xff", "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "Counter": "0", "EventCode": "0xff", "EventName": "UNC_MC0_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "Counter": "2", "EventCode": "0xff", "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN", "PerPkg": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts every read (RdCAS) issued by the Memor= y Controller to DRAM (sum of all channels). All requests result in 64 byte = data transfers from DRAM.", + "Counter": "4", "EventCode": "0xff", "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN", "PerPkg": "1", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Counts every 64B read and write request enter= ing the Memory Controller to DRAM (sum of all channels). Each write request= counts as a new request incrementing this counter. However, same cache lin= e write requests (both full and partial) are combined to a single 64 byte d= ata transfer to DRAM.", + "Counter": "3", "EventCode": "0xff", "EventName": "UNC_MC1_TOTAL_REQCOUNT_FREERUN", "PerPkg": "1", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Counts every write (WrCAS) issued by the Memo= ry Controller to DRAM (sum of all channels). All requests result in 64 byte= data transfers from DRAM.", + "Counter": "5", "EventCode": "0xff", "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json b/t= ools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json index c6596ba09195..cc8110ac020c 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/uncore-other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "UNC_CLOCK.SOCKET", + "Counter": "FIXED", "EventCode": "0xff", "EventName": "UNC_CLOCK.SOCKET", "PerPkg": "1", diff --git a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json b= /tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json index adb2f6b3e77c..62dc0fc76748 100644 --- a/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/tigerlake/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Loads that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Counts loads that miss the DTLB (Data TLB) a= nd hit the STLB (Second level TLB).", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a demand load.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data loads. This implies it missed in the DTLB and furth= er levels of TLB. The page walk can end with or without a fault.", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M sizes) c= aused by demand data loads. This implies address translations missed in the= DTLB and further levels of TLB. The page walk can end with or without a fa= ult.", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data loa= d to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K sizes) caus= ed by demand data loads. This implies address translations missed in the DT= LB and further levels of TLB. The page walk can end with or without a fault= .", @@ -42,6 +47,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a demand= load in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a demand load in the PMH (Page Miss Handler) each cycle.", @@ -50,6 +56,7 @@ }, { "BriefDescription": "Stores that miss the DTLB and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Counts stores that miss the DTLB (Data TLB) = and hit the STLB (2nd Level TLB).", @@ -58,6 +65,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for a store.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE", @@ -67,6 +75,7 @@ }, { "BriefDescription": "Store misses in all TLB levels causes a page = walk that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes= ) caused by demand data stores. This implies it missed in the DTLB and furt= her levels of TLB. The page walk can end with or without a fault.", @@ -75,6 +84,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 2M/4M page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 2= M/4M pages. The page walks can end with or without a page fault.", @@ -83,6 +93,7 @@ }, { "BriefDescription": "Page walks completed due to a demand data sto= re to a 4K page.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts page walks completed due to demand da= ta stores whose address translations missed in the TLB and were mapped to 4= K pages. The page walks can end with or without a page fault.", @@ -91,6 +102,7 @@ }, { "BriefDescription": "Number of page walks outstanding for a store = in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for a store in the PMH (Page Miss Handler) each cycle.", @@ -99,6 +111,7 @@ }, { "BriefDescription": "Instruction fetch requests that miss the ITLB= and hit the STLB.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "Counts instruction fetch requests that miss = the ITLB (Instruction TLB) and hit the STLB (Second-level TLB).", @@ -107,6 +120,7 @@ }, { "BriefDescription": "Cycles when at least one PMH is busy with a p= age walk for code (instruction fetch) request.", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_ACTIVE", @@ -116,6 +130,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (All page sizes)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Counts completed page walks (all page sizes)= caused by a code fetch. This implies it missed in the ITLB (Instruction TL= B) and further levels of TLB. The page walk can end with or without a fault= .", @@ -124,6 +139,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Counts completed page walks (2M/4M page size= s) caused by a code fetch. This implies it missed in the ITLB (Instruction = TLB) and further levels of TLB. The page walk can end with or without a fau= lt.", @@ -132,6 +148,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page wal= k that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Counts completed page walks (4K page sizes) = caused by a code fetch. This implies it missed in the ITLB (Instruction TLB= ) and further levels of TLB. The page walk can end with or without a fault.= ", @@ -140,6 +157,7 @@ }, { "BriefDescription": "Number of page walks outstanding for an outst= anding code request in the PMH each cycle.", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_PENDING", "PublicDescription": "Counts the number of page walks outstanding = for an outstanding code (instruction fetch) request in the PMH (Page Miss H= andler) each cycle.", @@ -148,6 +166,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific en= tries", + "Counter": "0,1,2,3", "EventCode": "0xbd", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "Counts the number of DTLB flush attempts of = the thread-specific entries.", @@ -156,6 +175,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xbd", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Counts the number of any STLB flush attempts= (such as entire, VPID, PCID, InvPage, CR3 write, etc.).", --=20 2.45.2.627.g7a2c4fd464-goog From nobody Tue Dec 16 10:52:24 2025 Received: from mail-pf1-f202.google.com (mail-pf1-f202.google.com [209.85.210.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 379911BBBE4 for ; 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Thu, 20 Jun 2024 11:20:39 -0700 (PDT) Date: Thu, 20 Jun 2024 11:17:49 -0700 In-Reply-To: <20240620181752.3945845-1-irogers@google.com> Message-Id: <20240620181752.3945845-36-irogers@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20240620181752.3945845-1-irogers@google.com> X-Mailer: git-send-email 2.45.2.627.g7a2c4fd464-goog Subject: [PATCH v2 35/37] perf vendor events: Add westmereep-dp counter information From: Ian Rogers To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/westmereep-dp/cache.json | 282 ++++++++++++++++++ .../arch/x86/westmereep-dp/counter.json | 7 + .../x86/westmereep-dp/floating-point.json | 28 ++ .../arch/x86/westmereep-dp/frontend.json | 3 + .../arch/x86/westmereep-dp/memory.json | 69 +++++ .../arch/x86/westmereep-dp/other.json | 28 ++ .../arch/x86/westmereep-dp/pipeline.json | 111 +++++++ .../x86/westmereep-dp/virtual-memory.json | 21 ++ 8 files changed, 549 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/westmereep-dp/counter.js= on diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json b/tool= s/perf/pmu-events/arch/x86/westmereep-dp/cache.json index 4dae735fb636..30845c7dbf08 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request= ", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +563,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +574,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +596,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +607,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +618,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +629,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +640,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +651,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +662,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +684,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +695,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +706,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +717,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +726,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +735,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +744,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +753,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +762,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +780,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +789,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -704,6 +797,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -711,6 +805,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -718,6 +813,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -725,6 +821,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -732,6 +829,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -739,6 +837,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -746,6 +845,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -753,6 +853,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -761,6 +862,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -768,6 +870,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", @@ -776,6 +879,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -783,6 +887,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", @@ -791,6 +896,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -798,6 +904,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -806,6 +913,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -813,6 +921,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ALL_LOCAL_DRAM_AND_REMOTE_= CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -822,6 +931,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -831,6 +941,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -840,6 +951,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D IO= _CSR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -849,6 +961,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -858,6 +971,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -867,6 +981,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -876,6 +991,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -885,6 +1001,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM_AND_REMOTE_CACH= E_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -894,6 +1011,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -903,6 +1021,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -912,6 +1031,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_C= ACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -921,6 +1041,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= OCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -930,6 +1051,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D IO_CS= R_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -939,6 +1061,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -948,6 +1071,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -957,6 +1081,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -966,6 +1091,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -975,6 +1101,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -984,6 +1111,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -993,6 +1121,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1002,6 +1131,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1011,6 +1141,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1020,6 +1151,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D IO_C= SR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1029,6 +1161,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1038,6 +1171,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1047,6 +1181,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1056,6 +1191,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1065,6 +1201,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1074,6 +1211,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1083,6 +1221,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1092,6 +1231,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_CACH= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1101,6 +1241,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LOCA= TION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1110,6 +1251,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D IO_CSR_M= MIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1119,6 +1261,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1128,6 +1271,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1137,6 +1281,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1146,6 +1291,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_CA= CHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1155,6 +1301,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1164,6 +1311,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_C= ACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1173,6 +1321,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ALL_LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1182,6 +1331,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_CACH= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1191,6 +1341,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LOCA= TION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1200,6 +1351,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D IO_CSR_M= MIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1209,6 +1361,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1218,6 +1371,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1227,6 +1381,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1236,6 +1391,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_CA= CHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1245,6 +1401,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM_AND_REMOTE_CACHE_= HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1254,6 +1411,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_C= ACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1263,6 +1421,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1272,6 +1431,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1281,6 +1441,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1290,6 +1451,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D IO_C= SR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1299,6 +1461,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1308,6 +1471,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1317,6 +1481,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1326,6 +1491,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1335,6 +1501,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1344,6 +1511,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1353,6 +1521,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1362,6 +1531,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_CACH= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1371,6 +1541,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LOCA= TION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1380,6 +1551,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D IO_CSR_M= MIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1389,6 +1561,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1398,6 +1571,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1407,6 +1581,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1416,6 +1591,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_CA= CHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1425,6 +1601,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1434,6 +1611,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_C= ACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1443,6 +1621,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ALL_= LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ALL_LOCAL_DRAM_AND_REMO= TE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1452,6 +1631,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1461,6 +1641,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1470,6 +1651,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D IO_C= SR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1479,6 +1661,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1488,6 +1671,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1497,6 +1681,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LLC_= HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1506,6 +1691,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1515,6 +1701,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1524,6 +1711,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1533,6 +1721,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= LL_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ALL_LOCAL_DRAM_AND_R= EMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1542,6 +1731,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1551,6 +1741,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1560,6 +1751,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D I= O_CSR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1569,6 +1761,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1578,6 +1771,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1a6,0x1a7", @@ -1587,6 +1781,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= LC_HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -1596,6 +1791,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1605,6 +1801,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D L= OCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1614,6 +1811,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1623,6 +1821,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AL= L_LOCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ALL_LOCAL_DRAM_AND_RE= MOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1632,6 +1831,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_CACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1641,6 +1841,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LOCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1650,6 +1851,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D IO= _CSR_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1659,6 +1861,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1668,6 +1871,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1a6,0x1a7", @@ -1677,6 +1881,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LL= C_HIT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1a6,0x1a7", @@ -1686,6 +1891,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1695,6 +1901,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D LO= CAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM_AND_REMOTE= _CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1704,6 +1911,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1713,6 +1921,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1722,6 +1931,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_C= ACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1731,6 +1941,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= OCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1740,6 +1951,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D IO_CS= R_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1749,6 +1961,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1758,6 +1971,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1767,6 +1981,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1776,6 +1991,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1785,6 +2001,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1794,6 +2011,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1803,6 +2021,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ALL_LOCAL_= DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ALL_LOCAL_DRAM_AND_REMOTE_CAC= HE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1812,6 +2031,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_CACHE_= DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1821,6 +2041,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LOCATI= ON", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1830,6 +2051,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D IO_CSR_MMI= O", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1839,6 +2061,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_NO= _OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1848,6 +2071,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1857,6 +2081,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LLC_HIT_OT= HER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1866,6 +2091,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_CACH= E", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1875,6 +2101,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D LOCAL_DRAM= AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_DRAM_AND_REMOTE_CACHE_H= IT", "MSRIndex": "0x1a6,0x1a7", @@ -1884,6 +2111,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_CAC= HE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1893,6 +2121,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ALL_LOCA= L_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ALL_LOCAL_DRAM_AND_REMOTE_C= ACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1902,6 +2131,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_CACH= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1911,6 +2141,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LOCA= TION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1920,6 +2151,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D IO_CSR_M= MIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1929,6 +2161,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1938,6 +2171,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1947,6 +2181,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LLC_HIT_= OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1956,6 +2191,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_CA= CHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1965,6 +2201,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D LOCAL_DR= AM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM_AND_REMOTE_CACHE= _HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1974,6 +2211,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_C= ACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1983,6 +2221,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ALL_L= OCAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ALL_LOCAL_DRAM_AND_REMOT= E_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1992,6 +2231,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_C= ACHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2001,6 +2241,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= OCATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2010,6 +2251,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D IO_CS= R_MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2019,6 +2261,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2028,6 +2271,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2037,6 +2281,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LLC_H= IT_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2046,6 +2291,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2055,6 +2301,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D LOCAL= _DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2064,6 +2311,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2073,6 +2321,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ALL_LOCAL= _DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ALL_LOCAL_DRAM_AND_REMOTE= _CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2082,6 +2331,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_CACHE= _DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2091,6 +2341,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LOCAT= ION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2100,6 +2351,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D IO_CSR_MM= IO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2109,6 +2361,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_N= O_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2118,6 +2371,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2127,6 +2381,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LLC_HIT_O= THER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2136,6 +2391,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_CAC= HE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2145,6 +2401,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D LOCAL_DRA= M AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM_AND_REMOTE_CAC= HE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2154,6 +2411,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_CA= CHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2163,6 +2421,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ALL_LO= CAL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ALL_LOCAL_DRAM_AND_REMOTE_CA= CHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2172,6 +2431,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_CA= CHE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2181,6 +2441,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LO= CATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2190,6 +2451,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D IO_CSR= _MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2199,6 +2461,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2208,6 +2471,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2217,6 +2481,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LLC_HI= T_OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2226,6 +2491,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= CACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2235,6 +2501,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D LOCAL_= DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM_AND_REMOTE_CACHE_= HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2244,6 +2511,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2253,6 +2521,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ALL_LOC= AL_DRAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ALL_LOCAL_DRAM_AND_REMOTE_= CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2262,6 +2531,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_CAC= HE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2271,6 +2541,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LOC= ATION", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2280,6 +2551,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D IO_CSR_= MMIO", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2289,6 +2561,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _NO_OTHER_CORE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2298,6 +2571,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2307,6 +2581,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LLC_HIT= _OTHER_CORE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2316,6 +2591,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_C= ACHE", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2325,6 +2601,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D LOCAL_D= RAM AND REMOTE_CACHE_HIT", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM_AND_REMOTE_CACH= E_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2334,6 +2611,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= CACHE_HITM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2343,6 +2621,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2350,6 +2629,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2357,6 +2637,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2364,6 +2645,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/counter.json b/to= ols/perf/pmu-events/arch/x86/westmereep-dp/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input = value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transition= s", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json b/too= ls/perf/pmu-events/arch/x86/westmereep-dp/memory.json index 7085c3307c91..dcf1bf3f880d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Misaligned store references", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -17,6 +19,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D AN= Y_LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -26,6 +29,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D OT= HER_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -35,6 +39,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_DATA read and RESPONSE =3D RE= MOTE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -44,6 +49,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -53,6 +59,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D ANY_L= LC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -62,6 +69,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D OTHER= _LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -71,6 +79,7 @@ }, { "BriefDescription": "REQUEST =3D ANY IFETCH and RESPONSE =3D REMOT= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -80,6 +89,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -89,6 +99,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D ANY_= LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -98,6 +109,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D OTHE= R_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -107,6 +119,7 @@ }, { "BriefDescription": "REQUEST =3D ANY_REQUEST and RESPONSE =3D REMO= TE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -116,6 +129,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -125,6 +139,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D ANY_LLC_= MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -134,6 +149,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D OTHER_LO= CAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -143,6 +159,7 @@ }, { "BriefDescription": "REQUEST =3D ANY RFO and RESPONSE =3D REMOTE_D= RAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -152,6 +169,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -161,6 +179,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D ANY_LLC_= MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -170,6 +189,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D OTHER_LO= CAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -179,6 +199,7 @@ }, { "BriefDescription": "REQUEST =3D CORE_WB and RESPONSE =3D REMOTE_D= RAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -188,6 +209,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -197,6 +219,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D ANY_= LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -206,6 +229,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D OTHE= R_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -215,6 +239,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IFETCH and RESPONSE =3D REMO= TE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -224,6 +249,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -233,6 +259,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D ANY_LLC_= MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -242,6 +269,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D OTHER_LO= CAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -251,6 +279,7 @@ }, { "BriefDescription": "REQUEST =3D DATA_IN and RESPONSE =3D REMOTE_D= RAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -260,6 +289,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM_AND_REMOTE_FWD= ", "MSRIndex": "0x1a6,0x1a7", @@ -269,6 +299,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D ANY_= LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -278,6 +309,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D OTHE= R_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -287,6 +319,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA and RESPONSE =3D REMO= TE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -296,6 +329,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM_AND_REMOTE_= FWD", "MSRIndex": "0x1a6,0x1a7", @@ -305,6 +339,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D A= NY_LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -314,6 +349,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D O= THER_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -323,6 +359,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_DATA_RD and RESPONSE =3D R= EMOTE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -332,6 +369,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_DRAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM_AND_REMOTE_F= WD", "MSRIndex": "0x1a6,0x1a7", @@ -341,6 +379,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D AN= Y_LLC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -350,6 +389,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D OT= HER_LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -359,6 +399,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_IFETCH and RESPONSE =3D RE= MOTE_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -368,6 +409,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -377,6 +419,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D ANY_L= LC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -386,6 +429,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D OTHER= _LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -395,6 +439,7 @@ }, { "BriefDescription": "REQUEST =3D DEMAND_RFO and RESPONSE =3D REMOT= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -404,6 +449,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_DRAM A= ND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -413,6 +459,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D ANY_LLC_MI= SS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -422,6 +469,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D OTHER_LOCA= L_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -431,6 +479,7 @@ }, { "BriefDescription": "REQUEST =3D OTHER and RESPONSE =3D REMOTE_DRA= M", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -440,6 +489,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_DRAM= AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -449,6 +499,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D ANY_LLC_= MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -458,6 +509,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D OTHER_LO= CAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -467,6 +519,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA and RESPONSE =3D REMOTE_D= RAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -476,6 +529,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_D= RAM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -485,6 +539,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D ANY_L= LC_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -494,6 +549,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D OTHER= _LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -503,6 +559,7 @@ }, { "BriefDescription": "REQUEST =3D PF_DATA_RD and RESPONSE =3D REMOT= E_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -512,6 +569,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_DRAM = AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -521,6 +579,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D ANY_LLC_M= ISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -530,6 +589,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D OTHER_LOC= AL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -539,6 +599,7 @@ }, { "BriefDescription": "REQUEST =3D PF_RFO and RESPONSE =3D REMOTE_DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -548,6 +609,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_DR= AM AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -557,6 +619,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D ANY_LL= C_MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -566,6 +629,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D OTHER_= LOCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -575,6 +639,7 @@ }, { "BriefDescription": "REQUEST =3D PF_IFETCH and RESPONSE =3D REMOTE= _DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -584,6 +649,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_DRA= M AND REMOTE_FWD", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM_AND_REMOTE_FWD", "MSRIndex": "0x1a6,0x1a7", @@ -593,6 +659,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D ANY_LLC= _MISS", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -602,6 +669,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D OTHER_L= OCAL_DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.OTHER_LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -611,6 +679,7 @@ }, { "BriefDescription": "REQUEST =3D PREFETCH and RESPONSE =3D REMOTE_= DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json b/tool= s/perf/pmu-events/arch/x86/westmereep-dp/other.json index 488274980564..bcf5bcf637c0 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Loads that partially overlap an earlier store= ", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "False dependencies due to partial address ali= asing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Snoop code requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Snoop data requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Snoop invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Outstanding snoop code requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "Cycles snoop code requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", @@ -142,6 +162,7 @@ }, { "BriefDescription": "Outstanding snoop data requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", @@ -149,6 +170,7 @@ }, { "BriefDescription": "Cycles snoop data requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", @@ -157,6 +179,7 @@ }, { "BriefDescription": "Outstanding snoop invalidate requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", @@ -164,6 +187,7 @@ }, { "BriefDescription": "Cycles snoop invalidate requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", @@ -172,6 +196,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json b/t= ools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json index a29ed3522779..0267788d9dce 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediciton Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event= )", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -246,6 +280,7 @@ }, { "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -254,6 +289,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -262,11 +298,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -274,17 +312,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed count= er)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -293,6 +334,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -300,6 +342,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -307,6 +350,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -314,6 +358,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -321,6 +366,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -328,6 +374,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder = 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -335,6 +382,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -342,6 +390,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instru= ction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -349,11 +398,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -362,6 +413,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -370,6 +422,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -380,6 +433,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -390,6 +444,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -398,6 +453,7 @@ }, { "BriefDescription": "Load operations conflicting with software pre= fetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -405,6 +461,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -422,6 +480,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction = queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -429,6 +488,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -436,6 +496,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -450,6 +512,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -457,6 +520,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -464,6 +528,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -471,6 +536,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -478,6 +544,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -485,6 +552,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -492,6 +560,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -499,6 +568,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -506,6 +576,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -513,6 +584,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -520,6 +592,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -527,6 +600,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -534,6 +608,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -573,6 +652,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -581,6 +661,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -588,6 +669,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -595,6 +677,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -603,6 +686,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -613,6 +697,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -622,6 +707,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -631,6 +717,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -642,6 +729,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -653,6 +741,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -663,6 +752,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -672,6 +762,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -679,6 +770,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -686,6 +778,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -695,6 +788,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -703,6 +797,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -711,6 +806,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -719,6 +815,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -727,6 +824,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -734,6 +832,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -741,6 +840,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -749,6 +849,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -759,6 +860,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -767,6 +869,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -774,6 +877,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -783,6 +887,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -816,6 +924,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -826,6 +935,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -836,6 +946,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index f75084309041..53d7f76325a3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB misses caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "ITLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -135,6 +154,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", + "Counter": "0,1,2,3", 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Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../arch/x86/westmereep-sp/cache.json | 321 ++++++++++++++++++ .../arch/x86/westmereep-sp/counter.json | 7 + .../x86/westmereep-sp/floating-point.json | 28 ++ .../arch/x86/westmereep-sp/frontend.json | 3 + .../arch/x86/westmereep-sp/memory.json | 67 ++++ .../arch/x86/westmereep-sp/other.json | 28 ++ .../arch/x86/westmereep-sp/pipeline.json | 111 ++++++ .../x86/westmereep-sp/virtual-memory.json | 18 + 8 files changed, 583 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/westmereep-sp/counter.js= on diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json b/tool= s/perf/pmu-events/arch/x86/westmereep-sp/cache.json index d025e2c0cf1c..90cb367f5798 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request= ", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +563,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +574,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +596,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +607,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +618,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +629,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +640,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +651,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +662,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +684,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +695,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +706,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +717,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +726,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +735,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +744,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +753,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +762,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +780,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +789,7 @@ }, { "BriefDescription": "Load instructions retired with a data source = of local DRAM or locally homed remote hitm (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM", "PEBS": "1", @@ -705,6 +798,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.OTHER_CORE_L2_HITM", "PEBS": "1", @@ -713,6 +807,7 @@ }, { "BriefDescription": "Load instructions retired remote cache HIT da= ta source (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_CACHE_LOCAL_HOME_HIT", "PEBS": "1", @@ -721,6 +816,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -729,6 +825,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -737,6 +834,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -744,6 +842,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -751,6 +850,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -758,6 +858,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -765,6 +866,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -772,6 +874,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -779,6 +882,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -786,6 +890,7 @@ }, { "BriefDescription": "Offcore uncached memory accesses", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.UNCACHED_MEM", "SampleAfterValue": "100000", @@ -793,6 +898,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -815,6 +923,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", @@ -823,6 +932,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -830,6 +940,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", @@ -838,6 +949,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -845,6 +957,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -853,6 +966,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -860,6 +974,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -869,6 +984,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -878,6 +994,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -887,6 +1004,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -896,6 +1014,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -905,6 +1024,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -914,6 +1034,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -923,6 +1044,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -932,6 +1054,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -941,6 +1064,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -950,6 +1074,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -959,6 +1084,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cach= e", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -968,6 +1094,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -977,6 +1104,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -986,6 +1114,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -995,6 +1124,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1004,6 +1134,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1013,6 +1144,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1022,6 +1154,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1031,6 +1164,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1040,6 +1174,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1049,6 +1184,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1058,6 +1194,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1067,6 +1204,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cach= e", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1076,6 +1214,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1085,6 +1224,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1094,6 +1234,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1103,6 +1244,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1112,6 +1254,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1121,6 +1264,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1130,6 +1274,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1139,6 +1284,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1148,6 +1294,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1157,6 +1304,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1166,6 +1314,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1175,6 +1324,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1184,6 +1334,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1193,6 +1344,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1202,6 +1354,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1211,6 +1364,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1220,6 +1374,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1229,6 +1384,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1238,6 +1394,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1247,6 +1404,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1256,6 +1414,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1265,6 +1424,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1274,6 +1434,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1283,6 +1444,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1292,6 +1454,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1301,6 +1464,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1310,6 +1474,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1319,6 +1484,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1328,6 +1494,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1337,6 +1504,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1346,6 +1514,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1355,6 +1524,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1364,6 +1534,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1373,6 +1544,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1382,6 +1554,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1391,6 +1564,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1400,6 +1574,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1409,6 +1584,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1418,6 +1594,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1427,6 +1604,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1436,6 +1614,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1445,6 +1624,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1454,6 +1634,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1463,6 +1644,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1472,6 +1654,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1481,6 +1664,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1490,6 +1674,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1499,6 +1684,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1508,6 +1694,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y location", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1517,6 +1704,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1526,6 +1714,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1535,6 +1724,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1544,6 +1734,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1553,6 +1744,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1562,6 +1754,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1571,6 +1764,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1580,6 +1774,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1589,6 +1784,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1598,6 +1794,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1607,6 +1804,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1616,6 +1814,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1625,6 +1824,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1634,6 +1834,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1643,6 +1844,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1652,6 +1854,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1a6,0x1a7", @@ -1661,6 +1864,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1670,6 +1874,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1679,6 +1884,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1688,6 +1894,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1697,6 +1904,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1706,6 +1914,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1715,6 +1924,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1724,6 +1934,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1733,6 +1944,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1742,6 +1954,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1a6,0x1a7", @@ -1751,6 +1964,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1a6,0x1a7", @@ -1760,6 +1974,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1a6,0x1a7", @@ -1769,6 +1984,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1778,6 +1994,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1787,6 +2004,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1796,6 +2014,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1805,6 +2024,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1814,6 +2034,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1823,6 +2044,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1832,6 +2054,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1841,6 +2064,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1850,6 +2074,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1a6,0x1a7", @@ -1859,6 +2084,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1a6,0x1a7", @@ -1868,6 +2094,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1a6,0x1a7", @@ -1877,6 +2104,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1886,6 +2114,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1895,6 +2124,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1904,6 +2134,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1913,6 +2144,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1922,6 +2154,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1931,6 +2164,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -1940,6 +2174,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -1949,6 +2184,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -1958,6 +2194,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -1967,6 +2204,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -1976,6 +2214,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -1985,6 +2224,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -1994,6 +2234,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2003,6 +2244,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2012,6 +2254,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2021,6 +2264,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2030,6 +2274,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2039,6 +2284,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2048,6 +2294,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2057,6 +2304,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2066,6 +2314,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2075,6 +2324,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2084,6 +2334,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2093,6 +2344,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2102,6 +2354,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2111,6 +2364,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2120,6 +2374,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2129,6 +2384,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote c= ache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2138,6 +2394,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote = cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2147,6 +2404,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2156,6 +2414,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2165,6 +2424,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2174,6 +2434,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2183,6 +2444,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2192,6 +2454,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2201,6 +2464,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2210,6 +2474,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2219,6 +2484,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2228,6 +2494,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2237,6 +2504,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2246,6 +2514,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2255,6 +2524,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2264,6 +2534,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2273,6 +2544,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2282,6 +2554,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2291,6 +2564,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2300,6 +2574,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2309,6 +2584,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2318,6 +2594,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2327,6 +2604,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2336,6 +2614,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2345,6 +2624,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2354,6 +2634,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2363,6 +2644,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2372,6 +2654,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2381,6 +2664,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2390,6 +2674,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2399,6 +2684,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2408,6 +2694,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2417,6 +2704,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2426,6 +2714,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2435,6 +2724,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2444,6 +2734,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2453,6 +2744,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2462,6 +2754,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2471,6 +2764,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2480,6 +2774,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2489,6 +2784,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2498,6 +2794,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2507,6 +2804,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2516,6 +2814,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2525,6 +2824,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2534,6 +2834,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2543,6 +2844,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2552,6 +2854,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2561,6 +2864,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2570,6 +2874,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2579,6 +2884,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2588,6 +2894,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1a6,0x1a7", @@ -2597,6 +2904,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1a6,0x1a7", @@ -2606,6 +2914,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1a6,0x1a7", @@ -2615,6 +2924,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2624,6 +2934,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2633,6 +2944,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2642,6 +2954,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2651,6 +2964,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1a6,0x1a7", @@ -2660,6 +2974,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -2669,6 +2984,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1a6,0x1a7", @@ -2678,6 +2994,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1a6,0x1a7", @@ -2687,6 +3004,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2694,6 +3012,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2701,6 +3020,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2708,6 +3028,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json b/to= ols/perf/pmu-events/arch/x86/westmereep-sp/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input = value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transition= s", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json b/t= ools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json b/too= ls/perf/pmu-events/arch/x86/westmereep-sp/memory.json index b65c5294bcf1..37a69ffe8521 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -10,6 +11,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -19,6 +21,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRA= M", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -28,6 +31,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -37,6 +41,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -46,6 +51,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -55,6 +61,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRA= M", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -64,6 +71,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -73,6 +81,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -82,6 +91,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -91,6 +101,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -100,6 +111,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -109,6 +121,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -118,6 +131,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -127,6 +141,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -136,6 +151,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -145,6 +161,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -154,6 +171,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -163,6 +181,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -172,6 +191,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -181,6 +201,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -190,6 +211,7 @@ }, { "BriefDescription": "Offcore code or data read requests that misse= d the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -199,6 +221,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -208,6 +231,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -217,6 +241,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -226,6 +251,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -235,6 +261,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -244,6 +271,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -253,6 +281,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -262,6 +291,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the = LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -271,6 +301,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -280,6 +311,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -289,6 +321,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -298,6 +331,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -307,6 +341,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -316,6 +351,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -325,6 +361,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -334,6 +371,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -343,6 +381,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -352,6 +391,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -361,6 +401,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -370,6 +411,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the L= LC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -379,6 +421,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -388,6 +431,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -397,6 +441,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -406,6 +451,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -415,6 +461,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -424,6 +471,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -433,6 +481,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -442,6 +491,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -451,6 +501,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -460,6 +511,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -469,6 +521,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the L= LC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -478,6 +531,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -487,6 +541,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -496,6 +551,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -505,6 +561,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the L= LC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -514,6 +571,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -523,6 +581,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -532,6 +591,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -541,6 +601,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -550,6 +611,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -559,6 +621,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -568,6 +631,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -577,6 +641,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC= ", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1a6,0x1a7", @@ -586,6 +651,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -595,6 +661,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1a6,0x1a7", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json b/tool= s/perf/pmu-events/arch/x86/westmereep-sp/other.json index 488274980564..bcf5bcf637c0 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Loads that partially overlap an earlier store= ", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "False dependencies due to partial address ali= asing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Snoop code requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Snoop data requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Snoop invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Outstanding snoop code requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "Cycles snoop code requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", @@ -142,6 +162,7 @@ }, { "BriefDescription": "Outstanding snoop data requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", @@ -149,6 +170,7 @@ }, { "BriefDescription": "Cycles snoop data requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", @@ -157,6 +179,7 @@ }, { "BriefDescription": "Outstanding snoop invalidate requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", @@ -164,6 +187,7 @@ }, { "BriefDescription": "Cycles snoop invalidate requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", @@ -172,6 +196,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json b/t= ools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json index a29ed3522779..0267788d9dce 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediciton Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event= )", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -246,6 +280,7 @@ }, { "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -254,6 +289,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -262,11 +298,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -274,17 +312,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed count= er)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -293,6 +334,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -300,6 +342,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -307,6 +350,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -314,6 +358,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -321,6 +366,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -328,6 +374,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder = 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -335,6 +382,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -342,6 +390,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instru= ction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -349,11 +398,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -362,6 +413,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -370,6 +422,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -380,6 +433,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -390,6 +444,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -398,6 +453,7 @@ }, { "BriefDescription": "Load operations conflicting with software pre= fetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -405,6 +461,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -422,6 +480,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction = queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -429,6 +488,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -436,6 +496,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -450,6 +512,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -457,6 +520,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -464,6 +528,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -471,6 +536,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -478,6 +544,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -485,6 +552,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -492,6 +560,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -499,6 +568,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -506,6 +576,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -513,6 +584,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -520,6 +592,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -527,6 +600,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -534,6 +608,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -573,6 +652,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -581,6 +661,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -588,6 +669,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -595,6 +677,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -603,6 +686,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -613,6 +697,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -622,6 +707,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -631,6 +717,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -642,6 +729,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -653,6 +741,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -663,6 +752,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -672,6 +762,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -679,6 +770,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -686,6 +778,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -695,6 +788,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -703,6 +797,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -711,6 +806,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -719,6 +815,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -727,6 +824,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -734,6 +832,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -741,6 +840,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -749,6 +849,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -759,6 +860,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -767,6 +869,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -774,6 +877,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -783,6 +887,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -792,6 +897,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -800,6 +906,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -816,6 +924,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -826,6 +935,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -836,6 +946,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.js= on b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json index 80efcfd48239..e7affdf7f41b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-sp/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", 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Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Kan Liang , Maxime Coquelin , Alexandre Torgue , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org Cc: Weilin Wang , Caleb Biggers Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add counter information necessary for optimizing event grouping the perf tool. The most recent RFC patch set using this information: https://lore.kernel.org/lkml/20240412210756.309828-1-weilin.wang@intel.com/ The information was added in: https://github.com/intel/perfmon/commit/475892a9690cb048949e593fe39cee65cd4= 765e1 and later patches. Co-authored-by: Weilin Wang Co-authored-by: Caleb Biggers Signed-off-by: Ian Rogers Reviewed-by: Kan Liang --- .../pmu-events/arch/x86/westmereex/cache.json | 320 ++++++++++++++++++ .../arch/x86/westmereex/counter.json | 7 + .../arch/x86/westmereex/floating-point.json | 28 ++ .../arch/x86/westmereex/frontend.json | 3 + .../arch/x86/westmereex/memory.json | 68 ++++ .../pmu-events/arch/x86/westmereex/other.json | 28 ++ .../arch/x86/westmereex/pipeline.json | 111 ++++++ .../arch/x86/westmereex/virtual-memory.json | 21 ++ 8 files changed, 586 insertions(+) create mode 100644 tools/perf/pmu-events/arch/x86/westmereex/counter.json diff --git a/tools/perf/pmu-events/arch/x86/westmereex/cache.json b/tools/p= erf/pmu-events/arch/x86/westmereex/cache.json index 18d61d43e4c9..9f922370ee8b 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/cache.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/cache.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles L1D locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Cycles L1D and L2 locked", + "Counter": "0,1", "EventCode": "0x63", "EventName": "CACHE_LOCK_CYCLES.L1D_L2", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1D cache lines replaced in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_EVICT", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1D cache lines allocated in the M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_REPL", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1D snoop eviction of cache lines in M state", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.M_SNOOP_EVICT", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1 data cache lines allocated", + "Counter": "0,1", "EventCode": "0x51", "EventName": "L1D.REPL", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "L1D prefetch load lock accepted in fill buffe= r", + "Counter": "0,1", "EventCode": "0x52", "EventName": "L1D_CACHE_PREFETCH_LOCK_FB_HIT", "SampleAfterValue": "2000000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "L1D hardware prefetch misses", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.MISS", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.REQUESTS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "L1D hardware prefetch requests triggered", + "Counter": "0,1", "EventCode": "0x4E", "EventName": "L1D_PREFETCH.TRIGGERS", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in E state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.E_STATE", "SampleAfterValue": "100000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.I_STATE", "SampleAfterValue": "100000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "All L1 writebacks to L2", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.MESI", "SampleAfterValue": "100000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in M state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.M_STATE", "SampleAfterValue": "100000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "L1 writebacks to L2 in S state", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "L1D_WB_L2.S_STATE", "SampleAfterValue": "100000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "All L2 data requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.ANY", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "L2 data demand loads in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.E_STATE", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "L2 data demand loads in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.I_STATE", "SampleAfterValue": "200000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "L2 data demand requests", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.MESI", "SampleAfterValue": "200000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "L2 data demand loads in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.M_STATE", "SampleAfterValue": "200000", @@ -141,6 +161,7 @@ }, { "BriefDescription": "L2 data demand loads in S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.DEMAND.S_STATE", "SampleAfterValue": "200000", @@ -148,6 +169,7 @@ }, { "BriefDescription": "L2 data prefetches in E state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.E_STATE", "SampleAfterValue": "200000", @@ -155,6 +177,7 @@ }, { "BriefDescription": "L2 data prefetches in the I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.I_STATE", "SampleAfterValue": "200000", @@ -162,6 +185,7 @@ }, { "BriefDescription": "All L2 data prefetches", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.MESI", "SampleAfterValue": "200000", @@ -169,6 +193,7 @@ }, { "BriefDescription": "L2 data prefetches in M state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.M_STATE", "SampleAfterValue": "200000", @@ -176,6 +201,7 @@ }, { "BriefDescription": "L2 data prefetches in the S state", + "Counter": "0,1,2,3", "EventCode": "0x26", "EventName": "L2_DATA_RQSTS.PREFETCH.S_STATE", "SampleAfterValue": "200000", @@ -183,6 +209,7 @@ }, { "BriefDescription": "L2 lines allocated", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.ANY", "SampleAfterValue": "100000", @@ -190,6 +217,7 @@ }, { "BriefDescription": "L2 lines allocated in the E state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.E_STATE", "SampleAfterValue": "100000", @@ -197,6 +225,7 @@ }, { "BriefDescription": "L2 lines allocated in the S state", + "Counter": "0,1,2,3", "EventCode": "0xF1", "EventName": "L2_LINES_IN.S_STATE", "SampleAfterValue": "100000", @@ -204,6 +233,7 @@ }, { "BriefDescription": "L2 lines evicted", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.ANY", "SampleAfterValue": "100000", @@ -211,6 +241,7 @@ }, { "BriefDescription": "L2 lines evicted by a demand request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_CLEAN", "SampleAfterValue": "100000", @@ -218,6 +249,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a demand request= ", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.DEMAND_DIRTY", "SampleAfterValue": "100000", @@ -225,6 +257,7 @@ }, { "BriefDescription": "L2 lines evicted by a prefetch request", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_CLEAN", "SampleAfterValue": "100000", @@ -232,6 +265,7 @@ }, { "BriefDescription": "L2 modified lines evicted by a prefetch reque= st", + "Counter": "0,1,2,3", "EventCode": "0xF2", "EventName": "L2_LINES_OUT.PREFETCH_DIRTY", "SampleAfterValue": "100000", @@ -239,6 +273,7 @@ }, { "BriefDescription": "L2 instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCHES", "SampleAfterValue": "200000", @@ -246,6 +281,7 @@ }, { "BriefDescription": "L2 instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_HIT", "SampleAfterValue": "200000", @@ -253,6 +289,7 @@ }, { "BriefDescription": "L2 instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.IFETCH_MISS", "SampleAfterValue": "200000", @@ -260,6 +297,7 @@ }, { "BriefDescription": "L2 load hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_HIT", "SampleAfterValue": "200000", @@ -267,6 +305,7 @@ }, { "BriefDescription": "L2 load misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LD_MISS", "SampleAfterValue": "200000", @@ -274,6 +313,7 @@ }, { "BriefDescription": "L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.LOADS", "SampleAfterValue": "200000", @@ -281,6 +321,7 @@ }, { "BriefDescription": "All L2 misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.MISS", "SampleAfterValue": "200000", @@ -288,6 +329,7 @@ }, { "BriefDescription": "All L2 prefetches", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCHES", "SampleAfterValue": "200000", @@ -295,6 +337,7 @@ }, { "BriefDescription": "L2 prefetch hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_HIT", "SampleAfterValue": "200000", @@ -302,6 +345,7 @@ }, { "BriefDescription": "L2 prefetch misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.PREFETCH_MISS", "SampleAfterValue": "200000", @@ -309,6 +353,7 @@ }, { "BriefDescription": "All L2 requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.REFERENCES", "SampleAfterValue": "200000", @@ -316,6 +361,7 @@ }, { "BriefDescription": "L2 RFO requests", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFOS", "SampleAfterValue": "200000", @@ -323,6 +369,7 @@ }, { "BriefDescription": "L2 RFO hits", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_HIT", "SampleAfterValue": "200000", @@ -330,6 +377,7 @@ }, { "BriefDescription": "L2 RFO misses", + "Counter": "0,1,2,3", "EventCode": "0x24", "EventName": "L2_RQSTS.RFO_MISS", "SampleAfterValue": "200000", @@ -337,6 +385,7 @@ }, { "BriefDescription": "All L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.ANY", "SampleAfterValue": "200000", @@ -344,6 +393,7 @@ }, { "BriefDescription": "L2 fill transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.FILL", "SampleAfterValue": "200000", @@ -351,6 +401,7 @@ }, { "BriefDescription": "L2 instruction fetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.IFETCH", "SampleAfterValue": "200000", @@ -358,6 +409,7 @@ }, { "BriefDescription": "L1D writeback to L2 transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.L1D_WB", "SampleAfterValue": "200000", @@ -365,6 +417,7 @@ }, { "BriefDescription": "L2 Load transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.LOAD", "SampleAfterValue": "200000", @@ -372,6 +425,7 @@ }, { "BriefDescription": "L2 prefetch transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.PREFETCH", "SampleAfterValue": "200000", @@ -379,6 +433,7 @@ }, { "BriefDescription": "L2 RFO transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.RFO", "SampleAfterValue": "200000", @@ -386,6 +441,7 @@ }, { "BriefDescription": "L2 writeback to LLC transactions", + "Counter": "0,1,2,3", "EventCode": "0xF0", "EventName": "L2_TRANSACTIONS.WB", "SampleAfterValue": "200000", @@ -393,6 +449,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in E state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.E_STATE", "SampleAfterValue": "100000", @@ -400,6 +457,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.HIT", "SampleAfterValue": "100000", @@ -407,6 +465,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.I_STATE", "SampleAfterValue": "100000", @@ -414,6 +473,7 @@ }, { "BriefDescription": "All demand L2 lock RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.MESI", "SampleAfterValue": "100000", @@ -421,6 +481,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.M_STATE", "SampleAfterValue": "100000", @@ -428,6 +489,7 @@ }, { "BriefDescription": "L2 demand lock RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.LOCK.S_STATE", "SampleAfterValue": "100000", @@ -435,6 +497,7 @@ }, { "BriefDescription": "All L2 demand store RFOs that hit the cache", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.HIT", "SampleAfterValue": "100000", @@ -442,6 +505,7 @@ }, { "BriefDescription": "L2 demand store RFOs in I state (misses)", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.I_STATE", "SampleAfterValue": "100000", @@ -449,6 +513,7 @@ }, { "BriefDescription": "All L2 demand store RFOs", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.MESI", "SampleAfterValue": "100000", @@ -456,6 +521,7 @@ }, { "BriefDescription": "L2 demand store RFOs in M state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.M_STATE", "SampleAfterValue": "100000", @@ -463,6 +529,7 @@ }, { "BriefDescription": "L2 demand store RFOs in S state", + "Counter": "0,1,2,3", "EventCode": "0x27", "EventName": "L2_WRITE.RFO.S_STATE", "SampleAfterValue": "100000", @@ -470,6 +537,7 @@ }, { "BriefDescription": "Longest latency cache miss", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.MISS", "SampleAfterValue": "100000", @@ -477,6 +545,7 @@ }, { "BriefDescription": "Longest latency cache reference", + "Counter": "0,1,2,3", "EventCode": "0x2E", "EventName": "LONGEST_LAT_CACHE.REFERENCE", "SampleAfterValue": "200000", @@ -484,6 +553,7 @@ }, { "BriefDescription": "Memory instructions retired above 0 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_0", "MSRIndex": "0x3F6", @@ -493,6 +563,7 @@ }, { "BriefDescription": "Memory instructions retired above 1024 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_1024", "MSRIndex": "0x3F6", @@ -503,6 +574,7 @@ }, { "BriefDescription": "Memory instructions retired above 128 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_128", "MSRIndex": "0x3F6", @@ -513,6 +585,7 @@ }, { "BriefDescription": "Memory instructions retired above 16 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16", "MSRIndex": "0x3F6", @@ -523,6 +596,7 @@ }, { "BriefDescription": "Memory instructions retired above 16384 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_16384", "MSRIndex": "0x3F6", @@ -533,6 +607,7 @@ }, { "BriefDescription": "Memory instructions retired above 2048 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_2048", "MSRIndex": "0x3F6", @@ -543,6 +618,7 @@ }, { "BriefDescription": "Memory instructions retired above 256 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_256", "MSRIndex": "0x3F6", @@ -553,6 +629,7 @@ }, { "BriefDescription": "Memory instructions retired above 32 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32", "MSRIndex": "0x3F6", @@ -563,6 +640,7 @@ }, { "BriefDescription": "Memory instructions retired above 32768 clock= s (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_32768", "MSRIndex": "0x3F6", @@ -573,6 +651,7 @@ }, { "BriefDescription": "Memory instructions retired above 4 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4", "MSRIndex": "0x3F6", @@ -583,6 +662,7 @@ }, { "BriefDescription": "Memory instructions retired above 4096 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_4096", "MSRIndex": "0x3F6", @@ -593,6 +673,7 @@ }, { "BriefDescription": "Memory instructions retired above 512 clocks = (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_512", "MSRIndex": "0x3F6", @@ -603,6 +684,7 @@ }, { "BriefDescription": "Memory instructions retired above 64 clocks (= Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_64", "MSRIndex": "0x3F6", @@ -613,6 +695,7 @@ }, { "BriefDescription": "Memory instructions retired above 8 clocks (P= recise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8", "MSRIndex": "0x3F6", @@ -623,6 +706,7 @@ }, { "BriefDescription": "Memory instructions retired above 8192 clocks= (Precise Event)", + "Counter": "3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LATENCY_ABOVE_THRESHOLD_8192", "MSRIndex": "0x3F6", @@ -633,6 +717,7 @@ }, { "BriefDescription": "Instructions retired which contains a load (P= recise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.LOADS", "PEBS": "1", @@ -641,6 +726,7 @@ }, { "BriefDescription": "Instructions retired which contains a store (= Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xB", "EventName": "MEM_INST_RETIRED.STORES", "PEBS": "1", @@ -649,6 +735,7 @@ }, { "BriefDescription": "Retired loads that miss L1D and hit an previo= usly allocated LFB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.HIT_LFB", "PEBS": "1", @@ -657,6 +744,7 @@ }, { "BriefDescription": "Retired loads that hit the L1 data cache (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L1D_HIT", "PEBS": "1", @@ -665,6 +753,7 @@ }, { "BriefDescription": "Retired loads that hit the L2 cache (Precise = Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.L2_HIT", "PEBS": "1", @@ -673,6 +762,7 @@ }, { "BriefDescription": "Retired loads that miss the LLC cache (Precis= e Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_MISS", "PEBS": "1", @@ -681,6 +771,7 @@ }, { "BriefDescription": "Retired loads that hit valid versions in the = LLC cache (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.LLC_UNSHARED_HIT", "PEBS": "1", @@ -689,6 +780,7 @@ }, { "BriefDescription": "Retired loads that hit sibling core's L2 in m= odified or unmodified states (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.OTHER_CORE_L2_HIT_HITM", "PEBS": "1", @@ -697,6 +789,7 @@ }, { "BriefDescription": "Load instructions retired local dram and remo= te cache HIT data sources (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_DRAM_AND_REMOTE_CACHE_HIT", "PEBS": "1", @@ -705,6 +798,7 @@ }, { "BriefDescription": "Load instructions retired that HIT modified d= ata in sibling core (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.LOCAL_HITM", "PEBS": "1", @@ -713,6 +807,7 @@ }, { "BriefDescription": "Load instructions retired remote DRAM and rem= ote home-remote cache HITM (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_DRAM", "PEBS": "1", @@ -721,6 +816,7 @@ }, { "BriefDescription": "Retired loads that hit remote socket in modif= ied state (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.REMOTE_HITM", "PEBS": "1", @@ -729,6 +825,7 @@ }, { "BriefDescription": "Load instructions retired IO (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF", "EventName": "MEM_UNCORE_RETIRED.UNCACHEABLE", "PEBS": "1", @@ -737,6 +834,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY", "SampleAfterValue": "100000", @@ -744,6 +842,7 @@ }, { "BriefDescription": "Offcore read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.READ", "SampleAfterValue": "100000", @@ -751,6 +850,7 @@ }, { "BriefDescription": "Offcore RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.ANY.RFO", "SampleAfterValue": "100000", @@ -758,6 +858,7 @@ }, { "BriefDescription": "Offcore demand code read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_CODE", "SampleAfterValue": "100000", @@ -765,6 +866,7 @@ }, { "BriefDescription": "Offcore demand data read requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.READ_DATA", "SampleAfterValue": "100000", @@ -772,6 +874,7 @@ }, { "BriefDescription": "Offcore demand RFO requests", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.DEMAND.RFO", "SampleAfterValue": "100000", @@ -779,6 +882,7 @@ }, { "BriefDescription": "Offcore L1 data cache writebacks", + "Counter": "0,1,2,3", "EventCode": "0xB0", "EventName": "OFFCORE_REQUESTS.L1D_WRITEBACK", "SampleAfterValue": "100000", @@ -786,6 +890,7 @@ }, { "BriefDescription": "Outstanding offcore reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ", "SampleAfterValue": "2000000", @@ -793,6 +898,7 @@ }, { "BriefDescription": "Cycles offcore reads busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ANY.READ_NOT_EMPTY", @@ -801,6 +907,7 @@ }, { "BriefDescription": "Outstanding offcore demand code reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE", "SampleAfterValue": "2000000", @@ -808,6 +915,7 @@ }, { "BriefDescription": "Cycles offcore demand code read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_CODE_NOT_EM= PTY", @@ -816,6 +924,7 @@ }, { "BriefDescription": "Outstanding offcore demand data reads", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA", "SampleAfterValue": "2000000", @@ -823,6 +932,7 @@ }, { "BriefDescription": "Cycles offcore demand data read busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.READ_DATA_NOT_EM= PTY", @@ -831,6 +941,7 @@ }, { "BriefDescription": "Outstanding offcore demand RFOs", + "Counter": "0", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO", "SampleAfterValue": "2000000", @@ -838,6 +949,7 @@ }, { "BriefDescription": "Cycles offcore demand RFOs busy", + "Counter": "0", "CounterMask": "1", "EventCode": "0x60", "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND.RFO_NOT_EMPTY", @@ -846,6 +958,7 @@ }, { "BriefDescription": "Offcore requests blocked due to Super Queue f= ull", + "Counter": "0,1,2,3", "EventCode": "0xB2", "EventName": "OFFCORE_REQUESTS_SQ_FULL", "SampleAfterValue": "100000", @@ -853,6 +966,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -862,6 +976,7 @@ }, { "BriefDescription": "All offcore data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -871,6 +986,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -880,6 +996,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -889,6 +1006,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -898,6 +1016,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -907,6 +1026,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -916,6 +1036,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -925,6 +1046,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -934,6 +1056,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -943,6 +1066,7 @@ }, { "BriefDescription": "Offcore data reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -952,6 +1076,7 @@ }, { "BriefDescription": "Offcore data reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -961,6 +1086,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any cache or = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -970,6 +1096,7 @@ }, { "BriefDescription": "All offcore code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -979,6 +1106,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the IO, CSR, = MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -988,6 +1116,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and n= ot found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -997,6 +1126,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and H= IT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1006,6 +1136,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC and = HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1015,6 +1146,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1024,6 +1156,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the LLC or lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1033,6 +1166,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1042,6 +1176,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote cach= e or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1051,6 +1186,7 @@ }, { "BriefDescription": "Offcore code reads that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1060,6 +1196,7 @@ }, { "BriefDescription": "Offcore code reads that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1069,6 +1206,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any cache or DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1078,6 +1216,7 @@ }, { "BriefDescription": "All offcore requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1087,6 +1226,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the IO, CSR, MM= IO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1096,6 +1236,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and not= found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1105,6 +1246,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HIT= in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1114,6 +1256,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC and HI= TM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1123,6 +1266,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1132,6 +1276,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the LLC or loca= l DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1141,6 +1286,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1150,6 +1296,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote cache = or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1159,6 +1306,7 @@ }, { "BriefDescription": "Offcore requests that HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1168,6 +1316,7 @@ }, { "BriefDescription": "Offcore requests that HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1177,6 +1326,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any cache o= r DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1186,6 +1336,7 @@ }, { "BriefDescription": "All offcore RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1195,6 +1346,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the IO, CSR= , MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1204,6 +1356,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1213,6 +1366,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC and= HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1222,6 +1376,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC an= d HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1231,6 +1386,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1240,6 +1396,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the LLC or = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1249,6 +1406,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1258,6 +1416,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote ca= che or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1267,6 +1426,7 @@ }, { "BriefDescription": "Offcore RFO requests that HIT in a remote cac= he", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1276,6 +1436,7 @@ }, { "BriefDescription": "Offcore RFO requests that HITM in a remote ca= che", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1285,6 +1446,7 @@ }, { "BriefDescription": "Offcore writebacks to any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1294,6 +1456,7 @@ }, { "BriefDescription": "All offcore writebacks", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1303,6 +1466,7 @@ }, { "BriefDescription": "Offcore writebacks to the IO, CSR, MMIO unit.= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1312,6 +1476,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and not found i= n a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1321,6 +1486,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC and HITM in a = sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1330,6 +1496,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1339,6 +1506,7 @@ }, { "BriefDescription": "Offcore writebacks to the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1348,6 +1516,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1357,6 +1526,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote cache or remot= e DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1366,6 +1536,7 @@ }, { "BriefDescription": "Offcore writebacks that HIT in a remote cache= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1375,6 +1546,7 @@ }, { "BriefDescription": "Offcore writebacks that HITM in a remote cach= e", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1384,6 +1556,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1393,6 +1566,7 @@ }, { "BriefDescription": "All offcore code or data read requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1402,6 +1576,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1411,6 +1586,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1420,6 +1596,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1429,6 +1606,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1438,6 +1616,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1447,6 +1626,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1456,6 +1636,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1465,6 +1646,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1474,6 +1656,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HIT i= n a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1483,6 +1666,7 @@ }, { "BriefDescription": "Offcore code or data read requests that HITM = in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1492,6 +1676,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y cache_dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1501,6 +1686,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y location", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1510,6 +1696,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1519,6 +1706,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1528,6 +1716,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1537,6 +1726,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1546,6 +1736,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1555,6 +1746,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D lo= cal cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1564,6 +1756,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1573,6 +1766,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D re= mote cache or dram", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1582,6 +1776,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HIT in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1591,6 +1786,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches that= HITM in a remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1600,6 +1796,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1609,6 +1806,7 @@ }, { "BriefDescription": "All offcore demand data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1618,6 +1816,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1627,6 +1826,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1636,6 +1836,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1645,6 +1846,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LLC_HIT_OTHER_CORE_HITM= ", "MSRIndex": "0x1A6", @@ -1654,6 +1856,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1663,6 +1866,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1672,6 +1876,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1681,6 +1886,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1690,6 +1896,7 @@ }, { "BriefDescription": "Offcore demand data requests that HIT in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1699,6 +1906,7 @@ }, { "BriefDescription": "Offcore demand data requests that HITM in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1708,6 +1916,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1717,6 +1926,7 @@ }, { "BriefDescription": "All offcore demand data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1726,6 +1936,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1735,6 +1946,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_NO_OTHER_COR= E", "MSRIndex": "0x1A6", @@ -1744,6 +1956,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= IT", "MSRIndex": "0x1A6", @@ -1753,6 +1966,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT_OTHER_CORE_H= ITM", "MSRIndex": "0x1A6", @@ -1762,6 +1976,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1771,6 +1986,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1780,6 +1996,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1789,6 +2006,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1798,6 +2016,7 @@ }, { "BriefDescription": "Offcore demand data reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1807,6 +2026,7 @@ }, { "BriefDescription": "Offcore demand data reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1816,6 +2036,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1825,6 +2046,7 @@ }, { "BriefDescription": "All offcore demand code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1834,6 +2056,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1843,6 +2066,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_NO_OTHER_CORE= ", "MSRIndex": "0x1A6", @@ -1852,6 +2076,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= T", "MSRIndex": "0x1A6", @@ -1861,6 +2086,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LLC_HIT_OTHER_CORE_HI= TM", "MSRIndex": "0x1A6", @@ -1870,6 +2096,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1879,6 +2106,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1888,6 +2116,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -1897,6 +2126,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1906,6 +2136,7 @@ }, { "BriefDescription": "Offcore demand code reads that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -1915,6 +2146,7 @@ }, { "BriefDescription": "Offcore demand code reads that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -1924,6 +2156,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1933,6 +2166,7 @@ }, { "BriefDescription": "All offcore demand RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -1942,6 +2176,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -1951,6 +2186,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -1960,6 +2196,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -1969,6 +2206,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -1978,6 +2216,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -1987,6 +2226,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -1996,6 +2236,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2005,6 +2246,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2014,6 +2256,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2023,6 +2266,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2032,6 +2276,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any cache= or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2041,6 +2286,7 @@ }, { "BriefDescription": "All offcore other requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2050,6 +2296,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the IO, C= SR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2059,6 +2306,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2068,6 +2316,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC a= nd HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2077,6 +2326,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC = and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2086,6 +2336,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2095,6 +2346,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by the LLC o= r local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2104,6 +2356,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2113,6 +2366,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2122,6 +2376,7 @@ }, { "BriefDescription": "Offcore other requests that HIT in a remote c= ache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2131,6 +2386,7 @@ }, { "BriefDescription": "Offcore other requests that HITM in a remote = cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2140,6 +2396,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny cache or DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2149,6 +2406,7 @@ }, { "BriefDescription": "All offcore prefetch data requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2158,6 +2416,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he IO, CSR, MMIO unit.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2167,6 +2426,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2176,6 +2436,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2185,6 +2446,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2194,6 +2456,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2203,6 +2466,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2212,6 +2476,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2221,6 +2486,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2230,6 +2496,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HIT in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2239,6 +2506,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that HITM in a= remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2248,6 +2516,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2257,6 +2526,7 @@ }, { "BriefDescription": "All offcore prefetch data reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2266,6 +2536,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2275,6 +2546,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2284,6 +2556,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2293,6 +2566,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2302,6 +2576,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2311,6 +2586,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2320,6 +2596,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2329,6 +2606,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2338,6 +2616,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2347,6 +2626,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2356,6 +2636,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2365,6 +2646,7 @@ }, { "BriefDescription": "All offcore prefetch code reads", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2374,6 +2656,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2383,6 +2666,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2392,6 +2676,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2401,6 +2686,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2410,6 +2696,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2419,6 +2706,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2428,6 +2716,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2437,6 +2726,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2446,6 +2736,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HIT in a rem= ote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2455,6 +2746,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that HITM in a re= mote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2464,6 +2756,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y cache or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2473,6 +2766,7 @@ }, { "BriefDescription": "All offcore prefetch RFO requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2482,6 +2776,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e IO, CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2491,6 +2786,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2500,6 +2796,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2509,6 +2806,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2518,6 +2816,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2527,6 +2826,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e LLC or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2536,6 +2836,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2545,6 +2846,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2554,6 +2856,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HIT in a r= emote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2563,6 +2866,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that HITM in a = remote cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2572,6 +2876,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any ca= che or DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2581,6 +2886,7 @@ }, { "BriefDescription": "All offcore prefetch requests", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LOCATION", "MSRIndex": "0x1A6", @@ -2590,6 +2896,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the IO= , CSR, MMIO unit", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.IO_CSR_MMIO", "MSRIndex": "0x1A6", @@ -2599,6 +2906,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and not found in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_NO_OTHER_CORE", "MSRIndex": "0x1A6", @@ -2608,6 +2916,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HIT in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HIT", "MSRIndex": "0x1A6", @@ -2617,6 +2926,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C and HITM in a sibling core", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LLC_HIT_OTHER_CORE_HITM", "MSRIndex": "0x1A6", @@ -2626,6 +2936,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE", "MSRIndex": "0x1A6", @@ -2635,6 +2946,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the LL= C or local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2644,6 +2956,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE", "MSRIndex": "0x1A6", @@ -2653,6 +2966,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te cache or remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_DRAM", "MSRIndex": "0x1A6", @@ -2662,6 +2976,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HIT in a remot= e cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HIT", "MSRIndex": "0x1A6", @@ -2671,6 +2986,7 @@ }, { "BriefDescription": "Offcore prefetch requests that HITM in a remo= te cache", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_CACHE_HITM", "MSRIndex": "0x1A6", @@ -2680,6 +2996,7 @@ }, { "BriefDescription": "Super Queue LRU hints sent to LLC", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.LRU_HINTS", "SampleAfterValue": "2000000", @@ -2687,6 +3004,7 @@ }, { "BriefDescription": "Super Queue lock splits across a cache line", + "Counter": "0,1,2,3", "EventCode": "0xF4", "EventName": "SQ_MISC.SPLIT_LOCK", "SampleAfterValue": "2000000", @@ -2694,6 +3012,7 @@ }, { "BriefDescription": "Loads delayed with at-Retirement block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.AT_RET", "SampleAfterValue": "200000", @@ -2701,6 +3020,7 @@ }, { "BriefDescription": "Cacheable loads delayed with L1D block code", + "Counter": "0,1,2,3", "EventCode": "0x6", "EventName": "STORE_BLOCKS.L1D_BLOCK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/counter.json b/tools= /perf/pmu-events/arch/x86/westmereex/counter.json new file mode 100644 index 000000000000..ecf0795dceab --- /dev/null +++ b/tools/perf/pmu-events/arch/x86/westmereex/counter.json @@ -0,0 +1,7 @@ +[ + { + "Unit": "core", + "CountersNumFixed": "4", + "CountersNumGeneric": "4" + } +] \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json = b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json index 196ae1d9b157..9bac9313b65c 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/floating-point.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "X87 Floating point assists (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.ALL", "PEBS": "1", @@ -9,6 +10,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid input = value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.INPUT", "PEBS": "1", @@ -17,6 +19,7 @@ }, { "BriefDescription": "X87 Floating point assists for invalid output= value (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xF7", "EventName": "FP_ASSIST.OUTPUT", "PEBS": "1", @@ -25,6 +28,7 @@ }, { "BriefDescription": "MMX Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.MMX", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "SSE2 integer Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "SSE* FP double precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "SSE and SSE2 FP Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "SSE FP packed Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "SSE FP scalar Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "SSE* FP single precision Uops", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Computational floating-point operations execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x10", "EventName": "FP_COMP_OPS_EXE.X87", "SampleAfterValue": "2000000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "All Floating Point to and from MMX transition= s", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.ANY", "SampleAfterValue": "2000000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Transitions from MMX to Floating Point instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_FP", "SampleAfterValue": "2000000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Transitions from Floating Point to MMX instru= ctions", + "Counter": "0,1,2,3", "EventCode": "0xCC", "EventName": "FP_MMX_TRANS.TO_MMX", "SampleAfterValue": "2000000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "128 bit SIMD integer pack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACK", "SampleAfterValue": "200000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "128 bit SIMD integer arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_ARITH", "SampleAfterValue": "200000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "128 bit SIMD integer logical operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "128 bit SIMD integer multiply operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_MPY", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "128 bit SIMD integer shift operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "128 bit SIMD integer shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "128 bit SIMD integer unpack operations", + "Counter": "0,1,2,3", "EventCode": "0x12", "EventName": "SIMD_INT_128.UNPACK", "SampleAfterValue": "200000", @@ -151,6 +172,7 @@ }, { "BriefDescription": "SIMD integer 64 bit pack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACK", "SampleAfterValue": "200000", @@ -158,6 +180,7 @@ }, { "BriefDescription": "SIMD integer 64 bit arithmetic operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_ARITH", "SampleAfterValue": "200000", @@ -165,6 +188,7 @@ }, { "BriefDescription": "SIMD integer 64 bit logical operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_LOGICAL", "SampleAfterValue": "200000", @@ -172,6 +196,7 @@ }, { "BriefDescription": "SIMD integer 64 bit packed multiply operation= s", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_MPY", "SampleAfterValue": "200000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shift operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.PACKED_SHIFT", "SampleAfterValue": "200000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "SIMD integer 64 bit shuffle/move operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.SHUFFLE_MOVE", "SampleAfterValue": "200000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "SIMD integer 64 bit unpack operations", + "Counter": "0,1,2,3", "EventCode": "0xFD", "EventName": "SIMD_INT_64.UNPACK", "SampleAfterValue": "200000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json b/tool= s/perf/pmu-events/arch/x86/westmereex/frontend.json index f7f28510e3ae..c561ac24d91d 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/frontend.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/frontend.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD0", "EventName": "MACRO_INSTS.DECODED", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Macro-fused instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xA6", "EventName": "MACRO_INSTS.FUSIONS_DECODED", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "Two Uop instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0x19", "EventName": "TWO_UOP_INSTS_DECODED", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/memory.json b/tools/= perf/pmu-events/arch/x86/westmereex/memory.json index f3c0d2d4bc6a..aaa7c43a7fec 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Misaligned store references", + "Counter": "0,1,2,3", "EventCode": "0x5", "EventName": "MISALIGN_MEM_REF.STORE", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Offcore data reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -26,6 +29,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -35,6 +39,7 @@ }, { "BriefDescription": "Offcore data reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -44,6 +49,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -53,6 +59,7 @@ }, { "BriefDescription": "Offcore code reads that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -62,6 +69,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by the local DRA= M", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -71,6 +79,7 @@ }, { "BriefDescription": "Offcore code reads satisfied by a remote DRAM= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -80,6 +89,7 @@ }, { "BriefDescription": "Offcore requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_DRAM", "MSRIndex": "0x1A6", @@ -89,6 +99,7 @@ }, { "BriefDescription": "Offcore requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -98,6 +109,7 @@ }, { "BriefDescription": "Offcore requests satisfied by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -107,6 +119,7 @@ }, { "BriefDescription": "Offcore requests satisfied by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_REQUEST.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -116,6 +129,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -125,6 +139,7 @@ }, { "BriefDescription": "Offcore RFO requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -134,6 +149,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by the local D= RAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -143,6 +159,7 @@ }, { "BriefDescription": "Offcore RFO requests satisfied by a remote DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.ANY_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -152,6 +169,7 @@ }, { "BriefDescription": "Offcore writebacks to any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_DRAM", "MSRIndex": "0x1A6", @@ -161,6 +179,7 @@ }, { "BriefDescription": "Offcore writebacks that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -170,6 +189,7 @@ }, { "BriefDescription": "Offcore writebacks to the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -179,6 +199,7 @@ }, { "BriefDescription": "Offcore writebacks to a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.COREWB.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -188,6 +209,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -197,6 +219,7 @@ }, { "BriefDescription": "Offcore code or data read requests that misse= d the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -206,6 +229,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by the local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -215,6 +239,7 @@ }, { "BriefDescription": "Offcore code or data read requests satisfied = by a remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -224,6 +249,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_DRAM", "MSRIndex": "0x1A6", @@ -233,6 +259,7 @@ }, { "BriefDescription": "Offcore request =3D all data, response =3D an= y LLC miss", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -242,6 +269,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the local DRAM.", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -251,6 +279,7 @@ }, { "BriefDescription": "Offcore data reads, RFOs, and prefetches sati= sfied by the remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DATA_IN.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -260,6 +289,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by any= DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -269,6 +299,7 @@ }, { "BriefDescription": "Offcore demand data requests that missed the = LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -278,6 +309,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by the= local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -287,6 +319,7 @@ }, { "BriefDescription": "Offcore demand data requests satisfied by a r= emote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -296,6 +329,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -305,6 +339,7 @@ }, { "BriefDescription": "Offcore demand data reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -314,6 +349,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -323,6 +359,7 @@ }, { "BriefDescription": "Offcore demand data reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -332,6 +369,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -341,6 +379,7 @@ }, { "BriefDescription": "Offcore demand code reads that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -350,6 +389,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -359,6 +399,7 @@ }, { "BriefDescription": "Offcore demand code reads satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -368,6 +409,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -377,6 +419,7 @@ }, { "BriefDescription": "Offcore demand RFO requests that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -386,6 +429,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -395,6 +439,7 @@ }, { "BriefDescription": "Offcore demand RFO requests satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -404,6 +449,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by any DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_DRAM", "MSRIndex": "0x1A6", @@ -413,6 +459,7 @@ }, { "BriefDescription": "Offcore other requests that missed the LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -422,6 +469,7 @@ }, { "BriefDescription": "Offcore other requests satisfied by a remote = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.OTHER.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -431,6 +479,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= ny DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_DRAM", "MSRIndex": "0x1A6", @@ -440,6 +489,7 @@ }, { "BriefDescription": "Offcore prefetch data requests that missed th= e LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -449,6 +499,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by t= he local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -458,6 +509,7 @@ }, { "BriefDescription": "Offcore prefetch data requests satisfied by a= remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -467,6 +519,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_DRAM", "MSRIndex": "0x1A6", @@ -476,6 +529,7 @@ }, { "BriefDescription": "Offcore prefetch data reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -485,6 +539,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -494,6 +549,7 @@ }, { "BriefDescription": "Offcore prefetch data reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_DATA_RD.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -503,6 +559,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by any = DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -512,6 +569,7 @@ }, { "BriefDescription": "Offcore prefetch code reads that missed the L= LC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -521,6 +579,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by the = local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -530,6 +589,7 @@ }, { "BriefDescription": "Offcore prefetch code reads satisfied by a re= mote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_IFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -539,6 +599,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by an= y DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_DRAM", "MSRIndex": "0x1A6", @@ -548,6 +609,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests that missed the= LLC", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -557,6 +619,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by th= e local DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -566,6 +629,7 @@ }, { "BriefDescription": "Offcore prefetch RFO requests satisfied by a = remote DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PF_RFO.REMOTE_DRAM", "MSRIndex": "0x1A6", @@ -575,6 +639,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by any DR= AM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_DRAM", "MSRIndex": "0x1A6", @@ -584,6 +649,7 @@ }, { "BriefDescription": "Offcore prefetch requests that missed the LLC= ", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.ANY_LLC_MISS", "MSRIndex": "0x1A6", @@ -593,6 +659,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by the lo= cal DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.LOCAL_DRAM", "MSRIndex": "0x1A6", @@ -602,6 +669,7 @@ }, { "BriefDescription": "Offcore prefetch requests satisfied by a remo= te DRAM", + "Counter": "2", "EventCode": "0xB7", "EventName": "OFFCORE_RESPONSE.PREFETCH.REMOTE_DRAM", "MSRIndex": "0x1A6", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/other.json b/tools/p= erf/pmu-events/arch/x86/westmereex/other.json index 488274980564..bcf5bcf637c0 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/other.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "ES segment renames", + "Counter": "0,1,2,3", "EventCode": "0xD5", "EventName": "ES_REG_RENAMES", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "I/O transactions", + "Counter": "0,1,2,3", "EventCode": "0x6C", "EventName": "IO_TRANSACTIONS", "SampleAfterValue": "2000000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "L1I instruction fetch stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.CYCLES_STALLED", "SampleAfterValue": "2000000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "L1I instruction fetch hits", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.HITS", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "L1I instruction fetch misses", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.MISSES", "SampleAfterValue": "2000000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "L1I Instruction fetches", + "Counter": "0,1,2,3", "EventCode": "0x80", "EventName": "L1I.READS", "SampleAfterValue": "2000000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "Large ITLB hit", + "Counter": "0,1,2,3", "EventCode": "0x82", "EventName": "LARGE_ITLB.HIT", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "Loads that partially overlap an earlier store= ", + "Counter": "0,1,2,3", "EventCode": "0x3", "EventName": "LOAD_BLOCK.OVERLAP_STORE", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "All loads dispatched", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.ANY", "SampleAfterValue": "2000000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "Loads dispatched from the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.MOB", "SampleAfterValue": "2000000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "Loads dispatched that bypass the MOB", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS", "SampleAfterValue": "2000000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "Loads dispatched from stage 305", + "Counter": "0,1,2,3", "EventCode": "0x13", "EventName": "LOAD_DISPATCH.RS_DELAYED", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "False dependencies due to partial address ali= asing", + "Counter": "0,1,2,3", "EventCode": "0x7", "EventName": "PARTIAL_ADDRESS_ALIAS", "SampleAfterValue": "200000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "All Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x4", "EventName": "SB_DRAIN.ANY", "SampleAfterValue": "200000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "Segment rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD4", "EventName": "SEG_RENAME_STALLS", "SampleAfterValue": "2000000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "Snoop code requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.CODE", "SampleAfterValue": "100000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "Snoop data requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.DATA", "SampleAfterValue": "100000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "Snoop invalidate requests", + "Counter": "0,1,2,3", "EventCode": "0xB4", "EventName": "SNOOPQ_REQUESTS.INVALIDATE", "SampleAfterValue": "100000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Outstanding snoop code requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE", "SampleAfterValue": "2000000", @@ -134,6 +153,7 @@ }, { "BriefDescription": "Cycles snoop code requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY", @@ -142,6 +162,7 @@ }, { "BriefDescription": "Outstanding snoop data requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA", "SampleAfterValue": "2000000", @@ -149,6 +170,7 @@ }, { "BriefDescription": "Cycles snoop data requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY", @@ -157,6 +179,7 @@ }, { "BriefDescription": "Outstanding snoop invalidate requests", + "Counter": "0", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE", "SampleAfterValue": "2000000", @@ -164,6 +187,7 @@ }, { "BriefDescription": "Cycles snoop invalidate requests queued", + "Counter": "0", "CounterMask": "1", "EventCode": "0xB3", "EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY", @@ -172,6 +196,7 @@ }, { "BriefDescription": "Thread responded HIT to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HIT", "SampleAfterValue": "100000", @@ -179,6 +204,7 @@ }, { "BriefDescription": "Thread responded HITE to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITE", "SampleAfterValue": "100000", @@ -186,6 +212,7 @@ }, { "BriefDescription": "Thread responded HITM to snoop", + "Counter": "0,1,2,3", "EventCode": "0xB8", "EventName": "SNOOP_RESPONSE.HITM", "SampleAfterValue": "100000", @@ -193,6 +220,7 @@ }, { "BriefDescription": "Super Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xF6", "EventName": "SQ_FULL_STALL_CYCLES", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json b/tool= s/perf/pmu-events/arch/x86/westmereex/pipeline.json index 026236558d05..e8cac8622b30 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/pipeline.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Cycles the divider is busy", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.CYCLES_DIV_BUSY", "SampleAfterValue": "2000000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Divide Operations executed", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x14", @@ -18,6 +20,7 @@ }, { "BriefDescription": "Multiply operations executed", + "Counter": "0,1,2,3", "EventCode": "0x14", "EventName": "ARITH.MUL", "SampleAfterValue": "2000000", @@ -25,6 +28,7 @@ }, { "BriefDescription": "BACLEAR asserted with bad target address", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.BAD_TARGET", "SampleAfterValue": "2000000", @@ -32,6 +36,7 @@ }, { "BriefDescription": "BACLEAR asserted, regardless of cause", + "Counter": "0,1,2,3", "EventCode": "0xE6", "EventName": "BACLEAR.CLEAR", "SampleAfterValue": "2000000", @@ -39,6 +44,7 @@ }, { "BriefDescription": "Instruction queue forced BACLEAR", + "Counter": "0,1,2,3", "EventCode": "0xA7", "EventName": "BACLEAR_FORCE_IQ", "SampleAfterValue": "2000000", @@ -46,6 +52,7 @@ }, { "BriefDescription": "Early Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.EARLY", "SampleAfterValue": "2000000", @@ -53,6 +60,7 @@ }, { "BriefDescription": "Late Branch Prediction Unit clears", + "Counter": "0,1,2,3", "EventCode": "0xE8", "EventName": "BPU_CLEARS.LATE", "SampleAfterValue": "2000000", @@ -60,6 +68,7 @@ }, { "BriefDescription": "Branch prediction unit missed call or return", + "Counter": "0,1,2,3", "EventCode": "0xE5", "EventName": "BPU_MISSED_CALL_RET", "SampleAfterValue": "2000000", @@ -67,6 +76,7 @@ }, { "BriefDescription": "Branch instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xE0", "EventName": "BR_INST_DECODED", "SampleAfterValue": "2000000", @@ -74,6 +84,7 @@ }, { "BriefDescription": "Branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.ANY", "SampleAfterValue": "200000", @@ -81,6 +92,7 @@ }, { "BriefDescription": "Conditional branch instructions executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.COND", "SampleAfterValue": "200000", @@ -88,6 +100,7 @@ }, { "BriefDescription": "Unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT", "SampleAfterValue": "200000", @@ -95,6 +108,7 @@ }, { "BriefDescription": "Unconditional call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -102,6 +116,7 @@ }, { "BriefDescription": "Indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "20000", @@ -109,6 +124,7 @@ }, { "BriefDescription": "Indirect non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "20000", @@ -116,6 +132,7 @@ }, { "BriefDescription": "Call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NEAR_CALLS", "SampleAfterValue": "20000", @@ -123,6 +140,7 @@ }, { "BriefDescription": "All non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.NON_CALLS", "SampleAfterValue": "200000", @@ -130,6 +148,7 @@ }, { "BriefDescription": "Indirect return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.RETURN_NEAR", "SampleAfterValue": "20000", @@ -137,6 +156,7 @@ }, { "BriefDescription": "Taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x88", "EventName": "BR_INST_EXEC.TAKEN", "SampleAfterValue": "200000", @@ -144,6 +164,7 @@ }, { "BriefDescription": "Retired branch instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -152,6 +173,7 @@ }, { "BriefDescription": "Retired conditional branch instructions (Prec= ise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.CONDITIONAL", "PEBS": "1", @@ -160,6 +182,7 @@ }, { "BriefDescription": "Retired near call instructions (Precise Event= )", + "Counter": "0,1,2,3", "EventCode": "0xC4", "EventName": "BR_INST_RETIRED.NEAR_CALL", "PEBS": "1", @@ -168,6 +191,7 @@ }, { "BriefDescription": "Mispredicted branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.ANY", "SampleAfterValue": "20000", @@ -175,6 +199,7 @@ }, { "BriefDescription": "Mispredicted conditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.COND", "SampleAfterValue": "20000", @@ -182,6 +207,7 @@ }, { "BriefDescription": "Mispredicted unconditional branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT", "SampleAfterValue": "20000", @@ -189,6 +215,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.DIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -196,6 +223,7 @@ }, { "BriefDescription": "Mispredicted indirect call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NEAR_CALL", "SampleAfterValue": "2000", @@ -203,6 +231,7 @@ }, { "BriefDescription": "Mispredicted indirect non call branches execu= ted", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.INDIRECT_NON_CALL", "SampleAfterValue": "2000", @@ -210,6 +239,7 @@ }, { "BriefDescription": "Mispredicted call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NEAR_CALLS", "SampleAfterValue": "2000", @@ -217,6 +247,7 @@ }, { "BriefDescription": "Mispredicted non call branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.NON_CALLS", "SampleAfterValue": "20000", @@ -224,6 +255,7 @@ }, { "BriefDescription": "Mispredicted return branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.RETURN_NEAR", "SampleAfterValue": "2000", @@ -231,6 +263,7 @@ }, { "BriefDescription": "Mispredicted taken branches executed", + "Counter": "0,1,2,3", "EventCode": "0x89", "EventName": "BR_MISP_EXEC.TAKEN", "SampleAfterValue": "20000", @@ -238,6 +271,7 @@ }, { "BriefDescription": "Mispredicted retired branch instructions (Pre= cise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.ALL_BRANCHES", "PEBS": "1", @@ -246,6 +280,7 @@ }, { "BriefDescription": "Mispredicted conditional retired branches (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.CONDITIONAL", "PEBS": "1", @@ -254,6 +289,7 @@ }, { "BriefDescription": "Mispredicted near retired calls (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC5", "EventName": "BR_MISP_RETIRED.NEAR_CALL", "PEBS": "1", @@ -262,11 +298,13 @@ }, { "BriefDescription": "Reference cycles when thread is not halted (f= ixed counter)", + "Counter": "Fixed counter 3", "EventName": "CPU_CLK_UNHALTED.REF", "SampleAfterValue": "2000000" }, { "BriefDescription": "Reference base clock (133 Mhz) cycles when th= read is not halted (programmable counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.REF_P", "SampleAfterValue": "100000", @@ -274,17 +312,20 @@ }, { "BriefDescription": "Cycles when thread is not halted (fixed count= er)", + "Counter": "Fixed counter 2", "EventName": "CPU_CLK_UNHALTED.THREAD", "SampleAfterValue": "2000000" }, { "BriefDescription": "Cycles when thread is not halted (programmabl= e counter)", + "Counter": "0,1,2,3", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.THREAD_P", "SampleAfterValue": "2000000" }, { "BriefDescription": "Total CPU cycles", + "Counter": "0,1,2,3", "CounterMask": "2", "EventCode": "0x3C", "EventName": "CPU_CLK_UNHALTED.TOTAL_CYCLES", @@ -293,6 +334,7 @@ }, { "BriefDescription": "Any Instruction Length Decoder stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.ANY", "SampleAfterValue": "2000000", @@ -300,6 +342,7 @@ }, { "BriefDescription": "Instruction Queue full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.IQ_FULL", "SampleAfterValue": "2000000", @@ -307,6 +350,7 @@ }, { "BriefDescription": "Length Change Prefix stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.LCP", "SampleAfterValue": "2000000", @@ -314,6 +358,7 @@ }, { "BriefDescription": "Stall cycles due to BPU MRU bypass", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.MRU", "SampleAfterValue": "2000000", @@ -321,6 +366,7 @@ }, { "BriefDescription": "Regen stall cycles", + "Counter": "0,1,2,3", "EventCode": "0x87", "EventName": "ILD_STALL.REGEN", "SampleAfterValue": "2000000", @@ -328,6 +374,7 @@ }, { "BriefDescription": "Instructions that must be decoded by decoder = 0", + "Counter": "0,1,2,3", "EventCode": "0x18", "EventName": "INST_DECODED.DEC0", "SampleAfterValue": "2000000", @@ -335,6 +382,7 @@ }, { "BriefDescription": "Instructions written to instruction queue.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INST_QUEUE_WRITES", "SampleAfterValue": "2000000", @@ -342,6 +390,7 @@ }, { "BriefDescription": "Cycles instructions are written to the instru= ction queue", + "Counter": "0,1,2,3", "EventCode": "0x1E", "EventName": "INST_QUEUE_WRITE_CYCLES", "SampleAfterValue": "2000000", @@ -349,11 +398,13 @@ }, { "BriefDescription": "Instructions retired (fixed counter)", + "Counter": "Fixed counter 1", "EventName": "INST_RETIRED.ANY", "SampleAfterValue": "2000000" }, { "BriefDescription": "Instructions retired (Programmable counter an= d Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.ANY_P", "PEBS": "1", @@ -362,6 +413,7 @@ }, { "BriefDescription": "Retired MMX instructions (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.MMX", "PEBS": "1", @@ -370,6 +422,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES", @@ -380,6 +433,7 @@ }, { "BriefDescription": "Total cycles (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC0", "EventName": "INST_RETIRED.TOTAL_CYCLES_PS", @@ -390,6 +444,7 @@ }, { "BriefDescription": "Retired floating-point operations (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC0", "EventName": "INST_RETIRED.X87", "PEBS": "1", @@ -398,6 +453,7 @@ }, { "BriefDescription": "Load operations conflicting with software pre= fetches", + "Counter": "0,1", "EventCode": "0x4C", "EventName": "LOAD_HIT_PRE", "SampleAfterValue": "200000", @@ -405,6 +461,7 @@ }, { "BriefDescription": "Cycles when uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.ACTIVE", @@ -413,6 +470,7 @@ }, { "BriefDescription": "Cycles no uops were delivered by the LSD", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xA8", "EventName": "LSD.INACTIVE", @@ -422,6 +480,7 @@ }, { "BriefDescription": "Loops that can't stream from the instruction = queue", + "Counter": "0,1,2,3", "EventCode": "0x20", "EventName": "LSD_OVERFLOW", "SampleAfterValue": "2000000", @@ -429,6 +488,7 @@ }, { "BriefDescription": "Cycles machine clear asserted", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.CYCLES", "SampleAfterValue": "20000", @@ -436,6 +496,7 @@ }, { "BriefDescription": "Execution pipeline restart due to Memory orde= ring conflicts", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.MEM_ORDER", "SampleAfterValue": "20000", @@ -443,6 +504,7 @@ }, { "BriefDescription": "Self-Modifying Code detected", + "Counter": "0,1,2,3", "EventCode": "0xC3", "EventName": "MACHINE_CLEARS.SMC", "SampleAfterValue": "20000", @@ -450,6 +512,7 @@ }, { "BriefDescription": "All RAT stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ANY", "SampleAfterValue": "2000000", @@ -457,6 +520,7 @@ }, { "BriefDescription": "Flag stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.FLAGS", "SampleAfterValue": "2000000", @@ -464,6 +528,7 @@ }, { "BriefDescription": "Partial register stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.REGISTERS", "SampleAfterValue": "2000000", @@ -471,6 +536,7 @@ }, { "BriefDescription": "ROB read port stalls cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.ROB_READ_PORT", "SampleAfterValue": "2000000", @@ -478,6 +544,7 @@ }, { "BriefDescription": "Scoreboard stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xD2", "EventName": "RAT_STALLS.SCOREBOARD", "SampleAfterValue": "2000000", @@ -485,6 +552,7 @@ }, { "BriefDescription": "Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ANY", "SampleAfterValue": "2000000", @@ -492,6 +560,7 @@ }, { "BriefDescription": "FPU control word write stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.FPCW", "SampleAfterValue": "2000000", @@ -499,6 +568,7 @@ }, { "BriefDescription": "Load buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.LOAD", "SampleAfterValue": "2000000", @@ -506,6 +576,7 @@ }, { "BriefDescription": "MXCSR rename stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.MXCSR", "SampleAfterValue": "2000000", @@ -513,6 +584,7 @@ }, { "BriefDescription": "Other Resource related stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.OTHER", "SampleAfterValue": "2000000", @@ -520,6 +592,7 @@ }, { "BriefDescription": "ROB full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.ROB_FULL", "SampleAfterValue": "2000000", @@ -527,6 +600,7 @@ }, { "BriefDescription": "Reservation Station full stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.RS_FULL", "SampleAfterValue": "2000000", @@ -534,6 +608,7 @@ }, { "BriefDescription": "Store buffer stall cycles", + "Counter": "0,1,2,3", "EventCode": "0xA2", "EventName": "RESOURCE_STALLS.STORE", "SampleAfterValue": "2000000", @@ -541,6 +616,7 @@ }, { "BriefDescription": "SIMD Packed-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_DOUBLE", "PEBS": "1", @@ -549,6 +625,7 @@ }, { "BriefDescription": "SIMD Packed-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.PACKED_SINGLE", "PEBS": "1", @@ -557,6 +634,7 @@ }, { "BriefDescription": "SIMD Scalar-Double Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_DOUBLE", "PEBS": "1", @@ -565,6 +643,7 @@ }, { "BriefDescription": "SIMD Scalar-Single Uops retired (Precise Even= t)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.SCALAR_SINGLE", "PEBS": "1", @@ -573,6 +652,7 @@ }, { "BriefDescription": "SIMD Vector Integer Uops retired (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xC7", "EventName": "SSEX_UOPS_RETIRED.VECTOR_INTEGER", "PEBS": "1", @@ -581,6 +661,7 @@ }, { "BriefDescription": "Stack pointer instructions decoded", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_FOLDING", "SampleAfterValue": "2000000", @@ -588,6 +669,7 @@ }, { "BriefDescription": "Stack pointer sync operations", + "Counter": "0,1,2,3", "EventCode": "0xD1", "EventName": "UOPS_DECODED.ESP_SYNC", "SampleAfterValue": "2000000", @@ -595,6 +677,7 @@ }, { "BriefDescription": "Uops decoded by Microcode Sequencer", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.MS_CYCLES_ACTIVE", @@ -603,6 +686,7 @@ }, { "BriefDescription": "Cycles no Uops are decoded", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xD1", "EventName": "UOPS_DECODED.STALL_CYCLES", @@ -613,6 +697,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on any port (core count)= ", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES", @@ -622,6 +707,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops executed on ports 0-4 (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_ACTIVE_CYCLES_NO_PORT5", @@ -630,6 +716,7 @@ }, { "BriefDescription": "Uops executed on any port (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -640,6 +727,7 @@ }, { "BriefDescription": "Uops executed on ports 0-4 (core count)", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0xB1", @@ -651,6 +739,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on any port (core count= )", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES", @@ -661,6 +750,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops issued on ports 0-4 (core coun= t)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.CORE_STALL_CYCLES_NO_PORT5", @@ -670,6 +760,7 @@ }, { "BriefDescription": "Uops executed on port 0", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT0", "SampleAfterValue": "2000000", @@ -677,6 +768,7 @@ }, { "BriefDescription": "Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015", "SampleAfterValue": "2000000", @@ -684,6 +776,7 @@ }, { "BriefDescription": "Cycles no Uops issued on ports 0, 1 or 5", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT015_STALL_CYCLES", @@ -693,6 +786,7 @@ }, { "BriefDescription": "Uops executed on port 1", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT1", "SampleAfterValue": "2000000", @@ -701,6 +795,7 @@ { "AnyThread": "1", "BriefDescription": "Uops issued on ports 2, 3 or 4", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT234_CORE", "SampleAfterValue": "2000000", @@ -709,6 +804,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 2 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT2_CORE", "SampleAfterValue": "2000000", @@ -717,6 +813,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 3 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT3_CORE", "SampleAfterValue": "2000000", @@ -725,6 +822,7 @@ { "AnyThread": "1", "BriefDescription": "Uops executed on port 4 (core count)", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT4_CORE", "SampleAfterValue": "2000000", @@ -732,6 +830,7 @@ }, { "BriefDescription": "Uops executed on port 5", + "Counter": "0,1,2,3", "EventCode": "0xB1", "EventName": "UOPS_EXECUTED.PORT5", "SampleAfterValue": "2000000", @@ -739,6 +838,7 @@ }, { "BriefDescription": "Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.ANY", "SampleAfterValue": "2000000", @@ -747,6 +847,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles no Uops were issued on any thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CORE_STALL_CYCLES", @@ -757,6 +858,7 @@ { "AnyThread": "1", "BriefDescription": "Cycles Uops were issued on either thread", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.CYCLES_ALL_THREADS", @@ -765,6 +867,7 @@ }, { "BriefDescription": "Fused Uops issued", + "Counter": "0,1,2,3", "EventCode": "0xE", "EventName": "UOPS_ISSUED.FUSED", "SampleAfterValue": "2000000", @@ -772,6 +875,7 @@ }, { "BriefDescription": "Cycles no Uops were issued", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xE", "EventName": "UOPS_ISSUED.STALL_CYCLES", @@ -781,6 +885,7 @@ }, { "BriefDescription": "Cycles Uops are being retired", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ACTIVE_CYCLES", @@ -790,6 +895,7 @@ }, { "BriefDescription": "Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.ANY", "PEBS": "1", @@ -798,6 +904,7 @@ }, { "BriefDescription": "Macro-fused Uops retired (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.MACRO_FUSED", "PEBS": "1", @@ -806,6 +913,7 @@ }, { "BriefDescription": "Retirement slots used (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.RETIRE_SLOTS", "PEBS": "1", @@ -814,6 +922,7 @@ }, { "BriefDescription": "Cycles Uops are not retiring (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "1", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.STALL_CYCLES", @@ -824,6 +933,7 @@ }, { "BriefDescription": "Total cycles using precise uop retired event = (Precise Event)", + "Counter": "0,1,2,3", "CounterMask": "16", "EventCode": "0xC2", "EventName": "UOPS_RETIRED.TOTAL_CYCLES", @@ -834,6 +944,7 @@ }, { "BriefDescription": "Uop unfusions due to FP exceptions", + "Counter": "0,1,2,3", "EventCode": "0xDB", "EventName": "UOP_UNFUSION", "SampleAfterValue": "2000000", diff --git a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json = b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json index 6c92b2be2d06..0c3501e6e5a3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereex/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB misses caused by low part of address. Co= unt also includes 2M page references because 2M pages do not use the PDE.", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "ITLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Pr= ecise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -135,6 +154,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Eve= nt)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -143,6 +163,7 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Ev= ent)", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "PEBS": "1", --=20 2.45.2.627.g7a2c4fd464-goog